1 2 /******************************************************************************/ 3 /* Device Specific Peripheral registers structures */ 4 /******************************************************************************/ 5 6 /** @addtogroup REGISTER Control Register 7 8 @{ 9 10 */ 11 12 13 /*---------------------- USB Host Controller -------------------------*/ 14 /** 15 @addtogroup USBH USB Host Controller(USBH) 16 Memory Mapped Structure for USBH Controller 17 @{ */ 18 19 typedef struct 20 { 21 22 23 /** 24 * @var USBH_T::HcRevision 25 * Offset: 0x00 Host Controller Revision Register 26 * --------------------------------------------------------------------------------------------------- 27 * |Bits |Field |Descriptions 28 * | :----: | :----: | :---- | 29 * |[7:0] |REV |Revision Number 30 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware 31 * | | |Host Controller supports 1.1 specification. 32 * | | |(X.Y = XYh). 33 * @var USBH_T::HcControl 34 * Offset: 0x04 Host Controller Control Register 35 * --------------------------------------------------------------------------------------------------- 36 * |Bits |Field |Descriptions 37 * | :----: | :----: | :---- | 38 * |[1:0] |CBSR |Control Bulk Service Ratio 39 * | | |This specifies the service ratio between Control and Bulk EDs 40 * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs 41 * | | |The internal count will be retained when crossing the frame boundary 42 * | | |In case of reset, HCD is responsible for restoring this value. 43 * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. 44 * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. 45 * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. 46 * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. 47 * |[2] |PLE |Periodic List Enable Bit 48 * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list 49 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. 50 * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. 51 * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. 52 * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. 53 * |[3] |IE |Isochronous List Enable Bit 54 * | | |Both IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list 55 * | | |Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. 56 * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. 57 * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. 58 * |[4] |CLE |Control List Enable Bit 59 * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. 60 * | | |1 = Processing of the Control list in the next frame Enabled. 61 * |[5] |BLE |Bulk List Enable Bit 62 * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. 63 * | | |1 = Processing of the Bulk list in the next frame Enabled. 64 * |[7:6] |HCFS |Host Controller Functional State 65 * | | |This field sets the Host Controller state 66 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port 67 * | | |States are: 68 * | | |00 = USBRESET. 69 * | | |01 = USBRESUME. 70 * | | |10 = USBOPERATIONAL. 71 * | | |11 = USBSUSPEND. 72 * @var USBH_T::HcCommandStatus 73 * Offset: 0x08 Host Controller Command Status Register 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[0] |HCR |Host Controller Reset 78 * | | |This bit is set to initiate the software reset of Host Controller 79 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. 80 * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. 81 * | | |0 = Host Controller is not in software reset state. 82 * | | |1 = Host Controller is in software reset state. 83 * |[1] |CLF |Control List Filled 84 * | | |Set high to indicate there is an active TD on the Control List 85 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. 86 * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. 87 * | | |1 = An active TD added or found on the Control list. 88 * |[2] |BLF |Bulk List Filled 89 * | | |Set high to indicate there is an active TD on the Bulk list 90 * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. 91 * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. 92 * | | |1 = An active TD added or found on the Bulk list. 93 * |[17:16] |SOC |Schedule Overrun Count (Read Only) 94 * | | |These bits are incremented on each scheduling overrun error 95 * | | |It is initialized to 00b and wraps around at 11b 96 * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. 97 * @var USBH_T::HcInterruptStatus 98 * Offset: 0x0C Host Controller Interrupt Status Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[0] |SO |Scheduling Overrun 103 * | | |Set when the List Processor determines a Schedule Overrun has occurred. 104 * | | |0 = Schedule Overrun didn't occur. 105 * | | |1 = Schedule Overrun has occurred. 106 * | | |Note: This bit is cleared by writing 1 to it. 107 * |[1] |WDH |Write Back Done Head 108 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead 109 * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. 110 * | | |0 = Host Controller didn't update HccaDoneHead. 111 * | | |1 = Host Controller has written HcDoneHead to HccaDoneHead. 112 * | | |Note: This bit is cleared by writing 1 to it. 113 * |[2] |SF |Start of Frame 114 * | | |Set when the Frame Management functional block signals a 'Start of Frame' event 115 * | | |Host Control generates a SOF token at the same time. 116 * | | |0 = Not the start of a frame. 117 * | | |1 = Indicate the start of a frame and Host Controller generates a SOF token. 118 * | | |Note: This bit is cleared by writing 1 to it. 119 * |[3] |RD |Resume Detected 120 * | | |Set when Host Controller detects resume signaling on a downstream port. 121 * | | |0 = No resume signaling detected on a downstream port. 122 * | | |1 = Resume signaling detected on a downstream port. 123 * | | |Note: This bit is cleared by writing 1 to it. 124 * |[5] |FNO |Frame Number Overflow 125 * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 126 * | | |0 = The bit 15 of Frame Number didn't change. 127 * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 128 * | | |Note: This bit is cleared by writing 1 to it. 129 * |[6] |RHSC |Root Hub Status Change 130 * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed. 131 * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change. 132 * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus1 register has changed. 133 * | | |Note: This bit is cleared by writing '1Fh' to HcRhPortStatus1[20:16]. 134 * @var USBH_T::HcInterruptEnable 135 * Offset: 0x10 Host Controller Interrupt Enable Register 136 * --------------------------------------------------------------------------------------------------- 137 * |Bits |Field |Descriptions 138 * | :----: | :----: | :---- | 139 * |[0] |SO |Scheduling Overrun Enable Bit 140 * | | |Write Operation: 141 * | | |0 = No effect. 142 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 143 * | | |Read Operation: 144 * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 145 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 146 * |[1] |WDH |Write Back Done Head Enable Bit 147 * | | |Write Operation: 148 * | | |0 = No effect. 149 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 150 * | | |Read Operation: 151 * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 152 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 153 * |[2] |SF |Start of Frame Enable Bit 154 * | | |Write Operation: 155 * | | |0 = No effect. 156 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 157 * | | |Read Operation: 158 * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 159 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 160 * |[3] |RD |Resume Detected Enable Bit 161 * | | |Write Operation: 162 * | | |0 = No effect. 163 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 164 * | | |Read Operation: 165 * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 166 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 167 * |[5] |FNO |Frame Number Overflow Enable Bit 168 * | | |Write Operation: 169 * | | |0 = No effect. 170 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 171 * | | |Read Operation: 172 * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 173 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 174 * |[6] |RHSC |Root Hub Status Change Enable Bit 175 * | | |Write Operation: 176 * | | |0 = No effect. 177 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 178 * | | |Read Operation: 179 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 180 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 181 * |[31] |MIE |Master Interrupt Enable Bit 182 * | | |This bit is a global interrupt enable 183 * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. 184 * | | |Write Operation: 185 * | | |0 = No effect. 186 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 187 * | | |Read Operation: 188 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. 189 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 190 * @var USBH_T::HcInterruptDisable 191 * Offset: 0x14 Host Controller Interrupt Disable Register 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[0] |SO |Scheduling Overrun Disable Bit 196 * | | |Write Operation: 197 * | | |0 = No effect. 198 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 199 * | | |Read Operation: 200 * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. 201 * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. 202 * |[1] |WDH |Write Back Done Head Disable Bit 203 * | | |Write Operation: 204 * | | |0 = No effect. 205 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 206 * | | |Read Operation: 207 * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. 208 * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. 209 * |[2] |SF |Start of Frame Disable Bit 210 * | | |Write Operation: 211 * | | |0 = No effect. 212 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 213 * | | |Read Operation: 214 * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. 215 * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. 216 * |[3] |RD |Resume Detected Disable Bit 217 * | | |Write Operation: 218 * | | |0 = No effect. 219 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 220 * | | |Read Operation: 221 * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. 222 * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. 223 * |[5] |FNO |Frame Number Overflow Disable Bit 224 * | | |Write Operation: 225 * | | |0 = No effect. 226 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 227 * | | |Read Operation: 228 * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. 229 * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. 230 * |[6] |RHSC |Root Hub Status Change Disable Bit 231 * | | |Write Operation: 232 * | | |0 = No effect. 233 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 234 * | | |Read Operation: 235 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. 236 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. 237 * |[31] |MIE |Master Interrupt Disable Bit 238 * | | |Global interrupt disable. Writing '1' to disable all interrupts. 239 * | | |Write Operation: 240 * | | |0 = No effect. 241 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. 242 * | | |Read Operation: 243 * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. 244 * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. 245 * @var USBH_T::HcHCCA 246 * Offset: 0x18 Host Controller Communication Area Register 247 * --------------------------------------------------------------------------------------------------- 248 * |Bits |Field |Descriptions 249 * | :----: | :----: | :---- | 250 * |[31:8] |HCCA |Host Controller Communication Area 251 * | | |Pointer to indicate the base address of the Host Controller Communication Area (HCCA). 252 * @var USBH_T::HcPeriodCurrentED 253 * Offset: 0x1C Host Controller Period Current ED Register 254 * --------------------------------------------------------------------------------------------------- 255 * |Bits |Field |Descriptions 256 * | :----: | :----: | :---- | 257 * |[31:4] |PCED |Periodic Current ED 258 * | | |Pointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor. 259 * @var USBH_T::HcControlHeadED 260 * Offset: 0x20 Host Controller Control Head ED Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[31:4] |CHED |Control Head ED 265 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Control list. 266 * @var USBH_T::HcControlCurrentED 267 * Offset: 0x24 Host Controller Control Current ED Register 268 * --------------------------------------------------------------------------------------------------- 269 * |Bits |Field |Descriptions 270 * | :----: | :----: | :---- | 271 * |[31:4] |CCED |Control Current Head ED 272 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. 273 * @var USBH_T::HcBulkHeadED 274 * Offset: 0x28 Host Controller Bulk Head ED Register 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[31:4] |BHED |Bulk Head ED 279 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. 280 * @var USBH_T::HcBulkCurrentED 281 * Offset: 0x2C Host Controller Bulk Current ED Register 282 * --------------------------------------------------------------------------------------------------- 283 * |Bits |Field |Descriptions 284 * | :----: | :----: | :---- | 285 * |[31:4] |BCED |Bulk Current Head ED 286 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Bulk list. 287 * @var USBH_T::HcDoneHead 288 * Offset: 0x30 Host Controller Done Head Register 289 * --------------------------------------------------------------------------------------------------- 290 * |Bits |Field |Descriptions 291 * | :----: | :----: | :---- | 292 * |[31:4] |DH |Done Head 293 * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. 294 * @var USBH_T::HcFmInterval 295 * Offset: 0x34 Host Controller Frame Interval Register 296 * --------------------------------------------------------------------------------------------------- 297 * |Bits |Field |Descriptions 298 * | :----: | :----: | :---- | 299 * |[13:0] |FI |Frame Interval 300 * | | |This field specifies the length of a frame as (bit times - 1) 301 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. 302 * |[29:16] |FSMPS |FS Largest Data Packet 303 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. 304 * |[31] |FIT |Frame Interval Toggle 305 * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). 306 * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). 307 * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). 308 * @var USBH_T::HcFmRemaining 309 * Offset: 0x38 Host Controller Frame Remaining Register 310 * --------------------------------------------------------------------------------------------------- 311 * |Bits |Field |Descriptions 312 * | :----: | :----: | :---- | 313 * |[13:0] |FR |Frame Remaining 314 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period 315 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval 316 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. 317 * |[31] |FRT |Frame Remaining Toggle 318 * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. 319 * @var USBH_T::HcFmNumber 320 * Offset: 0x3C Host Controller Frame Number Register 321 * --------------------------------------------------------------------------------------------------- 322 * |Bits |Field |Descriptions 323 * | :----: | :----: | :---- | 324 * |[15:0] |FN |Frame Number 325 * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) 326 * | | |The count rolls over from 'FFFFh' to '0h' 327 * @var USBH_T::HcPeriodicStart 328 * Offset: 0x40 Host Controller Periodic Start Register 329 * --------------------------------------------------------------------------------------------------- 330 * |Bits |Field |Descriptions 331 * | :----: | :----: | :---- | 332 * |[13:0] |PS |Periodic Start 333 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. 334 * @var USBH_T::HcLSThreshold 335 * Offset: 0x44 Host Controller Low-speed Threshold Register 336 * --------------------------------------------------------------------------------------------------- 337 * |Bits |Field |Descriptions 338 * | :----: | :----: | :---- | 339 * |[11:0] |LST |Low-speed Threshold 340 * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction 341 * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field 342 * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. 343 * @var USBH_T::HcRhDescriptorA 344 * Offset: 0x48 Host Controller Root Hub Descriptor A Register 345 * --------------------------------------------------------------------------------------------------- 346 * |Bits |Field |Descriptions 347 * | :----: | :----: | :---- | 348 * |[7:0] |NDP |Number Downstream Ports 349 * | | |USB host control supports two downstream ports and only one port is available in this series of chip. 350 * | | |Note: NDP = 1 in this series of chip. 351 * |[8] |PSM |Power Switching Mode 352 * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. 353 * | | |0 = Global switching. 354 * | | |1 = Individual switching. 355 * |[11] |OCPM |Overcurrent Protection Mode 356 * | | |This bit describes how the overcurrent status for the Root Hub ports reported 357 * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. 358 * | | |0 = Global overcurrent. 359 * | | |1 = Individual overcurrent. 360 * |[12] |NOCP |No Overcurrent Protection 361 * | | |This bit describes how the overcurrent status for the Root Hub ports reported. 362 * | | |0 = Overcurrent status is reported. 363 * | | |1 = Overcurrent status is not reported. 364 * @var USBH_T::HcRhDescriptorB 365 * Offset: 0x4C Host Controller Root Hub Descriptor B Register 366 * --------------------------------------------------------------------------------------------------- 367 * |Bits |Field |Descriptions 368 * | :----: | :----: | :---- | 369 * |[31:16] |PPCM |Port Power Control Mask 370 * | | |Global power switching 371 * | | |This field is only valid if Power Switching Mode is set (individual port switching) 372 * | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power) 373 * | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power). 374 * | | |0 = Port power controlled by global power switching. 375 * | | |1 = Port power controlled by port power switching. 376 * | | |Note: PPCM[15:2] and PPCM[0] are reserved. 377 * @var USBH_T::HcRhStatus 378 * Offset: 0x50 Host Controller Root Hub Status Register 379 * --------------------------------------------------------------------------------------------------- 380 * |Bits |Field |Descriptions 381 * | :----: | :----: | :---- | 382 * |[0] |LPS |Clear Global Power 383 * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. 384 * | | |This bit is always read as 0. 385 * | | |Write Operation: 386 * | | |0 = No effect. 387 * | | |1 = Clear global power. 388 * |[1] |OCI |Overcurrent Indicator (Read Only) 389 * | | |This bit reflects the state of the overcurrent status pin 390 * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared. 391 * | | |0 = No overcurrent condition. 392 * | | |1 = Overcurrent condition. 393 * |[15] |DRWE |Device Remote Wakeup Enable Bit 394 * | | |This bit controls if port's Connect Status Change as a remote wake-up event. 395 * | | |Write Operation: 396 * | | |0 = No effect. 397 * | | |1 = Connect Status Change as a remote wake-up event Enabled. 398 * | | |Read Operation: 399 * | | |0 = Connect Status Change as a remote wake-up event Disabled. 400 * | | |1 = Connect Status Change as a remote wake-up event Enabled. 401 * |[16] |LPSC |Set Global Power 402 * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. 403 * | | |This bit is always read as 0. 404 * | | |Write Operation: 405 * | | |0 = No effect. 406 * | | |1 = Set global power. 407 * |[17] |OCIC |Overcurrent Indicator Change 408 * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). 409 * | | |Write 1 to clear this bit to 0. 410 * | | |0 = OCI (HcRhStatus[1]) didn't change. 411 * | | |1 = OCI (HcRhStatus[1]) changed. 412 * |[31] |CRWE |Clear Remote Wake-up Enable Bit 413 * | | |This bit is use to clear DRWE (HcRhStatus[15]). 414 * | | |This bit is always read as 0. 415 * | | |Write Operation: 416 * | | |0 = No effect. 417 * | | |1 = Clear DRWE (HcRhStatus[15]). 418 * @var USBH_T::HcRhPortStatus1 419 * Offset: 0x58 Host Controller Root Hub Port Status [1] 420 * --------------------------------------------------------------------------------------------------- 421 * |Bits |Field |Descriptions 422 * | :----: | :----: | :---- | 423 * |[0] |CCS |Current Connect Status 424 * | | |Write Operation: 425 * | | |0 = No effect. 426 * | | |1 = Clear port enable. 427 * | | |Read Operation: 428 * | | |0 = No device connected. 429 * | | |1 = Device connected. 430 * |[1] |PES |Port Enable Status 431 * | | |Write Operation: 432 * | | |0 = No effect. 433 * | | |1 = Set port enable. 434 * | | |Read Operation: 435 * | | |0 = Port Disabled. 436 * | | |1 = Port Enabled. 437 * |[2] |PSS |Port Suspend Status 438 * | | |This bit indicates the port is suspended 439 * | | |Write Operation: 440 * | | |0 = No effect. 441 * | | |1 = Set port suspend. 442 * | | |Read Operation: 443 * | | |0 = Port is not suspended. 444 * | | |1 = Port is selectively suspended. 445 * |[3] |POCI |Port Overcurrent Indicator 446 * | | |This bit reflects the state of the overcurrent status pin dedicated to this port 447 * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. 448 * | | |This bit is also used to initiate the selective result sequence for the port. 449 * | | |Write Operation: 450 * | | |0 = No effect. 451 * | | |1 = Clear port suspend. 452 * | | |Read Operation: 453 * | | |0 = No overcurrent condition. 454 * | | |1 = Overcurrent condition. 455 * |[4] |PRS |Port Reset Status 456 * | | |This bit reflects the reset state of the port. 457 * | | |Write Operation: 458 * | | |0 = No effect. 459 * | | |1 = Set port reset. 460 * | | |Read Operation 461 * | | |0 = Port reset signal is not active. 462 * | | |1 = Port reset signal is active. 463 * |[8] |PPS |Port Power Status 464 * | | |This bit reflects the power state of the port regardless of the power switching mode. 465 * | | |Write Operation: 466 * | | |0 = No effect. 467 * | | |1 = Port Power Enabled. 468 * | | |Read Operation: 469 * | | |0 = Port power is Disabled. 470 * | | |1 = Port power is Enabled. 471 * |[9] |LSDA |Low Speed Device Attached 472 * | | |This bit defines the speed (and bus idle) of the attached device 473 * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. 474 * | | |This bit is also used to clear port power. 475 * | | |Write Operation: 476 * | | |0 = No effect. 477 * | | |1 = Clear PPS (HcRhPortStatus1[8]). 478 * | | |Read Operation: 479 * | | |0 = Full Speed device. 480 * | | |1 = Low-speed device. 481 * |[16] |CSC |Connect Status Change 482 * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). 483 * | | |Write 1 to clear this bit to 0. 484 * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). 485 * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). 486 * |[17] |PESC |Port Enable Status Change 487 * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. 488 * | | |Write 1 to clear this bit to 0. 489 * | | |0 = PES (HcRhPortStatus1[1]) didn't change. 490 * | | |1 = PES (HcRhPortStatus1[1]) changed. 491 * |[18] |PSSC |Port Suspend Status Change 492 * | | |This bit indicates the completion of the selective resume sequence for the port. 493 * | | |Write 1 to clear this bit to 0. 494 * | | |0 = Port resume is not complete. 495 * | | |1 = Port resume is complete. 496 * |[19] |OCIC |Port Overcurrent Indicator Change 497 * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. 498 * | | |Write 1 to clear this bit to 0. 499 * | | |0 = POCI (HcRhPortStatus1[3]) didn't change. 500 * | | |1 = POCI (HcRhPortStatus1[3]) changed. 501 * |[20] |PRSC |Port Reset Status Change 502 * | | |This bit indicates that the port reset signal has completed. 503 * | | |Write 1 to clear this bit to 0. 504 * | | |0 = Port reset is not complete. 505 * | | |1 = Port reset is complete. 506 * @var USBH_T::HcPhyControl 507 * Offset: 0x200 Host Controller PHY Control Register 508 * --------------------------------------------------------------------------------------------------- 509 * |Bits |Field |Descriptions 510 * | :----: | :----: | :---- | 511 * |[27] |STBYEN |USB Transceiver Standby Enable Bit 512 * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. 513 * | | |0 = The USB transceiver would never enter the standby mode. 514 * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). 515 * @var USBH_T::HcMiscControl 516 * Offset: 0x204 Host Controller Miscellaneous Control Register 517 * --------------------------------------------------------------------------------------------------- 518 * |Bits |Field |Descriptions 519 * | :----: | :----: | :---- | 520 * |[1] |ABORT |AHB Bus Error Response 521 * | | |This bit indicates there is an Error response received in AHB bus. 522 * | | |0 = No Error response received. 523 * | | |1 = Error response received. 524 * | | |Note: This bit is cleared by writing 1 to it. 525 * |[3] |OCAL |Overcurrent Active Low 526 * | | |This bit controls the polarity of overcurrent flag from external power IC. 527 * | | |0 = Overcurrent flag is high active. 528 * | | |1 = Overcurrent flag is low active. 529 * |[4] |PPCAL |Port Power Control Active Low 530 * | | |This bit controls the polarity of port power control to external power IC. 531 * | | |0 = Port power control is high active. 532 * | | |1 = Port power control is low active. 533 * |[16] |DPRT1 |Disable Port 1 534 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled 535 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. 536 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. 537 * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. 538 * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. 539 */ 540 __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ 541 __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ 542 __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ 543 __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ 544 __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ 545 __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ 546 __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ 547 __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ 548 __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ 549 __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ 550 __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ 551 __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ 552 __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ 553 __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ 554 __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ 555 __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ 556 __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ 557 __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ 558 __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ 559 __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ 560 __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ 561 __I uint32_t RESERVE0[1]; 562 __IO uint32_t HcRhPortStatus1; /*!< [0x0058] Host Controller Root Hub Port Status [1] */ 563 __I uint32_t RESERVE1[105]; 564 __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ 565 __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ 566 567 } USBH_T; 568 569 /** 570 @addtogroup USBH_CONST USBH Bit Field Definition 571 Constant Definitions for USBH Controller 572 @{ */ 573 574 #define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ 575 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ 576 577 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ 578 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ 579 580 #define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ 581 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ 582 583 #define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ 584 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ 585 586 #define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ 587 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ 588 589 #define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ 590 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ 591 592 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ 593 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ 594 595 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ 596 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ 597 598 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ 599 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ 600 601 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ 602 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ 603 604 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ 605 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ 606 607 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ 608 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ 609 610 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ 611 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ 612 613 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ 614 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ 615 616 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ 617 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ 618 619 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ 620 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ 621 622 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ 623 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ 624 625 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ 626 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ 627 628 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ 629 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ 630 631 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ 632 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ 633 634 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ 635 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ 636 637 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ 638 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ 639 640 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ 641 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ 642 643 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ 644 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ 645 646 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ 647 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ 648 649 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ 650 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ 651 652 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ 653 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ 654 655 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ 656 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ 657 658 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ 659 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ 660 661 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ 662 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ 663 664 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ 665 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ 666 667 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ 668 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ 669 670 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ 671 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ 672 673 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ 674 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ 675 676 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ 677 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ 678 679 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ 680 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ 681 682 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ 683 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ 684 685 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ 686 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ 687 688 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ 689 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ 690 691 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ 692 #define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ 693 694 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ 695 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ 696 697 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ 698 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ 699 700 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ 701 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ 702 703 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ 704 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ 705 706 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ 707 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ 708 709 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ 710 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ 711 712 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ 713 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ 714 715 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ 716 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ 717 718 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ 719 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ 720 721 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ 722 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ 723 724 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ 725 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ 726 727 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ 728 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ 729 730 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ 731 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ 732 733 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ 734 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ 735 736 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ 737 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ 738 739 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ 740 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ 741 742 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ 743 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ 744 745 #define USBH_HcRhPortStatus1_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ 746 #define USBH_HcRhPortStatus1_CCS_Msk (0x1ul << USBH_HcRhPortStatus1_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ 747 748 #define USBH_HcRhPortStatus1_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ 749 #define USBH_HcRhPortStatus1_PES_Msk (0x1ul << USBH_HcRhPortStatus1_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ 750 751 #define USBH_HcRhPortStatus1_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ 752 #define USBH_HcRhPortStatus1_PSS_Msk (0x1ul << USBH_HcRhPortStatus1_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ 753 754 #define USBH_HcRhPortStatus1_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ 755 #define USBH_HcRhPortStatus1_POCI_Msk (0x1ul << USBH_HcRhPortStatus1_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ 756 757 #define USBH_HcRhPortStatus1_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ 758 #define USBH_HcRhPortStatus1_PRS_Msk (0x1ul << USBH_HcRhPortStatus1_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ 759 760 #define USBH_HcRhPortStatus1_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ 761 #define USBH_HcRhPortStatus1_PPS_Msk (0x1ul << USBH_HcRhPortStatus1_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ 762 763 #define USBH_HcRhPortStatus1_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ 764 #define USBH_HcRhPortStatus1_LSDA_Msk (0x1ul << USBH_HcRhPortStatus1_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ 765 766 #define USBH_HcRhPortStatus1_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ 767 #define USBH_HcRhPortStatus1_CSC_Msk (0x1ul << USBH_HcRhPortStatus1_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ 768 769 #define USBH_HcRhPortStatus1_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ 770 #define USBH_HcRhPortStatus1_PESC_Msk (0x1ul << USBH_HcRhPortStatus1_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ 771 772 #define USBH_HcRhPortStatus1_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ 773 #define USBH_HcRhPortStatus1_PSSC_Msk (0x1ul << USBH_HcRhPortStatus1_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ 774 775 #define USBH_HcRhPortStatus1_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ 776 #define USBH_HcRhPortStatus1_OCIC_Msk (0x1ul << USBH_HcRhPortStatus1_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ 777 778 #define USBH_HcRhPortStatus1_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ 779 #define USBH_HcRhPortStatus1_PRSC_Msk (0x1ul << USBH_HcRhPortStatus1_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ 780 781 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ 782 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ 783 784 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ 785 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ 786 787 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ 788 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ 789 790 #define USBH_HcMiscControl_PPCAL_Pos (4) /*!< USBH_T::HcMiscControl: PPCAL Position */ 791 #define USBH_HcMiscControl_PPCAL_Msk (0x1ul << USBH_HcMiscControl_PPCAL_Pos) /*!< USBH_T::HcMiscControl: PPCAL Mask */ 792 793 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ 794 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ 795 796 /**@}*/ /* USBH_CONST */ 797 /**@}*/ /* end of USBH register group */ 798 799 800 /**@}*/ /* end of REGISTER group */ 801
