1 /**************************************************************************//** 2 * @file ttmr_reg.h 3 * @version V1.00 4 * @brief TTMR register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TTMR_REG_H__ 10 #define __TTMR_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup TTMR Tick Timer Controller (TTMR) 23 Memory Mapped Structure for TTMR Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var TTMR_T::CTL 32 * Offset: 0x00 TTMR Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |PSC |Prescale Counter 37 * | | |Tick Timer input clock or event source is divided by (PSC+1) before it is fed to the tick timer up counter. 38 * | | |If this field is 0 (PSC = 0), then there is no scaling. 39 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 40 * |[16] |PDCLKEN |Power-down Engine Clock Enable 41 * | | |0 = Disable engine clock in Power-down mode. 42 * | | |1 = Enable engine clock in Power-down mode. 43 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit 44 * | | |0 = The behavior selection in periodic mode is Disabled. 45 * | | |When user updates CMPDAT while timer is running in periodic mode, 46 * | | |CNT will be reset to default value. 47 * | | |1 = The behavior selection in periodic mode is Enabled. 48 * | | |When user updates CMPDAT while timer is running in periodic mode, the limitations as bellows list, 49 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. 50 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. 51 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. 52 * |[23] |WKEN |Wake-up Function Enable Bit 53 * | | |If this bit is set to 1, while timer interrupt flag TIF (TTMRx_INTSTS[0]) is 1 and INTEN (TTMRx_CTL[29]) is enabled, the tick timer interrupt signal will generate a wake-up trigger event to CPU. 54 * | | |0 = Wake-up function Disabled if timer interrupt signal generated. 55 * | | |1 = Wake-up function Enabled if timer interrupt signal generated. 56 * |[25] |ACTSTS |Tick Timer Active Status Bit (Read Only) 57 * | | |This bit indicates the 24-bit up counter status. 58 * | | |0 = 24-bit up counter is not active. 59 * | | |1 = 24-bit up counter is active. 60 * | | |Note: This bit may be active when CNT 0 is transitioned to CNT 1. 61 * |[28:27] |OPMODE |Tick Timer Counting Mode Select 62 * | | |00 = Tick timer controller is operated in One-shot mode. 63 * | | |01 = Tick timer controller is operated in Periodic mode. 64 * | | |11 = Tick timer controller is operated in Continuous Counting mode. 65 * |[29] |INTEN |Tick Timer Interrupt Enable Bit 66 * | | |0 = Tick Timer time-out interrupt Disabled. 67 * | | |1 = Tick Timer time-out interrupt Enabled. 68 * | | |Note: If this bit is enabled, when the tick timer time-out interrupt flag TIF is set to 1, the tick timer interrupt signal is generated and inform to CPU. 69 * |[30] |CNTEN |Tick Timer Counting Enable Bit 70 * | | |0 = Stops/Suspends counting. 71 * | | |1 = Starts counting. 72 * | | |Note 1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. 73 * | | |Note 2: This bit is auto-cleared by hardware in one-shot mode (TTMR_CTL[28:27] = 00) when the tick timer time-out interrupt flag TIF (TTMRx_INTSTS[0]) is generated. 74 * | | |Note 3: Set enable/disable this bit needs 2 * TTMR_CLK period to become active, user can read ACTSTS (TTMRx_CTL[25]) to check enable/disable command is completed or not. 75 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 76 * | | |0 = ICE debug mode acknowledgement effects TTMR counting. 77 * | | |TTMR counter will be held while CPU is held by ICE. 78 * | | |1 = ICE debug mode acknowledgement Disabled. 79 * | | |TTMR counter will keep going no matter CPU is held by ICE or not. 80 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 81 * @var TTMR_T::CMP 82 * Offset: 0x04 TTMR Comparator Register 83 * --------------------------------------------------------------------------------------------------- 84 * |Bits |Field |Descriptions 85 * | :----: | :----: | :---- | 86 * |[23:0] |CMPDAT |Tick Timer Comparator Value 87 * | | |CMPDAT is a 24-bit compared value register 88 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TTMRx_INTSTS[0] Tick Timer Interrupt Flag) will set to 1. 89 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). 90 * | | |Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. 91 * | | |Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field 92 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the tick timer compared value while user writes a new value into CMPDAT field. 93 * @var TTMR_T::INTSTS 94 * Offset: 0x08 TTMR Interrupt Status Register 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[0] |TIF |Tick Timer Interrupt Flag 99 * | | |This bit indicates the interrupt flag status of Tick Timer while 24-bit timer up counter CNT (TTMRx_CNT[23:0]) value reaches to CMPDAT (TTMRx_CMP[23:0]) value. 100 * | | |0 = No effect. 101 * | | |1 = CNT value matches the CMPDAT value. 102 * | | |Note: This bit is cleared by writing 1 to it. 103 * |[1] |TWKF |Tick Timer Wake-up Flag 104 * | | |This bit indicates the interrupt wake-up flag status of timer. 105 * | | |0 = Tick Timer does not cause CPU wake-up. 106 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. 107 * | | |Note: This bit is cleared by writing 1 to it. 108 * @var TTMR_T::CNT 109 * Offset: 0x0C TTMR Data Register 110 * --------------------------------------------------------------------------------------------------- 111 * |Bits |Field |Descriptions 112 * | :----: | :----: | :---- | 113 * |[23:0] |CNT |Tick Timer Data Register 114 * | | |Read operation: 115 * | | |Read this register to get CNT value. For example: 116 * | | |Write operation: 117 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 118 * |[31] |RSTACT |Tick Timer Data Register Reset Active (Read Only) 119 * | | |This bit indicates if the counter reset operation active. 120 * | | |When user writes this CNT register, tick timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter 121 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress 122 * | | |Once the counter reset operation done, tick timer clear this bit to 0 automatically. 123 * | | |0 = Reset operation is done. 124 * | | |1 = Reset operation triggered by writing TTMRx_CNT is in progress. 125 * @var TTMR_T::TRGCTL 126 * Offset: 0x1C TTMR Trigger Control Register 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[1] |TRGEN |Trigger Low power IPs Enable Bit 131 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered Low Power IPs conversion. 132 * | | |0 = Tick Timer interrupt trigger Low Power IPs Disabled. 133 * | | |1 = Tick Timer interrupt trigger Low Power IPs Enabled. 134 * |[4] |TRGLPPDMA |Trigger LPPDMA Enable Bit 135 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered LPPDMA transfer. 136 * | | |0 = Tick Timer interrupt trigger LPPDMA Disabled. 137 * | | |1 = Tick Timer interrupt trigger LPPDMA Enabled. 138 */ 139 __IO uint32_t CTL; /*!< [0x0000] TTMR Control Register */ 140 __IO uint32_t CMP; /*!< [0x0004] TTMR Comparator Register */ 141 __IO uint32_t INTSTS; /*!< [0x0008] TTMR Interrupt Status Register */ 142 __IO uint32_t CNT; /*!< [0x000c] TTMR Data Register */ 143 __I uint32_t RESERVE0[3]; 144 __IO uint32_t TRGCTL; /*!< [0x001c] TTMR Trigger Control Register */ 145 146 } TTMR_T; 147 148 /** 149 @addtogroup TTMR_CONST TTMR Bit Field Definition 150 Constant Definitions for TTMR Controller 151 @{ */ 152 153 #define TTMR_CTL_PSC_Pos (0) /*!< TTMR_T::CTL: PSC Position */ 154 #define TTMR_CTL_PSC_Msk (0xfful << TTMR_CTL_PSC_Pos) /*!< TTMR_T::CTL: PSC Mask */ 155 156 #define TTMR_CTL_PDCLKEN_Pos (16) /*!< TTMR_T::CTL: PDCLKEN Position */ 157 #define TTMR_CTL_PDCLKEN_Msk (0x1uL << TTMR_CTL_PDCLKEN_Pos) /*!< TTMR_T::CTL: PDCLKEN Mask */ 158 159 #define TTMR_CTL_PERIOSEL_Pos (20) /*!< TTMR_T::CTL: PERIOSEL Position */ 160 #define TTMR_CTL_PERIOSEL_Msk (0x1ul << TTMR_CTL_PERIOSEL_Pos) /*!< TTMR_T::CTL: PERIOSEL Mask */ 161 162 #define TTMR_CTL_WKEN_Pos (23) /*!< TTMR_T::CTL: WKEN Position */ 163 #define TTMR_CTL_WKEN_Msk (0x1ul << TTMR_CTL_WKEN_Pos) /*!< TTMR_T::CTL: WKEN Mask */ 164 165 #define TTMR_CTL_ACTSTS_Pos (25) /*!< TTMR_T::CTL: ACTSTS Position */ 166 #define TTMR_CTL_ACTSTS_Msk (0x1ul << TTMR_CTL_ACTSTS_Pos) /*!< TTMR_T::CTL: ACTSTS Mask */ 167 168 #define TTMR_CTL_OPMODE_Pos (27) /*!< TTMR_T::CTL: OPMODE Position */ 169 #define TTMR_CTL_OPMODE_Msk (0x3ul << TTMR_CTL_OPMODE_Pos) /*!< TTMR_T::CTL: OPMODE Mask */ 170 171 #define TTMR_CTL_INTEN_Pos (29) /*!< TTMR_T::CTL: INTEN Position */ 172 #define TTMR_CTL_INTEN_Msk (0x1ul << TTMR_CTL_INTEN_Pos) /*!< TTMR_T::CTL: INTEN Mask */ 173 174 #define TTMR_CTL_CNTEN_Pos (30) /*!< TTMR_T::CTL: CNTEN Position */ 175 #define TTMR_CTL_CNTEN_Msk (0x1ul << TTMR_CTL_CNTEN_Pos) /*!< TTMR_T::CTL: CNTEN Mask */ 176 177 #define TTMR_CTL_ICEDEBUG_Pos (31) /*!< TTMR_T::CTL: ICEDEBUG Position */ 178 #define TTMR_CTL_ICEDEBUG_Msk (0x1ul << TTMR_CTL_ICEDEBUG_Pos) /*!< TTMR_T::CTL: ICEDEBUG Mask */ 179 180 #define TTMR_CMP_CMPDAT_Pos (0) /*!< TTMR_T::CMP: CMPDAT Position */ 181 #define TTMR_CMP_CMPDAT_Msk (0xfffffful << TTMR_CMP_CMPDAT_Pos) /*!< TTMR_T::CMP: CMPDAT Mask */ 182 183 #define TTMR_INTSTS_TIF_Pos (0) /*!< TTMR_T::INTSTS: TIF Position */ 184 #define TTMR_INTSTS_TIF_Msk (0x1ul << TTMR_INTSTS_TIF_Pos) /*!< TTMR_T::INTSTS: TIF Mask */ 185 186 #define TTMR_INTSTS_TWKF_Pos (1) /*!< TTMR_T::INTSTS: TWKF Position */ 187 #define TTMR_INTSTS_TWKF_Msk (0x1ul << TTMR_INTSTS_TWKF_Pos) /*!< TTMR_T::INTSTS: TWKF Mask */ 188 189 #define TTMR_CNT_CNT_Pos (0) /*!< TTMR_T::CNT: CNT Position */ 190 #define TTMR_CNT_CNT_Msk (0xfffffful << TTMR_CNT_CNT_Pos) /*!< TTMR_T::CNT: CNT Mask */ 191 192 #define TTMR_CNT_RSTACT_Pos (31) /*!< TTMR_T::CNT: RSTACT Position */ 193 #define TTMR_CNT_RSTACT_Msk (0x1ul << TTMR_CNT_RSTACT_Pos) /*!< TTMR_T::CNT: RSTACT Mask */ 194 195 #define TTMR_TRGCTL_TRGEN_Pos (1) /*!< TTMR_T::TRGCTL: TRGEN Position */ 196 #define TTMR_TRGCTL_TRGEN_Msk (0x1ul << TTMR_TRGCTL_TRGEN_Pos) /*!< TTMR_T::TRGCTL: TRGEN Mask */ 197 198 #define TTMR_TRGCTL_TRGLPPDMA_Pos (4) /*!< TTMR_T::TRGCTL: TRGLPPDMA Position */ 199 #define TTMR_TRGCTL_TRGLPPDMA_Msk (0x1ul << TTMR_TRGCTL_TRGLPPDMA_Pos) /*!< TTMR_T::TRGCTL: TRGLPPDMA Mask */ 200 201 /**@}*/ /* TTMR_CONST */ 202 /**@}*/ /* end of TTMR register group */ 203 /**@}*/ /* end of REGISTER group */ 204 205 #if defined ( __CC_ARM ) 206 #pragma no_anon_unions 207 #endif 208 209 #endif /* __TTMR_REG_H__ */ 210
