1 /**************************************************************************//** 2 * @file spi_reg.h 3 * @version V1.00 4 * @brief SPI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 * 9 *****************************************************************************/ 10 #ifndef __SPI_REG_H__ 11 #define __SPI_REG_H__ 12 13 #if defined ( __CC_ARM ) 14 #pragma anon_unions 15 #endif 16 17 /** 18 @addtogroup REGISTER Control Register 19 @{ 20 */ 21 22 /** 23 @addtogroup SPI Serial Peripheral Interface Controller(SPI) 24 Memory Mapped Structure for SPI Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var SPI_T::CTL 33 * Offset: 0x00 SPI Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |SPIEN |SPI Transfer Control Enable Bit 38 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 39 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 40 * | | |0 = Transfer control Disabled. 41 * | | |1 = Transfer control Enabled. 42 * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 43 * |[1] |RXNEG |Receive on Negative Edge 44 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. 45 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. 46 * |[2] |TXNEG |Transmit on Negative Edge 47 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. 48 * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. 49 * |[3] |CLKPOL |Clock Polarity 50 * | | |0 = SPI bus clock is idle low. 51 * | | |1 = SPI bus clock is idle high. 52 * |[7:4] |SUSPITV |Suspend Interval 53 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer 54 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 55 * | | |The default value is 0x3 56 * | | |The period of the suspend interval is obtained according to the following equation. 57 * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle 58 * | | |Example: 59 * | | |SUSPITV = 0x0, it means 0.5 SPI_CLK clock cycle. 60 * | | |SUSPITV = 0x1, it means 1.5 SPI_CLK clock cycle. 61 * | | | ... 62 * | | |SUSPITV = 0xE, it means 14.5 SPI_CLK clock cycle. 63 * | | |SUSPITV = 0xF, it means 15.5 SPI_CLK clock cycle. 64 * |[12:8] |DWIDTH |Data Width 65 * | | |This field specifies how many bits can be transmitted/received in one transaction 66 * | | |The minimum bit length is 4 bits and can up to 32 bits. 67 * | | |DWIDTH = 0x04, it means 4 bits. 68 * | | |DWIDTH = 0x05, it means 5 bits. 69 * | | |DWIDTH = 0x06, it means 6 bits. 70 * | | |DWIDTH = 0x07, it means 7 bits. 71 * | | |DWIDTH = 0x08, it means 8 bits. 72 * | | |DWIDTH = 0x09, it means 9 bits. 73 * | | | ... 74 * | | |DWIDTH = 0x1F, it means 31 bits. 75 * | | |DWIDTH = 0x00, it means 32 bits. 76 * | | |Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode 77 * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 78 * |[13] |LSB |Send LSB First 79 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 80 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). 81 * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit 82 * | | |This bit is used to select full-duplex or half-duplex for SPI transfer 83 * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 84 * | | |0 = SPI operates in full-duplex transfer. 85 * | | |1 = SPI operates in half-duplex transfer. 86 * |[15] |RXONLY |Receive-only Mode Enable Bit 87 * | | |This bit field is only available in Master mode 88 * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 89 * | | |0 = Receive-only mode Disabled. 90 * | | |1 = Receive-only mode Enabled. 91 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 92 * | | |0 = SPI unit transfer interrupt Disabled. 93 * | | |1 = SPI unit transfer interrupt Enabled. 94 * |[18] |SLAVE |Slave Mode Control 95 * | | |0 = Master mode. 96 * | | |1 = Slave mode. 97 * |[19] |REORDER |Byte Reorder Function Enable Bit 98 * | | |0 = Byte Reorder function Disabled. 99 * | | |1 = Byte Reorder function Enabled 100 * | | |A byte suspend interval will be inserted among each byte 101 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 102 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 103 * |[20] |DATDIR |Data Port Direction Control 104 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 105 * | | |0 = SPI data is input direction. 106 * | | |1 = SPI data is output direction. 107 * @var SPI_T::CLKDIV 108 * Offset: 0x04 SPI Clock Divider Register 109 * --------------------------------------------------------------------------------------------------- 110 * |Bits |Field |Descriptions 111 * | :----: | :----: | :---- | 112 * |[8:0] |DIVIDER |Clock Divider 113 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master 114 * | | |The frequency is obtained according to the following equation. 115 * | | | SPI_eclk = SPI_clk_src/(DIVIDER+1) 116 * | | |where 117 * | | |SPI_clk_src is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2 or CLK_CLKSEL3. 118 * | | |Note 1: Not supported in I2S mode. 119 * | | |Note 2: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 120 * @var SPI_T::SSCTL 121 * Offset: 0x08 SPI Slave Select Control Register 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[0] |SS |Slave Selection Control 126 * | | |If AUTOSS bit is cleared to 0, 127 * | | |0 = set the SPIx_SS line to inactive state. 128 * | | |1 = set the SPIx_SS line to active state. 129 * | | |If the AUTOSS bit is set to 1, 130 * | | |0 = Keep the SPIx_SS line at inactive state. 131 * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 132 * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) 133 * | | |Note: It is Master Only 134 * |[2] |SSACTPOL |Slave Selection Active Polarity 135 * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). 136 * | | |0 = The slave selection signal SPIx_SS is active low. 137 * | | |1 = The slave selection signal SPIx_SS is active high. 138 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit 139 * | | |0 = Automatic slave selection function Disabled 140 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). 141 * | | |1 = Automatic slave selection function Enabled (Master Only). 142 * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit 143 * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. 144 * | | |0 = 4-wire bi-direction interface. 145 * | | |1 = 3-wire bi-direction interface. 146 * | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled in SPI Slave mode Only. 147 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 148 * | | |0 = Slave mode bit count error interrupt Disabled. 149 * | | |1 = Slave mode bit count error interrupt Enabled. 150 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 151 * | | |0 = Slave mode TX under run interrupt Disabled. 152 * | | |1 = Slave mode TX under run interrupt Enabled. 153 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 154 * | | |0 = Slave select active interrupt Disabled. 155 * | | |1 = Slave select active interrupt Enabled. 156 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 157 * | | |0 = Slave select inactive interrupt Disabled. 158 * | | |1 = Slave select inactive interrupt Enabled. 159 * @var SPI_T::PDMACTL 160 * Offset: 0x0C SPI PDMA Control Register 161 * --------------------------------------------------------------------------------------------------- 162 * |Bits |Field |Descriptions 163 * | :----: | :----: | :---- | 164 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 165 * | | |0 = Transmit PDMA function Disabled. 166 * | | |1 = Transmit PDMA function Enabled. 167 * | | |Note 1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 168 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 169 * | | |Note 2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function 170 * | | |User can disable RX PDMA function firstly or disable both functions simultaneously. 171 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 172 * | | |0 = Receive PDMA function Disabled. 173 * | | |1 = Receive PDMA function Enabled. 174 * |[2] |PDMARST |PDMA Reset 175 * | | |0 = No effect. 176 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. 177 * @var SPI_T::FIFOCTL 178 * Offset: 0x10 SPI FIFO Control Register 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[0] |RXRST |Receive Reset 183 * | | |0 = No effect. 184 * | | |1 = Reset receive FIFO pointer and receive circuit 185 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 186 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 187 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 188 * |[1] |TXRST |Transmit Reset 189 * | | |0 = No effect. 190 * | | |1 = Reset transmit FIFO pointer and transmit circuit 191 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 192 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 193 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 194 * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 195 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 196 * | | |0 = RX FIFO threshold interrupt Disabled. 197 * | | |1 = RX FIFO threshold interrupt Enabled. 198 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 199 * | | |0 = TX FIFO threshold interrupt Disabled. 200 * | | |1 = TX FIFO threshold interrupt Enabled. 201 * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit 202 * | | |0 = Receive time-out interrupt Disabled. 203 * | | |1 = Receive time-out interrupt Enabled. 204 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 205 * | | |0 = Receive FIFO overrun interrupt Disabled. 206 * | | |1 = Receive FIFO overrun interrupt Enabled. 207 * |[6] |TXUFPOL |TX Underflow Data Polarity 208 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 209 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. 210 * | | |Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 211 * | | |Note 2: This bit should be set as 0 in I2S mode. 212 * | | |Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 213 * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 214 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 215 * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 216 * | | |This bit is used to enable the TX underflow interrupt. 217 * | | |0 = Slave TX underflow interrupt Disabled. 218 * | | |1 = Slave TX underflow interrupt Enabled. 219 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 220 * | | |0 = No effect. 221 * | | |1 = Clear receive FIFO pointer 222 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 223 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 224 * | | |Note: The RX shift register will not be cleared. 225 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 226 * | | |0 = No effect. 227 * | | |1 = Clear transmit FIFO pointer 228 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 229 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 230 * | | |Note: The TX shift register will not be cleared. 231 * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error 232 * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. 233 * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode 234 * | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened 235 * | | |(SPI Slave mode Only) 236 * |[26:24] |RXTH |Receive FIFO Threshold 237 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 238 * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 239 * |[30:28] |TXTH |Transmit FIFO Threshold 240 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 241 * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length 242 * @var SPI_T::STATUS 243 * Offset: 0x14 SPI Status Register 244 * --------------------------------------------------------------------------------------------------- 245 * |Bits |Field |Descriptions 246 * | :----: | :----: | :---- | 247 * |[0] |BUSY |Busy Status (Read Only) 248 * | | |0 = SPI controller is in idle state. 249 * | | |1 = SPI controller is in busy state. 250 * | | |The following lists the bus busy conditions: 251 * | | |a. SPIEN (SPIx_CTL[0]) = 1 and TXEMPTY = 0. 252 * | | |b 253 * | | |For SPI Master mode, SPIEN (SPIx_CTL[0]) = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 254 * | | |c. For SPI Master mode, SPIEN (SPIx_CTL[0]) = 1 and RXONLY = 1. 255 * | | |d 256 * | | |For SPI Slave mode, SPIEN (SPIx_CTL[0]) = 1 and there is serial clock input into the SPI core logic when slave select is active. 257 * | | |e 258 * | | |For SPI Slave mode, SPIEN (SPIx_CTL[0]) = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 259 * | | |Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF 260 * | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. 261 * |[1] |UNITIF |Unit Transfer Interrupt Flag 262 * | | |0 = No transaction has been finished since this bit was cleared to 0. 263 * | | |1 = SPI controller has finished one unit transfer. 264 * | | |Note: This bit will be cleared by writing 1 to it. 265 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 266 * | | |0 = Slave select active interrupt was cleared or not occurred. 267 * | | |1 = Slave select active interrupt event occurred. 268 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 269 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 270 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 271 * | | |1 = Slave select inactive interrupt event occurred. 272 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 273 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 274 * | | |0 = The slave select line status is 0. 275 * | | |1 = The slave select line status is 1. 276 * | | |Note: This bit is only available in Slave mode 277 * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 278 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 279 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 280 * | | |0 = No Slave mode bit count error event. 281 * | | |1 = Slave mode bit count error event occurred. 282 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 283 * | | |This bit will be cleared by writing 1 to it. 284 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 285 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 286 * | | |0 = No Slave TX under run event. 287 * | | |1 = Slave TX under run event occurred. 288 * | | |Note: This bit will be cleared by writing 1 to it. 289 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 290 * | | |0 = Receive FIFO buffer is not empty. 291 * | | |1 = Receive FIFO buffer is empty. 292 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 293 * | | |0 = Receive FIFO buffer is not full. 294 * | | |1 = Receive FIFO buffer is full. 295 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 296 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 297 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 298 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 299 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 300 * | | |0 = No FIFO is overrun. 301 * | | |1 = Receive FIFO is overrun. 302 * | | |Note: This bit will be cleared by writing 1 to it. 303 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 304 * | | |0 = No receive FIFO time-out event. 305 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode 306 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 307 * | | |Note: This bit will be cleared by writing 1 to it. 308 * |[15] |SPIENSTS |SPI Enable Status (Read Only) 309 * | | |0 = SPI controller Disabled. 310 * | | |1 = SPI controller Enabled. 311 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 312 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 313 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 314 * | | |0 = Transmit FIFO buffer is not empty. 315 * | | |1 = Transmit FIFO buffer is empty. 316 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 317 * | | |0 = Transmit FIFO buffer is not full. 318 * | | |1 = Transmit FIFO buffer is full. 319 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 320 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 321 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 322 * |[19] |TXUFIF |TX Underflow Interrupt Flag 323 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 324 * | | |0 = No effect. 325 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 326 * | | |Note 1: This bit will be cleared by writing 1 to it. 327 * | | |Note 2: If reset the slave transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 328 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 329 * | | |0 = The reset function of TXRST or RXRST is done. 330 * | | |1 = Doing the reset function of TXRST or RXRST. 331 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 332 * | | |User can check the status of this bit to monitor the reset function is doing or done. 333 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 334 * | | |This bit field indicates the valid data count of receive FIFO buffer. 335 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 336 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 337 * @var SPI_T::STATUS2 338 * Offset: 0x18 SPI Status2 Register 339 * --------------------------------------------------------------------------------------------------- 340 * |Bits |Field |Descriptions 341 * | :----: | :----: | :---- | 342 * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX data 343 * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. 344 * | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. 345 * | | |Note: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]) and SPI Slave mode Only 346 * @var SPI_T::TX 347 * Offset: 0x20 SPI Data Transmit Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[31:0] |TX |Data Transmit Register 352 * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers 353 * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. 354 * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted 355 * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer. 356 * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] 357 * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section 358 * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 359 * @var SPI_T::RX 360 * Offset: 0x30 SPI Data Receive Register 361 * --------------------------------------------------------------------------------------------------- 362 * |Bits |Field |Descriptions 363 * | :----: | :----: | :---- | 364 * |[31:0] |RX |Data Receive Register (Read Only) 365 * | | |There are 4-level FIFO buffers in this controller 366 * | | |The data receive register holds the data received from SPI data input pin 367 * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 368 * @var SPI_T::I2SCTL 369 * Offset: 0x60 I2S Control Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[0] |I2SEN |I2S Controller Enable Bit 374 * | | |0 = I2S mode Disabled. 375 * | | |1 = I2S mode Enabled. 376 * | | |Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode. 377 * | | |Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 378 * |[1] |TXEN |Transmit Enable Bit 379 * | | |0 = Data transmit Disabled. 380 * | | |1 = Data transmit Enabled. 381 * |[2] |RXEN |Receive Enable Bit 382 * | | |0 = Data receive Disabled. 383 * | | |1 = Data receive Enabled. 384 * |[3] |MUTE |Transmit Mute Enable Bit 385 * | | |0 = Transmit data is shifted from buffer. 386 * | | |1 = Transmit channel zero. 387 * |[5:4] |WDWIDTH |Word Width 388 * | | |00 = data size is 8-bit. 389 * | | |01 = data size is 16-bit. 390 * | | |10 = data size is 24-bit. 391 * | | |11 = data size is 32-bit. 392 * |[6] |MONO |Monaural Data 393 * | | |0 = Data is stereo format. 394 * | | |1 = Data is monaural format. 395 * |[7] |ORDER |Stereo Data Order in FIFO 396 * | | |0 = Left channel data at high byte. 397 * | | |1 = Left channel data at low byte. 398 * |[8] |SLAVE |Slave Mode 399 * | | |I2S can operate as master or slave 400 * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip 401 * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 402 * | | |0 = Master mode. 403 * | | |1 = Slave mode. 404 * |[15] |MCLKEN |Master Clock Enable Bit 405 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 406 * | | |0 = Master clock Disabled. 407 * | | |1 = Master clock Enabled. 408 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit 409 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 410 * | | |This function is only available in transmit operation. 411 * | | |0 = Right channel zero cross detection Disabled. 412 * | | |1 = Right channel zero cross detection Enabled. 413 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit 414 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 415 * | | |This function is only available in transmit operation. 416 * | | |0 = Left channel zero cross detection Disabled. 417 * | | |1 = Left channel zero cross detection Enabled. 418 * |[23] |RXLCH |Receive Left Channel Enable Bit 419 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. 420 * | | |0 = Receive right channel data in Mono mode. 421 * | | |1 = Receive left channel data in Mono mode. 422 * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit 423 * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 424 * | | |0 = Interrupt Disabled. 425 * | | |1 = Interrupt Enabled. 426 * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit 427 * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 428 * | | |0 = Interrupt Disabled. 429 * | | |1 = Interrupt Enabled. 430 * |[29:28] |FORMAT |Data Format Selection 431 * | | |00 = I2S data format. 432 * | | |01 = MSB justified data format. 433 * | | |10 = PCM mode A. 434 * | | |11 = PCM mode B. 435 * |[31] |SLVERRIEN |Bit Number Error Interrupt Enable Bit for Slave Mode 436 * | | |Interrupt occurs if this bit is set to 1 and bit number error event occurs. 437 * | | |0 = Interrupt Disabled. 438 * | | |1 = Interrupt Enabled. 439 * @var SPI_T::I2SCLK 440 * Offset: 0x64 I2S Clock Divider Control Register 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[6:0] |MCLKDIV |Master Clock Divider 445 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices 446 * | | |The frequency of master clock, f_MCLK, is determined by the following expressions: 447 * | | |If MCLKDIV >= 1, f_MCLK = f_i2s_clk_src/(2*MCLKDIV) 448 * | | |If MCLKDIV = 0, f_MCLK = f_i2s_clk_src 449 * | | |where 450 * | | |f_i2s_clk_src is the frequency of I2S peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2 or CLK_CLKSEL3 451 * | | |In general, the master clock rate is 256 times sampling clock rate. 452 * |[17:8] |BCLKDIV |Bit Clock Divider 453 * | | |The I2S controller will generate bit clock in Master mode 454 * | | |The clock frequency of bit clock , f_BCLK, is determined by the following expression: 455 * | | | f_BCLK = f_i2s_clk_src/[2*(BCLKDIV+1)] 456 * | | |where 457 * | | |f_i2s_clk_src is the frequency of I2S peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2 or CLK_CLKSEL3. 458 * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it is determined by 459 * | | | f_i2s_clk_src/[(BCLKDIV/2)+1] 460 * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 461 * | | |Note: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 462 * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode 463 * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set. 464 * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. 465 * | | |0 = The frequency of peripheral clock is set to SPI mode. 466 * | | |1 = The frequency of peripheral clock is set to I2S mode. 467 * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode 468 * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S Master mode and I2S Slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. 469 * | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled. 470 * | | |0 = The frequency of peripheral clock is set to I2S Master mode. 471 * | | |1 = The frequency of peripheral clock is set to I2S Slave mode. 472 * @var SPI_T::I2SSTS 473 * Offset: 0x68 I2S Status Register 474 * --------------------------------------------------------------------------------------------------- 475 * |Bits |Field |Descriptions 476 * | :----: | :----: | :---- | 477 * |[4] |RIGHT |Right Channel (Read Only) 478 * | | |This bit indicates the current transmit data is belong to which channel. 479 * | | |0 = Left channel. 480 * | | |1 = Right channel. 481 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 482 * | | |0 = Receive FIFO buffer is not empty. 483 * | | |1 = Receive FIFO buffer is empty. 484 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 485 * | | |0 = Receive FIFO buffer is not full. 486 * | | |1 = Receive FIFO buffer is full. 487 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 488 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 489 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 490 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 491 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 492 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 493 * | | |Note: This bit will be cleared by writing 1 to it. 494 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 495 * | | |0 = No receive FIFO time-out event. 496 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode 497 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 498 * | | |Note: This bit will be cleared by writing 1 to it. 499 * |[15] |I2SENSTS |I2S Enable Status (Read Only) 500 * | | |0 = The SPI/I2S control logic is disabled. 501 * | | |1 = The SPI/I2S control logic is enabled. 502 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 503 * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 504 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 505 * | | |0 = Transmit FIFO buffer is not empty. 506 * | | |1 = Transmit FIFO buffer is empty. 507 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 508 * | | |0 = Transmit FIFO buffer is not full. 509 * | | |1 = Transmit FIFO buffer is full. 510 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 511 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 512 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 513 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 514 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag 515 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. 516 * | | |Note: This bit will be cleared by writing 1 to it. 517 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag 518 * | | |0 = No zero cross event occurred on right channel. 519 * | | |1 = Zero cross event occurred on right channel. 520 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag 521 * | | |0 = No zero cross event occurred on left channel. 522 * | | |1 = Zero cross event occurred on left channel. 523 * |[22] |SLVERRIF |Bit Number Error Interrupt Flag for Slave Mode 524 * | | |0 = No bit number error event occurred. 525 * | | |1 = Bit number error event occurred. 526 * | | |Note: This bit will be cleared by writing 1 to it. 527 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 528 * | | |0 = The reset function of TXRST or RXRST is done. 529 * | | |1 = Doing the reset function of TXRST or RXRST. 530 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 531 * | | |User can check the status of this bit to monitor the reset function is doing or done. 532 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) 533 * | | |This bit field indicates the valid data count of receive FIFO buffer. 534 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) 535 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 536 */ 537 __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ 538 __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ 539 __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ 540 __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ 541 __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ 542 __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ 543 __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ 544 __I uint32_t RESERVE0[1]; 545 __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ 546 __I uint32_t RESERVE1[3]; 547 __IO uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ 548 __I uint32_t RESERVE2[11]; 549 __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ 550 __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ 551 __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ 552 553 } SPI_T; 554 555 /** 556 @addtogroup SPI_CONST SPI Bit Field Definition 557 Constant Definitions for SPI Controller 558 @{ */ 559 560 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ 561 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ 562 563 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ 564 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ 565 566 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ 567 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ 568 569 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ 570 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ 571 572 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ 573 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ 574 575 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ 576 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ 577 578 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ 579 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ 580 581 #define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ 582 #define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ 583 584 #define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ 585 #define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ 586 587 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ 588 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ 589 590 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ 591 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ 592 593 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ 594 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ 595 596 #define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ 597 #define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ 598 599 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ 600 #define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ 601 602 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ 603 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ 604 605 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ 606 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ 607 608 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ 609 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ 610 611 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ 612 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ 613 614 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ 615 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ 616 617 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ 618 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ 619 620 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ 621 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ 622 623 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ 624 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ 625 626 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ 627 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ 628 629 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ 630 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ 631 632 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ 633 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ 634 635 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ 636 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ 637 638 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ 639 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ 640 641 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ 642 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ 643 644 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ 645 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ 646 647 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ 648 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ 649 650 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ 651 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ 652 653 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ 654 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ 655 656 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ 657 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ 658 659 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ 660 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ 661 662 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ 663 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ 664 665 #define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ 666 #define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ 667 668 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ 669 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ 670 671 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ 672 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ 673 674 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ 675 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ 676 677 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ 678 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ 679 680 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ 681 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ 682 683 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ 684 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ 685 686 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ 687 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ 688 689 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ 690 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ 691 692 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ 693 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ 694 695 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ 696 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ 697 698 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ 699 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ 700 701 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ 702 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ 703 704 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ 705 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ 706 707 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ 708 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ 709 710 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ 711 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ 712 713 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ 714 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ 715 716 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ 717 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ 718 719 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ 720 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ 721 722 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ 723 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ 724 725 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ 726 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ 727 728 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ 729 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ 730 731 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ 732 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ 733 734 #define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ 735 #define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ 736 737 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ 738 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ 739 740 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ 741 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ 742 743 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ 744 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ 745 746 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ 747 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ 748 749 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ 750 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ 751 752 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ 753 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ 754 755 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ 756 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ 757 758 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ 759 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ 760 761 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ 762 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ 763 764 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ 765 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ 766 767 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ 768 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ 769 770 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ 771 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ 772 773 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ 774 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ 775 776 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ 777 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ 778 779 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ 780 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ 781 782 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ 783 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ 784 785 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ 786 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ 787 788 #define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ 789 #define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ 790 791 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ 792 #define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ 793 794 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ 795 #define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ 796 797 #define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ 798 #define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ 799 800 #define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ 801 #define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ 802 803 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ 804 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ 805 806 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ 807 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ 808 809 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ 810 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ 811 812 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ 813 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ 814 815 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ 816 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ 817 818 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ 819 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ 820 821 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ 822 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ 823 824 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ 825 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ 826 827 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ 828 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ 829 830 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ 831 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ 832 833 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ 834 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ 835 836 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ 837 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ 838 839 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ 840 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ 841 842 #define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ 843 #define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ 844 845 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ 846 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ 847 848 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ 849 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ 850 851 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ 852 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ 853 854 855 856 /**@}*/ /* SPI_CONST */ 857 /**@}*/ /* end of SPI register group */ 858 /**@}*/ /* end of REGISTER group */ 859 860 #if defined ( __CC_ARM ) 861 #pragma no_anon_unions 862 #endif 863 864 #endif /* __SPI_REG_H__ */ 865
