1 /**************************************************************************//** 2 * @file rtc_reg.h 3 * @version V1.00 4 * @brief RTC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __RTC_REG_H__ 10 #define __RTC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Real Time Clock Controller -------------------------*/ 19 /** 20 @addtogroup RTC Real Time Clock Controller(RTC) 21 Memory Mapped Structure for RTC Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var RTC_T::INIT 31 * Offset: 0x00 RTC Initiation Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |ACTIVE |RTC Active Status (Read Only) 36 * | | |0 = RTC is at reset state. 37 * | | |1 = RTC is at normal active state. 38 * |[31:1] |INIT |RTC Initiation (Write Only) 39 * | | |When RTC block is powered on, RTC is at reset state 40 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state 41 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. 42 * | | |The INIT is a write-only field and read value will be always 0. 43 * @var RTC_T::FREQADJ 44 * Offset: 0x08 RTC Frequency Compensation Register 45 * --------------------------------------------------------------------------------------------------- 46 * |Bits |Field |Descriptions 47 * | :----: | :----: | :---- | 48 * |[5:0] |FRACTION |Fraction Part 49 * | | |Formula: FRACTION = (fraction part of detected value) X 64. 50 * | | |Note: Digit in FCR must be expressed as hexadecimal number. 51 * |[12:8] |INTEGER |Integer Part 52 * | | |00000 = Integer part of detected value is 32752. 53 * | | |00001 = Integer part of detected value is 32753. 54 * | | |00010 = Integer part of detected value is 32754. 55 * | | |00011 = Integer part of detected value is 32755. 56 * | | |00100 = Integer part of detected value is 32756. 57 * | | |00101 = Integer part of detected value is 32757. 58 * | | |00110 = Integer part of detected value is 32758. 59 * | | |00111 = Integer part of detected value is 32759. 60 * | | |01000 = Integer part of detected value is 32760. 61 * | | |01001 = Integer part of detected value is 32761. 62 * | | |01010 = Integer part of detected value is 32762. 63 * | | |01011 = Integer part of detected value is 32763. 64 * | | |01100 = Integer part of detected value is 32764. 65 * | | |01101 = Integer part of detected value is 32765. 66 * | | |01110 = Integer part of detected value is 32766. 67 * | | |01111 = Integer part of detected value is 32767. 68 * | | |10000 = Integer part of detected value is 32768. 69 * | | |10001 = Integer part of detected value is 32769. 70 * | | |10010 = Integer part of detected value is 32770. 71 * | | |10011 = Integer part of detected value is 32771. 72 * | | |10100 = Integer part of detected value is 32772. 73 * | | |10101 = Integer part of detected value is 32773. 74 * | | |10110 = Integer part of detected value is 32774. 75 * | | |10111 = Integer part of detected value is 32775. 76 * | | |11000 = Integer part of detected value is 32776. 77 * | | |11001 = Integer part of detected value is 32777. 78 * | | |11010 = Integer part of detected value is 32778. 79 * | | |11011 = Integer part of detected value is 32779. 80 * | | |11100 = Integer part of detected value is 32780. 81 * | | |11101 = Integer part of detected value is 32781. 82 * | | |11110 = Integer part of detected value is 32782. 83 * | | |11111 = Integer part of detected value is 32783. 84 * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) 85 * | | |0 = The new register write operation is acceptable. 86 * | | |1 = The last write operation is in progress and new register write operation prohibited. 87 * | | |Note: This bit is only used when DCOMPEN (RTC_CLKFMT[16]) enabled. 88 * @var RTC_T::TIME 89 * Offset: 0x0C RTC Time Loading Register 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[3:0] |SEC |1-Sec Time Digit (0~9) 94 * |[6:4] |TENSEC |10-Sec Time Digit (0~5) 95 * |[11:8] |MIN |1-Min Time Digit (0~9) 96 * |[14:12] |TENMIN |10-Min Time Digit (0~5) 97 * |[19:16] |HR |1-Hour Time Digit (0~9) 98 * |[21:20] |TENHR |10-Hour Time Digit (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 99 * |[30:24] |HZCNT |Index of sub-second counter (0x00~0x7F) 100 * @var RTC_T::CAL 101 * Offset: 0x10 RTC Calendar Loading Register 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[3:0] |DAY |1-Day Calendar Digit (0~9) 106 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) 107 * |[11:8] |MON |1-Month Calendar Digit (0~9) 108 * |[12] |TENMON |10-Month Calendar Digit (0~1) 109 * |[19:16] |YEAR |1-Year Calendar Digit (0~9) 110 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) 111 * @var RTC_T::CLKFMT 112 * Offset: 0x14 RTC Time Scale Selection Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[0] |24HEN |24-hour / 12-hour Time Scale Selection 117 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 118 * | | |0 = 12-hour time scale with AM and PM indication selected. 119 * | | |1 = 24-hour time scale selected. 120 * |[8] |HZCNTEN |Sub-second Counter Enable Bit 121 * | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM. 122 * | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM. 123 * |[16] |DCOMPEN |Dynamic Compensation Enable Bit 124 * | | |0 = Dynamic Compensation Disabled. 125 * | | |1 = Dynamic Compensation Enabled. 126 * @var RTC_T::WEEKDAY 127 * Offset: 0x18 RTC Day of the Week Register 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[2:0] |WEEKDAY |Day of the Week Register 132 * | | |000 = Sunday. 133 * | | |001 = Monday. 134 * | | |010 = Tuesday. 135 * | | |011 = Wednesday. 136 * | | |100 = Thursday. 137 * | | |101 = Friday. 138 * | | |110 = Saturday. 139 * | | |111 = Reserved. 140 * @var RTC_T::TALM 141 * Offset: 0x1C RTC Time Alarm Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) 146 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) 147 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) 148 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) 149 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) 150 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 151 * |[30:24] |HZCNT |Index of sub-second counter (0x00~0x7F) 152 * @var RTC_T::CALM 153 * Offset: 0x20 RTC Calendar Alarm Register 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) 158 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) 159 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) 160 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) 161 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) 162 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) 163 * @var RTC_T::LEAPYEAR 164 * Offset: 0x24 RTC Leap Year Indicator Register 165 * --------------------------------------------------------------------------------------------------- 166 * |Bits |Field |Descriptions 167 * | :----: | :----: | :---- | 168 * |[0] |LEAPYEAR |Leap Year Indication (Read Only) 169 * | | |0 = This year is not a leap year. 170 * | | |1 = This year is leap year. 171 * @var RTC_T::INTEN 172 * Offset: 0x28 RTC Interrupt Enable Register 173 * --------------------------------------------------------------------------------------------------- 174 * |Bits |Field |Descriptions 175 * | :----: | :----: | :---- | 176 * |[0] |ALMIEN |Alarm Interrupt Enable Bit 177 * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 178 * | | |0 = RTC Alarm interrupt Disabled. 179 * | | |1 = RTC Alarm interrupt Enabled. 180 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit 181 * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 182 * | | |0 = RTC Time Tick interrupt Disabled. 183 * | | |1 = RTC Time Tick interrupt Enabled. 184 * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit 185 * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 186 * | | |0 = Tamper 0 interrupt Disabled. 187 * | | |1 = Tamper 0 interrupt Enabled. 188 * |[9] |TAMP1IEN |Tamper 1 Interrupt Enable Bit 189 * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 190 * | | |0 = Tamper 1 interrupt Disabled. 191 * | | |1 = Tamper 1 interrupt Enabled. 192 * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit 193 * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 194 * | | |0 = Tamper 2 interrupt Disabled. 195 * | | |1 = Tamper 2 interrupt Enabled. 196 * @var RTC_T::INTSTS 197 * Offset: 0x2C RTC Interrupt Status Register 198 * --------------------------------------------------------------------------------------------------- 199 * |Bits |Field |Descriptions 200 * | :----: | :----: | :---- | 201 * |[0] |ALMIF |RTC Alarm Interrupt Flag 202 * | | |0 = Alarm condition is not matched. 203 * | | |1 = Alarm condition is matched. 204 * | | |Note: Write 1 to clear this bit. 205 * |[1] |TICKIF |RTC Time Tick Interrupt Flag 206 * | | |0 = Tick condition did not occur. 207 * | | |1 = Tick condition occurred. 208 * | | |Note: Write 1 to clear this bit. 209 * |[8] |TAMP0IF |Tamper 0 Interrupt Flag 210 * | | |This bit is set when TAMPER0 detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). 211 * | | |0 = No Tamper 0 interrupt flag is generated. 212 * | | |1 = Tamper 0 interrupt flag is generated. 213 * | | |Note 1: Write 1 to clear this bit. 214 * | | |Note 2: This interrupt flag will generate again when Tamper setting condition is not restoration. 215 * | | |Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values can loaded while a tamper event occurred. 216 * |[9] |TAMP1IF |Tamper 1 Interrupt Flag 217 * | | |This bit is set when TAMPER1 detected level non-equal TAMP1LV (RTC_TAMPCTL[13]). 218 * | | |0 = No Tamper 1 interrupt flag is generated. 219 * | | |1 = Tamper 1 interrupt flag is generated. 220 * | | |Note 1: Write 1 to clear this bit. 221 * | | |Note 2: This interrupt flag will generate again when Tamper setting condition is not restoration. 222 * | | |Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values can loaded while a tamper event occurred. 223 * |[10] |TAMP2IF |Tamper 2 Interrupt Flag 224 * | | |This bit is set when TAMPER2 detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). 225 * | | |0 = No Tamper 2 interrupt flag is generated. 226 * | | |1 = Tamper 2 interrupt flag is generated. 227 * | | |Note 1: Write 1 to clear this bit. 228 * | | |Note 2: This interrupt flag will generate again when Tamper setting condition is not restoration. 229 * | | |Note 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values can loaded while a tamper event occurred. 230 * @var RTC_T::TICK 231 * Offset: 0x30 RTC Time Tick Register 232 * --------------------------------------------------------------------------------------------------- 233 * |Bits |Field |Descriptions 234 * | :----: | :----: | :---- | 235 * |[2:0] |TICK |Time Tick Register 236 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 237 * | | |000 = Time tick is 1 second. 238 * | | |001 = Time tick is 1/2 second. 239 * | | |010 = Time tick is 1/4 second. 240 * | | |011 = Time tick is 1/8 second. 241 * | | |100 = Time tick is 1/16 second. 242 * | | |101 = Time tick is 1/32 second. 243 * | | |110 = Time tick is 1/64 second. 244 * | | |111 = Time tick is 1/128 second. 245 * @var RTC_T::TAMSK 246 * Offset: 0x34 RTC Time Alarm Mask Register 247 * --------------------------------------------------------------------------------------------------- 248 * |Bits |Field |Descriptions 249 * | :----: | :----: | :---- | 250 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) 251 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) 252 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) 253 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) 254 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) 255 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) 256 * @var RTC_T::CAMSK 257 * Offset: 0x38 RTC Calendar Alarm Mask Register 258 * --------------------------------------------------------------------------------------------------- 259 * |Bits |Field |Descriptions 260 * | :----: | :----: | :---- | 261 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) 262 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) 263 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) 264 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) 265 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) 266 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) 267 * @var RTC_T::SPRCTL 268 * Offset: 0x3C RTC Spare Functional Control Register 269 * --------------------------------------------------------------------------------------------------- 270 * |Bits |Field |Descriptions 271 * | :----: | :----: | :---- | 272 * |[2] |SPRRWEN |Spare Register Enable Bit 273 * | | |0 = Spare register Disabled. 274 * | | |1 = Spare register Enabled. 275 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed. 276 * |[5] |SPRCSTS |SPR Clear Flag 277 * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR4 content is cleared when specify tamper event is detected. 278 * | | |0 = Spare register content is not cleared. 279 * | | |1 = Spare register content is cleared. 280 * | | |Note 1: Write 1 to clear this bit. 281 * | | |Note 2: This bit keeps 1 when RTC_INTSTS[10:8] is not equal to 0. 282 * @var RTC_T::SPR0 283 * Offset: 0x40 RTC Spare Register 0 284 * --------------------------------------------------------------------------------------------------- 285 * |Bits |Field |Descriptions 286 * | :----: | :----: | :---- | 287 * |[31:0] |SPARE |Spare Register 288 * | | |This field is used to store back-up information defined by user. 289 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, or after RRAM mass operation. 290 * @var RTC_T::SPR1 291 * Offset: 0x44 RTC Spare Register 1 292 * --------------------------------------------------------------------------------------------------- 293 * |Bits |Field |Descriptions 294 * | :----: | :----: | :---- | 295 * |[31:0] |SPARE |Spare Register 296 * | | |This field is used to store back-up information defined by user. 297 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, or after RRAM mass operation. 298 * @var RTC_T::SPR2 299 * Offset: 0x48 RTC Spare Register 2 300 * --------------------------------------------------------------------------------------------------- 301 * |Bits |Field |Descriptions 302 * | :----: | :----: | :---- | 303 * |[31:0] |SPARE |Spare Register 304 * | | |This field is used to store back-up information defined by user. 305 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, or after RRAM mass operation. 306 * @var RTC_T::SPR3 307 * Offset: 0x4C RTC Spare Register 3 308 * --------------------------------------------------------------------------------------------------- 309 * |Bits |Field |Descriptions 310 * | :----: | :----: | :---- | 311 * |[31:0] |SPARE |Spare Register 312 * | | |This field is used to store back-up information defined by user. 313 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, or after RRAM mass operation. 314 * @var RTC_T::SPR4 315 * Offset: 0x50 RTC Spare Register 4 316 * --------------------------------------------------------------------------------------------------- 317 * |Bits |Field |Descriptions 318 * | :----: | :----: | :---- | 319 * |[31:0] |SPARE |Spare Register 320 * | | |This field is used to store back-up information defined by user. 321 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, or after RRAM mass operation. 322 * @var RTC_T::LXTCTL 323 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register 324 * --------------------------------------------------------------------------------------------------- 325 * |Bits |Field |Descriptions 326 * | :----: | :----: | :---- | 327 * |[0] |LIRC32KEN |Enable LIRC32K Source 328 * | | |0 = LIRC32K Disabled. 329 * | | |1 = LIRC32K Enabled. 330 * |[4:1] |GAIN |Oscillator Gain Option 331 * | | |User can select oscillator gain according to crystal external loading and operating temperature range 332 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. 333 * | | |0000 = L0 mode. 334 * | | |0001 = L1 mode. 335 * | | |0010 = L2 mode. 336 * | | |0011 = L3 mode. (Default) 337 * | | |0100 = L4 mode. 338 * | | |0101 = L5 mode. 339 * | | |0110 = L6 mode. 340 * | | |0111 = L7 mode. 341 * | | |1000 = L8 mode. 342 * | | |1001 = L9 mode. 343 * | | |1010 = L10 mode. 344 * | | |1011 = L11 mode. 345 * | | |1100 = L12 mode. 346 * | | |1101 = L13 mode. 347 * | | |1110 = L14 mode. 348 * | | |1111 = L15 mode. 349 * |[6] |C32KSEL |Clock 32K Source Selection 350 * | | |0 = Clock source from external low speed crystal oscillator (LXT). 351 * | | |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K). 352 353 * |[7] |RTCCKSEL |RTC Clock Source Selection 354 * | | |0 = Clock source from external low speed crystal oscillator (LXT) 355 * | | |1 = Clock source from internal low speed RC oscillator (LIRC). 356 * |[8] |IOCTLSEL |I/O Pin Backup Control Selection 357 * | | |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, PF.4 pin (X32_OUT pin), PF.5 pin (X32_IN pin) or PF.6~8 pin (TAMPERx pin) can be used as GPIO function 358 * | | |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. 359 * | | |0 = PF.4~11 pin I/O function is controlled by GPIO module. 360 * | | |1 = PF.4~11 pin I/O function is controlled by VBAT power domain. 361 * | | |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled. 362 * @var RTC_T::GPIOCTL0 363 * Offset: 0x104 RTC GPIO Control 0 Register 364 * --------------------------------------------------------------------------------------------------- 365 * |Bits |Field |Descriptions 366 * | :----: | :----: | :---- | 367 * |[1:0] |OPMODE0 |I/O Operation Mode 368 * | | |00 = PF.4 is input only mode. 369 * | | |01 = PF.4 is output push pull mode. 370 * | | |10 = PF.4 is open drain mode. 371 * | | |11 = PF.4 is quasi-bidirectional mode. 372 * |[2] |DOUT0 |I/O Output Data 373 * | | |0 = PF.4 output low. 374 * | | |1 = PF.4 output high. 375 * |[3] |DINOFF0 |I/O Pin Digital Input Path Disable Bit 376 * | | |0 = PF.4 digital input path Enabled. 377 * | | |1 = PF.4 digital input path Disabled (digital input tied to low). 378 * |[5:4] |PUSEL0 |I/O Pull-up and Pull-down Enable Bits 379 * | | |Determine PF.4 I/O pull-up or pull-down. 380 * | | |00 = PF.4 pull-up and pull-down Disabled. 381 * | | |01 = PF.4 pull-up Enabled. 382 * | | |10 = PF.4 pull-down Enabled. 383 * | | |11 = PF.4 pull-up and pull-down Disabled. 384 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 385 * | | |The independent pull-up / pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode. 386 * |[9:8] |OPMODE1 |I/O Operation Mode 387 * | | |00 = PF.5 is input only mode. 388 * | | |01 = PF.5 is output push pull mode. 389 * | | |10 = PF.5 is open drain mode. 390 * | | |11 = PF.5 is quasi-bidirectional mode. 391 * |[10] |DOUT1 |I/O Output Data 392 * | | |0 = PF.5 output low. 393 * | | |1 = PF.5 output high. 394 * |[11] |DINOFF1 |I/O Pin Digital Input Path Disable Bit 395 * | | |0 = PF.5 digital input path Enabled. 396 * | | |1 = PF.5 digital input path Disabled (digital input tied to low). 397 * |[13:12] |PUSEL1 |I/O Pull-up and Pull-down Enable Bits 398 * | | |Determine PF.5 I/O pull-up or pull-down. 399 * | | |00 = PF.5 pull-up and pull-down Disabled. 400 * | | |01 = PF.5 pull-up Enabled. 401 * | | |10 = PF.5 pull-down Enabled. 402 * | | |11 = PF.5 pull-up and pull-down Disabled. 403 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 404 * | | |The independent pull-up / pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode. 405 * |[17:16] |OPMODE2 |I/O Operation Mode 406 * | | |00 = PF.6 is input only mode. 407 * | | |01 = PF.6 is output push pull mode. 408 * | | |10 = PF.6 is open drain mode. 409 * | | |11 = PF.6 is quasi-bidirectional mode. 410 * |[18] |DOUT2 |I/O Output Data 411 * | | |0 = PF.6 output low. 412 * | | |1 = PF.6 output high. 413 * |[19] |DINOFF2 |I/O Pin Digital Input Path Disable Bit 414 * | | |0 = PF.6 digital input path Enabled. 415 * | | |1 = PF.6 digital input path Disabled (digital input tied to low). 416 * |[21:20] |PUSEL2 |I/O Pull-up and Pull-down Enable Bits 417 * | | |Determine PF.6 I/O Pull-up or Pull-down. 418 * | | |00 = PF.6 pull-up and pull-down Disabled. 419 * | | |01 = PF.6 pull-up Enabled. 420 * | | |10 = PF.6 pull-down Enabled. 421 * | | |11 = PF.6 pull-up and pull-down Disabled. 422 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 423 * | | |The independent pull-up / pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode. 424 * |[25:24] |OPMODE3 |I/O Operation Mode 425 * | | |00 = PF.7 is input only mode. 426 * | | |01 = PF.7 is output push pull mode. 427 * | | |10 = PF.7 is open drain mode. 428 * | | |11 = PF.7 is quasi-bidirectional mode. 429 * |[26] |DOUT3 |I/O Output Data 430 * | | |0 = PF.7 output low. 431 * | | |1 = PF.7 output high. 432 * |[27] |DINOFF3 |I/O Pin Digital Input Path Disable Bit 433 * | | |0 = PF.7 digital input path Enabled. 434 * | | |1 = PF.7 digital input path Disabled (digital input tied to low). 435 * |[29:28] |PUSEL3 |I/O Pull-up and Pull-down Enable Bits 436 * | | |Determine PF.7 I/O pull-up or pull-down. 437 * | | |00 = PF.7 pull-up and pull-down Disabled. 438 * | | |01 = PF.7 pull-up Enabled. 439 * | | |10 = PF.7 pull-down Enabled. 440 * | | |11 = PF.7 pull-up and pull-down Disabled. 441 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 442 * | | |The independent pull-up / pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode. 443 * @var RTC_T::GPIOCTL1 444 * Offset: 0x108 RTC GPIO Control 1 Register 445 * --------------------------------------------------------------------------------------------------- 446 * |Bits |Field |Descriptions 447 * | :----: | :----: | :---- | 448 * |[1:0] |OPMODE4 |I/O Operation Mode 449 * | | |00 = PF.8 is input only mode. 450 * | | |01 = PF.8 is output push pull mode. 451 * | | |10 = PF.8 is open drain mode. 452 * | | |11 = PF.8 is quasi-bidirectional mode. 453 * |[2] |DOUT4 |I/O Output Data 454 * | | |0 = PF.8 output low. 455 * | | |1 = PF.8 output high. 456 * |[3] |DINOFF4 |I/O Pin Digital Input Path Disable Bit 457 * | | |0 = PF.8 digital input path Enabled. 458 * | | |1 = PF.8 digital input path Disabled (digital input tied to low). 459 * |[5:4] |PUSEL4 |I/O Pull-up and Pull-down Enable Bits 460 * | | |Determine PF.8 I/O pull-up or pull-down. 461 * | | |00 = PF.8 pull-up and pull-down Disabled. 462 * | | |01 = PF.8 pull-up Enabled. 463 * | | |10 = PF.8 pull-down Enabled. 464 * | | |11 = PF.8 pull-up and pull-down Disabled. 465 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 466 * | | |The independent pull-up / pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode. 467 * |[9:8] |OPMODE5 |I/O Operation Mode 468 * | | |00 = PF.9 is input only mode. 469 * | | |01 = PF.9 is output push pull mode. 470 * | | |10 = PF.9 is open drain mode. 471 * | | |11 = PF.9 is quasi-bidirectional mode . 472 * |[10] |DOUT5 |I/O Output Data 473 * | | |0 = PF.9 output low. 474 * | | |1 = PF.9 output high. 475 * |[11] |DINOFF5 |I/O Pin Digital Input Path Disable Bit 476 * | | |0 = PF.9 digital input path Enabled. 477 * | | |1 = PF.9 digital input path Disabled (digital input tied to low). 478 * |[13:12] |PUSEL5 |I/O Pull-up and Pull-down Enable Bits 479 * | | |Determine PF.9 I/O pull-up or pull-down. 480 * | | |00 = PF.9 pull-up and pull-down Disabled. 481 * | | |01 = PF.9 pull-up Enabled. 482 * | | |10 = PF.9 pull-down Enabled. 483 * | | |11 = PF.9 pull-up and pull-down Disabled. 484 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 485 * | | |The independent pull-up / pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode. 486 * |[17:16] |OPMODE6 |I/O Operation Mode 487 * | | |00 = PF.10 is input only mode. 488 * | | |01 = PF.10 is output push pull mode. 489 * | | |10 = PF.10 is open drain mode. 490 * | | |11 = PF.10 is quasi-bidirectional mode . 491 * |[18] |DOUT6 |I/O Output Data 492 * | | |0 = PF.10 output low. 493 * | | |1 = PF.10 output high. 494 * |[19] |DINOFF6 |I/O Pin Digital Input Path Disable Bit 495 * | | |0 = PF.10 digital input path Enabled. 496 * | | |1 = PF.10 digital input path Disabled (digital input tied to low). 497 * |[21:20] |PUSEL6 |I/O Pull-up and Pull-down Enable Bits 498 * | | |Determine PF.10 I/O pull-up or pull-down. 499 * | | |00 = PF.10 pull-up and pull-down Disabled. 500 * | | |01 = PF.10 pull-up Enabled. 501 * | | |10 = PF.10 pull-down Enabled. 502 * | | |11 = PF.10 pull-up and pull-down Disabled. 503 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 504 * | | |The independent pull-up / pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode. 505 * |[25:24] |OPMODE7 |I/O Operation Mode 506 * | | |00 = PF.11 is input only mode. 507 * | | |01 = PF.11 is output push pull mode. 508 * | | |10 = PF.11 is open drain mode. 509 * | | |11 = PF.11 is quasi-bidirectional mode. 510 * |[26] |DOUT7 |I/O Output Data 511 * | | |0 = PF.11 output low. 512 * | | |1 = PF.11 output high. 513 * |[27] |DINOFF7 |I/O Pin Digital Input Path Disable Bit 514 * | | |0 = PF.11 digital input path Enabled. 515 * | | |1 = PF.11 digital input path Disabled (digital input tied to low). 516 * |[29:28] |PUSEL7 |I/O Pull-up and Pull-down Enable Bits 517 * | | |Determine PF.11 I/O pull-up or pull-down. 518 * | | |00 = PF.11 pull-up and pull-down Disabled. 519 * | | |01 = PF.11 pull-up Enabled. 520 * | | |10 = PF.11 pull-down Enabled. 521 * | | |11 = PF.11 pull-up and pull-down Disabled. 522 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 523 * | | |The independent pull-up / pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode. 524 * @var RTC_T::DSTCTL 525 * Offset: 0x110 RTC Daylight Saving Time Control Register 526 * --------------------------------------------------------------------------------------------------- 527 * |Bits |Field |Descriptions 528 * | :----: | :----: | :---- | 529 * |[0] |ADDHR |Add 1 Hour 530 * | | |0 = No effect. 531 * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. 532 * |[1] |SUBHR |Subtract 1 Hour 533 * | | |0 = No effect. 534 * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. 535 * |[2] |DSBAK |Daylight Saving Back 536 * | | |0 = Daylight Saving Change is not performed. 537 * | | |1 = Daylight Saving Change is performed. 538 * @var RTC_T::TAMPCTL 539 * Offset: 0x120 RTC Tamper Pin Control Register 540 * --------------------------------------------------------------------------------------------------- 541 * |Bits |Field |Descriptions 542 * | :----: | :----: | :---- | 543 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit 544 * | | |0 = Tamper 0 detect Disabled. 545 * | | |1 = Tamper 0 detect Enabled. 546 * | | |Note: The detection reference clock is RTC counter clock 547 * | | |Tamper detector needs to sync 2 ~ 3 RTC counter clock. 548 * |[9] |TAMP0LV |Tamper 0 Level 549 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 550 * | | |0 = Detect voltage level is low. 551 * | | |1 = Detect voltage level is high. 552 * |[10] |TAMP0DEN |Tamper 0 De-bounce Enable Bit 553 * | | |0 = Tamper 0 de-bounce Disabled. 554 * | | |1 = Tamper 0 de-bounce Enabled, tamper detection pin will sync 1 RTC counter clock. 555 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit 556 * | | |0 = Tamper 1 detect Disabled. 557 * | | |1 = Tamper 1 detect Enabled. 558 * | | |Note: The detection reference clock is RTC counter clock 559 * | | |Tamper detector needs to sync 2 ~ 3 RTC counter clock. 560 * |[13] |TAMP1LV |Tamper 1 Level 561 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 562 * | | |0 = Detect voltage level is low. 563 * | | |1 = Detect voltage level is high. 564 * |[14] |TAMP1DEN |Tamper 1 De-bounce Enable Bit 565 * | | |0 = Tamper 1 de-bounce Disabled. 566 * | | |1 = Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC counter clock. 567 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit 568 * | | |0 = Tamper 2 detect Disabled. 569 * | | |1 = Tamper 2 detect Enabled. 570 * | | |Note: The detection reference clock is RTC counter clock 571 * | | |Tamper detector need to sync 2 ~ 3 RTC counter clock. 572 * |[17] |TAMP2LV |Tamper 2 Level 573 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 574 * | | |0 = Detect voltage level is low. 575 * | | |1 = Detect voltage level is high. 576 * |[18] |TAMP2DEN |Tamper 2 De-bounce Enable Bit 577 * | | |0 = Tamper 2 de-bounce Disabled. 578 * | | |1 = Tamper 2 de-bounce Enabled, tamper detection pin will sync 1 RTC counter clock. 579 * @var RTC_T::TAMPTIME 580 * Offset: 0x130 RTC Tamper Time Register 581 * --------------------------------------------------------------------------------------------------- 582 * |Bits |Field |Descriptions 583 * | :----: | :----: | :---- | 584 * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) 585 * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) 586 * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) 587 * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) 588 * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) 589 * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only . 590 * |[30:24] |HZCNT |Index of sub-second counter (0x00~0x7F) 591 * @var RTC_T::TAMPCAL 592 * Offset: 0x134 RTC Tamper Calendar Register 593 * --------------------------------------------------------------------------------------------------- 594 * |Bits |Field |Descriptions 595 * | :----: | :----: | :---- | 596 * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) 597 * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) 598 * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) 599 * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) 600 * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) 601 * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) 602 */ 603 __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ 604 __I uint32_t RESERVE0[1]; 605 __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ 606 __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ 607 __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ 608 __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ 609 __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ 610 __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ 611 __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ 612 __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ 613 __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ 614 __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ 615 __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ 616 __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ 617 __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ 618 __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ 619 __IO uint32_t SPR[5]; /*!< [0x0040] ~ [0x0050] RTC Spare Register 0 ~ 19 */ 620 __I uint32_t RESERVE1[43]; 621 __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ 622 __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ 623 __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ 624 __I uint32_t RESERVE2[1]; 625 __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ 626 __I uint32_t RESERVE3[3]; 627 __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ 628 __I uint32_t RESERVE4[3]; 629 __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ 630 __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ 631 632 } RTC_T; 633 634 /** 635 @addtogroup RTC_CONST RTC Bit Field Definition 636 Constant Definitions for RTC Controller 637 @{ */ 638 639 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ 640 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ 641 642 #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ 643 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ 644 645 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ 646 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ 647 648 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ 649 #define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ 650 651 #define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ 652 #define RTC_FREQADJ_FCRBUSY_Msk (0x1ul << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ 653 654 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ 655 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ 656 657 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ 658 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ 659 660 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ 661 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ 662 663 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ 664 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ 665 666 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ 667 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ 668 669 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ 670 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ 671 672 #define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */ 673 #define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */ 674 675 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ 676 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ 677 678 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ 679 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ 680 681 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ 682 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ 683 684 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ 685 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ 686 687 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ 688 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ 689 690 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ 691 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ 692 693 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ 694 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ 695 696 #define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */ 697 #define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */ 698 699 #define RTC_CLKFMT_DCOMPEN_Pos (16) /*!< RTC_T::CLKFMT: DCOMPEN Position */ 700 #define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ 701 702 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ 703 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ 704 705 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ 706 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ 707 708 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ 709 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ 710 711 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ 712 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ 713 714 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ 715 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ 716 717 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ 718 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ 719 720 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ 721 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ 722 723 #define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */ 724 #define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */ 725 726 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ 727 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ 728 729 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ 730 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ 731 732 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ 733 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ 734 735 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ 736 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ 737 738 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ 739 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ 740 741 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ 742 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ 743 744 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ 745 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ 746 747 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ 748 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ 749 750 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ 751 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ 752 753 #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ 754 #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ 755 756 #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ 757 #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ 758 759 #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ 760 #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ 761 762 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ 763 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ 764 765 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ 766 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ 767 768 #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ 769 #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ 770 771 #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ 772 #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ 773 774 #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ 775 #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ 776 777 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ 778 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ 779 780 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ 781 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ 782 783 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ 784 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ 785 786 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ 787 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ 788 789 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ 790 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ 791 792 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ 793 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ 794 795 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ 796 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ 797 798 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ 799 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ 800 801 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ 802 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ 803 804 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ 805 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ 806 807 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ 808 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ 809 810 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ 811 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ 812 813 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ 814 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ 815 816 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ 817 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ 818 819 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ 820 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ 821 822 #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ 823 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ 824 825 #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ 826 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ 827 828 #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ 829 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ 830 831 #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ 832 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ 833 834 #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ 835 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ 836 837 #define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ 838 #define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ 839 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ 840 #define RTC_LXTCTL_GAIN_Msk (0xful << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ 841 #define RTC_LXTCTL_C32KSEL_Pos (6) /*!< RTC_T::LXTCTL: C32KSEL Position */ 842 #define RTC_LXTCTL_C32KSEL_Msk (0x1ul << RTC_LXTCTL_C32KSEL_Pos) /*!< RTC_T::LXTCTL: C32KSEL Mask */ 843 844 #define RTC_LXTCTL_RTCCKSEL_Pos (7) /*!< RTC_T::LXTCTL: RTCCKSEL Position */ 845 #define RTC_LXTCTL_RTCCKSEL_Msk (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos) /*!< RTC_T::LXTCTL: RTCCKSEL Mask */ 846 847 #define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ 848 #define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ 849 850 #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ 851 #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ 852 853 #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ 854 #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ 855 856 #define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ 857 #define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ 858 859 #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ 860 #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ 861 862 #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ 863 #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ 864 865 #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ 866 #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ 867 868 #define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ 869 #define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ 870 871 #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ 872 #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ 873 874 #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ 875 #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ 876 877 #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ 878 #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ 879 880 #define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ 881 #define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ 882 883 #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ 884 #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ 885 886 #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ 887 #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ 888 889 #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ 890 #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ 891 892 #define RTC_GPIOCTL0_DINOFF3_Pos (27) /*!< RTC_T::GPIOCTL0: DINOFF3 Position */ 893 #define RTC_GPIOCTL0_DINOFF3_Msk (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos) /*!< RTC_T::GPIOCTL0: DINOFF3 Mask */ 894 895 #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ 896 #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ 897 898 #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ 899 #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ 900 901 #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ 902 #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ 903 904 #define RTC_GPIOCTL1_DINOFF4_Pos (3) /*!< RTC_T::GPIOCTL1: DINOFF4 Position */ 905 #define RTC_GPIOCTL1_DINOFF4_Msk (0x1ul << RTC_GPIOCTL1_DINOFF4_Pos) /*!< RTC_T::GPIOCTL1: DINOFF4 Mask */ 906 907 #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ 908 #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ 909 910 #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ 911 #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ 912 913 #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ 914 #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ 915 916 #define RTC_GPIOCTL1_DINOFF5_Pos (11) /*!< RTC_T::GPIOCTL1: DINOFF5 Position */ 917 #define RTC_GPIOCTL1_DINOFF5_Msk (0x1ul << RTC_GPIOCTL1_DINOFF5_Pos) /*!< RTC_T::GPIOCTL1: DINOFF5 Mask */ 918 919 #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ 920 #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ 921 922 #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ 923 #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ 924 925 #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ 926 #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ 927 928 #define RTC_GPIOCTL1_DINOFF6_Pos (19) /*!< RTC_T::GPIOCTL1: DINOFF6 Position */ 929 #define RTC_GPIOCTL1_DINOFF6_Msk (0x1ul << RTC_GPIOCTL1_DINOFF6_Pos) /*!< RTC_T::GPIOCTL1: DINOFF6 Mask */ 930 931 #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ 932 #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ 933 934 #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ 935 #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ 936 937 #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ 938 #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ 939 940 #define RTC_GPIOCTL1_DINOFF7_Pos (27) /*!< RTC_T::GPIOCTL1: DINOFF7 Position */ 941 #define RTC_GPIOCTL1_DINOFF7_Msk (0x1ul << RTC_GPIOCTL1_DINOFF7_Pos) /*!< RTC_T::GPIOCTL1: DINOFF7 Mask */ 942 943 #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ 944 #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ 945 946 #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ 947 #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ 948 949 #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ 950 #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ 951 952 #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ 953 #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ 954 955 #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ 956 #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ 957 958 #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ 959 #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ 960 961 #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ 962 #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ 963 964 #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ 965 #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ 966 967 #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ 968 #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ 969 970 #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ 971 #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ 972 973 #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ 974 #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ 975 976 #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ 977 #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ 978 979 #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ 980 #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ 981 982 #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ 983 #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ 984 985 #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ 986 #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ 987 988 #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ 989 #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ 990 991 #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ 992 #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ 993 994 #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ 995 #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ 996 997 #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ 998 #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ 999 1000 #define RTC_TAMPTIME_HZCNT_Pos (24) /*!< RTC_T::TAMPTIME: HZCNT Position */ 1001 #define RTC_TAMPTIME_HZCNT_Msk (0x7ful << RTC_TAMPTIME_HZCNT_Pos) /*!< RTC_T::TAMPTIME: HZCNT Mask */ 1002 1003 #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ 1004 #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ 1005 1006 #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ 1007 #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ 1008 1009 #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ 1010 #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ 1011 1012 #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ 1013 #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ 1014 1015 #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ 1016 #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ 1017 1018 #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ 1019 #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ 1020 1021 /**@}*/ /* RTC_CONST */ 1022 /**@}*/ /* end of RTC register group */ 1023 1024 1025 /**@}*/ /* end of REGISTER group */ 1026 1027 #endif /* __RTC_REG_H__ */ 1028
