1 /**************************************************************************//** 2 * @file qspi_reg.h 3 * @version V1.00 4 * @brief QSPI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __QSPI_REG_H__ 10 #define __QSPI_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/ 24 /** 25 @addtogroup QSPI Quad Serial Peripheral Interface Controller (QSPI) 26 Memory Mapped Structure for QSPI Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var QSPI_T::CTL 35 * Offset: 0x00 QSPI Control Register 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[0] |SPIEN |QSPI Transfer Control Enable Bit 40 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 41 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 42 * | | |0 = Transfer control Disabled. 43 * | | |1 = Transfer control Enabled. 44 * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. 45 * |[1] |RXNEG |Receive on Negative Edge 46 * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. 47 * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. 48 * |[2] |TXNEG |Transmit on Negative Edge 49 * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. 50 * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. 51 * | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]). 52 * |[3] |CLKPOL |Clock Polarity 53 * | | |0 = QSPI bus clock is idle low. 54 * | | |1 = QSPI bus clock is idle high. 55 * |[7:4] |SUSPITV |Suspend Interval 56 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer 57 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 58 * | | |The default value is 0x3 59 * | | |The period of the suspend interval is obtained according to the following equation. 60 * | | |(SUSPITV[3:0] + 0.5) * period of QSPI_CLK clock cycle 61 * | | |Example: 62 * | | |SUSPITV = 0x0 .... 0.5 QSPI_CLK clock cycle. 63 * | | |SUSPITV = 0x1 .... 1.5 QSPI_CLK clock cycle. 64 * | | |.... 65 * | | |SUSPITV = 0xE .... 14.5 QSPI_CLK clock cycle. 66 * | | |SUSPITV = 0xF .... 15.5 QSPI_CLK clock cycle. 67 * | | |Note: Master Only and In TX DTR mode, SUSPITV equals to 0x0. 68 * |[12:8] |DWIDTH |Data Width 69 * | | |This field specifies how many bits can be transmitted/received in one transaction 70 * | | |The minimum bit length is 8 bits and can up to 32 bits. 71 * | | |DWIDTH = 0x08 .... 8 bits. 72 * | | |DWIDTH = 0x09 .... 9 bits. 73 * | | |.... 74 * | | |DWIDTH = 0x1F .... 31 bits. 75 * | | |DWIDTH = 0x00 .... 32 bits. 76 * |[13] |LSB |Send LSB First 77 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 78 * | | |1 = The LSB, bit 0 of the QSPIx TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPIx_RX). 79 * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit 80 * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer 81 * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 82 * | | |0 = QSPI operates in full-duplex transfer. 83 * | | |1 = QSPI operates in half-duplex transfer. 84 * |[15] |RXONLY |Receive-only Mode Enable Bit 85 * | | |This bit field is only available in Master mode 86 * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 87 * | | |0 = Receive-only mode Disabled. 88 * | | |1 = Receive-only mode Enabled. 89 * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit 90 * | | |0 = 2-bit Transfer mode Disabled. 91 * | | |1 = 2-bit Transfer mode Enabled. 92 * | | |Note: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data 93 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 94 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 95 * | | |0 = QSPI unit transfer interrupt Disabled. 96 * | | |1 = QSPI unit transfer interrupt Enabled. 97 * |[18] |SLAVE |Slave Mode Control 98 * | | |0 = Master mode. 99 * | | |1 = Slave mode. 100 * |[19] |REORDER |Byte Reorder Function Enable Bit 101 * | | |0 = Byte Reorder function Disabled. 102 * | | |1 = Byte Reorder function Enabled 103 * | | |A byte suspend interval will be inserted among each byte 104 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 105 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 106 * |[20] |DATDIR |Data Port Direction Control 107 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 108 * | | |0 = QSPI data is input direction. 109 * | | |1 = QSPI data is output direction. 110 * |[21] |DUALIOEN |Dual I/O Mode Enable Bit 111 * | | |0 = Dual I/O mode Disabled. 112 * | | |1 = Dual I/O mode Enabled. 113 * |[22] |QUADIOEN |Quad I/O Mode Enable Bit 114 * | | |0 = Quad I/O mode Disabled. 115 * | | |1 = Quad I/O mode Enabled. 116 * |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit 117 * | | |0 = TX DTR (Transmit Double Transfer Rate) mode Disabled. 118 * | | |1 = TX DTR (Transmit Double Transfer Rate) mode Enabled. 119 * | | |Note: QSPI Master mode supports TXDTR mode, and QSPI Slave mode does not support this mode. 120 * @var QSPI_T::CLKDIV 121 * Offset: 0x04 QSPI Clock Divider Register 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[8:0] |DIVIDER |Clock Divider 126 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master 127 * | | |The frequency is obtained according to the following equation. 128 * | | |where 129 * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 130 * | | |Note: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register. 131 * @var QSPI_T::SSCTL 132 * Offset: 0x08 QSPI Slave Select Control Register 133 * --------------------------------------------------------------------------------------------------- 134 * |Bits |Field |Descriptions 135 * | :----: | :----: | :---- | 136 * |[0] |SS |Slave Selection Control 137 * | | |If AUTOSS bit is cleared to 0, 138 * | | |0 = Set the QSPIx_SS line to inactive state. 139 * | | |1 = Set the QSPIx_SS line to active state. 140 * | | |If the AUTOSS bit is set to 1, 141 * | | |0 = Keep the QSPIx_SS line at inactive state. 142 * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 143 * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). 144 * | | |Note: Master Only. 145 * |[2] |SSACTPOL |Slave Selection Active Polarity 146 * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). 147 * | | |0 = The slave selection signal QSPIx_SS is active low. 148 * | | |1 = The slave selection signal QSPIx_SS is active high. 149 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit 150 * | | |0 = Automatic slave selection function Disabled 151 * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). 152 * | | |1 = Automatic slave selection function Enabled (Master only). 153 * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit 154 * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPIx_CLK, QSPIx_MISO and QSPIx_MOSI pins. 155 * | | |0 = 4-wire bi-direction interface. 156 * | | |1 = 3-wire bi-direction interface. 157 * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit 158 * | | |0 = Slave mode time-out interrupt Disabled. 159 * | | |1 = Slave mode time-out interrupt Enabled. 160 * |[6] |SLVTORST |Slave Mode Time-out Reset Control 161 * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. 162 * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. 163 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 164 * | | |0 = Slave mode bit count error interrupt Disabled. 165 * | | |1 = Slave mode bit count error interrupt Enabled. 166 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 167 * | | |0 = Slave mode TX under run interrupt Disabled. 168 * | | |1 = Slave mode TX under run interrupt Enabled. 169 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 170 * | | |0 = Slave select active interrupt Disabled. 171 * | | |1 = Slave select active interrupt Enabled. 172 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 173 * | | |0 = Slave select inactive interrupt Disabled. 174 * | | |1 = Slave select inactive interrupt Enabled. 175 * |[31:16] |SLVTOCNT |Slave Mode Time-out Period 176 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active 177 * | | |The clock source of the time-out counter is Slave peripheral clock 178 * | | |If the value is 0, it indicates the slave mode time-out function is disabled. 179 * @var QSPI_T::PDMACTL 180 * Offset: 0x0C QSPI PDMA Control Register 181 * --------------------------------------------------------------------------------------------------- 182 * |Bits |Field |Descriptions 183 * | :----: | :----: | :---- | 184 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 185 * | | |0 = Transmit PDMA function Disabled. 186 * | | |1 = Transmit PDMA function Enabled. 187 * | | |Note 1: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 188 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 189 * | | |Note 2: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function 190 * | | |User can disable RX PDMA function firstly or disable both functions simultaneously. 191 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 192 * | | |0 = Receive PDMA function Disabled. 193 * | | |1 = Receive PDMA function Enabled. 194 * |[2] |PDMARST |PDMA Reset 195 * | | |0 = No effect. 196 * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. 197 * @var QSPI_T::FIFOCTL 198 * Offset: 0x10 QSPI FIFO Control Register 199 * --------------------------------------------------------------------------------------------------- 200 * |Bits |Field |Descriptions 201 * | :----: | :----: | :---- | 202 * |[0] |RXRST |Receive Reset 203 * | | |0 = No effect. 204 * | | |1 = Reset receive FIFO pointer and receive circuit 205 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 206 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 207 * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. 208 * |[1] |TXRST |Transmit Reset 209 * | | |0 = No effect. 210 * | | |1 = Reset transmit FIFO pointer and transmit circuit 211 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 212 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 213 * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. 214 * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. 215 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 216 * | | |0 = RX FIFO threshold interrupt Disabled. 217 * | | |1 = RX FIFO threshold interrupt Enabled. 218 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 219 * | | |0 = TX FIFO threshold interrupt Disabled. 220 * | | |1 = TX FIFO threshold interrupt Enabled. 221 * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit 222 * | | |0 = Receive time-out interrupt Disabled. 223 * | | |1 = Receive time-out interrupt Enabled. 224 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 225 * | | |0 = Receive FIFO overrun interrupt Disabled. 226 * | | |1 = Receive FIFO overrun interrupt Enabled. 227 * |[6] |TXUFPOL |TX Underflow Data Polarity 228 * | | |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode. 229 * | | |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode. 230 * | | |Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 231 * | | |Note 2: When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 232 * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. 233 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 234 * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 235 * | | |This bit is used to enable the TX underflow interrupt. 236 * | | |0 = Slave TX underflow interrupt Disabled. 237 * | | |1 = Slave TX underflow interrupt Enabled. 238 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 239 * | | |0 = No effect. 240 * | | |1 = Clear receive FIFO pointer 241 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 242 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 243 * | | |Note: The RX shift register will not be cleared. 244 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 245 * | | |0 = No effect. 246 * | | |1 = Clear transmit FIFO pointer 247 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 248 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 249 * | | |Note: The TX shift register will not be cleared. 250 * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error 251 * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happen in QSPI slave mode. 252 * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happen in QSPI slave mode 253 * | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. 254 * | | |Note: Slave mode Only 255 * |[26:24] |RXTH |Receive FIFO Threshold 256 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 257 * |[30:28] |TXTH |Transmit FIFO Threshold 258 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 259 * @var QSPI_T::STATUS 260 * Offset: 0x14 QSPI Status Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[0] |BUSY |Busy Status (Read Only) 265 * | | |0 = QSPI controller is in idle state. 266 * | | |1 = QSPI controller is in busy state. 267 * | | |The following lists the bus busy conditions: 268 * | | |a. SPIEN (QSPIx_CTL[0]) = 1 and TXEMPTY = 0. 269 * | | |b. For QSPI Master mode, SPIEN (QSPIx_CTL[0]) = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 270 * | | |c. For QSPI Master mode, SPIEN (QSPIx_CTL[0]) = 1 and RXONLY = 1. 271 * | | |d. For QSPI Slave mode, SPIEN (QSPIx_CTL[0]) = 1 and there is serial clock input into the QSPI core logic when slave select is active. 272 * | | |e. For QSPI Slave mode, SPIEN (QSPIx_CTL[0]) = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 273 * | | |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF 274 * | | |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point. 275 * |[1] |UNITIF |Unit Transfer Interrupt Flag 276 * | | |0 = No transaction has been finished since this bit was cleared to 0. 277 * | | |1 = QSPI controller has finished one unit transfer. 278 * | | |Note: This bit will be cleared by writing 1 to it. 279 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 280 * | | |0 = Slave select active interrupt was cleared or not occurred. 281 * | | |1 = Slave select active interrupt event occurred. 282 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 283 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 284 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 285 * | | |1 = Slave select inactive interrupt event occurred. 286 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 287 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 288 * | | |0 = The slave select line status is 0. 289 * | | |1 = The slave select line status is 1. 290 * | | |Note: This bit is only available in Slave mode 291 * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. 292 * |[5] |SLVTOIF |Slave Time-out Interrupt Flag 293 * | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started 294 * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPIx_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. 295 * | | |0 = Slave time-out is not active. 296 * | | |1 = Slave time-out is active. 297 * | | |Note: This bit will be cleared by writing 1 to it. 298 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 299 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 300 * | | |0 = No Slave mode bit count error event. 301 * | | |1 = Slave mode bit count error event occurred. 302 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 303 * | | |This bit will be cleared by writing 1 to it. 304 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 305 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 306 * | | |0 = No Slave TX under run event. 307 * | | |1 = Slave TX under run event occurred. 308 * | | |Note: This bit will be cleared by writing 1 to it. 309 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 310 * | | |0 = Receive FIFO buffer is not empty. 311 * | | |1 = Receive FIFO buffer is empty. 312 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 313 * | | |0 = Receive FIFO buffer is not full. 314 * | | |1 = Receive FIFO buffer is full. 315 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 316 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 317 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 318 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 319 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 320 * | | |0 = No FIFO is overrun. 321 * | | |1 = Receive FIFO is overrun. 322 * | | |Note: This bit will be cleared by writing 1 to it. 323 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 324 * | | |0 = No receive FIFO time-out event. 325 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode 326 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 327 * | | |Note: This bit will be cleared by writing 1 to it. 328 * |[15] |SPIENSTS |QSPI Enable Status (Read Only) 329 * | | |0 = QSPI controller Disabled. 330 * | | |1 = QSPI controller Enabled. 331 * | | |Note: The QSPI peripheral clock is asynchronous with the system clock 332 * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. 333 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 334 * | | |0 = Transmit FIFO buffer is not empty. 335 * | | |1 = Transmit FIFO buffer is empty. 336 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 337 * | | |0 = Transmit FIFO buffer is not full. 338 * | | |1 = Transmit FIFO buffer is full. 339 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 340 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 341 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 342 * |[19] |TXUFIF |TX Underflow Interrupt Flag 343 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 344 * | | |0 = No effect. 345 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 346 * | | |Note 1: This bit will be cleared by writing 1 to it. 347 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 348 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 349 * | | |0 = The reset function of TXRST or RXRST is done. 350 * | | |1 = Doing the reset function of TXRST or RXRST. 351 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 352 * | | |User can check the status of this bit to monitor the reset function is doing or done. 353 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 354 * | | |This bit field indicates the valid data count of receive FIFO buffer. 355 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 356 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 357 * @var QSPI_T::STATUS2 358 * Offset: 0x18 QSPI Status2 Register 359 * --------------------------------------------------------------------------------------------------- 360 * |Bits |Field |Descriptions 361 * | :----: | :----: | :---- | 362 * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX data 363 * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happened in QSPI slave mode. 364 * | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled. 365 * | | |Note: Slave mode Only and this register will be cleared to 0x0 when user write 0x1 to SLVBEIF (QSPIx_STATUS[6]). 366 * @var QSPI_T::TX 367 * Offset: 0x20 QSPI Data Transmit Register 368 * --------------------------------------------------------------------------------------------------- 369 * |Bits |Field |Descriptions 370 * | :----: | :----: | :---- | 371 * |[31:0] |TX |Data Transmit Register 372 * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers 373 * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode. 374 * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted 375 * | | |If DWIDTH is set to 0x00, the QSPI controller will perform a 32-bit transfer. 376 * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 377 * @var QSPI_T::RX 378 * Offset: 0x30 QSPI Data Receive Register 379 * --------------------------------------------------------------------------------------------------- 380 * |Bits |Field |Descriptions 381 * | :----: | :----: | :---- | 382 * |[31:0] |RX |Data Receive Register (Read Only) 383 * | | |There are 8-level FIFO buffers in this controller 384 * | | |The data receive register holds the data received from QSPI data input pin 385 * | | |If the RXEMPTY (QSPIx_STATUS[8) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 386 */ 387 __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ 388 __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ 389 __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ 390 __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ 391 __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ 392 __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ 393 __I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */ 394 __I uint32_t RESERVE0[1]; 395 __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ 396 __I uint32_t RESERVE1[3]; 397 __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ 398 399 } QSPI_T; 400 401 /** 402 @addtogroup QSPI_CONST QSPI Bit Field Definition 403 Constant Definitions for QSPI Controller 404 @{ */ 405 406 #define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */ 407 #define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */ 408 409 #define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ 410 #define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ 411 412 #define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ 413 #define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ 414 415 #define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ 416 #define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ 417 418 #define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ 419 #define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ 420 421 #define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ 422 #define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ 423 424 #define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ 425 #define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ 426 427 #define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ 428 #define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ 429 430 #define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ 431 #define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ 432 433 #define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ 434 #define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ 435 436 #define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ 437 #define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ 438 439 #define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ 440 #define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ 441 442 #define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ 443 #define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ 444 445 #define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ 446 #define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ 447 448 #define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ 449 #define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ 450 451 #define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ 452 #define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ 453 454 #define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */ 455 #define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */ 456 457 #define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ 458 #define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ 459 460 #define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ 461 #define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ 462 463 #define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ 464 #define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ 465 466 #define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ 467 #define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ 468 469 #define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ 470 #define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ 471 472 #define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ 473 #define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ 474 475 #define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ 476 #define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ 477 478 #define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ 479 #define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ 480 481 #define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ 482 #define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ 483 484 #define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ 485 #define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ 486 487 #define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ 488 #define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ 489 490 #define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ 491 #define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ 492 493 #define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ 494 #define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ 495 496 #define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ 497 #define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ 498 499 #define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ 500 #define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ 501 502 #define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ 503 #define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ 504 505 #define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ 506 #define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ 507 508 #define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ 509 #define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ 510 511 #define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ 512 #define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ 513 514 #define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ 515 #define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ 516 517 #define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ 518 #define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ 519 520 #define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ 521 #define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ 522 523 #define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ 524 #define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ 525 526 #define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ 527 #define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ 528 529 #define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ 530 #define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ 531 532 #define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */ 533 #define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */ 534 535 #define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ 536 #define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ 537 538 #define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ 539 #define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ 540 541 #define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ 542 #define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ 543 544 #define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ 545 #define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ 546 547 #define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ 548 #define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ 549 550 #define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ 551 #define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ 552 553 #define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ 554 #define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ 555 556 #define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ 557 #define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ 558 559 #define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ 560 #define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ 561 562 #define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ 563 #define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ 564 565 #define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ 566 #define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ 567 568 #define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ 569 #define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ 570 571 #define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ 572 #define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ 573 574 #define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ 575 #define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ 576 577 #define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ 578 #define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ 579 580 #define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */ 581 #define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */ 582 583 #define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ 584 #define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ 585 586 #define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ 587 #define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ 588 589 #define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ 590 #define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ 591 592 #define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ 593 #define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ 594 595 #define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ 596 #define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ 597 598 #define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ 599 #define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ 600 601 #define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ 602 #define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ 603 604 #define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */ 605 #define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */ 606 607 #define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ 608 #define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ 609 610 #define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ 611 #define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ 612 613 /**@}*/ /* QSPI_CONST */ 614 /**@}*/ /* end of QSPI register group */ 615 /**@}*/ /* end of REGISTER group */ 616 617 #if defined ( __CC_ARM ) 618 #pragma no_anon_unions 619 #endif 620 621 #endif /* __QSPI_REG_H__ */
