1 /**************************************************************************//** 2 * @file i2c_reg.h 3 * @version V1.00 4 * @brief I2C register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __I2C_REG_H__ 10 #define __I2C_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Inter-IC Bus Controller -------------------------*/ 24 /** 25 @addtogroup I2C Inter-IC Bus Controller(I2C) 26 Memory Mapped Structure for I2C Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var I2C_T::CTL0 35 * Offset: 0x00 I2C Control Register 0 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[2] |AA |Assert Acknowledge Control 40 * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter 41 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line 42 * |[3] |SI |I2C Interrupt Flag 43 * | | |When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware 44 * | | |If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested 45 * | | |SI must be cleared by software 46 * | | |Clear SI by writing 1 to this bit. 47 * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 48 * |[4] |STO |I2C STOP Control 49 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected 50 * | | |This bit will be cleared by hardware automatically. 51 * |[5] |STA |I2C START Control 52 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 53 * |[6] |I2CEN |I2C Controller Enable Bit 54 * | | |Set to enable I2C serial function controller 55 * | | |When I2CEN=1 the I2C serial function enable 56 * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. 57 * | | |0 = I2C controller Disabled. 58 * | | |1 = I2C controller Enabled. 59 * |[7] |INTEN |Enable Interrupt 60 * | | |0 = I2C interrupt Disabled. 61 * | | |1 = I2C interrupt Enabled. 62 * |[9:8] |DPBITSEL |Data Phase Bit Count Select 63 * | | |00 = DPCIF never set by hardware. 64 * | | |01 = When I2C is transfer data and bit count equal to 6, DPCIF will be set by hardware. 65 * | | |10 = When I2C is transfer data and bit count equal to 7, DPCIF will be set by hardware. 66 * | | |11 = When I2C is transfer data and bit count equal to 8, DPCIF will be set by hardware. 67 * |[12] |DPCINTEN |Data Phase Count Interrupt Enable Bit 68 * | | |0 = Data Phase Count Interrupt Disabled. 69 * | | |1 = Data Phase Count Interrupt Enabled. 70 * |[13] |SRCINTEN |Slave Read Command Interrupt Enable Bit 71 * | | |0 = Slave Read Command Interrupt Disabled. 72 * | | |1 = Slave Read Command Interrupt Enabled. 73 * |[14] |DPCIF |Data Phase Count Interrupt Flag 74 * | | |This bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting 75 * | | |This bit is cleared by write 1 to it. 76 * |[15] |SARCIF |Slave Address Read Command Interrupt Flag 77 * | | |This bit is set by hardware when I2C receive address match read command. 78 * | | |This bit is cleared by write 1 to it. 79 * @var I2C_T::ADDR0 80 * Offset: 0x04 I2C Slave Address Register0 81 * --------------------------------------------------------------------------------------------------- 82 * |Bits |Field |Descriptions 83 * | :----: | :----: | :---- | 84 * |[0] |GC |General Call Function 85 * | | |0 = General Call Function Disabled. 86 * | | |1 = General Call Function Enabled. 87 * |[10:1] |ADDR |I2C Address 88 * | | |The content of this register is irrelevant when I2C is in Master mode 89 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 90 * | | |The I2C hardware will react if either of the address is matched. 91 * | | |Note: When software set 10'h000, the address cannot be used. 92 * @var I2C_T::DAT 93 * Offset: 0x08 I2C Data Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[7:0] |DAT |I2C Data 98 * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 99 * @var I2C_T::STATUS0 100 * Offset: 0x0C I2C Status Register 0 101 * --------------------------------------------------------------------------------------------------- 102 * |Bits |Field |Descriptions 103 * | :----: | :----: | :---- | 104 * |[7:0] |STATUS |I2C Status 105 * | | |The three least significant bits are always 0 106 * | | |The five most significant bits contain the status code 107 * | | |There are 28 possible status codes 108 * | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested 109 * | | |Others I2C_STATUS0 values correspond to defined I2C states 110 * | | |When each of these states is entered, a status interrupt is requested (SI = 1) 111 * | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software 112 * | | |In addition, states 00H stands for a Bus Error 113 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame 114 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 115 * @var I2C_T::CLKDIV 116 * Offset: 0x10 I2C Clock Divided Register 117 * --------------------------------------------------------------------------------------------------- 118 * |Bits |Field |Descriptions 119 * | :----: | :----: | :---- | 120 * |[9:0] |DIVIDER |I2C Clock Divided 121 * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (DIVIDER+1)). 122 * | | |Note: The minimum value of DIVIDER is 4. 123 * |[15:12] |NFCNT |Noise Filter Count 124 * | | |The register bits control the input filter width. 125 * | | |If the pulse width is narrower than the setting((3+N)*PCLK), it will be ignored. 126 * | | |0 : filter width 3*PCLK 127 * | | |1 : filter width 4*PCLK 128 * | | |N : filter width (3+N)*PCKL 129 * | | |Note: Filter width Min :3*PCLK, Max : 18*PCLK 130 * @var I2C_T::TOCTL 131 * Offset: 0x14 I2C Time-out Control Register 132 * --------------------------------------------------------------------------------------------------- 133 * |Bits |Field |Descriptions 134 * | :----: | :----: | :---- | 135 * |[0] |TOIF |Time-out Flag 136 * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. 137 * | | |Note: Software can write 1 to clear this bit. 138 * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 139 * | | |When enabled, the time-out period is extended 4 times. 140 * | | |0 = Time-out period is extend 4 times Disabled. 141 * | | |1 = Time-out period is extend 4 times Enabled. 142 * |[2] |TOCEN |Time-out Counter Enable Bit 143 * | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared 144 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 145 * | | |0 = Time-out counter Disabled. 146 * | | |1 = Time-out counter Enabled. 147 * @var I2C_T::ADDR1 148 * Offset: 0x18 I2C Slave Address Register1 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[0] |GC |General Call Function 153 * | | |0 = General Call Function Disabled. 154 * | | |1 = General Call Function Enabled. 155 * |[10:1] |ADDR |I2C Address 156 * | | |The content of this register is irrelevant when I2C is in Master mode 157 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 158 * | | |The I2C hardware will react if either of the address is matched. 159 * | | |Note: When software set 10'h000, the address cannot be used. 160 * @var I2C_T::ADDR2 161 * Offset: 0x1C I2C Slave Address Register2 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[0] |GC |General Call Function 166 * | | |0 = General Call Function Disabled. 167 * | | |1 = General Call Function Enabled. 168 * |[10:1] |ADDR |I2C Address 169 * | | |The content of this register is irrelevant when I2C is in Master mode 170 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 171 * | | |The I2C hardware will react if either of the address is matched. 172 * | | |Note: When software set 10'h000, the address cannot be used. 173 * @var I2C_T::ADDR3 174 * Offset: 0x20 I2C Slave Address Register3 175 * --------------------------------------------------------------------------------------------------- 176 * |Bits |Field |Descriptions 177 * | :----: | :----: | :---- | 178 * |[0] |GC |General Call Function 179 * | | |0 = General Call Function Disabled. 180 * | | |1 = General Call Function Enabled. 181 * |[10:1] |ADDR |I2C Address 182 * | | |The content of this register is irrelevant when I2C is in Master mode 183 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 184 * | | |The I2C hardware will react if either of the address is matched. 185 * | | |Note: When software set 10'h000, the address cannot be used. 186 * @var I2C_T::ADDRMSK0 187 * Offset: 0x24 I2C Slave Address Mask Register0 188 * --------------------------------------------------------------------------------------------------- 189 * |Bits |Field |Descriptions 190 * | :----: | :----: | :---- | 191 * |[10:1] |ADDRMSK |I2C Address Mask 192 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 193 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 194 * | | |I2C bus controllers support multiple address recognition with four address mask register 195 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 196 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 197 * | | |Note: The wake-up function cannot use address mask in 10-bit mode. 198 * @var I2C_T::ADDRMSK1 199 * Offset: 0x28 I2C Slave Address Mask Register1 200 * --------------------------------------------------------------------------------------------------- 201 * |Bits |Field |Descriptions 202 * | :----: | :----: | :---- | 203 * |[10:1] |ADDRMSK |I2C Address Mask 204 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 205 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 206 * | | |I2C bus controllers support multiple address recognition with four address mask register 207 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 208 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 209 * | | |Note: The wake-up function cannot use address mask in 10-bit mode. 210 * @var I2C_T::ADDRMSK2 211 * Offset: 0x2C I2C Slave Address Mask Register2 212 * --------------------------------------------------------------------------------------------------- 213 * |Bits |Field |Descriptions 214 * | :----: | :----: | :---- | 215 * |[10:1] |ADDRMSK |I2C Address Mask 216 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 217 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 218 * | | |I2C bus controllers support multiple address recognition with four address mask register 219 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 220 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 221 * | | |Note: The wake-up function cannot use address mask in 10-bit mode. 222 * @var I2C_T::ADDRMSK3 223 * Offset: 0x30 I2C Slave Address Mask Register3 224 * --------------------------------------------------------------------------------------------------- 225 * |Bits |Field |Descriptions 226 * | :----: | :----: | :---- | 227 * |[10:1] |ADDRMSK |I2C Address Mask 228 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 229 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 230 * | | |I2C bus controllers support multiple address recognition with four address mask register 231 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 232 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 233 * | | |Note: The wake-up function cannot use address mask in 10-bit mode. 234 * @var I2C_T::WKCTL 235 * Offset: 0x3C I2C Wake-up Control Register 236 * --------------------------------------------------------------------------------------------------- 237 * |Bits |Field |Descriptions 238 * | :----: | :----: | :---- | 239 * |[0] |WKEN |I2C Wake-up Enable Bit 240 * | | |0 = I2C wake-up function Disabled. 241 * | | |1= I2C wake-up function Enabled. 242 * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit 243 * | | |0 = I2C hold bus after wake-up. 244 * | | |1= I2C don't hold bus after wake-up. 245 * | | |Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received 246 * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 247 * @var I2C_T::WKSTS 248 * Offset: 0x40 I2C Wake-up Status Register 249 * --------------------------------------------------------------------------------------------------- 250 * |Bits |Field |Descriptions 251 * | :----: | :----: | :---- | 252 * |[0] |WKIF |I2C Wake-up Flag 253 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 254 * | | |Software can write 1 to clear this bit. 255 * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done 256 * | | |0 = The ACK bit cycle of address match frame isn't done. 257 * | | |1 = The ACK bit cycle of address match frame is done in power-down. 258 * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. 259 * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame 260 * | | |0 = Write command be record on the address match wakeup frame. 261 * | | |1 = Read command be record on the address match wakeup frame. 262 * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. 263 * @var I2C_T::CTL1 264 * Offset: 0x44 I2C Control Register 1 265 * --------------------------------------------------------------------------------------------------- 266 * |Bits |Field |Descriptions 267 * | :----: | :----: | :---- | 268 * |[0] |TXPDMAEN |PDMA Transmit Channel Available 269 * | | |0 = Transmit PDMA function Disabled. 270 * | | |1 = Transmit PDMA function Enabled. 271 * |[1] |RXPDMAEN |PDMA Receive Channel Available 272 * | | |0 = Receive PDMA function Disabled. 273 * | | |1 = Receive PDMA function Enabled. 274 * |[2] |PDMARST |PDMA Reset 275 * | | |0 = No effect. 276 * | | |1 = Reset the I2C request to PDMA. 277 * |[3] |OVRIEN |I2C over Run Interrupt Control Bit 278 * | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer. 279 * |[4] |UDRIEN |I2C Under Run Interrupt Control Bit 280 * | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer. 281 * |[5] |TWOBUFEN |Two-level Buffer Enable Bit 282 * | | |0 = Two-level buffer Disabled. 283 * | | |1 = Two-level buffer Enabled. 284 * | | |Set to enable the two-level buffer for I2C transmitted or received buffer 285 * | | |It is used to improve the performance of the I2C bus 286 * |[8] |PDMASTR |PDMA Stretch Bit 287 * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) 288 * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared 289 * | | |(only master TX) 290 * |[9] |ADDR10EN |Address 10-bit Function Enable Bit 291 * | | |0 = Address match 10-bit function Disabled. 292 * | | |1 = Address match 10-bit function Enabled. 293 * |[10] |SWITCHEN |SCL And SDA Pin Switch Enable Bit 294 * | | |0 = I2C use original pin configuration. 295 * | | |1 = I2C switch SCL and SDA pin configuration. 296 * | | |Note: Original pin configuration table is shown in Basic Configuration chapter. 297 * @var I2C_T::STATUS1 298 * Offset: 0x48 I2C Status Register 1 299 * --------------------------------------------------------------------------------------------------- 300 * |Bits |Field |Descriptions 301 * | :----: | :----: | :---- | 302 * |[0] |ADMAT0 |I2C Address 0 Match Status 303 * | | |When address 0 is matched, hardware will inform which address used 304 * | | |This bit will set to 1, and software can write 1 to clear this bit. 305 * |[1] |ADMAT1 |I2C Address 1 Match Status 306 * | | |When address 1 is matched, hardware will inform which address used 307 * | | |This bit will set to 1, and software can write 1 to clear this bit. 308 * |[2] |ADMAT2 |I2C Address 2 Match Status 309 * | | |When address 2 is matched, hardware will inform which address used 310 * | | |This bit will set to 1, and software can write 1 to clear this bit. 311 * |[3] |ADMAT3 |I2C Address 3 Match Status 312 * | | |When address 3 is matched, hardware will inform which address used 313 * | | |This bit will set to 1, and software can write 1 to clear this bit. 314 * |[4] |FULL |TWO-LEVEL BUFFER FULL 315 * | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1. 316 * | | |This bit is set when POINTER is equal to 2 317 * | | |Note: This bit is read only. 318 * |[5] |EMPTY |TWO-LEVEL BUFFER EMPTY 319 * | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1. 320 * | | |This bit is set when POINTER is equal to 0. 321 * | | |Note: This bit is read only. 322 * |[6] |OVR |I2C over Run Status Bit 323 * | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1. 324 * | | |Note: This bit is read only. 325 * |[7] |UDR |I2C Under Run Status Bit 326 * | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1. 327 * | | |Note: This bit is read only. 328 * |[8] |ONBUSY |On Bus Busy (Read Only) 329 * | | |Indicates that a communication is in progress on the bus 330 * | | |It is set by hardware when a START condition is detected 331 * | | |It is cleared by hardware when a STOP condition is detected. 332 * | | |0 = The bus is IDLE (both SCL and SDA High). 333 * | | |1 = The bus is busy. 334 * @var I2C_T::TMCTL 335 * Offset: 0x4C I2C Timing Configure Control Register 336 * --------------------------------------------------------------------------------------------------- 337 * |Bits |Field |Descriptions 338 * | :----: | :----: | :---- | 339 * |[8:0] |STCTL |Setup Time Configure Control 340 * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. 341 * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. 342 * | | |Note: Setup time setting should not make SCL output less than three PCLKs. 343 * |[24:16] |HTCTL |Hold Time Configure Control 344 * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 345 * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. 346 * @var I2C_T::BUSCTL 347 * Offset: 0x50 I2C Bus Management Control Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[0] |ACKMEN |Acknowledge Control by Manual 352 * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 353 * | | |0 = Slave byte control Disabled. 354 * | | |1 = Slave byte control Enabled 355 * | | |The 9th bit can response the ACK or NACK according the received data by user 356 * | | |When the byte is received, stretching the SCL signal low between the 8th and 9th SCL pulse. 357 * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS0 will be fixed as 0xF0 in slave receive condition. 358 * |[1] |PECEN |Packet Error Checking Calculation Enable Bit 359 * | | |0 = Packet Error Checking Calculation Disabled. 360 * | | |1 = Packet Error Checking Calculation Enabled. 361 * | | |Note: When I2C enter power-down mode, the bit should be enabled after wake-up if needed PEC calculation. 362 * |[2] |BMDEN |Bus Management Device Default Address Enable Bit 363 * | | |0 = Device default address Disable 364 * | | |When the address 0'b1100001x comes and either BMDEN or ACKMEN is disabled, the device responses NACK. 365 * | | |1 = Device default address Enabled 366 * | | |When the address 0'b1100001x comes and both BMDEN and ACKMEN are enabled, the device responses ACK. 367 * |[3] |BMHEN |Bus Management Host Enable Bit 368 * | | |0 = Host function Disabled. 369 * | | |1 = Host function Enabled. 370 * |[4] |ALERTEN |Bus Management Alert Enable Bit 371 * | | |Device Mode (BMHEN =0). 372 * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. 373 * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. 374 * | | |Host Mode (BMHEN =1). 375 * | | |0 = BM_ALERT pin not supported. 376 * | | |1 = BM_ALERT pin supported. 377 * |[5] |SCTLOSTS |Suspend/Control Data Output Status 378 * | | |0 = The output of SUSCON pin is low. 379 * | | |1 = The output of SUSCON pin is high. 380 * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit 381 * | | |0 = The SUSCON pin in input. 382 * | | |1 = The output enable is active on the SUSCON pin. 383 * |[7] |BUSEN |BUS Enable Bit 384 * | | |0 = The system management function Disabled. 385 * | | |1 = The system management function Enabled. 386 * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 387 * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception 388 * | | |0 = No PEC transfer. 389 * | | |1 = PEC transmission is requested. 390 * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0. 391 * |[9] |TIDLE |Timer Check in Idle State 392 * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle 393 * | | |This bit is used to define which condition is enabled. 394 * | | |0 = BUSTOUT is used to calculate the clock low period in bus active. 395 * | | |1 = BUSTOUT is used to calculate the IDLE period in bus Idle. 396 * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 397 * |[10] |PECCLR |PEC Clear at Repeat Start 398 * | | |The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected 399 * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 400 * | | |0 = PEC calculation is cleared by "Repeat Start" function Disabled. 401 * | | |1 = PEC calculation is cleared by "Repeat Start" function Enabled. 402 * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt 403 * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. 404 * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. 405 * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit 406 * | | |0 = Byte count done interrupt Disabled. 407 * | | |1 = Byte count done interrupt Enabled. 408 * | | |Note: This bit is used in PECEN =1. 409 * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit 410 * | | |0 = PEC transfer done interrupt Disabled. 411 * | | |1 = PEC transfer done interrupt Enabled. 412 * | | |Note: This bit is used in PECEN =1. 413 * @var I2C_T::BUSTCTL 414 * Offset: 0x54 I2C Bus Management Timer Control Register 415 * --------------------------------------------------------------------------------------------------- 416 * |Bits |Field |Descriptions 417 * | :----: | :----: | :---- | 418 * |[0] |BUSTOEN |Bus Time Out Enable Bit 419 * | | |0 = Bus clock low time-out detection Disabled. 420 * | | |1 = Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in TIDLE=0) or high more than BUSTO (in TIDLE =1) 421 * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit 422 * | | |0 = Cumulative clock low time-out detection Disabled. 423 * | | |1 = Cumulative clock low time-out detection Enabled. 424 * | | |For Master, it calculates the period from START to ACK 425 * | | |For Slave, it calculates the period from START to STOP 426 * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit 427 * | | |BUSY =1. 428 * | | |0 = SCL low time-out interrupt Disabled. 429 * | | |1 = SCL low time-out interrupt Enabled. 430 * | | |BUSY =0. 431 * | | |0 = Bus IDLE time-out interrupt Disabled. 432 * | | |1 = Bus IDLE time-out interrupt Enabled. 433 * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit 434 * | | |0 = Clock time out interrupt Disabled. 435 * | | |1 = Clock time out interrupt Enabled. 436 * |[4] |TORSTEN |Time Out Reset Enable Bit 437 * | | |0 = I2C state machine reset Disabled. 438 * | | |1 = I2C state machine reset Enabled. (The clock and data bus will be released to high) 439 * @var I2C_T::BUSSTS 440 * Offset: 0x58 I2C Bus Management Status Register 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[0] |BUSY |Bus Busy 445 * | | |Indicates that a communication is in progress on the bus 446 * | | |It is set by hardware when a START condition is detected 447 * | | |It is cleared by hardware when a STOP condition is detected 448 * | | |0 = Bus is IDLE (both SCL and SDA High). 449 * | | |1 = Bus is busy. 450 * |[1] |BCDONE |Byte Count Transmission/Receive Done 451 * | | |0 = Byte count transmission/ receive is not finished when the PECEN is set. 452 * | | |1 = Byte count transmission/ receive is finished when the PECEN is set. 453 * | | |Note: Software can write 1 to clear this bit. 454 * |[2] |PECERR |PEC Error in Reception 455 * | | |0 = PEC value equal the received PEC data packet. 456 * | | |1 = PEC value doesn't match the receive PEC data packet. 457 * | | |Note: Software can write 1 to clear this bit. 458 * |[3] |ALERT |SMBus Alert Status 459 * | | |Device Mode (BMHEN =0). 460 * | | |0 = SMBALERT pin state is low. 461 * | | |1 = SMBALERT pin state is high. 462 * | | |Host Mode (BMHEN =1). 463 * | | |0 = No SMBALERT event. 464 * | | |1 = There is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. 465 * | | |Note: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system 466 * | | |2. Software can write 1 to clear this bit. 467 * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status 468 * | | |0 = The input status of SUSCON pin is 0. 469 * | | |1 = The input status of SUSCON pin is 1. 470 * |[5] |BUSTO |Bus Time-out Status 471 * | | |0 = There is no any time-out or external clock time-out. 472 * | | |1 = A time-out or external clock time-out occurred. 473 * | | |In bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred. 474 * | | |Note: Software can write 1 to clear this bit. 475 * |[6] |CLKTO |Clock Low Cumulate Time-out Status 476 * | | |0 = Cumulative clock low is no any time-out. 477 * | | |1 = Cumulative clock low time-out occurred. 478 * | | |Note: Software can write 1 to clear this bit. 479 * |[7] |PECDONE |PEC Byte Transmission/Receive Done 480 * | | |0 = PEC transmission/ receive is not finished when the PECEN is set. 481 * | | |1 = PEC transmission/ receive is finished when the PECEN is set. 482 * | | |Note: Software can write 1 to clear this bit. 483 * @var I2C_T::PKTSIZE 484 * Offset: 0x5C I2C Packet Error Checking Byte Number Register 485 * --------------------------------------------------------------------------------------------------- 486 * |Bits |Field |Descriptions 487 * | :----: | :----: | :---- | 488 * |[8:0] |PLDSIZE |Transfer Byte Number 489 * | | |The transmission or receive byte number in one transaction when the PECEN is set 490 * | | |The maximum transaction or receive byte is 256 Bytes. 491 * | | |Note: The byte number counting includes address, command code, and data frame. 492 * @var I2C_T::PKTCRC 493 * Offset: 0x60 I2C Packet Error Checking Byte Value Register 494 * --------------------------------------------------------------------------------------------------- 495 * |Bits |Field |Descriptions 496 * | :----: | :----: | :---- | 497 * |[7:0] |PECCRC |Packet Error Checking Byte Value 498 * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 499 * | | |It is read only. 500 * @var I2C_T::BUSTOUT 501 * Offset: 0x64 I2C Bus Management Timer Register 502 * --------------------------------------------------------------------------------------------------- 503 * |Bits |Field |Descriptions 504 * | :----: | :----: | :---- | 505 * |[7:0] |BUSTO |Bus Management Time-out Value 506 * | | |Indicates the bus time-out value in bus is IDLE or SCL low. 507 * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first when the BUSEN(I2C_BUSCTL[7]) is set. 508 * @var I2C_T::CLKTOUT 509 * Offset: 0x68 I2C Bus Management Clock Low Timer Register 510 * --------------------------------------------------------------------------------------------------- 511 * |Bits |Field |Descriptions 512 * | :----: | :----: | :---- | 513 * |[7:0] |CLKTO |Bus Clock Low Timer 514 * | | |The field is used to configure the cumulative clock extension time-out. 515 * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and cleared to 0 first when the BUSEN is set. 516 */ 517 __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ 518 __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ 519 __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ 520 __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ 521 __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ 522 __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ 523 __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ 524 __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ 525 __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ 526 __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ 527 __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ 528 __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ 529 __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ 530 __I uint32_t RESERVE0[2]; 531 __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ 532 __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ 533 __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ 534 __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ 535 __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ 536 __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ 537 __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ 538 __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ 539 __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ 540 __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ 541 __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ 542 __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ 543 544 } I2C_T; 545 546 /** 547 @addtogroup I2C_CONST I2C Bit Field Definition 548 Constant Definitions for I2C Controller 549 @{ */ 550 551 #define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */ 552 #define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */ 553 554 #define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */ 555 #define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */ 556 557 #define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */ 558 #define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */ 559 560 #define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */ 561 #define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */ 562 563 #define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */ 564 #define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */ 565 566 #define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */ 567 #define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */ 568 569 #define I2C_CTL0_DPBITSEL_Pos (8) /*!< I2C_T::CTL0: DPBITSEL Position */ 570 #define I2C_CTL0_DPBITSEL_Msk (0x3ul << I2C_CTL0_DPBITSEL_Pos) /*!< I2C_T::CTL0: DPBITSEL Mask */ 571 572 #define I2C_CTL0_DPCINTEN_Pos (12) /*!< I2C_T::CTL0: DPCINTEN Position */ 573 #define I2C_CTL0_DPCINTEN_Msk (0x1ul << I2C_CTL0_DPCINTEN_Pos) /*!< I2C_T::CTL0: DPCINTEN Mask */ 574 575 #define I2C_CTL0_SRCINTEN_Pos (13) /*!< I2C_T::CTL0: SRCINTEN Position */ 576 #define I2C_CTL0_SRCINTEN_Msk (0x1ul << I2C_CTL0_SRCINTEN_Pos) /*!< I2C_T::CTL0: SRCINTEN Mask */ 577 578 #define I2C_CTL0_DPCIF_Pos (14) /*!< I2C_T::CTL0: DPCIF Position */ 579 #define I2C_CTL0_DPCIF_Msk (0x1ul << I2C_CTL0_DPCIF_Pos) /*!< I2C_T::CTL0: DPCIF Mask */ 580 581 #define I2C_CTL0_SARCIF_Pos (15) /*!< I2C_T::CTL0: SARCIF Position */ 582 #define I2C_CTL0_SARCIF_Msk (0x1ul << I2C_CTL0_SARCIF_Pos) /*!< I2C_T::CTL0: SARCIF Mask */ 583 584 #define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ 585 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ 586 587 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ 588 #define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ 589 590 #define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ 591 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ 592 593 #define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */ 594 #define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */ 595 596 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ 597 #define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ 598 599 #define I2C_CLKDIV_NFCNT_Pos (12) /*!< I2C_T::CLKDIV: NFCNT Position */ 600 #define I2C_CLKDIV_NFCNT_Msk (0xful << I2C_CLKDIV_NFCNT_Pos) /*!< I2C_T::CLKDIV: NFCNT Mask */ 601 602 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ 603 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ 604 605 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ 606 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ 607 608 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ 609 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ 610 611 #define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ 612 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ 613 614 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ 615 #define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ 616 617 #define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ 618 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ 619 620 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ 621 #define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ 622 623 #define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ 624 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ 625 626 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ 627 #define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ 628 629 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ 630 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ 631 632 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ 633 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ 634 635 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ 636 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ 637 638 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ 639 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ 640 641 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ 642 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ 643 644 #define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ 645 #define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ 646 647 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ 648 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ 649 650 #define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ 651 #define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ 652 653 #define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ 654 #define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ 655 656 #define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ 657 #define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ 658 659 #define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ 660 #define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ 661 662 #define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ 663 #define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ 664 665 #define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */ 666 #define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */ 667 668 #define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */ 669 #define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */ 670 671 #define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */ 672 #define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */ 673 674 #define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ 675 #define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ 676 677 #define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ 678 #define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ 679 680 #define I2C_CTL1_SWITCHEN_Pos (10) /*!< I2C_T::CTL1: SWITCHEN Position */ 681 #define I2C_CTL1_SWITCHEN_Msk (0x1ul << I2C_CTL1_SWITCHEN_Pos) /*!< I2C_T::CTL1: SWITCHEN Mask */ 682 683 #define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ 684 #define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ 685 686 #define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ 687 #define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ 688 689 #define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ 690 #define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ 691 692 #define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ 693 #define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ 694 695 #define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */ 696 #define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */ 697 698 #define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */ 699 #define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */ 700 701 #define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */ 702 #define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */ 703 704 #define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */ 705 #define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */ 706 707 #define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ 708 #define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ 709 710 #define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ 711 #define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ 712 713 #define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ 714 #define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ 715 716 #define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ 717 #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ 718 719 #define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ 720 #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ 721 722 #define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ 723 #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ 724 725 #define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ 726 #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ 727 728 #define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ 729 #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ 730 731 #define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ 732 #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ 733 734 #define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ 735 #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ 736 737 #define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ 738 #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ 739 740 #define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ 741 #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ 742 743 #define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ 744 #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ 745 746 #define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ 747 #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ 748 749 #define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ 750 #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ 751 752 #define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ 753 #define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ 754 755 #define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ 756 #define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ 757 758 #define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ 759 #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ 760 761 #define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ 762 #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ 763 764 #define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ 765 #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ 766 767 #define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ 768 #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ 769 770 #define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ 771 #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ 772 773 #define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ 774 #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ 775 776 #define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ 777 #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ 778 779 #define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ 780 #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ 781 782 #define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ 783 #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ 784 785 #define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ 786 #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ 787 788 #define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ 789 #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ 790 791 #define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ 792 #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ 793 794 #define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ 795 #define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ 796 797 #define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ 798 #define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ 799 800 #define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ 801 #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ 802 803 #define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ 804 #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ 805 806 #define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ 807 #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ 808 809 /**@}*/ /* I2C_CONST */ 810 /**@}*/ /* end of I2C register group */ 811 /**@}*/ /* end of REGISTER group */ 812 813 #if defined ( __CC_ARM ) 814 #pragma no_anon_unions 815 #endif 816 817 #endif /* __I2C_REG_H__ */
