1 /**************************************************************************//** 2 * @file ecap_reg.h 3 * @version V1.00 4 * @brief ECAP register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __ECAP_REG_H__ 10 #define __ECAP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup ECAP Enhanced Input Capture Timer(ECAP) 23 Memory Mapped Structure for ECAP Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var ECAP_T::CNT 32 * Offset: 0x00 Input Capture Counter (24-bit Up Counter) 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[23:0] |CNT |Input Capture Timer/Counter 37 * | | |The input Capture Timer/Counter is a 24-bit up-counting counter 38 * | | |The clock source for the counter is from the clock divider 39 * @var ECAP_T::HLD0 40 * Offset: 0x04 Input Capture Hold Register 0 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[23:0] |HOLD |Input Capture Counter Hold Register 45 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register 46 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 47 * @var ECAP_T::HLD1 48 * Offset: 0x08 Input Capture Hold Register 1 49 * --------------------------------------------------------------------------------------------------- 50 * |Bits |Field |Descriptions 51 * | :----: | :----: | :---- | 52 * |[23:0] |HOLD |Input Capture Counter Hold Register 53 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register 54 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 55 * @var ECAP_T::HLD2 56 * Offset: 0x0C Input Capture Hold Register 2 57 * --------------------------------------------------------------------------------------------------- 58 * |Bits |Field |Descriptions 59 * | :----: | :----: | :---- | 60 * |[23:0] |HOLD |Input Capture Counter Hold Register 61 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register 62 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. 63 * @var ECAP_T::CNTCMP 64 * Offset: 0x10 Input Capture Compare Register 65 * --------------------------------------------------------------------------------------------------- 66 * |Bits |Field |Descriptions 67 * | :----: | :----: | :---- | 68 * |[23:0] |CNTCMP |Input Capture Counter Compare Register 69 * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). 70 * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. 71 * @var ECAP_T::CTL0 72 * Offset: 0x14 Input Capture Control Register 0 73 * --------------------------------------------------------------------------------------------------- 74 * |Bits |Field |Descriptions 75 * | :----: | :----: | :---- | 76 * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection 77 * | | |To determine the sampling frequency of the Noise Filter clock 78 * | | |000 = ECAP_CLK. 79 * | | |001 = ECAP_CLK/2. 80 * | | |010 = ECAP_CLK/4. 81 * | | |011 = ECAP_CLK/16. 82 * | | |100 = ECAP_CLK/32. 83 * | | |101 = ECAP_CLK/64. 84 * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Bit 85 * | | |0 = Noise filter of Input Capture Enabled. 86 * | | |1 = Noise filter of Input Capture Disabled (Bypass). 87 * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Bit 88 * | | |0 = IC0 input to Input Capture Unit Disabled. 89 * | | |1 = IC0 input to Input Capture Unit Enabled. 90 * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Bit 91 * | | |0 = IC1 input to Input Capture Unit Disabled. 92 * | | |1 = IC1 input to Input Capture Unit Enabled. 93 * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Bit 94 * | | |0 = IC2 input to Input Capture Unit Disabled. 95 * | | |1 = IC2 input to Input Capture Unit Enabled. 96 * |[9:8] |CAPSEL0 |CAP0 Input Source Selection 97 * | | |00 = CAP0 input is from port pin ICAP0. 98 * | | |01 = CAP0 input is from signal ACMP0_O. 99 * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. 100 * | | |11 = Reserved. 101 * | | |Note: Input capture unit n matches QEIn, where n = 0~1. 102 * |[11:10] |CAPSEL1 |CAP1 Input Source Selection 103 * | | |00 = CAP1 input is from port pin ICAP1. 104 * | | |01 = CAP1 input is from signal ACMP1_O. 105 * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. 106 * | | |11 = Reserved. 107 * | | |Note: Input capture unit n matches QEIn, where n = 0~1. 108 * |[13:12] |CAPSEL2 |CAP2 Input Source Selection 109 * | | |00 = CAP2 input is from port pin ICAP2. 110 * | | |01 = CAP2 input is from signal ACMP2_O. 111 * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. 112 * | | |11 = Reserved. 113 * | | |Note: Input capture unit n matches QEIn, where n = 0~1. 114 * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Bit 115 * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. 116 * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. 117 * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Bit 118 * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. 119 * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. 120 * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Bit 121 * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. 122 * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. 123 * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Bit 124 * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. 125 * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. 126 * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Bit 127 * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. 128 * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. 129 * |[24] |CNTEN |Input Capture Counter Start Counting Control 130 * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . 131 * | | |0 = ECAP_CNT stop counting. 132 * | | |1 = ECAP_CNT starts up-counting. 133 * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control 134 * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. 135 * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. 136 * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. 137 * |[28] |CMPEN |Compare Function Enable Bit 138 * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. 139 * | | |0 = The compare function Disabled. 140 * | | |1 = The compare function Enabled. 141 * |[29] |CAPEN |Input Capture Timer/Counter Enable Bit 142 * | | |0 = Input Capture function Disabled. 143 * | | |1 = Input Capture function Enabled. 144 * @var ECAP_T::CTL1 145 * Offset: 0x18 Input Capture Control Register 1 146 * --------------------------------------------------------------------------------------------------- 147 * |Bits |Field |Descriptions 148 * | :----: | :----: | :---- | 149 * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection 150 * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change 151 * | | |00 = Detect rising edge only. 152 * | | |01 = Detect falling edge only. 153 * | | |1x = Detect both rising and falling edge. 154 * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection 155 * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change 156 * | | |00 = Detect rising edge only. 157 * | | |01 = Detect falling edge only. 158 * | | |1x = Detect both rising and falling edge. 159 * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection 160 * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes 161 * | | |00 = Detect rising edge only. 162 * | | |01 = Detect falling edge only. 163 * | | |1x = Detect both rising and falling edge. 164 * |[8] |CAP0RLDEN |Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit 165 * | | |0 = The reload triggered by Event CAPTE0 Disabled. 166 * | | |1 = The reload triggered by Event CAPTE0 Enabled. 167 * |[9] |CAP1RLDEN |Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit 168 * | | |0 = The reload triggered by Event CAPTE1 Disabled. 169 * | | |1 = The reload triggered by Event CAPTE1 Enabled. 170 * |[10] |CAP2RLDEN |Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit 171 * | | |0 = The reload triggered by Event CAPTE2 Disabled. 172 * | | |1 = The reload triggered by Event CAPTE2 Enabled. 173 * |[11] |OVRLDEN |Capture Counter's Reload Function Triggered by Overflow Enable Bit 174 * | | |0 = The reload triggered by CAPOV Disabled. 175 * | | |1 = The reload triggered by CAPOV Enabled. 176 * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection 177 * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. 178 * | | |000 = ECAP_CLK/1. 179 * | | |001 = ECAP_CLK/4. 180 * | | |010 = ECAP_CLK/16. 181 * | | |011 = ECAP_CLK/32. 182 * | | |100 = ECAP_CLK/64. 183 * | | |101 = ECAP_CLK/96. 184 * | | |110 = ECAP_CLK/112. 185 * | | |111 = ECAP_CLK/128. 186 * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection 187 * | | |Select the capture timer/counter clock source. 188 * | | |00 = ECAP_CLK (default). 189 * | | |01 = CAP0. 190 * | | |10 = CAP1. 191 * | | |11 = CAP2. 192 * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control 193 * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. 194 * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. 195 * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control 196 * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. 197 * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. 198 * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control 199 * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. 200 * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. 201 * @var ECAP_T::STATUS 202 * Offset: 0x1C Input Capture Status Register 203 * --------------------------------------------------------------------------------------------------- 204 * |Bits |Field |Descriptions 205 * | :----: | :----: | :---- | 206 * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag 207 * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. 208 * | | |0 = No valid edge change has been detected at CAP0 input since last clear. 209 * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. 210 * | | |Note: This bit is only cleared by writing 1 to it. 211 * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag 212 * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. 213 * | | |0 = No valid edge change has been detected at CAP1 input since last clear. 214 * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. 215 * | | |Note: This bit is only cleared by writing 1 to it. 216 * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag 217 * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. 218 * | | |0 = No valid edge change has been detected at CAP2 input since last clear. 219 * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. 220 * | | |Note: This bit is only cleared by writing 1 to it. 221 * |[4] |CAPCMPF |Input Capture Compare-match Flag 222 * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. 223 * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. 224 * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. 225 * | | |Note: This bit is only cleared by writing 1 to it. 226 * |[5] |CAPOVF |Input Capture Counter Overflow Flag 227 * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to 0. 228 * | | |0 = No overflow event has occurred since last clear. 229 * | | |1 = Overflow event(s) has/have occurred since last clear. 230 * | | |Note: This bit is only cleared by writing 1 to it. 231 * |[8] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) 232 * | | |Reflecting the value of input channel 0, CAP0 233 * | | |Note: The bit is read only and write is ignored. 234 * |[9] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) 235 * | | |Reflecting the value of input channel 1, CAP1 236 * | | |Note: The bit is read only and write is ignored. 237 * |[10] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) 238 * | | |Reflecting the value of input channel 2, CAP2. 239 * | | |Note: The bit is read only and write is ignored. 240 */ 241 __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter (24-bit Up Counter) */ 242 __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ 243 __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ 244 __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ 245 __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ 246 __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ 247 __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ 248 __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ 249 250 } ECAP_T; 251 252 /** 253 @addtogroup ECAP_CONST ECAP Bit Field Definition 254 Constant Definitions for ECAP Controller 255 @{ */ 256 257 #define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ 258 #define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ 259 260 #define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ 261 #define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ 262 263 #define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ 264 #define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ 265 266 #define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ 267 #define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ 268 269 #define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ 270 #define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ 271 272 #define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ 273 #define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ 274 275 #define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ 276 #define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ 277 278 #define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ 279 #define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ 280 281 #define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ 282 #define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ 283 284 #define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ 285 #define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ 286 287 #define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ 288 #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ 289 290 #define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ 291 #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ 292 293 #define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ 294 #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ 295 296 #define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ 297 #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ 298 299 #define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ 300 #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ 301 302 #define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ 303 #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ 304 305 #define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ 306 #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ 307 308 #define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ 309 #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ 310 311 #define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ 312 #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ 313 314 #define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ 315 #define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ 316 317 #define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ 318 #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ 319 320 #define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ 321 #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ 322 323 #define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ 324 #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ 325 326 #define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ 327 #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ 328 329 #define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ 330 #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ 331 332 #define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ 333 #define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ 334 335 #define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ 336 #define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ 337 338 #define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ 339 #define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ 340 341 #define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ 342 #define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ 343 344 #define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ 345 #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ 346 347 #define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ 348 #define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ 349 350 #define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ 351 #define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ 352 353 #define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ 354 #define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ 355 356 #define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ 357 #define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ 358 359 #define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ 360 #define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ 361 362 #define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ 363 #define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ 364 365 #define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ 366 #define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ 367 368 #define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ 369 #define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ 370 371 #define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ 372 #define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ 373 374 #define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ 375 #define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ 376 377 #define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ 378 #define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ 379 380 #define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ 381 #define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ 382 383 /**@}*/ /* ECAP_CONST */ 384 /**@}*/ /* end of ECAP register group */ 385 /**@}*/ /* end of REGISTER group */ 386 387 #if defined ( __CC_ARM ) 388 #pragma no_anon_unions 389 #endif 390 391 #endif /* __ECAP_REG_H__ */ 392
