1 /**************************************************************************//** 2 * @file dac_reg.h 3 * @version V1.00 4 * @brief DAC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 * 9 *****************************************************************************/ 10 #ifndef __DAC_REG_H__ 11 #define __DAC_REG_H__ 12 13 #if defined ( __CC_ARM ) 14 #pragma anon_unions 15 #endif 16 17 /** 18 @addtogroup REGISTER Control Register 19 @{ 20 */ 21 22 /** 23 @addtogroup DAC Digital to Analog Converter(DAC) 24 Memory Mapped Structure for DAC Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var DAC_T::CTL 33 * Offset: 0x00 DAC0 Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |DACEN |DAC Enable Bit 38 * | | |0 = DAC Disabled. 39 * | | |1 = DAC Enabled. 40 * |[1] |DACIEN |DAC Interrupt Enable Bit 41 * | | |0 = DAC interrupt Disabled. 42 * | | |1 = DAC interrupt Enabled. 43 * |[2] |DMAEN |DMA Mode Enable Bit 44 * | | |0 = DMA mode Disabled. 45 * | | |1 = DMA mode Enabled. 46 * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit 47 * | | |0 = DMA under-run interrupt Disabled. 48 * | | |1 = DMA under-run interrupt Enabled. 49 * |[4] |TRGEN |Trigger Mode Enable Bit 50 * | | |0 = DAC event trigger mode Disabled. 51 * | | |1 = DAC event trigger mode Enabled. 52 * |[8:5] |TRGSEL |Trigger Source Selection 53 * | | |0000 = Software trigger. 54 * | | |0001 = External pin DAC0_ST trigger. 55 * | | |0010 = Timer 0 trigger. 56 * | | |0011 = Timer 1 trigger. 57 * | | |0100 = Timer 2 trigger. 58 * | | |0101 = Timer 3 trigger. 59 * | | |0110 = EPWM0 trigger. 60 * | | |0111 = EPWM1 trigger. 61 * | | |1000 = PWM0 trigger. 62 * | | |1001 = PWM1 trigger. 63 * |[10] |LALIGN |DAC Data Left-aligned Enabled Bit 64 * | | |0 = Right alignment. 65 * | | |1 = Left alignment. 66 * |[13:12] |ETRGSEL |External Pin Trigger Selection 67 * | | |00 = Low level trigger. 68 * | | |01 = High level trigger. 69 * | | |10 = Falling edge trigger. 70 * | | |11 = Rising edge trigger. 71 * |[15:14] |BWSEL |DAC Data Bit-width Selection 72 * | | |00 = data is 12 bits. 73 * | | |01 = data is 8 bits. 74 * | | |Others = reserved. 75 * |[16] |GRPEN |DAC Group Mode Enable Bit 76 * | | |0 = DAC0 and DAC1 are not grouped. 77 * | | |1 = DAC0 and DAC1 are grouped. 78 * |[17] |GPIOEN |GPIO Mode Enable Bit 79 * | | |0 = GPIO PIN can output DAC0_OUT voltage. 80 * | | |1 = GPIO PIN can be used as other MFP. 81 * |[18] |BYPASS |Bypass Buffer Mode 82 * | | |0 = Output voltage buffer Enabled. 83 * | | |1 = Output voltage buffer Disabled. 84 * @var DAC_T::SWTRG 85 * Offset: 0x04 DAC0 Software Trigger Control Register 86 * --------------------------------------------------------------------------------------------------- 87 * |Bits |Field |Descriptions 88 * | :----: | :----: | :---- | 89 * |[0] |SWTRG |Software Trigger 90 * | | |0 = Software trigger Disabled. 91 * | | |1 = Software trigger Enabled. 92 * | | |Note: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; reading this bit will always get 0. 93 * @var DAC_T::DAT 94 * Offset: 0x08 DAC0 Data Holding Register 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[15:0] |DACDAT |DAC0 12-bit Holding Data 99 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output 100 * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 101 * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 102 * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 103 * @var DAC_T::DATOUT 104 * Offset: 0x0C DAC0 Data Output Register 105 * --------------------------------------------------------------------------------------------------- 106 * |Bits |Field |Descriptions 107 * | :----: | :----: | :---- | 108 * |[11:0] |DATOUT |DAC 12-bit Output Data 109 * | | |These bits are current digital data for DAC output conversion. 110 * | | |It is loaded from DAC_DAT register and user cannot write it directly. 111 * @var DAC_T::STATUS 112 * Offset: 0x10 DAC0 Status Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[0] |FINISH |DAC Conversion Complete Finish Flag 117 * | | |0 = DAC is in conversion state. 118 * | | |1 = DAC conversion finish. 119 * | | |Note: This bit is set to 1 when conversion time counter counts to SETTLET 120 * | | |It is cleared to 0 when DAC starts a new conversion 121 * | | |User writes 1 to clear this bit to 0. 122 * |[1] |DMAUDR |DMA Under-run Interrupt Flag 123 * | | |0 = No DMA under-run error condition occurred. 124 * | | |1 = DMA under-run error condition occurred. 125 * | | |Note: User writes 1 to clear this bit. 126 * |[8] |BUSY |DAC Busy Flag (Read Only) 127 * | | |0 = DAC is ready for next conversion. 128 * | | |1 = DAC is busy in conversion. 129 * @var DAC_T::TCTL 130 * Offset: 0x14 DAC0 Timing Control Register 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[9:0] |SETTLET |DAC Output Settling Time 135 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. 136 * | | |For example, DAC controller clock speed is 72 MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x48. 137 * | | |SELTTLET = DAC controller clock speed x settling time. 138 * @var DAC_T::GRPDAT 139 * Offset: 0x30 DAC Group Mode Data Holding Register 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[15:0] |DAC0DAT |DAC0 12-bit Holding Data 144 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output 145 * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 146 * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. 147 * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. 148 * | | |Note: In group mode, the advantage of writing 12-bit conversion data in DAC_GRPDAT[15:0] is that can share one PDMA transfer mechanism. 149 * | | |Note: After set GRPEN(DAC0_CTL[16]), user can write 12-bit conversion data for DAC0 in DAC_GRPDAT[15:0] 150 * |[31:16] |DAC1DAT |DAC1 12-bit Holding Data 151 * | | |In group mode, user can write these bits for DAC1 12-bit conversion data 152 * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 153 * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. 154 * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. 155 * | | |Note: In group mode, the advantage of writing 12-bit conversion data in DAC_GRPDAT[31:16] is that can share one PDMA transfer mechanism. 156 * | | |Note: After set GRPEN(DAC0_CTL[16]), user can write 12-bit conversion data for DAC1 in DAC_GRPDAT[31:16] 157 */ 158 __IO uint32_t CTL; /*!< [0x0000] DAC0 Control Register */ 159 __IO uint32_t SWTRG; /*!< [0x0004] DAC0 Software Trigger Control Register */ 160 __IO uint32_t DAT; /*!< [0x0008] DAC0 Data Holding Register */ 161 __I uint32_t DATOUT; /*!< [0x000c] DAC0 Data Output Register */ 162 __IO uint32_t STATUS; /*!< [0x0010] DAC0 Status Register */ 163 __IO uint32_t TCTL; /*!< [0x0014] DAC0 Timing Control Register */ 164 __I uint32_t RESERVE0[6]; 165 __IO uint32_t GRPDAT; /*!< [0x0030] DAC Group Mode Data Holding Register */ 166 } DAC_T; 167 168 /** 169 @addtogroup DAC_CONST DAC Bit Field Definition 170 Constant Definitions for DAC Controller 171 @{ */ 172 173 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ 174 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ 175 176 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ 177 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ 178 179 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ 180 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ 181 182 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ 183 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ 184 185 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ 186 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ 187 188 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ 189 #define DAC_CTL_TRGSEL_Msk (0xful << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ 190 191 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ 192 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ 193 194 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ 195 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ 196 197 #define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ 198 #define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ 199 200 #define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ 201 #define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ 202 203 #define DAC_CTL_GPIOEN_Pos (17) /*!< DAC_T::CTL: GPIOEN Position */ 204 #define DAC_CTL_GPIOEN_Msk (0x1ul << DAC_CTL_GPIOEN_Pos) /*!< DAC_T::CTL: GPIOEN Mask */ 205 206 #define DAC_CTL_BYPASS_Pos (18) /*!< DAC_T::CTL: BYPASS Position */ 207 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ 208 209 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ 210 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ 211 212 #define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ 213 #define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ 214 215 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ 216 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ 217 218 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ 219 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ 220 221 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ 222 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ 223 224 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ 225 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ 226 227 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ 228 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ 229 230 #define DAC_GRPDAT_DAC0DAT_Pos (0) /*!< DAC_T::GRPDAT: DAC0DAT Position */ 231 #define DAC_GRPDAT_DAC0DAT_Msk (0xfffful << DAC_GRPDAT_DAC0DAT_Pos) /*!< DAC_T::GRPDAT: DAC0DAT Mask */ 232 233 #define DAC_GRPDAT_DAC1DAT_Pos (16) /*!< DAC_T::GRPDAT: DAC1DAT Position */ 234 #define DAC_GRPDAT_DAC1DAT_Msk (0xfffful << DAC_GRPDAT_DAC1DAT_Pos) /*!< DAC_T::GRPDAT: DAC1DAT Mask */ 235 236 /**@}*/ /* DAC_CONST */ 237 /**@}*/ /* end of DAC register group */ 238 /**@}*/ /* end of REGISTER group */ 239 240 #if defined ( __CC_ARM ) 241 #pragma no_anon_unions 242 #endif 243 244 #endif /* __DAC_REG_H__ */ 245
