1 /**************************************************************************//** 2 * @file crpt_reg.h 3 * @version V1.00 4 * @brief CRPT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRPT_REG_H__ 10 #define __CRPT_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Cryptographic Accelerator -------------------------*/ 21 /** 22 @addtogroup CRPT Cryptographic Accelerator(CRPT) 23 Memory Mapped Structure for CRPT Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var CRPT_T::INTEN 33 * Offset: 0x00 Crypto Interrupt Enable Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |AESIEN |AES Interrupt Enable Bit 38 * | | |0 = AES interrupt Disabled. 39 * | | |1 = AES interrupt Enabled. 40 * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in AES_DMA_CNT is fed into the AES engine. 41 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. 42 * |[1] |AESEIEN |AES Error Flag Enable Bit 43 * | | |0 = AES error interrupt flag Disabled. 44 * | | |1 = AES error interrupt flag Enabled. 45 * |[16] |PRNGIEN |PRNG Interrupt Enable Bit 46 * | | |0 = PRNG interrupt Disabled. 47 * | | |1 = PRNG interrupt Enabled. 48 * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit 49 * | | |0 = PRNG error interrupt flag Disabled. 50 * | | |1 = PRNG error interrupt flag Enabled. 51 * @var CRPT_T::INTSTS 52 * Offset: 0x04 Crypto Interrupt Flag 53 * --------------------------------------------------------------------------------------------------- 54 * |Bits |Field |Descriptions 55 * | :----: | :----: | :---- | 56 * |[0] |AESIF |AES Finish Interrupt Flag 57 * | | |0 = No AES interrupt. 58 * | | |1 = AES done interrupt. 59 * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. 60 * |[1] |AESEIF |AES Error Flag 61 * | | |This register includes operating and setting error 62 * | | |The detail flag is shown in CRPT_AES_STS register. 63 * | | |0 = No AES error. 64 * | | |1 = AES error interrupt. 65 * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. 66 * |[16] |PRNGIF |PRNG Finish Interrupt Flag 67 * | | |0 = No PRNG interrupt. 68 * | | |1 = PRNG done interrupt. 69 * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. 70 * |[17] |PRNGEIF |PRNG Error Flag 71 * | | |This register includes operating and setting error 72 * | | |The detail flag is shown in CRYPT_PRNG_STS register. 73 * | | |0 = No PRNG error. 74 * | | |1 = PRNG error interrupt. 75 * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. 76 * @var CRPT_T::PRNG_CTL 77 * Offset: 0x08 PRNG Control Register 78 * --------------------------------------------------------------------------------------------------- 79 * |Bits |Field |Descriptions 80 * | :----: | :----: | :---- | 81 * |[0] |START |Start PRNG Engine 82 * | | |0 = Stop PRNG engine. 83 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. 84 * |[1] |SEEDRLD |Reload New Seed for PRNG Engine 85 * | | |0 = Generating key based on the current seed. 86 * | | |1 = Reload new seed. 87 * |[4:2] |KEYSZ |PRNG Generate Key Size 88 * | | |000 = 128 bits. 89 * | | |001 = 163 bits. 90 * | | |010 = 192 bits. 91 * | | |011 = 224 bits. 92 * | | |100 = 233 bits. 93 * | | |101 = 255 bits. 94 * | | |110 = 256 bits. 95 * | | |111 = Reserved. 96 * |[8] |BUSY |PRNG Busy (Read Only) 97 * | | |0 = PRNG engine is idle. 98 * | | |1 = PRNG engine is generating CRPT_PRNG_KEYx. 99 * | | |Note: This bit is equal to the busy bit of CRPT_PRNG_STS[0]. 100 * |[16] |SEEDSRC |Seed Source 101 * | | |0 = Seed is from TRNG. 102 * | | |1 = Seed is from PRNG seed register. 103 * | | |Note: When SEEDRLD is set to 0, this bit (SEEDSRC) is meaningless. 104 * @var CRPT_T::PRNG_SEED 105 * Offset: 0x0C Seed for PRNG 106 * --------------------------------------------------------------------------------------------------- 107 * |Bits |Field |Descriptions 108 * | :----: | :----: | :---- | 109 * |[31:0] |SEED |Seed for PRNG (Write Only) 110 * | | |The bits store the seed for PRNG engine. 111 * @var CRPT_T::PRNG_KEY[8] 112 * Offset: 0x10 PRNG Generated Key0~Key7 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[31:0] |KEY |Store PRNG Generated Key (Read Only) 117 * | | |The bits store the key that is generated by PRNG. 118 * @var CRPT_T::PRNG_STS 119 * Offset: 0x30 PRNG Status Register 120 * --------------------------------------------------------------------------------------------------- 121 * |Bits |Field |Descriptions 122 * | :----: | :----: | :---- | 123 * |[0] |BUSY |PRNG Busy Flag 124 * | | |0 = PRNG engine is idle. 125 * | | |1 = PRNG engine is generating CRPT_PRNG_KEYx. 126 * | | |Note: This bit is equal to the busy bit of CRPT_PRNG_CTL[8]. 127 * |[18] |TRNGERR |True Random Number Generator Error Flag 128 * | | |0 = No error. 129 * | | |1 = Getting random number or seed failed. 130 * @var CRPT_T::AES_FDBCK[4] 131 * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation 132 * --------------------------------------------------------------------------------------------------- 133 * |Bits |Field |Descriptions 134 * | :----: | :----: | :---- | 135 * |[31:0] |FDBCK |AES Feedback Information 136 * | | |The feedback value is 128 bits in size. 137 * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. 138 * | | |The AES engine outputs feedback information for IV in the next block's operation 139 * | | |Software can use this feedback information to implement more than four DMA channels 140 * | | |Software can store that feedback value temporarily 141 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. 142 * @var CRPT_T::AES_CTL 143 * Offset: 0x100 AES Control Register 144 * --------------------------------------------------------------------------------------------------- 145 * |Bits |Field |Descriptions 146 * | :----: | :----: | :---- | 147 * |[0] |START |AES Engine Start 148 * | | |0 = No effect. 149 * | | |1 = Start AES engine. BUSY flag will be set. 150 * | | |Note: This bit is always 0 when it is read back. 151 * |[1] |STOP |AES Engine Stop 152 * | | |0 = No effect. 153 * | | |1 = Stop AES engine. 154 * | | |Note: This bit is always 0 when it is read back. 155 * |[3:2] |KEYSZ |AES Key Size 156 * | | |This bit defines three different key size for AES operation. 157 * | | |2'b00 = 128 bits key. 158 * | | |2'b01 = 192 bits key. 159 * | | |2'b10 = 256 bits key. 160 * | | |2'b11 = Reserved. 161 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. 162 * |[5] |DMALAST |AES Last Block 163 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 164 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. 165 * | | |This bit is always 0 when it is read back, and must be written again once START is triggered. 166 * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode 167 * | | |0 = DMA cascade function Disabled. 168 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 169 * | | |Note: The last two blocks of AES-CBC-CS1/2/3 must be in the last cascade operation. 170 * |[7] |DMAEN |AES Engine DMA Enable Bit 171 * | | |0 = AES DMA engine Disabled. 172 * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. 173 * | | |1 = AES_DMA engine Enabled. 174 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 175 * |[15:8] |OPMODE |AES Engine Operation Modes 176 * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 177 * | | |0x02 = CFB (Cipher Feedback Mode). 178 * | | |0x03 = OFB (Output Feedback Mode). 179 * | | |0x04 = CTR (Counter Mode). 180 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). 181 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). 182 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). 183 * |[16] |ENCRPT |AES Encryption/Decryption 184 * | | |0 = AES engine executes decryption operation. 185 * | | |1 = AES engine executes encryption operation. 186 * |[22] |OUTSWAP |AES Engine Output Data Swap 187 * | | |0 = Keep the original order. 188 * | | |1 = The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 189 * |[23] |INSWAP |AES Engine Input Data Swap 190 * | | |0 = Keep the original order. 191 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 192 * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap 193 * | | |0 = Keep the original order. 194 * | | |1 = The order that CPU reads key, initial vector and feedback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 195 * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap 196 * | | |0 = Keep the original order. 197 * | | |1 = The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 198 * |[30:26] |KEYUNPRT |Unprotect Key 199 * | | |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect the AES key. 200 * | | |The KEYUNPRT can be read and written 201 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 202 * |[31] |KEYPRT |Protect Key 203 * | | |Read as a flag to reflect KEYPRT. 204 * | | |0 = No effect. 205 * | | |1 = Protect the content of the AES key from reading 206 * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx 207 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 208 * | | |The key content would be cleared as well. 209 * @var CRPT_T::AES_STS 210 * Offset: 0x104 AES Engine Flag 211 * --------------------------------------------------------------------------------------------------- 212 * |Bits |Field |Descriptions 213 * | :----: | :----: | :---- | 214 * |[0] |BUSY |AES Engine Busy 215 * | | |0 = The AES engine is idle or finished. 216 * | | |1 = The AES engine is under processing. 217 * |[8] |INBUFEMPTY|AES Input Buffer Empty 218 * | | |0 = There are some data in input buffer waiting for the AES engine to process. 219 * | | |1 = AES input buffer is empty 220 * | | |Software needs to feed data to the AES engine 221 * | | |Otherwise, the AES engine will be pending to wait for input data. 222 * |[9] |INBUFFULL |AES Input Buffer Full Flag 223 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. 224 * | | |1 = AES input buffer is full 225 * | | |Software cannot feed data to the AES engine 226 * | | |Otherwise, the flag INBUFERR will be set to 1. 227 * |[10] |INBUFERR |AES Input Buffer Error Flag 228 * | | |0 = No error. 229 * | | |1 = Error happened during feeding data to the AES engine. 230 * |[12] |CNTERR |CRPT_AES_CNT Setting Error 231 * | | |0 = No error in CRPT_AES_CNT setting. 232 * | | |1 = CRPT_AES_CNT is 0 if DMAEN (CRPT_AES_CTL[7]) is enabled. 233 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty 234 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. 235 * | | |1 = AES output buffer is empty 236 * | | |Software cannot get data from CRPT_AES_DATOUT 237 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. 238 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag 239 * | | |0 = AES output buffer is not full. 240 * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT 241 * | | |Otherwise, the AES engine will be pending since the output buffer is full. 242 * |[18] |OUTBUFERR |AES Out Buffer Error Flag 243 * | | |0 = No error. 244 * | | |1 = Error happened during getting the result from AES engine. 245 * |[20] |BUSERR |AES DMA Access Bus Error Flag 246 * | | |0 = No error. 247 * | | |1 = Bus error will stop DMA operation and AES engine. 248 * @var CRPT_T::AES_DATIN 249 * Offset: 0x108 AES Engine Data Input Port Register 250 * --------------------------------------------------------------------------------------------------- 251 * |Bits |Field |Descriptions 252 * | :----: | :----: | :---- | 253 * |[31:0] |DATIN |AES Engine Input Port 254 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. 255 * @var CRPT_T::AES_DATOUT 256 * Offset: 0x10C AES Engine Data Output Port Register 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[31:0] |DATOUT |AES Engine Output Port 261 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS 262 * | | |Get data as OUTBUFEMPTY is 0. 263 * @var CRPT_T::AES_KEY[8] 264 * Offset: 0x110~0x12C AES Key Word 0~7 Register 265 * --------------------------------------------------------------------------------------------------- 266 * |Bits |Field |Descriptions 267 * | :----: | :----: | :---- | 268 * |[31:0] |KEY |CRPT_AES_KEYx 269 * | | |The KEY keeps the security key for AES operation. 270 * | | |n = 0, 1..3. 271 * | | |x = 0, 1..7. 272 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 273 * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation 274 * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation 275 * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. 276 * @var CRPT_T::AES_IV[4] 277 * Offset: 0x130~0x13C AES Initial Vector Word 0~3 Register 278 * --------------------------------------------------------------------------------------------------- 279 * |Bits |Field |Descriptions 280 * | :----: | :----: | :---- | 281 * |[31:0] |IV |AES Initial Vectors 282 * | | |n = 0, 1..3. 283 * | | |x = 0, 1..3. 284 * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode 285 * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 286 * @var CRPT_T::AES_SADDR 287 * Offset: 0x140 AES DMA Source Address Register 288 * --------------------------------------------------------------------------------------------------- 289 * |Bits |Field |Descriptions 290 * | :----: | :----: | :---- | 291 * |[31:0] |SADDR |AES DMA Source Address 292 * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO 293 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 294 * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do AES operation 295 * | | |The start of source address should be located at word boundary 296 * | | |In other words, bit 1 and 0 of SADDR are ignored. 297 * | | |SADDR can be read and written 298 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 299 * | | |But the value of SADDR will be updated later on 300 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 301 * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. 302 * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. 303 * @var CRPT_T::AES_DADDR 304 * Offset: 0x144 AES DMA Destination Address Register 305 * --------------------------------------------------------------------------------------------------- 306 * |Bits |Field |Descriptions 307 * | :----: | :----: | :---- | 308 * |[31:0] |DADDR |AES DMA Destination Address 309 * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO 310 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 311 * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished 312 * | | |The start of destination address should be located at word boundary 313 * | | |In other words, bit 1 and 0 of DADDR are ignored. 314 * | | |DADDR can be read and written 315 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 316 * | | |But the value of DADDR will be updated later on 317 * | | |Consequently, software can prepare the destination address for the next AES operation. 318 * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. 319 * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. 320 * @var CRPT_T::AES_CNT 321 * Offset: 0x148 AES Byte Count Register 322 * --------------------------------------------------------------------------------------------------- 323 * |Bits |Field |Descriptions 324 * | :----: | :----: | :---- | 325 * |[31:0] |CNT |AES Byte Count 326 * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 327 * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. 328 * | | |CRPT_AES_CNT can be read and written 329 * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation 330 * | | |But the value of CRPT_AES_CNT will be updated later on 331 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 332 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes 333 * | | |Operations that are qual to or less than one block will output unexpected result. 334 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data 335 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 336 */ 337 __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ 338 __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ 339 __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ 340 __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ 341 __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ 342 __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ 343 __I uint32_t RESERVE0[7]; 344 __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ 345 __I uint32_t RESERVE1[40]; 346 __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ 347 __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ 348 __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ 349 __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ 350 __IO uint32_t AES_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ 351 __IO uint32_t AES_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ 352 __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ 353 __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ 354 __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ 355 } CRPT_T; 356 357 /** 358 @addtogroup CRPT_CONST CRPT Bit Field Definition 359 Constant Definitions for CRPT Controller 360 @{ */ 361 362 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ 363 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ 364 365 #define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ 366 #define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ 367 368 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ 369 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ 370 371 #define CRPT_INTEN_PRNGEIEN_Pos (17) /*!< CRPT_T::INTEN: PRNGEIEN Position */ 372 #define CRPT_INTEN_PRNGEIEN_Msk (0x1ul << CRPT_INTEN_PRNGEIEN_Pos) /*!< CRPT_T::INTEN: PRNGEIEN Mask */ 373 374 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ 375 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ 376 377 #define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ 378 #define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ 379 380 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ 381 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ 382 383 #define CRPT_INTSTS_PRNGEIF_Pos (17) /*!< CRPT_T::INTSTS: PRNGEIF Position */ 384 #define CRPT_INTSTS_PRNGEIF_Msk (0x1ul << CRPT_INTSTS_PRNGEIF_Pos) /*!< CRPT_T::INTSTS: PRNGEIF Mask */ 385 386 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ 387 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ 388 389 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ 390 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ 391 392 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ 393 #define CRPT_PRNG_CTL_KEYSZ_Msk (0x7ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPR_T::PRNG_CTL: KEYSZ Mask */ 394 395 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ 396 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ 397 398 #define CRPT_PRNG_CTL_SEEDSRC_Pos (16) /*!< CRPT_T::PRNG_CTL: SEEDSRC Position */ 399 #define CRPT_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask */ 400 401 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ 402 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ 403 404 #define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY0: KEY Position */ 405 #define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT_T::PRNG_KEY0: KEY Mask */ 406 407 #define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY1: KEY Position */ 408 #define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT_T::PRNG_KEY1: KEY Mask */ 409 410 #define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY2: KEY Position */ 411 #define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT_T::PRNG_KEY2: KEY Mask */ 412 413 #define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY3: KEY Position */ 414 #define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT_T::PRNG_KEY3: KEY Mask */ 415 416 #define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY4: KEY Position */ 417 #define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT_T::PRNG_KEY4: KEY Mask */ 418 419 #define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY5: KEY Position */ 420 #define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT_T::PRNG_KEY5: KEY Mask */ 421 422 #define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY6: KEY Position */ 423 #define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT_T::PRNG_KEY6: KEY Mask */ 424 425 #define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY7: KEY Position */ 426 #define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT_T::PRNG_KEY7: KEY Mask */ 427 428 #define CRPT_PRNG_STS_BUSY_Pos (0) /*!< CRPT_T::PRNG_STS: BUSY Position */ 429 #define CRPT_PRNG_STS_BUSY_Msk (0x1ul << CRPT_PRNG_STS_BUSY_Pos) /*!< CRPT_T::PRNG_STS: BUSY Mask */ 430 431 #define CRPT_PRNG_STS_TRNGERR_Pos (18) /*!< CRPT_T::PRNG_STS: TRNGERR Position */ 432 #define CRPT_PRNG_STS_TRNGERR_Msk (0x1ul << CRPT_PRNG_STS_TRNGERR_Pos) /*!< CRPT_T::PRNG_STS: TRNGERR Mask */ 433 434 #define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK0: FDBCK Position */ 435 #define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK0: FDBCK Mask */ 436 437 #define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK1: FDBCK Position */ 438 #define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK1: FDBCK Mask */ 439 440 #define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK2: FDBCK Position */ 441 #define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK2: FDBCK Mask */ 442 443 #define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK3: FDBCK Position */ 444 #define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK3: FDBCK Mask */ 445 446 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ 447 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ 448 449 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ 450 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ 451 452 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ 453 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ 454 455 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ 456 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ 457 458 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ 459 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ 460 461 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ 462 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ 463 464 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ 465 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ 466 467 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ 468 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ 469 470 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ 471 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ 472 473 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ 474 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ 475 476 #define CRPT_AES_CTL_KOUTSWAP_Pos (24) /*!< CRPT_T::AES_CTL: KOUTSWAP Position */ 477 #define CRPT_AES_CTL_KOUTSWAP_Msk (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos) /*!< CRPT_T::AES_CTL: KOUTSWAP Mask */ 478 479 #define CRPT_AES_CTL_KINSWAP_Pos (25) /*!< CRPT_T::AES_CTL: KINSWAP Position */ 480 #define CRPT_AES_CTL_KINSWAP_Msk (0x1ul << CRPT_AES_CTL_KINSWAP_Pos) /*!< CRPT_T::AES_CTL: KINSWAP Mask */ 481 482 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ 483 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ 484 485 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ 486 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ 487 488 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ 489 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ 490 491 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ 492 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ 493 494 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ 495 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ 496 497 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ 498 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ 499 500 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ 501 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ 502 503 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/ 504 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ 505 506 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ 507 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ 508 509 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ 510 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ 511 512 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ 513 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ 514 515 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ 516 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ 517 518 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ 519 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ 520 521 #define CRPT_AES_KEY0_KEY_Pos (0) /*!< CRPT_T::AES_KEY0: KEY Position */ 522 #define CRPT_AES_KEY0_KEY_Msk (0xfffffffful << CRPT_AES_KEY0_KEY_Pos) /*!< CRPT_T::AES_KEY0: KEY Mask */ 523 524 #define CRPT_AES_KEY1_KEY_Pos (0) /*!< CRPT_T::AES_KEY1: KEY Position */ 525 #define CRPT_AES_KEY1_KEY_Msk (0xfffffffful << CRPT_AES_KEY1_KEY_Pos) /*!< CRPT_T::AES_KEY1: KEY Mask */ 526 527 #define CRPT_AES_KEY2_KEY_Pos (0) /*!< CRPT_T::AES_KEY2: KEY Position */ 528 #define CRPT_AES_KEY2_KEY_Msk (0xfffffffful << CRPT_AES_KEY2_KEY_Pos) /*!< CRPT_T::AES_KEY2: KEY Mask */ 529 530 #define CRPT_AES_KEY3_KEY_Pos (0) /*!< CRPT_T::AES_KEY3: KEY Position */ 531 #define CRPT_AES_KEY3_KEY_Msk (0xfffffffful << CRPT_AES_KEY3_KEY_Pos) /*!< CRPT_T::AES_KEY3: KEY Mask */ 532 533 #define CRPT_AES_KEY4_KEY_Pos (0) /*!< CRPT_T::AES_KEY4: KEY Position */ 534 #define CRPT_AES_KEY4_KEY_Msk (0xfffffffful << CRPT_AES_KEY4_KEY_Pos) /*!< CRPT_T::AES_KEY4: KEY Mask */ 535 536 #define CRPT_AES_KEY5_KEY_Pos (0) /*!< CRPT_T::AES_KEY5: KEY Position */ 537 #define CRPT_AES_KEY5_KEY_Msk (0xfffffffful << CRPT_AES_KEY5_KEY_Pos) /*!< CRPT_T::AES_KEY5: KEY Mask */ 538 539 #define CRPT_AES_KEY6_KEY_Pos (0) /*!< CRPT_T::AES_KEY6: KEY Position */ 540 #define CRPT_AES_KEY6_KEY_Msk (0xfffffffful << CRPT_AES_KEY6_KEY_Pos) /*!< CRPT_T::AES_KEY6: KEY Mask */ 541 542 #define CRPT_AES_KEY7_KEY_Pos (0) /*!< CRPT_T::AES_KEY7: KEY Position */ 543 #define CRPT_AES_KEY7_KEY_Msk (0xfffffffful << CRPT_AES_KEY7_KEY_Pos) /*!< CRPT_T::AES_KEY7: KEY Mask */ 544 545 #define CRPT_AES_IV0_IV_Pos (0) /*!< CRPT_T::AES_IV0: IV Position */ 546 #define CRPT_AES_IV0_IV_Msk (0xfffffffful << CRPT_AES_IV0_IV_Pos) /*!< CRPT_T::AES_IV0: IV Mask */ 547 548 #define CRPT_AES_IV1_IV_Pos (0) /*!< CRPT_T::AES_IV1: IV Position */ 549 #define CRPT_AES_IV1_IV_Msk (0xfffffffful << CRPT_AES_IV1_IV_Pos) /*!< CRPT_T::AES_IV1: IV Mask */ 550 551 #define CRPT_AES_IV2_IV_Pos (0) /*!< CRPT_T::AES_IV2: IV Position */ 552 #define CRPT_AES_IV2_IV_Msk (0xfffffffful << CRPT_AES_IV2_IV_Pos) /*!< CRPT_T::AES_IV2: IV Mask */ 553 554 #define CRPT_AES_IV3_IV_Pos (0) /*!< CRPT_T::AES_IV3: IV Position */ 555 #define CRPT_AES_IV3_IV_Msk (0xfffffffful << CRPT_AES_IV3_IV_Pos) /*!< CRPT_T::AES_IV3: IV Mask */ 556 557 #define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ 558 #define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ 559 560 #define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ 561 #define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ 562 563 #define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ 564 #define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ 565 566 /**@}*/ /* CRPT_CONST */ 567 /**@}*/ /* end of CRPT register group */ 568 569 570 /**@}*/ /* end of REGISTER group */ 571 572 #endif /* __CRPT_REG_H__ */ 573
