1 /**************************************************************************//** 2 * @file M2L31.h 3 * @version V1.0 4 * @brief Peripheral Access Layer Header File 5 * 6 * @note 7 * SPDX-License-Identifier: Apache-2.0 8 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 9 ******************************************************************************/ 10 11 /** 12 \mainpage NuMicro M2L31 Series CMSIS BSP Driver Reference 13 * 14 * <b>Introduction</b> 15 * 16 * This user manual describes the usage of M2L31 Series MCU device driver 17 * 18 * <b>Disclaimer</b> 19 * 20 * The Software is furnished "AS IS", without warranty as to performance or results, and 21 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all 22 * warranties, express, implied or otherwise, with regard to the Software, its use, or 23 * operation, including without limitation any and all warranties of merchantability, fitness 24 * for a particular purpose, and non-infringement of intellectual property rights. 25 * 26 * <b>Important Notice</b> 27 * 28 * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, 29 * any malfunction or failure of which may cause loss of human life, bodily injury or severe 30 * property damage. Such applications are deemed, "Insecure Usage". 31 * 32 * Insecure usage includes, but is not limited to: equipment for surgical implementation, 33 * atomic energy control instruments, airplane or spaceship instruments, the control or 34 * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal 35 * instruments, all types of safety devices, and other applications intended to support or 36 * sustain life. 37 * 38 * All Insecure Usage shall be made at customer's risk, and in the event that third parties 39 * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify 40 * the damages and liabilities thus incurred by Nuvoton. 41 * 42 * Please note that all data and specifications are subject to change without notice. All the 43 * trademarks of products and companies mentioned in this datasheet belong to their respective 44 * owners. 45 * 46 * <b>Copyright Notice</b> 47 * 48 * SPDX-License-Identifier: Apache-2.0 49 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 50 */ 51 52 #ifndef __M2L31_H__ 53 #define __M2L31_H__ 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 /******************************************************************************/ 60 /* Processor and Core Peripherals */ 61 /******************************************************************************/ 62 /** @addtogroup CMSIS_Device CMSIS Definitions 63 Configuration of the Cortex-M23 Processor and Core Peripherals 64 @{ 65 */ 66 67 68 /* 69 * ========================================================================== 70 * ---------- Interrupt Number Definition ----------------------------------- 71 * ========================================================================== 72 */ 73 74 /** 75 * @details Interrupt Number Definition. 76 */ 77 typedef enum IRQn 78 { 79 /****** Cortex-M0 Processor Exceptions Numbers ***********************************************/ 80 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 81 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 82 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 83 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 84 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 85 86 /****** ARMIKMCU Swift specific Interrupt Numbers ********************************************/ 87 BOD_IRQn = 0, /*!< Brown-Out low voltage detected interrupt */ 88 IRCTRIM_IRQn = 1, /*!< IRC TRIM interrupt */ 89 PWRWU_IRQn = 2, /*!< Clock controller interrupt for chip wake-up from power-down state */ 90 SRAM_PERR_IRQn = 3, /*!< SRAM parity check error interrupt */ 91 CLKFAIL_IRQn = 4, /*!< Clock fail detected interrupt */ 92 RMC_IRQn = 5, /*!< RRAM Memory Controller interrupt */ 93 RTC_IRQn = 6, /*!< Real time clock interrupt */ 94 TAMPER_IRQn = 7, /*!< Backup register tamper interrupt */ 95 WDT_IRQn = 8, /*!< Watchdog Timer interrupt */ 96 WWDT_IRQn = 9, /*!< Window Watchdog Timer interrupt */ 97 EINT0_IRQn = 10, /*!< External interrupt from INT0 pins */ 98 EINT1_IRQn = 11, /*!< External interrupt from INT1 pins */ 99 EINT2_IRQn = 12, /*!< External interrupt from INT2 pin */ 100 EINT3_IRQn = 13, /*!< External interrupt from INT3 pin */ 101 EINT4_IRQn = 14, /*!< External interrupt from INT4 pin */ 102 EINT5_IRQn = 15, /*!< External interrupt from INT5 pin */ 103 GPA_IRQn = 16, /*!< External interrupt from PA[15:0] pin */ 104 GPB_IRQn = 17, /*!< External interrupt from PB[15:0] pin */ 105 GPC_IRQn = 18, /*!< External interrupt from PC[15:0] pin */ 106 GPD_IRQn = 19, /*!< External interrupt from PD[15:0] pin */ 107 GPE_IRQn = 20, /*!< External interrupt from PE[15:0] pin */ 108 GPF_IRQn = 21, /*!< External interrupt from PF[15:0] pin */ 109 QSPI0_IRQn = 22, /*!< QSPI0 interrupt */ 110 SPI0_IRQn = 23, /*!< SPI0 interrupt */ 111 EBRAKE0_IRQn = 24, /*!< EPWM0 brake interrupt */ 112 EPWM0_P0_IRQn = 25, /*!< EPWM0 pair 0 interrupt */ 113 EPWM0_P1_IRQn = 26, /*!< EPWM0 pair 1 interrupt */ 114 EPWM0_P2_IRQn = 27, /*!< EPWM0 pair 2 interrupt */ 115 EBRAKE1_IRQn = 28, /*!< EPWM1 brake interrupt */ 116 EPWM1_P0_IRQn = 29, /*!< EPWM1 pair 0 interrupt */ 117 EPWM1_P1_IRQn = 30, /*!< EPWM1 pair 1 interrupt */ 118 EPWM1_P2_IRQn = 31, /*!< EPWM1 pair 2 interrupt */ 119 TMR0_IRQn = 32, /*!< Timer 0 interrupt */ 120 TMR1_IRQn = 33, /*!< Timer 1 interrupt */ 121 TMR2_IRQn = 34, /*!< Timer 2 interrupt */ 122 TMR3_IRQn = 35, /*!< Timer 3 interrupt */ 123 UART0_IRQn = 36, /*!< UART0 interrupt */ 124 UART1_IRQn = 37, /*!< UART1 interrupt */ 125 I2C0_IRQn = 38, /*!< I2C0 interrupt */ 126 I2C1_IRQn = 39, /*!< I2C1 interrupt */ 127 PDMA0_IRQn = 40, /*!< PDMA0 interrupt */ 128 DAC_IRQn = 41, /*!< DAC interrupt */ 129 EADC0_INT0_IRQn = 42, /*!< EADC0 interrupt source 0 */ 130 EADC0_INT1_IRQn = 43, /*!< EADC0 interrupt source 1 */ 131 ACMP01_IRQn = 44, /*!< ACMP0 and ACMP1 interrupt */ 132 ACMP2_IRQn = 45, /*!< ACMP2 interrupt */ 133 EADC0_INT2_IRQn = 46, /*!< EADC0 interrupt source 2 */ 134 EADC0_INT3_IRQn = 47, /*!< EADC0 interrupt source 3 */ 135 UART2_IRQn = 48, /*!< UART2 interrupt */ 136 UART3_IRQn = 49, /*!< UART3 interrupt */ 137 RESERVED0 = 50, /*!< Reserved */ 138 SPI1_IRQn = 51, /*!< SPI1 interrupt */ 139 SPI2_IRQn = 52, /*!< SPI2 interrupt */ 140 USBD_IRQn = 53, /*!< USB device interrupt */ 141 USBH_IRQn = 54, /*!< USB host interrupt */ 142 USBOTG_IRQn = 55, /*!< USB OTG interrupt */ 143 ETI_IRQn = 56, /*!< External Trigger Interface interrupt */ 144 CRC0_IRQn = 57, /*!< CRC0 interrupt */ 145 RESERVED1 = 58, /*!< Reserved */ 146 RESERVED2 = 59, /*!< Reserved */ 147 RESERVED3 = 60, /*!< Reserved */ 148 RESERVED4 = 61, /*!< Reserved */ 149 SPI3_IRQn = 62, /*!< SPI3 interrupt */ 150 TK_IRQn = 63, /*!< Touchkey interrupt */ 151 RESERVED5 = 64, /*!< Reserved */ 152 RESERVED6 = 65, /*!< Reserved */ 153 RESERVED7 = 66, /*!< Reserved */ 154 RESERVED8 = 67, /*!< Reserved */ 155 RESERVED9 = 68, /*!< Reserved */ 156 RESERVED10 = 69, /*!< Reserved */ 157 OPA_IRQn = 70, /*!< Analog OPA interrupt */ 158 CRPT_IRQn = 71, /*!< Crypto interrupt */ 159 GPG_IRQn = 72, /*!< External interrupt from PG[15:0] pin */ 160 EINT6_IRQn = 73, /*!< External interrupt from INT6 pin */ 161 UART4_IRQn = 74, /*!< UART4 interrupt */ 162 UART5_IRQn = 75, /*!< UART5 interrupt */ 163 USCI0_IRQn = 76, /*!< USCI0 interrupt */ 164 USCI1_IRQn = 77, /*!< USCI1 interrupt */ 165 RESERVED11 = 78, /*!< Reserved */ 166 RESERVED12 = 79, /*!< Reserved */ 167 RESERVED13 = 80, /*!< Reserved */ 168 RESERVED14 = 81, /*!< Reserved */ 169 I2C2_IRQn = 82, /*!< I2C2 interrupt */ 170 I2C3_IRQn = 83, /*!< I2C3 interrupt */ 171 EQEI0_IRQn = 84, /*!< EQEI0 interrupt */ 172 EQEI1_IRQn = 85, /*!< EQEI1 interrupt */ 173 ECAP0_IRQn = 86, /*!< ECAP0 interrupt */ 174 ECAP1_IRQn = 87, /*!< ECAP1 interrupt */ 175 GPH_IRQn = 88, /*!< External interrupt from PH[15:0] pin */ 176 EINT7_IRQn = 89, /*!< External interrupt from INT7 pin */ 177 RESERVED15 = 90, /*!< Reserved */ 178 RESERVED16 = 91, /*!< Reserved */ 179 RESERVED17 = 92, /*!< Reserved */ 180 RESERVED18 = 93, /*!< Reserved */ 181 RESERVED19 = 94, /*!< Reserved */ 182 RESERVED20 = 95, /*!< Reserved */ 183 RESERVED21 = 96, /*!< Reserved */ 184 RESERVED22 = 97, /*!< Reserved */ 185 LPPDMA0_IRQn = 98, /*!< LPPDMA0 interrupt */ 186 RESERVED23 = 99, /*!< Reserved */ 187 RESERVED24 = 100, /*!< Reserved */ 188 TRNG_IRQn = 101, /*!< TRNG interrupt */ 189 UART6_IRQn = 102, /*!< UART6 interrupt */ 190 UART7_IRQn = 103, /*!< UART7 interrupt */ 191 RESERVED25 = 104, /*!< Reserved */ 192 RESERVED26 = 105, /*!< Reserved */ 193 RESERVED27 = 106, /*!< Reserved */ 194 RESERVED28 = 107, /*!< Reserved */ 195 UTCPD_IRQn = 108, /*!< UTCPD interrupt */ 196 RESERVED29 = 109, /*!< Reserved */ 197 RESERVED30 = 110, /*!< Reserved */ 198 RESERVED31 = 111, /*!< Reserved */ 199 CANFD00_IRQn = 112, /*!< CANFD00 interrupt */ 200 CANFD01_IRQn = 113, /*!< CANFD01 interrupt */ 201 CANFD10_IRQn = 114, /*!< CANFD10 interrupt */ 202 CANFD11_IRQn = 115, /*!< CANFD11 interrupt */ 203 RESERVED32 = 116, /*!< Reserved */ 204 RESERVED33 = 117, /*!< Reserved */ 205 RESERVED34 = 118, /*!< Reserved */ 206 RESERVED35 = 119, /*!< Reserved */ 207 RESERVED36 = 120, /*!< Reserved */ 208 RESERVED37 = 121, /*!< Reserved */ 209 RESERVED38 = 122, /*!< Reserved */ 210 RESERVED39 = 123, /*!< Reserved */ 211 RESERVED40 = 124, /*!< Reserved */ 212 RESERVED41 = 125, /*!< Reserved */ 213 RESERVED42 = 126, /*!< Reserved */ 214 RESERVED43 = 127, /*!< Reserved */ 215 BRAKE0_IRQn = 128, /*!< PWM0 brake interrupt */ 216 PWM0_P0_IRQn = 129, /*!< PWM0 pair 0 interrupt */ 217 PWM0_P1_IRQn = 130, /*!< PWM0 pair 1 interrupt */ 218 PWM0_P2_IRQn = 131, /*!< PWM0 pair 2 interrupt */ 219 BRAKE1_IRQn = 132, /*!< PWM1 brake interrupt */ 220 PWM1_P0_IRQn = 133, /*!< PWM1 pair 0 interrupt */ 221 PWM1_P1_IRQn = 134, /*!< PWM1 pair 1 interrupt */ 222 PWM1_P2_IRQn = 135, /*!< PWM1 pair 2 interrupt */ 223 LPADC0_IRQn = 136, /*!< LPADC0 interrupt */ 224 LPUART0_IRQn = 137, /*!< LPUART0 interrupt */ 225 LPI2C0_IRQn = 138, /*!< LPI2C0 interrupt */ 226 LPSPI0_IRQn = 139, /*!< LPSPI0 interrupt */ 227 LPTMR0_IRQn = 140, /*!< LPTMR0 interrupt */ 228 LPTMR1_IRQn = 141, /*!< LPTMR1 interrupt */ 229 TTMR0_IRQn = 142, /*!< TTMR0 interrupt */ 230 TTMR1_IRQn = 143, /*!< TTMR1 interrupt */ 231 } IRQn_Type; 232 233 234 /* ================================================================================ */ 235 /* ================ Processor and Core Peripheral Section ================ */ 236 /* ================================================================================ */ 237 238 /* ------- Start of section using anonymous unions and disabling warnings ------- */ 239 #if defined (__CC_ARM) 240 #pragma push 241 #pragma anon_unions 242 #elif defined (__ICCARM__) 243 #pragma language=extended 244 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 245 #pragma clang diagnostic push 246 #pragma clang diagnostic ignored "-Wc11-extensions" 247 #pragma clang diagnostic ignored "-Wreserved-id-macro" 248 #elif defined (__GNUC__) 249 /* anonymous unions are enabled by default */ 250 #elif defined (__TMS470__) 251 /* anonymous unions are enabled by default */ 252 #elif defined (__TASKING__) 253 #pragma warning 586 254 #elif defined (__CSMC__) 255 /* anonymous unions are enabled by default */ 256 #else 257 #warning Not supported compiler type 258 #endif 259 260 261 /* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ 262 #define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ 263 #define __SAU_PRESENT 0U /* SAU present */ 264 #define __MPU_PRESENT 1U /* MPU present */ 265 #define __VTOR_PRESENT 1U /* VTOR present */ 266 #define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ 267 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 268 #define USE_ASSERT 0U /* Define to use Assert function or not */ 269 270 /*@}*/ /* end of group CMSIS_Device */ 271 272 273 #include "core_cm23.h" /* Processor and core peripherals */ 274 #include "system_M2L31.h" /* System Header */ 275 276 /** 277 * Initialize the system clock 278 * 279 * @param none 280 * @return none 281 * 282 * @brief Setup the micro controller system 283 * Initialize the PLL and update the SystemFrequency variable 284 */ 285 extern void SystemInit(void); 286 287 288 /******************************************************************************/ 289 /* Device Specific Peripheral registers structures */ 290 /******************************************************************************/ 291 292 /** @addtogroup REGISTER Control Register 293 294 @{ 295 296 */ 297 298 #include "acmp_reg.h" 299 #include "canfd_reg.h" 300 #include "clk_reg.h" 301 #include "crc_reg.h" 302 #include "crypto_reg.h" 303 #include "dac_reg.h" 304 #include "eadc_reg.h" 305 #include "ebi_reg.h" 306 #include "ecap_reg.h" 307 #include "epwm_reg.h" 308 #include "eqei_reg.h" 309 #include "gpio_reg.h" 310 #include "i2c_reg.h" 311 #include "lpadc_reg.h" 312 #include "lpgpio_reg.h" 313 #include "lpi2c_reg.h" 314 #include "lppdma_reg.h" 315 #include "lpspi_reg.h" 316 #include "lptmr_reg.h" 317 #include "lpuart_reg.h" 318 #include "opa_reg.h" 319 #include "otg_reg.h" 320 #include "pdma_reg.h" 321 #include "pwm_reg.h" 322 #include "qspi_reg.h" 323 #include "rmc_reg.h" 324 #include "rtc_reg.h" 325 #include "spi_reg.h" 326 #include "sys_reg.h" 327 #include "timer_reg.h" 328 #include "tk_reg.h" 329 #include "trng_reg.h" 330 #include "ttmr_reg.h" 331 #include "uart_reg.h" 332 #include "ui2c_reg.h" 333 #include "usbd_reg.h" 334 #include "usbh_reg.h" 335 #include "uspi_reg.h" 336 #include "utcpd_reg.h" 337 #include "uuart_reg.h" 338 #include "wdt_reg.h" 339 #include "wwdt_reg.h" 340 341 342 /**@}*/ /* end of REGISTER group */ 343 344 345 /******************************************************************************/ 346 /* Peripheral memory map */ 347 /******************************************************************************/ 348 /** @addtogroup PERIPHERAL_BASE Peripheral Memory Base 349 Memory Mapped Structure for Series Peripheral 350 @{ 351 */ 352 353 354 /* Peripheral and SRAM base address */ 355 #define FLASH_BASE ((uint32_t)0x00000000UL) /*!< Flash Base Address */ 356 #define SRAM_BASE ((uint32_t)0x20000000UL) /*!< SRAM Base Address */ 357 #define LPSRAM_BASE ((uint32_t)0x28000000UL) /*!< LPSRAM Base Address */ 358 #define PERIPH_BASE ((uint32_t)0x40000000UL) /*!< Peripheral Base Address */ 359 360 /* Peripheral memory map */ 361 #define AHBPERIPH_BASE (PERIPH_BASE) /*!< AHB Base Address */ 362 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) /*!< APB Base Address */ 363 364 /*!< AHB peripherals */ 365 #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) 366 #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) 367 #define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) 368 #define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) 369 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) 370 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) 371 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) 372 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) 373 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) 374 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) 375 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) 376 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) 377 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04450UL) 378 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) 379 #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) 380 #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) 381 #define RMC_BASE (AHBPERIPH_BASE + 0x0C000UL) 382 #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) 383 #define CANFD0_BASE (AHBPERIPH_BASE + 0x20000UL) 384 #define CANFD1_BASE (AHBPERIPH_BASE + 0x24000UL) 385 #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) 386 #define CRYP_BASE (AHBPERIPH_BASE + 0x32000UL) 387 #define LPSCC_BASE (AHBPERIPH_BASE + 0x38000UL) 388 #define LPPDMA0_BASE (AHBPERIPH_BASE + 0x39000UL) 389 #define LPGPIO_BASE (AHBPERIPH_BASE + 0x3A000UL) 390 391 /*!< APB peripherals */ 392 #define WDT_BASE (APBPERIPH_BASE + 0x00000UL) 393 #define RTC_BASE (APBPERIPH_BASE + 0x01000UL) 394 #define EADC0_BASE (APBPERIPH_BASE + 0x03000UL) 395 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) 396 #define OPA_BASE (APBPERIPH_BASE + 0x06000UL) 397 #define DAC_BASE (APBPERIPH_BASE + 0x07000UL) 398 #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) 399 #define TIMER01_BASE (APBPERIPH_BASE + 0x10000UL) 400 #define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) 401 #define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) 402 #define TIMER23_BASE (APBPERIPH_BASE + 0x11000UL) 403 #define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) 404 #define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) 405 #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) 406 #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) 407 #define PWM0_BASE (APBPERIPH_BASE + 0x1C000UL) 408 #define PWM1_BASE (APBPERIPH_BASE + 0x1D000UL) 409 #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) 410 #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) 411 #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) 412 #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) 413 #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) 414 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) 415 #define UART1_BASE (APBPERIPH_BASE + 0x31000UL) 416 #define UART2_BASE (APBPERIPH_BASE + 0x32000UL) 417 #define UART3_BASE (APBPERIPH_BASE + 0x33000UL) 418 #define UART4_BASE (APBPERIPH_BASE + 0x34000UL) 419 #define UART5_BASE (APBPERIPH_BASE + 0x35000UL) 420 #define UART6_BASE (APBPERIPH_BASE + 0x36000UL) 421 #define UART7_BASE (APBPERIPH_BASE + 0x37000UL) 422 #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) 423 #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) 424 #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) 425 #define I2C3_BASE (APBPERIPH_BASE + 0x43000UL) 426 #define WWDT_BASE (APBPERIPH_BASE + 0x56000UL) 427 #define EQEI0_BASE (APBPERIPH_BASE + 0x70000UL) 428 #define EQEI1_BASE (APBPERIPH_BASE + 0x71000UL) 429 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) 430 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) 431 #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) 432 #define USBD_BASE (APBPERIPH_BASE + 0x80000UL) 433 #define TK_BASE (APBPERIPH_BASE + 0x84000UL) 434 #define UTCPD_BASE (APBPERIPH_BASE + 0x86000UL) 435 #define UTCPD0_BASE (APBPERIPH_BASE + 0x86000UL) 436 #define UTCPD1_BASE (APBPERIPH_BASE + 0x86000UL) 437 #define ACMP2_BASE (APBPERIPH_BASE + 0x89000UL) 438 #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) 439 #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) 440 #define LPUART0_BASE (APBPERIPH_BASE + 0xA0000UL) 441 #define LPSPI0_BASE (APBPERIPH_BASE + 0xA1000UL) 442 #define LPI2C0_BASE (APBPERIPH_BASE + 0xA2000UL) 443 #define LPADC0_BASE (APBPERIPH_BASE + 0xA3000UL) 444 #define LPTMR01_BASE (APBPERIPH_BASE + 0xA4000UL) 445 #define TTMR01_BASE (APBPERIPH_BASE + 0xA5000UL) 446 #define KS_BASE (0x40035000UL) 447 448 /**@}*/ /* end of group PERIPHERAL_BASE */ 449 450 451 /******************************************************************************/ 452 /* Peripheral declaration */ 453 /******************************************************************************/ 454 455 /** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer 456 The Declaration of Peripheral Pointer 457 @{ 458 */ 459 460 /*!< AHB peripherals */ 461 #define SYS ((SYS_T *) SYS_BASE) 462 #define CLK ((CLK_T *) CLK_BASE) 463 #define NMI ((NMI_T *) NMI_BASE) 464 #define PA ((GPIO_T *) GPIOA_BASE) 465 #define PB ((GPIO_T *) GPIOB_BASE) 466 #define PC ((GPIO_T *) GPIOC_BASE) 467 #define PD ((GPIO_T *) GPIOD_BASE) 468 #define PE ((GPIO_T *) GPIOE_BASE) 469 #define PF ((GPIO_T *) GPIOF_BASE) 470 #define PG ((GPIO_T *) GPIOG_BASE) 471 #define PH ((GPIO_T *) GPIOH_BASE) 472 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) 473 #define PDMA0 ((PDMA_T *) PDMA0_BASE) 474 #define PDMA ((PDMA_T *) PDMA0_BASE) 475 #define USBH ((USBH_T *) USBH_BASE) 476 #define RMC ((RMC_T *) RMC_BASE) 477 #define EBI ((EBI_T *) EBI_BASE) 478 #define CANFD0 ((CANFD_T *) CANFD0_BASE) 479 #define CANFD1 ((CANFD_T *) CANFD1_BASE) 480 #define CRC ((CRC_T *) CRC_BASE) 481 #define CRPT ((CRPT_T *) CRYP_BASE) 482 #define LPSCC ((LPSCC_T *) LPSCC_BASE) 483 #define LPPDMA0 ((LPPDMA_T *) LPPDMA0_BASE) 484 #define LPGPIO ((LPGPIO_T *) LPGPIO_BASE) 485 486 /*!< APB0 peripherals */ 487 #define WDT ((WDT_T *) WDT_BASE) 488 #define RTC ((RTC_T *) RTC_BASE) 489 #define EADC ((EADC_T *) EADC0_BASE) 490 #define EADC0 ((EADC_T *) EADC0_BASE) 491 #define ACMP01 ((ACMP_T *) ACMP01_BASE) 492 #define OPA ((OPA_T *) OPA_BASE) 493 #define DAC0 ((DAC_T *) DAC_BASE) 494 #define DAC1 ((DAC_T *) (DAC_BASE+0x40UL)) 495 #define OTG ((OTG_T *) OTG_BASE) 496 #define TIMER0 ((TIMER_T *) TIMER01_BASE) 497 #define TIMER1 ((TIMER_T *) (TIMER01_BASE + 0x100UL)) 498 #define TIMER2 ((TIMER_T *) TIMER23_BASE) 499 #define TIMER3 ((TIMER_T *) (TIMER23_BASE+ 0x100UL)) 500 #define TTMR0 ((TTMR_T *) TTMR01_BASE) 501 #define TTMR1 ((TTMR_T *) (TTMR01_BASE + 0x100UL)) 502 #define EPWM0 ((EPWM_T *) EPWM0_BASE) 503 #define EPWM1 ((EPWM_T *) EPWM1_BASE) 504 #define PWM0 ((PWM_T *) PWM0_BASE) 505 #define PWM1 ((PWM_T *) PWM1_BASE) 506 #define QSPI0 ((QSPI_T *) QSPI0_BASE) 507 #define SPI0 ((SPI_T *) SPI0_BASE) 508 #define SPI1 ((SPI_T *) SPI1_BASE) 509 #define SPI2 ((SPI_T *) SPI2_BASE) 510 #define SPI3 ((SPI_T *) SPI3_BASE) 511 #define UART0 ((UART_T *) UART0_BASE) 512 #define UART1 ((UART_T *) UART1_BASE) 513 #define UART2 ((UART_T *) UART2_BASE) 514 #define UART3 ((UART_T *) UART3_BASE) 515 #define UART4 ((UART_T *) UART4_BASE) 516 #define UART5 ((UART_T *) UART5_BASE) 517 #define UART6 ((UART_T *) UART6_BASE) 518 #define UART7 ((UART_T *) UART7_BASE) 519 #define I2C0 ((I2C_T *) I2C0_BASE) 520 #define I2C1 ((I2C_T *) I2C1_BASE) 521 #define I2C2 ((I2C_T *) I2C2_BASE) 522 #define I2C3 ((I2C_T *) I2C3_BASE) 523 #define WWDT ((WWDT_T *) WWDT_BASE) 524 #define EQEI0 ((EQEI_T *) EQEI0_BASE) 525 #define EQEI1 ((EQEI_T *) EQEI1_BASE) 526 #define ECAP0 ((ECAP_T *) ECAP0_BASE) 527 #define ECAP1 ((ECAP_T *) ECAP1_BASE) 528 #define TRNG ((TRNG_T *) TRNG_BASE) 529 #define USBD ((USBD_T *) USBD_BASE) 530 #define TK ((TK_T *) TK_BASE) 531 #define UTCPD ((UTCPD_T *) UTCPD_BASE) 532 #define ACMP2 ((ACMP_T *) ACMP2_BASE) 533 #define UI2C0 ((UI2C_T *) USCI0_BASE) 534 #define USPI0 ((USPI_T *) USCI0_BASE) 535 #define UUART0 ((UUART_T *) USCI0_BASE) 536 #define UI2C1 ((UI2C_T *) USCI1_BASE) 537 #define USPI1 ((USPI_T *) USCI1_BASE) 538 #define UUART1 ((UUART_T *) USCI1_BASE) 539 #define LPUART0 ((LPUART_T *) LPUART0_BASE) 540 #define LPSPI0 ((LPSPI_T *) LPSPI0_BASE) 541 #define LPI2C0 ((LPI2C_T *) LPI2C0_BASE) 542 #define LPADC0 ((LPADC_T *) LPADC0_BASE) 543 #define LPTMR0 ((LPTMR_T *) LPTMR01_BASE) 544 #define LPTMR1 ((LPTMR_T *) (LPTMR01_BASE + 0x100UL)) 545 #define TTMR0 ((TTMR_T *) TTMR01_BASE) 546 #define TTMR1 ((TTMR_T *) (TTMR01_BASE + 0x100UL)) 547 548 /**@}*/ /* end of group PERIPHERAL_DECLARATION */ 549 550 551 /* -------------------- End of section using anonymous unions ------------------- */ 552 #if defined (__CC_ARM) 553 #pragma pop 554 #elif defined (__ICCARM__) 555 /* leave anonymous unions enabled */ 556 #elif (__ARMCC_VERSION >= 6010050) 557 #pragma clang diagnostic pop 558 #elif defined (__GNUC__) 559 /* anonymous unions are enabled by default */ 560 #elif defined (__TMS470__) 561 /* anonymous unions are enabled by default */ 562 #elif defined (__TASKING__) 563 #pragma warning restore 564 #elif defined (__CSMC__) 565 /* anonymous unions are enabled by default */ 566 #else 567 #warning Not supported compiler type 568 #endif 569 570 #ifdef __cplusplus 571 } 572 #endif 573 574 575 /*=============================================================================*/ 576 577 /** @addtogroup IO_ROUTINE I/O Routines 578 The Declaration of I/O Routines 579 @{ 580 */ 581 582 typedef volatile unsigned char vu8; 583 typedef volatile unsigned long vu32; 584 typedef volatile unsigned short vu16; 585 586 /** 587 * @brief Get a 8-bit unsigned value from specified address 588 * @param[in] addr Address to get 8-bit data from 589 * @return 8-bit unsigned value stored in specified address 590 */ 591 #define M8(addr) (*((vu8 *) (addr))) 592 593 /** 594 * @brief Get a 16-bit unsigned value from specified address 595 * @param[in] addr Address to get 16-bit data from 596 * @return 16-bit unsigned value stored in specified address 597 * @note The input address must be 16-bit aligned 598 */ 599 #define M16(addr) (*((vu16 *) (addr))) 600 601 /** 602 * @brief Get a 32-bit unsigned value from specified address 603 * @param[in] addr Address to get 32-bit data from 604 * @return 32-bit unsigned value stored in specified address 605 * @note The input address must be 32-bit aligned 606 */ 607 #define M32(addr) (*((vu32 *) (addr))) 608 609 /** 610 * @brief Set a 32-bit unsigned value to specified I/O port 611 * @param[in] port Port address to set 32-bit data 612 * @param[in] value Value to write to I/O port 613 * @return None 614 * @note The output port must be 32-bit aligned 615 */ 616 #define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) 617 618 /** 619 * @brief Get a 32-bit unsigned value from specified I/O port 620 * @param[in] port Port address to get 32-bit data from 621 * @return 32-bit unsigned value stored in specified I/O port 622 * @note The input port must be 32-bit aligned 623 */ 624 #define inpw(port) ((*((volatile unsigned int *)(port)))) 625 626 /** 627 * @brief Set a 16-bit unsigned value to specified I/O port 628 * @param[in] port Port address to set 16-bit data 629 * @param[in] value Value to write to I/O port 630 * @return None 631 * @note The output port must be 16-bit aligned 632 */ 633 #define outps(port,value) (*((volatile unsigned short *)(port))=(value)) 634 635 /** 636 * @brief Get a 16-bit unsigned value from specified I/O port 637 * @param[in] port Port address to get 16-bit data from 638 * @return 16-bit unsigned value stored in specified I/O port 639 * @note The input port must be 16-bit aligned 640 */ 641 #define inps(port) ((*((volatile unsigned short *)(port)))) 642 643 /** 644 * @brief Set a 8-bit unsigned value to specified I/O port 645 * @param[in] port Port address to set 8-bit data 646 * @param[in] value Value to write to I/O port 647 * @return None 648 */ 649 #define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) 650 651 /** 652 * @brief Get a 8-bit unsigned value from specified I/O port 653 * @param[in] port Port address to get 8-bit data from 654 * @return 8-bit unsigned value stored in specified I/O port 655 */ 656 #define inpb(port) ((*((volatile unsigned char *)(port)))) 657 658 /** 659 * @brief Set a 32-bit unsigned value to specified I/O port 660 * @param[in] port Port address to set 32-bit data 661 * @param[in] value Value to write to I/O port 662 * @return None 663 * @note The output port must be 32-bit aligned 664 */ 665 #define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) 666 667 /** 668 * @brief Get a 32-bit unsigned value from specified I/O port 669 * @param[in] port Port address to get 32-bit data from 670 * @return 32-bit unsigned value stored in specified I/O port 671 * @note The input port must be 32-bit aligned 672 */ 673 #define inp32(port) ((*((volatile unsigned int *)(port)))) 674 675 /** 676 * @brief Set a 16-bit unsigned value to specified I/O port 677 * @param[in] port Port address to set 16-bit data 678 * @param[in] value Value to write to I/O port 679 * @return None 680 * @note The output port must be 16-bit aligned 681 */ 682 #define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) 683 684 /** 685 * @brief Get a 16-bit unsigned value from specified I/O port 686 * @param[in] port Port address to get 16-bit data from 687 * @return 16-bit unsigned value stored in specified I/O port 688 * @note The input port must be 16-bit aligned 689 */ 690 #define inp16(port) ((*((volatile unsigned short *)(port)))) 691 692 /** 693 * @brief Set a 8-bit unsigned value to specified I/O port 694 * @param[in] port Port address to set 8-bit data 695 * @param[in] value Value to write to I/O port 696 * @return None 697 */ 698 #define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) 699 700 /** 701 * @brief Get a 8-bit unsigned value from specified I/O port 702 * @param[in] port Port address to get 8-bit data from 703 * @return 8-bit unsigned value stored in specified I/O port 704 */ 705 #define inp8(port) ((*((volatile unsigned char *)(port)))) 706 707 /*@}*/ /* end of group IO_ROUTINE */ 708 709 710 /******************************************************************************/ 711 /* Legacy Constants */ 712 /******************************************************************************/ 713 714 /** @addtogroup Legacy_Constants Legacy Constants 715 Legacy Constants 716 @{ 717 */ 718 719 #define E_SUCCESS (0) 720 721 #ifndef NULL 722 #define NULL (0) ///< NULL pointer 723 #endif 724 725 /* 726 * Avoid redefined warning in the integration with cmsis_rtos_v2, so to match wrapper.h 727 * #define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value 728 * #define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value 729 */ 730 #define TRUE 1 731 #define FALSE 0 732 733 #define ENABLE (1UL) ///< Enable, define to use in API parameters 734 #define DISABLE (0UL) ///< Disable, define to use in API parameters 735 736 /* Define one bit mask */ 737 #define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer 738 #define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer 739 #define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer 740 #define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer 741 #define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer 742 #define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer 743 #define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer 744 #define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer 745 #define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer 746 #define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer 747 #define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer 748 #define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer 749 #define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer 750 #define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer 751 #define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer 752 #define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer 753 #define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer 754 #define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer 755 #define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer 756 #define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer 757 #define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer 758 #define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer 759 #define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer 760 #define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer 761 #define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer 762 #define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer 763 #define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer 764 #define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer 765 #define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer 766 #define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer 767 #define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer 768 #define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer 769 770 /* Byte Mask Definitions */ 771 #define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer 772 #define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer 773 #define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer 774 #define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer 775 776 #define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ 777 #define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ 778 #define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ 779 #define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ 780 781 /*@}*/ /* end of group Legacy_Constants */ 782 783 784 /******************************************************************************/ 785 /* Peripheral header files */ 786 /******************************************************************************/ 787 #include "acmp.h" 788 #include "canfd.h" 789 #include "clk.h" 790 #include "crc.h" 791 #include "crypto.h" 792 #include "dac.h" 793 #include "eadc.h" 794 #include "ebi.h" 795 #include "ecap.h" 796 #include "epwm.h" 797 #include "gpio.h" 798 #include "i2c.h" 799 #include "lpadc.h" 800 #include "lpgpio.h" 801 #include "lpi2c.h" 802 #include "lppdma.h" 803 #include "lptmr.h" 804 #include "lptmr_pwm.h" 805 #include "lpuart.h" 806 #include "opa.h" 807 #include "otg.h" 808 #include "lpspi.h" 809 #include "pdma.h" 810 #include "pwm.h" 811 #include "eqei.h" 812 #include "qspi.h" 813 #include "rmc.h" 814 #include "rng.h" 815 #include "rtc.h" 816 #include "spi.h" 817 #include "sys.h" 818 #include "timer.h" 819 #include "timer_pwm.h" 820 #include "tk.h" 821 #include "trng.h" 822 #include "ttmr.h" 823 #include "uart.h" 824 #include "usbd.h" 825 #include "usci_i2c.h" 826 #include "usci_spi.h" 827 #include "usci_uart.h" 828 #include "utcpd.h" 829 #include "wdt.h" 830 #include "wwdt.h" 831 832 #endif /* __M2L31_H__ */ 833
