1 /****************************************************************************//**
2 * @file i2c.h
3 * @version V1.00
4 * @brief M480 series I2C driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2C_H__
10 #define __I2C_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup I2C_Driver I2C Driver
23 @{
24 */
25
26 /** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
27 @{
28 */
29
30 /*---------------------------------------------------------------------------------------------------------*/
31 /* I2C_CTL constant definitions. */
32 /*---------------------------------------------------------------------------------------------------------*/
33 #define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
34 #define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
35 #define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
36 #define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
37 #define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
38 #define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
39 #define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
40 #define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
41 #define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
42
43 /*---------------------------------------------------------------------------------------------------------*/
44 /* I2C GCMode constant definitions. */
45 /*---------------------------------------------------------------------------------------------------------*/
46 #define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
47 #define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
48
49 /*---------------------------------------------------------------------------------------------------------*/
50 /* I2C SMBUS constant definitions. */
51 /*---------------------------------------------------------------------------------------------------------*/
52 #define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable \hideinitializer */
53 #define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable \hideinitializer */
54 #define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function \hideinitializer */
55 #define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function \hideinitializer */
56
57 /*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
58
59 /** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
60 @{
61 */
62 /**
63 * @brief The macro is used to set I2C bus condition at One Time
64 *
65 * @param[in] i2c Specify I2C port
66 * @param[in] u8Ctrl A byte writes to I2C control register
67 *
68 * @return None
69 *
70 * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
71 * \hideinitializer
72 */
73 #define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
74
75 /**
76 * @brief The macro is used to set START condition of I2C Bus
77 *
78 * @param[in] i2c Specify I2C port
79 *
80 * @return None
81 *
82 * @details Set the I2C bus START condition in I2C_CTL register.
83 * \hideinitializer
84 */
85 #define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
86
87 /**
88 * @brief The macro is used to wait I2C bus status get ready
89 *
90 * @param[in] i2c Specify I2C port
91 *
92 * @return None
93 *
94 * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
95 * \hideinitializer
96 */
97 #define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
98
99 /**
100 * @brief The macro is used to Read I2C Bus Data Register
101 *
102 * @param[in] i2c Specify I2C port
103 *
104 * @return A byte of I2C data register
105 *
106 * @details I2C controller read data from bus and save it in I2CDAT register.
107 * \hideinitializer
108 */
109 #define I2C_GET_DATA(i2c) ((i2c)->DAT)
110
111 /**
112 * @brief Write a Data to I2C Data Register
113 *
114 * @param[in] i2c Specify I2C port
115 * @param[in] u8Data A byte that writes to data register
116 *
117 * @return None
118 *
119 * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
120 * \hideinitializer
121 */
122 #define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
123
124 /**
125 * @brief Get I2C Bus status code
126 *
127 * @param[in] i2c Specify I2C port
128 *
129 * @return I2C status code
130 *
131 * @details To get this status code to monitor I2C bus event.
132 * \hideinitializer
133 */
134 #define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
135
136 /**
137 * @brief Get Time-out flag from I2C Bus
138 *
139 * @param[in] i2c Specify I2C port
140 *
141 * @retval 0 I2C Bus time-out is not happened
142 * @retval 1 I2C Bus time-out is happened
143 *
144 * @details When I2C bus occurs time-out event, the time-out flag will be set.
145 * \hideinitializer
146 */
147 #define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
148
149 /**
150 * @brief To get wake-up flag from I2C Bus
151 *
152 * @param[in] i2c Specify I2C port
153 *
154 * @retval 0 Chip is not woken-up from power-down mode
155 * @retval 1 Chip is woken-up from power-down mode
156 *
157 * @details I2C bus occurs wake-up event, wake-up flag will be set.
158 * \hideinitializer
159 */
160 #define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
161
162 /**
163 * @brief To clear wake-up flag
164 *
165 * @param[in] i2c Specify I2C port
166 *
167 * @return None
168 *
169 * @details If wake-up flag is set, use this macro to clear it.
170 * \hideinitializer
171 */
172 #define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
173
174 /**
175 * @brief To get SMBus Status
176 *
177 * @param[in] i2c Specify I2C port
178 *
179 * @return SMBus status
180 *
181 * @details To get the Bus Management status of I2C_BUSSTS register
182 * \hideinitializer
183 *
184 */
185 #define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
186
187 /**
188 * @brief Get SMBus CRC value
189 *
190 * @param[in] i2c Specify I2C port
191 *
192 * @return Packet error check byte value
193 *
194 * @details The CRC check value after a transmission or a reception by count by using CRC8
195 * \hideinitializer
196 */
197 #define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
198
199 /**
200 * @brief Set SMBus Bytes number of Transmission or reception
201 *
202 * @param[in] i2c Specify I2C port
203 * @param[in] u32PktSize Transmit / Receive bytes
204 *
205 * @return None
206 *
207 * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
208 * \hideinitializer
209 */
210 #define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
211
212 /**
213 * @brief Enable SMBus Alert function
214 *
215 * @param[in] i2c Specify I2C port
216 *
217 * @return None
218 *
219 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
220 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
221 * \hideinitializer
222 */
223 #define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
224
225 /**
226 * @brief Disable SMBus Alert pin function
227 *
228 * @param[in] i2c Specify I2C port
229 *
230 * @return None
231 *
232 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
233 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
234 * \hideinitializer
235 */
236 #define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
237
238 /**
239 * @brief Set SMBus SUSCON pin is output mode
240 *
241 * @param[in] i2c Specify I2C port
242 *
243 * @return None
244 *
245 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
246 *
247 * \hideinitializer
248 */
249 #define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
250
251 /**
252 * @brief Set SMBus SUSCON pin is input mode
253 *
254 * @param[in] i2c Specify I2C port
255 *
256 * @return None
257 *
258 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
259 *
260 * \hideinitializer
261 */
262 #define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
263
264 /**
265 * @brief Set SMBus SUSCON pin output high state
266 *
267 * @param[in] i2c Specify I2C port
268 *
269 * @return None
270 *
271 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
272 * \hideinitializer
273 */
274 #define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
275
276
277 /**
278 * @brief Set SMBus SUSCON pin output low state
279 *
280 * @param[in] i2c Specify I2C port
281 *
282 * @return None
283 *
284 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
285 * \hideinitializer
286 */
287 #define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
288
289 /**
290 * @brief Enable SMBus Acknowledge control by manual
291 *
292 * @param[in] i2c Specify I2C port
293 *
294 * @return None
295 *
296 * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
297 * \hideinitializer
298 */
299 #define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
300
301 /**
302 * @brief Disable SMBus Acknowledge control by manual
303 *
304 * @param[in] i2c Specify I2C port
305 *
306 * @return None
307 *
308 * @details Disable acknowledge response control by user.
309 * \hideinitializer
310 */
311 #define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
312
313 /**
314 * @brief Enable SMBus Acknowledge manual interrupt
315 *
316 * @param[in] i2c Specify I2C port
317 *
318 * @return None
319 *
320 * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
321 * \hideinitializer
322 */
323 #define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
324
325 /**
326 * @brief Disable SMBus Acknowledge manual interrupt
327 *
328 * @param[in] i2c Specify I2C port
329 *
330 * @return None
331 *
332 * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
333 * \hideinitializer
334 */
335 #define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
336
337 /**
338 * @brief Enable SMBus PEC clear at REPEAT START
339 *
340 * @param[in] i2c Specify I2C port
341 *
342 * @return None
343 *
344 * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
345 * \hideinitializer
346 */
347 #define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
348
349 /**
350 * @brief Disable SMBus PEC clear at Repeat START
351 *
352 * @param[in] i2c Specify I2C port
353 *
354 * @return None
355 *
356 * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
357 * \hideinitializer
358 */
359 #define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
360
361 /**
362 * @brief Enable RX PDMA function.
363 * @param[in] i2c The pointer of the specified I2C module.
364 * @return None.
365 * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
366 * \hideinitializer
367 */
368 #define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
369
370 /**
371 * @brief Enable TX PDMA function.
372 * @param[in] i2c The pointer of the specified I2C module.
373 * @return None.
374 * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
375 * \hideinitializer
376 */
377 #define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
378
379 /**
380 * @brief Disable RX PDMA transfer.
381 * @param[in] i2c The pointer of the specified I2C module.
382 * @return None.
383 * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
384 * \hideinitializer
385 */
386 #define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
387
388 /**
389 * @brief Disable TX PDMA transfer.
390 * @param[in] i2c The pointer of the specified I2C module.
391 * @return None.
392 * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
393 * \hideinitializer
394 */
395 #define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
396
397 /**
398 * @brief Enable PDMA stretch function.
399 * @param[in] i2c The pointer of the specified I2C module.
400 * @return None.
401 * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
402 * \hideinitializer
403 */
404 #define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
405
406 /**
407 * @brief Disable PDMA stretch function.
408 * @param[in] i2c The pointer of the specified I2C module.
409 * @return None.
410 * @details I2C will send STOP after PDMA transfers done automatically.
411 * \hideinitializer
412 */
413 #define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
414
415 /**
416 * @brief Reset PDMA function.
417 * @param[in] i2c The pointer of the specified I2C module.
418 * @return None.
419 * @details I2C PDMA engine will be reset after this function is called.
420 * \hideinitializer
421 */
422 #define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
423
424 /*---------------------------------------------------------------------------------------------------------*/
425 /* inline functions */
426 /*---------------------------------------------------------------------------------------------------------*/
427
428 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
429 __STATIC_INLINE void I2C_STOP(I2C_T *i2c);
430
431 /**
432 * @brief The macro is used to set STOP condition of I2C Bus
433 *
434 * @param[in] i2c Specify I2C port
435 *
436 * @return None
437 *
438 * @details Set the I2C bus STOP condition in I2C_CTL register.
439 */
I2C_STOP(I2C_T * i2c)440 __STATIC_INLINE void I2C_STOP(I2C_T *i2c)
441 {
442
443 (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
444 while(i2c->CTL0 & I2C_CTL0_STO_Msk)
445 {
446 }
447 }
448
449 void I2C_ClearTimeoutFlag(I2C_T *i2c);
450 void I2C_Close(I2C_T *i2c);
451 void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
452 void I2C_DisableInt(I2C_T *i2c);
453 void I2C_EnableInt(I2C_T *i2c);
454 uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
455 uint32_t I2C_GetIntFlag(I2C_T *i2c);
456 uint32_t I2C_GetStatus(I2C_T *i2c);
457 uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
458 uint8_t I2C_GetData(I2C_T *i2c);
459 void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
460 void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
461 uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
462 void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
463 void I2C_DisableTimeout(I2C_T *i2c);
464 void I2C_EnableWakeup(I2C_T *i2c);
465 void I2C_DisableWakeup(I2C_T *i2c);
466 void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
467 void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
468 uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
469 uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
470 uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
471 uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
472 uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
473 uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
474 uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
475 uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
476 uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
477 uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
478 uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
479 uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
480 uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
481 void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
482 void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
483 void I2C_SMBusClose(I2C_T *i2c);
484 void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
485 uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
486 void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
487 void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
488 void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
489
490 /*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
491
492 /*@}*/ /* end of group I2C_Driver */
493
494 /*@}*/ /* end of group Standard_Driver */
495
496 #ifdef __cplusplus
497 }
498 #endif
499
500 #endif
501
502 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
503
