1 /**************************************************************************//** 2 * @file trng_reg.h 3 * @version V1.00 4 * @brief TRNG register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TRNG_REG_H__ 10 #define __TRNG_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- True Random Number Generator -------------------------*/ 19 /** 20 @addtogroup TRNG True Random Number Generator(TRNG) 21 Memory Mapped Structure for TRNG Controller 22 @{ */ 23 24 typedef struct 25 { 26 27 28 /** 29 * @var TRNG_T::CTL 30 * Offset: 0x00 TRNG Control Register and Status 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[0] |TRNGEN |Random Number Generator Enable Bit 35 * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1. 36 * | | |0 = TRNG disabled. 37 * | | |1 = TRNG enabled. 38 * | | |Note: TRNGEN is an enable bit of digital part 39 * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. 40 * |[1] |DVIF |Data Valid (Read Only) 41 * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. 42 * | | |1 = Data is valid. A valid random number can be read form RNGD. 43 * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. 44 * |[5:2] |CLKP |Clock Prescaler 45 * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) 46 * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. 47 * | | |0000 = 80 ~ 100 MHz. 48 * | | |0001 = 60 ~ 80 MHz. 49 * | | |0010 = 50 ~60 MHz. 50 * | | |0011 = 40 ~50 MHz. 51 * | | |0100 = 30 ~40 MHz. 52 * | | |0101 = 25 ~30 MHz. 53 * | | |0110 = 20 ~25 MHz. 54 * | | |0111 = 15 ~20 MHz. 55 * | | |1000 = 12 ~15 MHz. 56 * | | |1001 = 9 ~12 MHz. 57 * | | |1010 = 7 ~9 MHz. 58 * | | |1011 = 6 ~7 MHz. 59 * | | |1100 = 5 ~6 MHz. 60 * | | |1101 = 4 ~5 MHz. 61 * | | |1111 = Reserved. 62 * |[6] |DVIEN |Data Valid Interrupt Enable Bit 63 * | | |0 = Interrupt disabled.. 64 * | | |1 = Interrupt enabled. 65 * |[7] |READY |Random Number Generator Ready (Read Only) 66 * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. 67 * | | |0 = RNG is not ready or was not activated. 68 * | | |1 = RNG is ready to be enabled.. 69 * |[31:8] |Reversed |Reversed 70 * @var TRNG_T::DATA 71 * Offset: 0x04 TRNG Data Register 72 * --------------------------------------------------------------------------------------------------- 73 * |Bits |Field |Descriptions 74 * | :----: | :----: | :---- | 75 * |[7:0] |DATA |Random Number Generator Data (Read Only) 76 * | | |The DATA store the random number generated by TRNG and can be read only once. 77 * @var TRNG_T::ACT 78 * Offset: 0x0C TRNG Activation Register 79 * --------------------------------------------------------------------------------------------------- 80 * |Bits |Field |Descriptions 81 * | :----: | :----: | :---- | 82 * |[6:0] |VER |TRNG Version 83 * | | |TRNG version number is dependent on TRNG module. 84 * | | |0x02:(Current Version Number) 85 * |[7] |ACT |Random Number Generator Activation 86 * | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. 87 * | | |0 = TRNG inactive. 88 * | | |1 = TRNG active. 89 * | | |Note: ACT is an enable bit of analog part 90 * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. 91 */ 92 __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ 93 __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ 94 /// @cond HIDDEN_SYMBOLS 95 __I uint32_t RESERVE0[1]; 96 /// @endcond //HIDDEN_SYMBOLS 97 __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ 98 99 } TRNG_T; 100 101 /** 102 @addtogroup TRNG_CONST TRNG Bit Field Definition 103 Constant Definitions for TRNG Controller 104 @{ */ 105 106 #define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ 107 #define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ 108 109 #define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ 110 #define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ 111 112 #define TRNG_CTL_CLKP_Pos (2) /*!< TRNG_T::CTL: CLKP Position */ 113 #define TRNG_CTL_CLKP_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKP Mask */ 114 115 #define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ 116 #define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ 117 118 #define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ 119 #define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ 120 121 #define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */ 122 #define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ 123 124 #define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ 125 #define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ 126 127 #define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ 128 #define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ 129 130 #define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ 131 #define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ 132 133 /**@}*/ /* TRNG_CONST */ 134 /**@}*/ /* end of TRNG register group */ 135 /**@}*/ /* end of REGISTER group */ 136 137 138 #endif /* __TRNG_REG_H__ */ 139
