1 /**************************************************************************//**
2  * @file     crc.c
3  * @version  V3.00
4  * @brief    Cyclic Redundancy Check(CRC) driver source file
5  *
6  * @copyright SPDX-License-Identifier: Apache-2.0
7  * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8  *****************************************************************************/
9 #include "NuMicro.h"
10 
11 
12 /** @addtogroup Standard_Driver Standard Driver
13   @{
14 */
15 
16 /** @addtogroup CRC_Driver CRC Driver
17   @{
18 */
19 
20 /** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
21   @{
22 */
23 
24 /**
25   * @brief      CRC Open
26   *
27   * @param[in]  u32Mode         CRC operation polynomial mode. Valid values are:
28   *                             - \ref CRC_CCITT
29   *                             - \ref CRC_8
30   *                             - \ref CRC_16
31   *                             - \ref CRC_32
32   * @param[in]  u32Attribute    CRC operation data attribute. Valid values are combined with:
33   *                             - \ref CRC_CHECKSUM_COM
34   *                             - \ref CRC_CHECKSUM_RVS
35   *                             - \ref CRC_WDATA_COM
36   *                             - \ref CRC_WDATA_RVS
37   * @param[in]  u32Seed         Seed value.
38   * @param[in]  u32DataLen      CPU Write Data Length. Valid values are:
39   *                             - \ref CRC_CPU_WDATA_8
40   *                             - \ref CRC_CPU_WDATA_16
41   *                             - \ref CRC_CPU_WDATA_32
42   *
43   * @return     None
44   *
45   * @details    This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
46   *             After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
47   */
CRC_Open(uint32_t u32Mode,uint32_t u32Attribute,uint32_t u32Seed,uint32_t u32DataLen)48 void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
49 {
50     CRC->SEED = u32Seed;
51 
52 	switch(u32Mode)
53 	{
54         case CRC_CCITT:
55             u32Mode = CRC_16;
56             CRC->POLYNOMIAL = 0x1021;
57             break;
58         case CRC_8:
59             CRC->POLYNOMIAL = 0x7;
60             break;
61         case CRC_16:
62             CRC->POLYNOMIAL = 0x8005;
63             break;
64         case CRC_32:
65             CRC->POLYNOMIAL = 0x04C11DB7;
66             break;
67 		default:
68             CRC->POLYNOMIAL = 0x0ul;
69             break;
70 	}
71 
72     CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
73 
74     /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */
75     CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
76 }
77 
78 /**
79   * @brief      Get CRC Checksum
80   *
81   * @param[in]  None
82   *
83   * @return     Checksum Result
84   *
85   * @details    This function gets the CRC checksum result by current CRC polynomial mode.
86   */
CRC_GetChecksum(void)87 uint32_t CRC_GetChecksum(void)
88 {
89     uint32_t u32Checksum = 0UL;
90 
91     switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
92     {
93         case CRC_CCITT:
94         case CRC_16:
95             u32Checksum = (CRC->CHECKSUM & 0xFFFFUL);
96             break;
97 
98         case CRC_32:
99             u32Checksum = CRC->CHECKSUM;
100             break;
101 
102         case CRC_8:
103             u32Checksum = (CRC->CHECKSUM & 0xFFUL);
104             break;
105 
106         default:
107             break;
108     }
109 
110     return u32Checksum;
111 }
112 
113 /**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
114 
115 /**@}*/ /* end of group CRC_Driver */
116 
117 /**@}*/ /* end of group Standard_Driver */
118