1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V1.00 4 * @brief CLK register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __KEYPAD_REG_H__ 10 #define __KEYPAD_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /******************************************************************************/ 17 /* Device Specific Peripheral registers structures */ 18 /******************************************************************************/ 19 20 /** @addtogroup REGISTER Control Register 21 22 @{ 23 24 */ 25 26 27 /*---------------------- Keypad Control Interface -------------------------*/ 28 /** 29 @addtogroup KPI Keypad Control Interface (KPI) 30 Memory Mapped Structure for KPI Controller 31 @{ */ 32 33 typedef struct 34 { 35 36 37 /** 38 * @var KPI_T::CTL 39 * Offset: 0x00 Keypad Control Register 40 * --------------------------------------------------------------------------------------------------- 41 * |Bits |Field |Descriptions 42 * | :----: | :----: | :---- | 43 * |[0] |KPEN |Keypad Scan Enable Bit 44 * | | |Setting this bit high enables the key scan function. 45 * | | |0 = Keypad scan Disabled. 46 * | | |1 = Keypad scan Enabled. 47 * |[1] |KPIEN |Key Press Key Interrupt Enable Bit 48 * | | |The keypad controller will generate an interrupt when the controller detects any effective key press. 49 * | | |0 = Keypad press interrupt Disabled. 50 * | | |1 = Keypad press interrupt Enabled. 51 * | | |Note: The bit will be reset when KPI reset occurs. 52 * |[2] |KRIEN |Key Release Key Interrupt Enable Bit 53 * | | |The keypad controller will generate an interrupt when the controller detects keypad status changes from press to release. 54 * | | |0 = Keypad release interrupt Disabled. 55 * | | |1 = Keypad release interrupt Enabled. 56 * | | |Note: The bit will be reset when KPI reset occurs. 57 * |[3] |KIEN |Key Interrupt Enable Bit 58 * | | |0 = Keypad interrupt Disabled. 59 * | | |1 = Keypad interrupt Enabled. 60 * | | |Note: The bit will be reset when KPI reset occurs. 61 * |[5:4] |DBCT |De-bounce Cycle Time 62 * | | |For keypad debounce, keypad will generate an interrupt when key press, key release or three key reset continued n * key array scan time. 63 * | | |00 = n=1. 64 * | | |01 = n=2. 65 * | | |10 = n=3. 66 * | | |11 = n=4. 67 * | | |Note: It would need more time to indicate key press and release event when users selected more debounce cycle time. 68 * |[15:8] |PSC |Row Scan Cycle Pre-scale Value 69 * | | |This value is used to pre-scale row scan cycle. 70 * | | |The pre-scale counter is clocked by the divided crystal clock, xCLOCK. 71 * | | |The divided number is from 1 to 256. 72 * | | |E.g.If the crystal clock is 1Mhz then the xCLOCK period is 1us. 73 * | | |If the keypad matric is 3x3 then 74 * | | |Each row scan time = xCLOCK x PRESCALE PSC x PrescaleDividerPSCDIV. 75 * | | |Key array scan time = Each row scan time x ROWS. 76 * | | |Example scan time for PRESCALE = 0x40, and PrescaleDividerPSCDIV = 0x1F. 77 * | | |Each row scan time = 1us x 65 x 32 = 2.08ms. 78 * | | |Scan time = 2.08 x 3 = 6.24ms. 79 * | | |Note: 80 * | | |When PRESCALEPSC is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV), 81 * | | |in the above example, and if scan row delay cycle is 4 xclock 82 * | | |The maximum DBCLKSEL should be 10244*256 xCLOCK, bouncing time is 1ms. 83 * |[19:16] |DBCLKSEL |Scan in De-bounce Sampling Cycle Selection 84 * | | |0000 = Reserved. 85 * | | |0001 = Reserved. 86 * | | |0010 = Reserved. 87 * | | |0011 = Sample interrupt input once per 8 clocks. 88 * | | |0100 = Sample interrupt input once per 16 clocks. 89 * | | |0101 = Sample interrupt input once per 32 clocks. 90 * | | |0110 = Sample interrupt input once per 64 clocks. 91 * | | |0111 = Sample interrupt input once per 128 clocks. 92 * | | |1000 = Sample interrupt input once per 256 clocks. 93 * | | |1001 = Sample interrupt input once per 512 clocks. 94 * | | |1010 = Sample interrupt input once per 1024 clocks. 95 * | | |1011 = Sample interrupt input once per 2048 clocks. 96 * | | |1100 = Sample interrupt input once per 4096 clocks. 97 * | | |1101 = Sample interrupt input once per 8192 clocks. 98 * | | |1110 = reserved. 99 * | | |1111 = reserved. 100 * | | |Note: 101 * | | |scan row delay cycle < debounce sampling cycle. 102 * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain). 103 * | | |row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIVprescale * 32 (xclock). 104 * | | |xclock = 1 MHz ~32 kHz. 105 * | | |bouncing time last for 1ms 106 * | | |For example, if xclock = 1 MHz,. 107 * | | |debounce sampling cycle choose 1024 xclock, 108 * | | |and scan row delay cycle choose 8 xclock, 109 * | | |row scan time should choose larger than (8+2048+3) xclock, 110 * | | |suppose PrescaleDividerPSCDIV = 0x1F, then prescale = 65 (20562059/32 = 64.2535). 111 * |[23:22] |ROWDLY |Scan Row Delay 112 * | | |Setting delay cycle when row change, for avoid KPI from detecting wrong key.. 113 * | | |00 = 4 KPI engine clock cycle. 114 * | | |01 = 8 KPI engine clock cycle. 115 * | | |10 = 16 KPI engine clock cycle. 116 * | | |11 = 32 KPI engine clock cycle. 117 * | | |Note: 118 * | | |scan row delay cycle < debounce sampling cycle. 119 * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain). 120 * |[26:24] |KCOL |Keypad Matrix COL Number 121 * | | |The keypad matrix is set by ROW x COL. The COL number can be set 1 to 8. 122 * | | |000 = 1. 123 * | | |001 = 2. 124 * | | |010 = 3. 125 * | | |011 = 4. 126 * | | |100 = 5. 127 * | | |101 = 6. 128 * | | |110 = 7. 129 * | | |111 = 8. 130 * |[30:28] |KROW |Keypad Matrix ROW Number 131 * | | |The keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6. 132 * | | |000 = reserved. 133 * | | |001 = 2. 134 * | | |010 = 3. 135 * | | |011 = 4. 136 * | | |100 = 5. 137 * | | |101 = 6. 138 * | | |110 = Reserved. 139 * | | |111 = Reserved. 140 * @var KPI_T::STATUS 141 * Offset: 0x08 Keypad Status Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[1] |TKRIF |3Three-keys Reset Interrupt Flag 146 * | | |This bit will be set after 3Three-keys reset occurs. 147 * | | |When READ: 148 * | | |0 = No reset. 149 * | | |1 = 3Three -keys reset interrupt occurred. 150 * | | |When WRITE: 151 * | | |0 = No operation. 152 * | | |1 = Clear interrupt flag. 153 * |[2] |KIF |Key Interrupt Flag 154 * | | |This bit indicates the key scan interrupt is active when any key press or, key release or three key reset or wake up. 155 * | | |When READ: 156 * | | |0 = No reset. 157 * | | |1 = Key press/Key release/3Three-key reset/wakeup interrupt occurred. 158 * | | |To clear KIF, software must clear KPIF, KRIF and TKRIF 159 * | | |(u9019u6BB5WSu81EAu5DF1u731Cu7684uFF0Cu5C0Du55CE?) 160 * |[3] |KRIF |Release Key Release Interrupt Flag 161 * | | |This bit indicates that some keys (one or multiple key) have been released. 162 * | | |When READ: 163 * | | |0 = No key release. 164 * | | |1 = At least one key release. 165 * | | |Note: To clear KRKEYINTIF, software must clear each releasing event flag that are shown on u201Ckey releasing eventu201D 166 * | | |KPI_KRF0/1 registers. 167 * | | |C code example: 168 * | | |DWORD RKE0, RKE1 169 * | | |PKE0 = reg_read(KPIKRE0); PKE1 = reg_read(KPIKRE1);. 170 * | | |Reg_write(KPIKRE0, RKE0); Reg_write(KPIKRE1, RKE1) 171 * |[4] |KPIF |Key Press Key Interrupt Flag 172 * | | |This bit indicates that some keys (one or multiple key) have been pressed. 173 * | | |When READ: 174 * | | |0 = No key press. 175 * | | |1 = At least one key press. 176 * | | |Note: To clear KPIFPKEYINT, software must clear each pressing event flag that are shown on u201CKPIKPE1KPI_KPF0/1, KPIKPE0u201D 177 * | | |registers. 178 * | | |C code example: 179 * | | |DWORD PKE0, PKE1 180 * | | |PKE0 = reg_read(KPIKPE0); PKE1 = reg_read(KPIKPE1);. 181 * | | |Reg_write(KPIKPE0, PKE0); Reg_write(KPIKPE1, PKE1) 182 * @var KPI_T::KST0 183 * Offset: 0x10 Keypad State Register 0 184 * --------------------------------------------------------------------------------------------------- 185 * |Bits |Field |Descriptions 186 * | :----: | :----: | :---- | 187 * |[31:0] |KSTmn |Key State 188 * | | |KESTm,n: m is row number, n is column number. 189 * | | |0 = Key m,n is pressing. 190 * | | |1 = Key m,n is releasing. 191 * @var KPI_T::KST1 192 * Offset: 0x14 Keypad State Register 1 193 * --------------------------------------------------------------------------------------------------- 194 * |Bits |Field |Descriptions 195 * | :----: | :----: | :---- | 196 * |[15:0] |KESTmn |Key State 197 * | | |KESTm,n: m is row number, n is column number. 198 * | | |0 = Key m,n is pressing. 199 * | | |1 = Key m,n is releasing. 200 * @var KPI_T::KPF0 201 * Offset: 0x18 Lower 32 Key Press Flag Register 0 202 * --------------------------------------------------------------------------------------------------- 203 * |Bits |Field |Descriptions 204 * | :----: | :----: | :---- | 205 * |[31:0] |KPFmn |Lower 32 Key Press Event Change IndicatorFlag 206 * | | |m is row number, n is column number. 207 * | | |KPE mn[X] = 1, m=row, n=column:. 208 * | | |0 = No key event. 209 * | | |1 = Corresponding key has a high to low event change. 210 * | | |Note: 211 * | | |Hardware will set this bit, and software should clear this bit by writing 1. 212 * | | |Software can clear PKEYINT KPIF (KPI_STATUS[4]) by writing 1 bit by bit to this register. 213 * @var KPI_T::KPF1 214 * Offset: 0x1C Upper 32 Key Press Flag Register 1 215 * --------------------------------------------------------------------------------------------------- 216 * |Bits |Field |Descriptions 217 * | :----: | :----: | :---- | 218 * |[15:0] |KPEmn |Upper 32 Key Press Event Change IndicatorFlag 219 * | | |KPE mn[X] = 1, m =is row number, n =is column number.:. 220 * | | |0 = No key event. 221 * | | |1 = Corresponding key has a high to low event change. 222 * | | |Note: 223 * | | |Hardware will set this bit, and software should clear this bit by writing 1. 224 * | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register. 225 * @var KPI_T::KRF0 226 * Offset: 0x20 Lower 32 Key Release Flag Register 0 227 * --------------------------------------------------------------------------------------------------- 228 * |Bits |Field |Descriptions 229 * | :----: | :----: | :---- | 230 * |[31:0] |KRFmn |Lower 32 Key Release Event Change IndicatorFlag 231 * | | |KRE mn[X] = 1, m= is row number, n= is column number.:. 232 * | | |0 = No key event. 233 * | | |1 = Corresponding key has a low to high event change. 234 * | | |Note: 235 * | | |Hardware will set this bit, and software should clear this bit by writing 1. 236 * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. 237 * @var KPI_T::KRF1 238 * Offset: 0x24 Upper 32 Key Release Flag Register 1 239 * --------------------------------------------------------------------------------------------------- 240 * |Bits |Field |Descriptions 241 * | :----: | :----: | :---- | 242 * |[15:0] |KRFmn |Upper 32 Key Release Event Change IndicatorFlag 243 * | | |KRE mn[X] = 1, m =is row number, n =is column number.:. 244 * | | |0 = No key event. 245 * | | |1 = Corresponding key has a low to high event change. 246 * | | |Note: 247 * | | |Hardware will set this bit, and software should clear this bit by writing 1. 248 * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. 249 * @var KPI_T::DLYCTL 250 * Offset: 0x28 Delay Control Register 251 * --------------------------------------------------------------------------------------------------- 252 * |Bits |Field |Descriptions 253 * | :----: | :----: | :---- | 254 * |[7:0] |PSCDIV |Pre-scale Divider 255 * | | |This value is used to divide RESCALE that is set in KPICONFKPI_CTL[15:8] 256 * | | |The prescale divider counter is clocked by the divided crystal clock, xCLOCK 257 * | | |The number is from 1 to 256. 258 * | | |E.g. If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matrix is 3x3. Then, 259 * | | |each row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIV. 260 * | | |key array scan time = each row scan time x ROWS. 261 * | | |example scan time for PRESCALEPSC = 0x40, and PrescaleDividerPSCDIV = 0x1F. 262 * | | |each row scan time = 1us x 65 x 32 = 2.08ms. 263 * | | |scan time = 2.08 x 3 = 6.24ms. 264 * | | |Note: 265 * | | |When PRESCALEPSC (KPICONFKPI_CTL[15:8]) is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV), 266 * | | |in the above example, and if scan row delay cycle is 4 xclock 267 * | | |The maximum DBCLKSEL(KPICONFKPI_CTL[19:16]) should be 1024 x clock, bouncing time is 1ms. 268 * |[17:8] |SCANDLY |Key Array Scan Delay 269 * | | |This value is used to insert delay cycle between each key array scan. 270 * | | |The key array scan delay counter is clocked by the divided crystal clock, xCLOCK. 271 * | | |Key array scan delay time = xCLOCK x KASDSCANDLY. 272 * | | |The number of key array scan delay cycle is 0 and from 2 to 1024. 273 * | | |0 = No delay. 274 * | | |Others = others + 1 cycles. 275 * | | |Note: 276 * | | |If the key array scan delay is set to 0, there are no delay between each key array scan. 277 * | | |There are no delay 1 cycle situation. 278 */ 279 __IO uint32_t CTL; /*!< [0x0000] Keypad Control Register */ 280 __IO uint32_t Reserved0; /*!< [0x0004] Reserved */ 281 __IO uint32_t STATUS; /*!< [0x0008] Keypad Status Register */ 282 __IO uint32_t Reserved1; /*!< [0x000c] Reserved */ 283 __I uint32_t KST[2]; /*!< [0x0010-0x0014] Keypad State Register 0 */ 284 __IO uint32_t KPF[2]; /*!< [0x0018-0x001c] Lower 32 Key Press Flag Register 0 */ 285 __IO uint32_t KRF[2]; /*!< [0x0020-0x0024] Lower 32 Key Release Flag Register 0 */ 286 __IO uint32_t DLYCTL; /*!< [0x0028] Delay Control Register */ 287 288 } KPI_T; 289 290 /** 291 @addtogroup KPI_CONST KPI Bit Field Definition 292 Constant Definitions for KPI Controller 293 @{ */ 294 295 #define KPI_CTL_KPEN_Pos (0) /*!< KPI_T::CTL: KPEN Position */ 296 #define KPI_CTL_KPEN_Msk (0x1ul << KPI_CTL_KPEN_Pos) /*!< KPI_T::CTL: KPEN Mask */ 297 298 #define KPI_CTL_KPIEN_Pos (1) /*!< KPI_T::CTL: KPIEN Position */ 299 #define KPI_CTL_KPIEN_Msk (0x1ul << KPI_CTL_KPIEN_Pos) /*!< KPI_T::CTL: KPIEN Mask */ 300 301 #define KPI_CTL_KRIEN_Pos (2) /*!< KPI_T::CTL: KRIEN Position */ 302 #define KPI_CTL_KRIEN_Msk (0x1ul << KPI_CTL_KRIEN_Pos) /*!< KPI_T::CTL: KRIEN Mask */ 303 304 #define KPI_CTL_KIEN_Pos (3) /*!< KPI_T::CTL: KIEN Position */ 305 #define KPI_CTL_KIEN_Msk (0x1ul << KPI_CTL_KIEN_Pos) /*!< KPI_T::CTL: KIEN Mask */ 306 307 #define KPI_CTL_DBCT_Pos (4) /*!< KPI_T::CTL: DBCT Position */ 308 #define KPI_CTL_DBCT_Msk (0x3ul << KPI_CTL_DBCT_Pos) /*!< KPI_T::CTL: DBCT Mask */ 309 310 #define KPI_CTL_PSC_Pos (8) /*!< KPI_T::CTL: PSC Position */ 311 #define KPI_CTL_PSC_Msk (0xfful << KPI_CTL_PSC_Pos) /*!< KPI_T::CTL: PSC Mask */ 312 313 #define KPI_CTL_DBCLKSEL_Pos (16) /*!< KPI_T::CTL: DBCLKSEL Position */ 314 #define KPI_CTL_DBCLKSEL_Msk (0xful << KPI_CTL_DBCLKSEL_Pos) /*!< KPI_T::CTL: DBCLKSEL Mask */ 315 316 #define KPI_CTL_ROWDLY_Pos (22) /*!< KPI_T::CTL: ROWDLY Position */ 317 #define KPI_CTL_ROWDLY_Msk (0x3ul << KPI_CTL_ROWDLY_Pos) /*!< KPI_T::CTL: ROWDLY Mask */ 318 319 #define KPI_CTL_KCOL_Pos (24) /*!< KPI_T::CTL: KCOL Position */ 320 #define KPI_CTL_KCOL_Msk (0x7ul << KPI_CTL_KCOL_Pos) /*!< KPI_T::CTL: KCOL Mask */ 321 322 #define KPI_CTL_KROW_Pos (28) /*!< KPI_T::CTL: KROW Position */ 323 #define KPI_CTL_KROW_Msk (0x7ul << KPI_CTL_KROW_Pos) /*!< KPI_T::CTL: KROW Mask */ 324 325 #define KPI_STATUS_TKRIF_Pos (1) /*!< KPI_T::STATUS: TKRIF Position */ 326 #define KPI_STATUS_TKRIF_Msk (0x1ul << KPI_STATUS_TKRIF_Pos) /*!< KPI_T::STATUS: TKRIF Mask */ 327 328 #define KPI_STATUS_KIF_Pos (2) /*!< KPI_T::STATUS: KIF Position */ 329 #define KPI_STATUS_KIF_Msk (0x1ul << KPI_STATUS_KIF_Pos) /*!< KPI_T::STATUS: KIF Mask */ 330 331 #define KPI_STATUS_KRIF_Pos (3) /*!< KPI_T::STATUS: KRIF Position */ 332 #define KPI_STATUS_KRIF_Msk (0x1ul << KPI_STATUS_KRIF_Pos) /*!< KPI_T::STATUS: KRIF Mask */ 333 334 #define KPI_STATUS_KPIF_Pos (4) /*!< KPI_T::STATUS: KPIF Position */ 335 #define KPI_STATUS_KPIF_Msk (0x1ul << KPI_STATUS_KPIF_Pos) /*!< KPI_T::STATUS: KPIF Mask */ 336 337 #define KPI_KST0_KSTmn_Pos (0) /*!< KPI_T::KST0: KSTmn Position */ 338 #define KPI_KST0_KSTmn_Msk (0xfffffffful << KPI_KST0_KSTmn_Pos) /*!< KPI_T::KST0: KSTmn Mask */ 339 340 #define KPI_KST1_KESTmn_Pos (0) /*!< KPI_T::KST1: KESTmn Position */ 341 #define KPI_KST1_KESTmn_Msk (0xfffful << KPI_KST1_KESTmn_Pos) /*!< KPI_T::KST1: KESTmn Mask */ 342 343 #define KPI_KPF0_KPFmn_Pos (0) /*!< KPI_T::KPF0: KPFmn Position */ 344 #define KPI_KPF0_KPFmn_Msk (0xfffffffful << KPI_KPF0_KPFmn_Pos) /*!< KPI_T::KPF0: KPFmn Mask */ 345 346 #define KPI_KPF1_KPEmn_Pos (0) /*!< KPI_T::KPF1: KPEmn Position */ 347 #define KPI_KPF1_KPEmn_Msk (0xfffful << KPI_KPF1_KPEmn_Pos) /*!< KPI_T::KPF1: KPEmn Mask */ 348 349 #define KPI_KRF0_KRFmn_Pos (0) /*!< KPI_T::KRF0: KRFmn Position */ 350 #define KPI_KRF0_KRFmn_Msk (0xfffffffful << KPI_KRF0_KRFmn_Pos) /*!< KPI_T::KRF0: KRFmn Mask */ 351 352 #define KPI_KRF1_KRFmn_Pos (0) /*!< KPI_T::KRF1: KRFmn Position */ 353 #define KPI_KRF1_KRFmn_Msk (0xfffful << KPI_KRF1_KRFmn_Pos) /*!< KPI_T::KRF1: KRFmn Mask */ 354 355 #define KPI_DLYCTL_PSCDIV_Pos (0) /*!< KPI_T::DLYCTL: PSCDIV Position */ 356 #define KPI_DLYCTL_PSCDIV_Msk (0xfful << KPI_DLYCTL_PSCDIV_Pos) /*!< KPI_T::DLYCTL: PSCDIV Mask */ 357 358 #define KPI_DLYCTL_SCANDLY_Pos (8) /*!< KPI_T::DLYCTL: SCANDLY Position */ 359 #define KPI_DLYCTL_SCANDLY_Msk (0x3fful << KPI_DLYCTL_SCANDLY_Pos) /*!< KPI_T::DLYCTL: SCANDLY Mask */ 360 361 /**@}*/ /* KPI_CONST */ 362 /**@}*/ /* end of KPI register group */ 363 364 365 /**@}*/ /* end of REGISTER group */ 366 #if defined ( __CC_ARM ) 367 #pragma no_anon_unions 368 #endif 369 370 #endif /* __KEYPAD_REG_H__ */ 371
