1 /**************************************************************************//** 2 * @file ccap_reg.h 3 * @version V3.00 4 * @brief CCAP register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CCAP_REG_H__ 10 #define __CCAP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CCAP Camera Capture Interface Controller (CCAP) 23 Memory Mapped Structure for CCAP Controller 24 @{ */ 25 26 27 typedef struct { 28 29 30 /** 31 * @var CCAP_T::CTL 32 * Offset: 0x00 Camera Capture Interface Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |CCAPEN |Camera Capture Interface Enable Bit 37 * | | |0 = Camera Capture Interface Disabled. 38 * | | |1 = Camera Capture Interface Enabled. 39 * |[6] |PKTEN |Packet Output Enable Bit 40 * | | |0 = Packet output Disabled. 41 * | | |1 = Packet output Enabled. 42 * |[7] |MONO |Monochrome CMOS Sensor Select 43 * | | |0 = Color CMOS Sensor. 44 * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled. 45 * |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured 46 * | | |0 = Shutter Disabled. 47 * | | |1 = Shutter Enabled. 48 * |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap 49 * | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB). 50 * | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB). 51 * |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface 52 * | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface. 53 * | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface. 54 * |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion 55 * | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled. 56 * | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled. 57 * | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled. 58 * |[20] |UPDATE |Update Register at New Frame 59 * | | |0 = Update register at new frame Disabled. 60 * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated). 61 * |[24] |VPRST |Capture Interface Reset 62 * | | |0 = Capture interface reset Disabled. 63 * | | |1 = Capture interface reset Enabled. 64 * @var CCAP_T::PAR 65 * Offset: 0x04 Camera Capture Interface Parameter Register 66 * --------------------------------------------------------------------------------------------------- 67 * |Bits |Field |Descriptions 68 * | :----: | :----: | :---- | 69 * |[0] |INFMT |Sensor Input Data Format 70 * | | |0 = YCbCr422. 71 * | | |1 = RGB565. 72 * |[1] |SENTYPE |Sensor Input Type 73 * | | |0 = CCIR601. 74 * | | |1 = CCIR656, VSync & Hsync embedded in the data signal. 75 * |[3:2] |INDATORD |Sensor Input Data Order 76 * | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr): 77 * | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0. 78 * | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0. 79 * | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1. 80 * | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1. 81 * | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565): 82 * | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}. 83 * | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}. 84 * | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}. 85 * | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}. 86 * |[5:4] |OUTFMT |Image Data Format Output to System Memory 87 * | | |00 = YCbCr422. 88 * | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled). 89 * | | |10 = RGB555. 90 * | | |11 = RGB565. 91 * |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range 92 * | | |0 = Default. 93 * | | |1 = Scale to full range. 94 * |[8] |PCLKP |Sensor Pixel Clock Polarity 95 * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock. 96 * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock. 97 * |[9] |HSP |Sensor Hsync Polarity 98 * | | |0 = Sync Low. 99 * | | |1 = Sync High. 100 * |[10] |VSP |Sensor Vsync Polarity 101 * | | |0 = Sync Low. 102 * | | |1 = Sync High. 103 * |[18] |FBB |Field by Blank 104 * | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not. 105 * | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory). 106 * | | |1 = Field by blank Enabled. (only active data will transfer to system memory). 107 * @var CCAP_T::INT 108 * Offset: 0x08 Camera Capture Interface Interrupt Register 109 * --------------------------------------------------------------------------------------------------- 110 * |Bits |Field |Descriptions 111 * | :----: | :----: | :---- | 112 * |[0] |VINTF |Video Frame End Interrupt 113 * | | |0 = Did not receive a frame completely. 114 * | | |1 = Received a frame completely. 115 * | | |Note: This bit is cleared by writing 1 to it. 116 * |[1] |MEINTF |Bus Master Transfer Error Interrupt 117 * | | |0 = Transfer Error did not occur. 118 * | | |1 = Transfer Error occurred. 119 * | | |Note: This bit is cleared by writing 1 to it. 120 * |[3] |ADDRMINTF |Memory Address Match Interrupt 121 * | | |0 = Memory Address Match Interrupt did not occur. 122 * | | |1 = Memory Address Match Interrupt occurred. 123 * | | |Note: This bit is cleared by writing 1 to it. 124 * |[16] |VIEN |Video Frame End Interrupt Enable Bit 125 * | | |0 = Video frame end interrupt Disabled. 126 * | | |1 = Video frame end interrupt Enabled. 127 * |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit 128 * | | |0 = Bus Master Transfer error interrupt Disabled. 129 * | | |1 = Bus Master Transfer error interrupt Enabled. 130 * |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit 131 * | | |0 = Memory address match interrupt Disabled. 132 * | | |1 = Memory address match interrupt Enabled. 133 * @var CCAP_T::CWSP 134 * Offset: 0x20 Cropping Window Starting Address Register 135 * --------------------------------------------------------------------------------------------------- 136 * |Bits |Field |Descriptions 137 * | :----: | :----: | :---- | 138 * |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address 139 * | | |Specify the value of the cropping window horizontal start address. 140 * |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address 141 * | | |Specify the value of the cropping window vertical start address. 142 * @var CCAP_T::CWS 143 * Offset: 0x24 Cropping Window Size Register 144 * --------------------------------------------------------------------------------------------------- 145 * |Bits |Field |Descriptions 146 * | :----: | :----: | :---- | 147 * |[11:0] |CWW |Cropping Window Width 148 * | | |Specify the size of the cropping window width. 149 * |[26:16] |CWH |Cropping Window Height 150 * | | |Specify the size of the cropping window height. 151 * @var CCAP_T::PKTSL 152 * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M 157 * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. 158 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKTSHMH) to form a 16-bit denominator (M) of vertical factor. 159 * | | |The output image width will be equal to the image width * N/M. 160 * | | |Note: The value of N must be equal to or less than M. 161 * |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N 162 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. 163 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKTSHNH) to form a 16-bit numerator of horizontal factor. 164 * |[23:16] |PKTSVML |Packet Scaling Vertical Factor M 165 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. 166 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKTSVMH) to form a 16-bit denominator (M) of vertical factor. 167 * | | |The output image width will be equal to the image height * N/M. 168 * | | |Note: The value of N must be equal to or less than M. 169 * |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N 170 * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. 171 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKTSVNH) to form a 16-bit numerator of vertical factor. 172 * @var CCAP_T::FRCTL 173 * Offset: 0x30 Scaling Frame Rate Factor Register 174 * --------------------------------------------------------------------------------------------------- 175 * |Bits |Field |Descriptions 176 * | :----: | :----: | :---- | 177 * |[5:0] |FRM |Scaling Frame Rate Factor M 178 * | | |Specify the denominator part (M) of the frame rate scaling factor. 179 * | | |The output image frame rate will be equal to input image frame rate * (N/M). 180 * | | |Note: The value of N must be equal to or less than M. 181 * |[13:8] |FRN |Scaling Frame Rate Factor N 182 * | | |Specify the numerator part (N) of the frame rate scaling factor. 183 * @var CCAP_T::STRIDE 184 * Offset: 0x34 Frame Output Pixel Stride Width Register 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width 189 * | | |The output pixel stride size of packet pipe. 190 * | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used. 191 * | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used. 192 * @var CCAP_T::FIFOTH 193 * Offset: 0x3C FIFO Threshold Register 194 * --------------------------------------------------------------------------------------------------- 195 * |Bits |Field |Descriptions 196 * | :----: | :----: | :---- | 197 * |[28:24] |PKTFTH |Packet FIFO Threshold 198 * | | |Specify the 5-bit value of the packet FIFO threshold. 199 * |[31] |OVF |FIFO Overflow Flag 200 * | | |Indicate the FIFO overflow flag. 201 * @var CCAP_T::CMPADDR 202 * Offset: 0x40 Compare Memory Base Address Register 203 * --------------------------------------------------------------------------------------------------- 204 * |Bits |Field |Descriptions 205 * | :----: | :----: | :---- | 206 * |[31:0] |CMPADDR |Compare Memory Base Address 207 * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. 208 * @var CCAP_T::LUMA_Y1_THD 209 * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register 210 * --------------------------------------------------------------------------------------------------- 211 * |Bits |Field |Descriptions 212 * | :----: | :-----------: | :---- | 213 * |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value 214 * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion. 215 * @var CCAP_T::PKTSM 216 * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) 217 * --------------------------------------------------------------------------------------------------- 218 * |Bits |Field |Descriptions 219 * | :----: | :----: | :---- | 220 * |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M 221 * | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor. 222 * | | |Please refer to the register CCAP_PKTSL for the detailed operation. 223 * |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N 224 * | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor. 225 * | | |Please refer to the register CCAP_PKTSL for the detailed operation. 226 * |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M 227 * | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor. 228 * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. 229 * |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N 230 * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. 231 * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. 232 * @var CCAP_T::CURADDRP 233 * Offset: 0x50 Current Packet System Memory Address Register 234 * --------------------------------------------------------------------------------------------------- 235 * |Bits |Field |Descriptions 236 * | :----: | :----: | :---- | 237 * |[31:0] |CURADDR |Current Packet Output Memory Address 238 * | | |Specify the 32-bit value of the current packet output memory address. 239 * @var CCAP_T::PKTBA0 240 * Offset: 0x60 System Memory Packet Base Address 0 Register 241 * --------------------------------------------------------------------------------------------------- 242 * |Bits |Field |Descriptions 243 * | :----: | :----: | :---- | 244 * |[31:0] |BASEADDR |System Memory Packet Base Address 0 245 * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. 246 */ 247 __IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */ 248 __IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */ 249 __IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */ 250 __I uint32_t RESERVE0[5]; 251 __IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */ 252 __IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */ 253 __IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */ 254 __IO uint32_t PLNSL; 255 __IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */ 256 __IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */ 257 __I uint32_t RESERVE1[1]; 258 __IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */ 259 __IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */ 260 __IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */ 261 __IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */ 262 __I uint32_t RESERVE2[1]; 263 __IO uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */ 264 __I uint32_t RESERVE3[3]; 265 __IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */ 266 } CCAP_T; 267 268 /** 269 @addtogroup CCAP_CONST CCAP Bit Field Definition 270 Constant Definitions for CCAP Controller 271 @{ */ 272 273 #define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */ 274 #define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */ 275 276 #define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */ 277 #define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */ 278 279 #define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */ 280 #define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */ 281 282 #define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */ 283 #define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */ 284 285 #define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */ 286 #define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */ 287 288 #define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */ 289 #define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */ 290 291 #define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */ 292 #define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */ 293 294 #define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */ 295 #define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */ 296 297 #define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */ 298 #define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */ 299 300 #define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */ 301 #define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */ 302 303 #define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */ 304 #define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */ 305 306 #define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */ 307 #define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */ 308 309 #define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */ 310 #define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ 311 312 #define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */ 313 #define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */ 314 315 #define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */ 316 #define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */ 317 318 #define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */ 319 #define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */ 320 321 #define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */ 322 #define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */ 323 324 #define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */ 325 #define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */ 326 327 #define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */ 328 #define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */ 329 330 #define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */ 331 #define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */ 332 333 #define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */ 334 #define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */ 335 336 #define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */ 337 #define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */ 338 339 #define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */ 340 #define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */ 341 342 #define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */ 343 #define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */ 344 345 #define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */ 346 #define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */ 347 348 #define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */ 349 #define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */ 350 351 #define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */ 352 #define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */ 353 354 #define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */ 355 #define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */ 356 357 #define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */ 358 #define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */ 359 360 #define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */ 361 #define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */ 362 363 #define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */ 364 #define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */ 365 366 #define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */ 367 #define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */ 368 369 #define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */ 370 #define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */ 371 372 #define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */ 373 #define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */ 374 375 #define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */ 376 #define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */ 377 378 #define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */ 379 #define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */ 380 381 #define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */ 382 #define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */ 383 384 #define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */ 385 #define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */ 386 387 #define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */ 388 #define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */ 389 390 #define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */ 391 #define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */ 392 393 #define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */ 394 #define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */ 395 396 #define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */ 397 #define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */ 398 399 #define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */ 400 #define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */ 401 402 #define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */ 403 #define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */ 404 405 /**@}*/ /* CCAP_CONST */ 406 /**@}*/ /* end of CCAP register group */ 407 /**@}*/ /* end of REGISTER group */ 408 409 #if defined ( __CC_ARM ) 410 #pragma no_anon_unions 411 #endif 412 413 #endif /* __CCAP_REG_H__ */ 414
