1 /****************************************************************************//**
2 * @file usci_spi.c
3 * @version V3.00
4 * @brief M2L31 series USCI_SPI driver source file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10
11 /** @addtogroup Standard_Driver Standard Driver
12 @{
13 */
14
15 /** @addtogroup USCI_SPI_Driver USCI_SPI Driver
16 @{
17 */
18
19
20 /** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
21 @{
22 */
23
24 /**
25 * @brief This function make USCI_SPI module be ready to transfer.
26 * By default, the USCI_SPI transfer sequence is MSB first, the slave selection
27 * signal is active low and the automatic slave select function is disabled. In
28 * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
29 * divider setting will be 0.
30 * @param[in] uspi The pointer of the specified USCI_SPI module.
31 * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
32 * - \ref USPI_SLAVE
33 * - \ref USPI_MASTER
34 * @param[in] u32SPIMode Decide the transfer timing. Valid values are:
35 * - \ref USPI_MODE_0
36 * - \ref USPI_MODE_1
37 * - \ref USPI_MODE_2
38 * - \ref USPI_MODE_3
39 * @param[in] u32DataWidth The data width of a USCI_SPI transaction.
40 * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
41 * @return Actual frequency of USCI_SPI peripheral clock.
42 */
USPI_Open(USPI_T * uspi,uint32_t u32MasterSlave,uint32_t u32SPIMode,uint32_t u32DataWidth,uint32_t u32BusClock)43 uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
44 {
45 uint32_t u32ClkDiv = 0ul;
46 uint32_t u32Pclk;
47 uint32_t u32UspiClk = 0ul;
48
49 if(uspi == (USPI_T *)USPI0)
50 {
51 u32Pclk = CLK_GetPCLK0Freq();
52 }
53 else
54 {
55 u32Pclk = CLK_GetPCLK1Freq();
56 }
57
58 if(u32BusClock != 0ul)
59 {
60 u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
61 }
62 else {}
63
64 /* Enable USCI_SPI protocol */
65 uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
66 uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos;
67
68 /* Data format configuration */
69 if(u32DataWidth == 16ul)
70 {
71 u32DataWidth = 0ul;
72 }
73 else {}
74 uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
75 uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
76
77 /* MSB data format */
78 uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
79
80 /* Set slave selection signal active low */
81 if(u32MasterSlave == USPI_MASTER)
82 {
83 uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
84 }
85 else
86 {
87 uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
88 }
89
90 /* Set operating mode and transfer timing */
91 uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
92 uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
93
94 /* Set USCI_SPI bus clock */
95 uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
96 uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
97 uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk;
98
99 if(u32BusClock != 0ul)
100 {
101 u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) );
102 }
103 else {}
104
105 return u32UspiClk;
106 }
107
108 /**
109 * @brief Disable USCI_SPI function mode.
110 * @param[in] uspi The pointer of the specified USCI_SPI module.
111 * @return None
112 */
USPI_Close(USPI_T * uspi)113 void USPI_Close(USPI_T *uspi)
114 {
115 uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
116 }
117
118 /**
119 * @brief Clear Rx buffer.
120 * @param[in] uspi The pointer of the specified USCI_SPI module.
121 * @return None
122 */
USPI_ClearRxBuf(USPI_T * uspi)123 void USPI_ClearRxBuf(USPI_T *uspi)
124 {
125 uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
126 }
127
128 /**
129 * @brief Clear Tx buffer.
130 * @param[in] uspi The pointer of the specified USCI_SPI module.
131 * @return None
132 */
USPI_ClearTxBuf(USPI_T * uspi)133 void USPI_ClearTxBuf(USPI_T *uspi)
134 {
135 uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
136 }
137
138 /**
139 * @brief Disable the automatic slave select function.
140 * @param[in] uspi The pointer of the specified USCI_SPI module.
141 * @return None
142 */
USPI_DisableAutoSS(USPI_T * uspi)143 void USPI_DisableAutoSS(USPI_T *uspi)
144 {
145 uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
146 }
147
148 /**
149 * @brief Enable the automatic slave select function. Only available in Master mode.
150 * @param[in] uspi The pointer of the specified USCI_SPI module.
151 * @param[in] u32SSPinMask This parameter is not used.
152 * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are:
153 * - \ref USPI_SS_ACTIVE_HIGH
154 * - \ref USPI_SS_ACTIVE_LOW
155 * @return None
156 */
USPI_EnableAutoSS(USPI_T * uspi,uint32_t u32SSPinMask,uint32_t u32ActiveLevel)157 void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
158 {
159 uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
160 uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
161 }
162
163 /**
164 * @brief Set the USCI_SPI bus clock. Only available in Master mode.
165 * @param[in] uspi The pointer of the specified USCI_SPI module.
166 * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock.
167 * @return Actual frequency of USCI_SPI peripheral clock.
168 */
USPI_SetBusClock(USPI_T * uspi,uint32_t u32BusClock)169 uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
170 {
171 uint32_t u32ClkDiv;
172 uint32_t u32Pclk;
173
174 if(uspi == USPI0)
175 {
176 u32Pclk = CLK_GetPCLK0Freq();
177 }
178 else
179 {
180 u32Pclk = CLK_GetPCLK1Freq();
181 }
182
183 u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
184
185 /* Set USCI_SPI bus clock */
186 uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
187 uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
188
189 return ( u32Pclk / ((u32ClkDiv+1ul)<<1) );
190 }
191
192 /**
193 * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
194 * @param[in] uspi The pointer of the specified USCI_SPI module.
195 * @return Actual USCI_SPI bus clock frequency.
196 */
USPI_GetBusClock(USPI_T * uspi)197 uint32_t USPI_GetBusClock(USPI_T *uspi)
198 {
199 uint32_t u32BusClk;
200 uint32_t u32ClkDiv;
201
202 u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
203
204 if(uspi == USPI0)
205 {
206 u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) );
207 }
208 else
209 {
210 u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) );
211 }
212
213 return u32BusClk;
214 }
215
216 /**
217 * @brief Enable related interrupts specified by u32Mask parameter.
218 * @param[in] uspi The pointer of the specified USCI_SPI module.
219 * @param[in] u32Mask The combination of all related interrupt enable bits.
220 * Each bit corresponds to a interrupt bit.
221 * This parameter decides which interrupts will be enabled. Valid values are:
222 * - \ref USPI_SSINACT_INT_MASK
223 * - \ref USPI_SSACT_INT_MASK
224 * - \ref USPI_SLVTO_INT_MASK
225 * - \ref USPI_SLVBE_INT_MASK
226 * - \ref USPI_TXUDR_INT_MASK
227 * - \ref USPI_RXOV_INT_MASK
228 * - \ref USPI_TXST_INT_MASK
229 * - \ref USPI_TXEND_INT_MASK
230 * - \ref USPI_RXST_INT_MASK
231 * - \ref USPI_RXEND_INT_MASK
232 * @return None
233 */
USPI_EnableInt(USPI_T * uspi,uint32_t u32Mask)234 void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
235 {
236 /* Enable slave selection signal inactive interrupt flag */
237 if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
238 {
239 uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
240 }
241 else {}
242
243 /* Enable slave selection signal active interrupt flag */
244 if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
245 {
246 uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
247 }
248 else {}
249
250 /* Enable slave time-out interrupt flag */
251 if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
252 {
253 uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
254 }
255 else {}
256
257 /* Enable slave bit count error interrupt flag */
258 if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
259 {
260 uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
261 }
262 else {}
263
264 /* Enable TX under run interrupt flag */
265 if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
266 {
267 uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
268 }
269 else {}
270
271 /* Enable RX overrun interrupt flag */
272 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
273 {
274 uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
275 }
276 else {}
277
278 /* Enable TX start interrupt flag */
279 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
280 {
281 uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
282 }
283 else {}
284
285 /* Enable TX end interrupt flag */
286 if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
287 {
288 uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
289 }
290 else {}
291
292 /* Enable RX start interrupt flag */
293 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
294 {
295 uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
296 }
297 else {}
298
299 /* Enable RX end interrupt flag */
300 if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
301 {
302 uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
303 }
304 else {}
305 }
306
307 /**
308 * @brief Disable related interrupts specified by u32Mask parameter.
309 * @param[in] uspi The pointer of the specified USCI_SPI module.
310 * @param[in] u32Mask The combination of all related interrupt enable bits.
311 * Each bit corresponds to a interrupt bit.
312 * This parameter decides which interrupts will be disabled. Valid values are:
313 * - \ref USPI_SSINACT_INT_MASK
314 * - \ref USPI_SSACT_INT_MASK
315 * - \ref USPI_SLVTO_INT_MASK
316 * - \ref USPI_SLVBE_INT_MASK
317 * - \ref USPI_TXUDR_INT_MASK
318 * - \ref USPI_RXOV_INT_MASK
319 * - \ref USPI_TXST_INT_MASK
320 * - \ref USPI_TXEND_INT_MASK
321 * - \ref USPI_RXST_INT_MASK
322 * - \ref USPI_RXEND_INT_MASK
323 * @return None
324 */
USPI_DisableInt(USPI_T * uspi,uint32_t u32Mask)325 void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
326 {
327 /* Disable slave selection signal inactive interrupt flag */
328 if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
329 {
330 uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
331 }
332 else {}
333
334 /* Disable slave selection signal active interrupt flag */
335 if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
336 {
337 uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
338 }
339 else {}
340
341 /* Disable slave time-out interrupt flag */
342 if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
343 {
344 uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
345 }
346 else {}
347
348 /* Disable slave bit count error interrupt flag */
349 if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
350 {
351 uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
352 }
353 else {}
354
355 /* Disable TX under run interrupt flag */
356 if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
357 {
358 uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
359 }
360 else {}
361
362 /* Disable RX overrun interrupt flag */
363 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
364 {
365 uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
366 }
367 else {}
368
369 /* Disable TX start interrupt flag */
370 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
371 {
372 uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
373 }
374 else {}
375
376 /* Disable TX end interrupt flag */
377 if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
378 {
379 uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
380 }
381 else {}
382
383 /* Disable RX start interrupt flag */
384 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
385 {
386 uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
387 }
388 else {}
389
390 /* Disable RX end interrupt flag */
391 if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
392 {
393 uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
394 }
395 else {}
396 }
397
398 /**
399 * @brief Get interrupt flag.
400 * @param[in] uspi The pointer of the specified USCI_SPI module.
401 * @param[in] u32Mask The combination of all related interrupt sources.
402 * Each bit corresponds to a interrupt source.
403 * This parameter decides which interrupt flags will be read. It is combination of:
404 * - \ref USPI_SSINACT_INT_MASK
405 * - \ref USPI_SSACT_INT_MASK
406 * - \ref USPI_SLVTO_INT_MASK
407 * - \ref USPI_SLVBE_INT_MASK
408 * - \ref USPI_TXUDR_INT_MASK
409 * - \ref USPI_RXOV_INT_MASK
410 * - \ref USPI_TXST_INT_MASK
411 * - \ref USPI_TXEND_INT_MASK
412 * - \ref USPI_RXST_INT_MASK
413 * - \ref USPI_RXEND_INT_MASK
414 * @return Interrupt flags of selected sources.
415 */
USPI_GetIntFlag(USPI_T * uspi,uint32_t u32Mask)416 uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
417 {
418 uint32_t u32TmpFlag;
419 uint32_t u32IntFlag = 0ul;
420
421 /* Check slave selection signal inactive interrupt flag */
422 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk;
423 if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) )
424 {
425 u32IntFlag |= USPI_SSINACT_INT_MASK;
426 }
427 else {}
428
429 /* Check slave selection signal active interrupt flag */
430 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk;
431 if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk))
432 {
433 u32IntFlag |= USPI_SSACT_INT_MASK;
434 }
435 else {}
436
437 /* Check slave time-out interrupt flag */
438 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk;
439 if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk))
440 {
441 u32IntFlag |= USPI_SLVTO_INT_MASK;
442 }
443 else {}
444
445 /* Check slave bit count error interrupt flag */
446 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk;
447 if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk))
448 {
449 u32IntFlag |= USPI_SLVBE_INT_MASK;
450 }
451 else {}
452
453 /* Check TX under run interrupt flag */
454 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk;
455 if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk))
456 {
457 u32IntFlag |= USPI_TXUDR_INT_MASK;
458 }
459 else {}
460
461 /* Check RX overrun interrupt flag */
462 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk;
463 if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk))
464 {
465 u32IntFlag |= USPI_RXOV_INT_MASK;
466 }
467 else {}
468
469 /* Check TX start interrupt flag */
470 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk;
471 if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk))
472 {
473 u32IntFlag |= USPI_TXST_INT_MASK;
474 }
475 else {}
476
477 /* Check TX end interrupt flag */
478 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk;
479 if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk))
480 {
481 u32IntFlag |= USPI_TXEND_INT_MASK;
482 }
483 else {}
484
485 /* Check RX start interrupt flag */
486 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk;
487 if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk))
488 {
489 u32IntFlag |= USPI_RXST_INT_MASK;
490 }
491 else {}
492
493 /* Check RX end interrupt flag */
494 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk;
495 if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk))
496 {
497 u32IntFlag |= USPI_RXEND_INT_MASK;
498 }
499 else {}
500
501 return u32IntFlag;
502 }
503
504 /**
505 * @brief Clear interrupt flag.
506 * @param[in] uspi The pointer of the specified USCI_SPI module.
507 * @param[in] u32Mask The combination of all related interrupt sources.
508 * Each bit corresponds to a interrupt source.
509 * This parameter decides which interrupt flags will be cleared. It could be the combination of:
510 * - \ref USPI_SSINACT_INT_MASK
511 * - \ref USPI_SSACT_INT_MASK
512 * - \ref USPI_SLVTO_INT_MASK
513 * - \ref USPI_SLVBE_INT_MASK
514 * - \ref USPI_TXUDR_INT_MASK
515 * - \ref USPI_RXOV_INT_MASK
516 * - \ref USPI_TXST_INT_MASK
517 * - \ref USPI_TXEND_INT_MASK
518 * - \ref USPI_RXST_INT_MASK
519 * - \ref USPI_RXEND_INT_MASK
520 * @return None
521 */
USPI_ClearIntFlag(USPI_T * uspi,uint32_t u32Mask)522 void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
523 {
524 /* Clear slave selection signal inactive interrupt flag */
525 if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK)
526 {
527 uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
528 }
529 else {}
530
531 /* Clear slave selection signal active interrupt flag */
532 if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK)
533 {
534 uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
535 }
536 else {}
537
538 /* Clear slave time-out interrupt flag */
539 if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK)
540 {
541 uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
542 }
543 else {}
544
545 /* Clear slave bit count error interrupt flag */
546 if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK)
547 {
548 uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
549 }
550 else {}
551
552 /* Clear TX under run interrupt flag */
553 if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK)
554 {
555 uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
556 }
557 else {}
558
559 /* Clear RX overrun interrupt flag */
560 if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK)
561 {
562 uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
563 }
564 else {}
565
566 /* Clear TX start interrupt flag */
567 if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK)
568 {
569 uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
570 }
571 else {}
572
573 /* Clear TX end interrupt flag */
574 if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK)
575 {
576 uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
577 }
578 else {}
579
580 /* Clear RX start interrupt flag */
581 if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK)
582 {
583 uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
584 }
585 else {}
586
587 /* Clear RX end interrupt flag */
588 if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK)
589 {
590 uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
591 }
592 else {}
593 }
594
595 /**
596 * @brief Get USCI_SPI status.
597 * @param[in] uspi The pointer of the specified USCI_SPI module.
598 * @param[in] u32Mask The combination of all related sources.
599 * Each bit corresponds to a source.
600 * This parameter decides which flags will be read. It is combination of:
601 * - \ref USPI_BUSY_MASK
602 * - \ref USPI_RX_EMPTY_MASK
603 * - \ref USPI_RX_FULL_MASK
604 * - \ref USPI_TX_EMPTY_MASK
605 * - \ref USPI_TX_FULL_MASK
606 * - \ref USPI_SSLINE_STS_MASK
607 * @return Flags of selected sources.
608 */
USPI_GetStatus(USPI_T * uspi,uint32_t u32Mask)609 uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
610 {
611 uint32_t u32Flag = 0ul;
612 uint32_t u32TmpFlag;
613
614 /* Check busy status */
615 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk;
616 if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk))
617 {
618 u32Flag |= USPI_BUSY_MASK;
619 }
620 else {}
621
622 /* Check RX empty flag */
623 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk;
624 if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk))
625 {
626 u32Flag |= USPI_RX_EMPTY_MASK;
627 }
628 else {}
629
630 /* Check RX full flag */
631 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk;
632 if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk))
633 {
634 u32Flag |= USPI_RX_FULL_MASK;
635 }
636 else {}
637
638 /* Check TX empty flag */
639 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk;
640 if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk))
641 {
642 u32Flag |= USPI_TX_EMPTY_MASK;
643 }
644 else {}
645
646 /* Check TX full flag */
647 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk;
648 if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk))
649 {
650 u32Flag |= USPI_TX_FULL_MASK;
651 }
652 else {}
653
654 /* Check USCI_SPI_SS line status */
655 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk;
656 if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk))
657 {
658 u32Flag |= USPI_SSLINE_STS_MASK;
659 }
660 else {}
661
662 return u32Flag;
663 }
664
665 /**
666 * @brief Enable USCI_SPI Wake-up Function.
667 * @param[in] uspi The pointer of the specified USCI_SPI module.
668 * @return None
669 */
USPI_EnableWakeup(USPI_T * uspi)670 void USPI_EnableWakeup(USPI_T *uspi)
671 {
672 uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
673 }
674
675 /**
676 * @brief Disable USCI_SPI Wake-up Function.
677 * @param[in] uspi The pointer of the specified USCI_SPI module.
678 * @return None
679 */
USPI_DisableWakeup(USPI_T * uspi)680 void USPI_DisableWakeup(USPI_T *uspi)
681 {
682 uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
683 }
684
685 /*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
686
687 /*@}*/ /* end of group USCI_SPI_Driver */
688
689 /*@}*/ /* end of group Standard_Driver */
690
691 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/
692
