1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V3.00 4 * @brief CLK register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /******************************************************************************/ 17 /* Device Specific Peripheral registers structures */ 18 /******************************************************************************/ 19 20 /** @addtogroup REGISTER Control Register 21 22 @{ 23 24 */ 25 26 27 28 /*---------------------- System Clock Controller -------------------------*/ 29 /** 30 @addtogroup CLK System Clock Controller(CLK) 31 Memory Mapped Structure for CLK Controller 32 @{ */ 33 #if 0 34 typedef struct 35 { 36 37 38 /** 39 * @var CLK_T::PWRCTL 40 * Offset: 0x00 System Power-down Control Register 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 45 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 46 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 47 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 48 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 49 * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. 50 * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. 51 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 52 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 53 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 54 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 55 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 56 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 57 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 58 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) 61 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. 62 * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 64 or 24 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). 63 * | | |0 = Clock cycles delay Disabled. 64 * | | |1 = Clock cycles delay Enabled. 65 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 66 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 67 * | | |0 = Power-down mode wake-up interrupt Disabled. 68 * | | |1 = Power-down mode wake-up interrupt Enabled. 69 * | | |Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. 70 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 71 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 72 * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. 73 * | | |The flag is set if any wake-up source ccurred. 74 * | | |Note 1: Write 1 to clear the bit to 0. 75 * | | |Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 76 * |[7] |PDEN |System Power-down Enable (Write Protect) 77 * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 78 * | | |When chip wakes up from Power-down mode, this bit is auto cleared 79 * | | |Users need to set this bit again for next Power-down. 80 * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. 81 * | | |In Power-down mode, the PLL, PLLFN and system clock are disabled, and ignored the clock source selection. 82 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 83 * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. 84 * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. 85 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 86 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 87 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. 88 * | | |00 = HXT frequency is lower than from 8 MHz. 89 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 90 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 91 * | | |11 = HXT frequency is higher than 16 MHz. 92 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 93 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 94 * | | |0 = Select INV type. 95 * | | |1 = Select GM type. 96 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 97 * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) 98 * | | |00 = HIRC stable count is 64 clocks. 99 * | | |01 = HIRC stable count is 24 clocks. 100 * | | |Others = Reserved 101 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 102 * |[18] |HIRC48MEN |HIRC48M Enable Bit (Write Protect) 103 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) Disabled. 104 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) Enabled. 105 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 106 * |[31] |HXTMD |HXT Bypass Mode (Write Protect) 107 * | | |0 = HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins. 108 * | | |1 = HXT works as external clock mode. PF.3 is configured as external clock input pin. 109 * | | |Note: This bit is write protected. Refer to the SYS_REGCTL register. 110 * @var CLK_T::AHBCLK0 111 * Offset: 0x04 AHB Devices Clock Enable Control Register 0 112 * --------------------------------------------------------------------------------------------------- 113 * |Bits |Field |Descriptions 114 * | :----: | :----: | :---- | 115 * |[1] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit 116 * | | |0 = PDMA0 peripheral clock Disabled. 117 * | | |1 = PDMA0 peripheral clock Enabled. 118 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 119 * | | |0 = Flash ISP peripheral clock Disabled. 120 * | | |1 = Flash ISP peripheral clock Enabled. 121 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 122 * | | |0 = EBI peripheral clock Disabled. 123 * | | |1 = EBI peripheral clock Enabled. 124 * |[4] |STCKEN |System Tick Clock Enable Bit 125 * | | |0 = System tick clock Disabled. 126 * | | |1 = System tick clock Enabled. 127 * |[5] |EMAC0CKEN |EMAC0 Controller Clock Enable Bit 128 * | | |0 = EMAC0 controller clock Disabled. 129 * | | |1 = EMAC0 controller clock Enabled. 130 * |[6] |SDH0CKEN |SDH0 Controller Clock Enable Bit 131 * | | |0 = SDH0 clock Disabled. 132 * | | |1 = SDH0 clock Enabled. 133 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 134 * | | |0 = CRC peripheral clock Disabled. 135 * | | |1 = CRC peripheral clock Enabled. 136 * |[8] |CCAPCKEN |Camera Capture Interface Controller Clock Enable Bit 137 * | | |0 = CCAP controller clock Disabled. 138 * | | |1 = CCAP controller clock Enabled. 139 * |[9] |SENCKEN |CCAP Sensor Clock Enable Bit 140 * | | |0 = CCAP Sensor clock Disabled. 141 * | | |1 = CCAP Sensor clock Enabled. 142 * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit 143 * | | |0 = HSUSB device controller clock Disabled. 144 * | | |1 = HSUSB device controller clock Enabled. 145 * |[11] |HBICKEN |Hyper Bus Interface Clock Enable Bit 146 * | | |0 = HBI clock Disabled. 147 * | | |1 = HBI clock Enabled. 148 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 149 * | | |0 = Cryptographic Accelerator clock Disabled. 150 * | | |1 = Cryptographic Accelerator clock Enabled. 151 * |[13] |KSCKEN |Key Stroe Clock Enable Bit 152 * | | |0 = Key Store clock Disabled. 153 * | | |1 = Key Store clock Enabled. 154 * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit 155 * | | |0 = SPIM controller clock Disabled. 156 * | | |1 = SPIM controller clock Enabled. 157 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 158 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 159 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 160 * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit 161 * | | |0 = USB HOST peripheral clock Disabled. 162 * | | |1 = USB HOST peripheral clock Enabled. 163 * |[17] |SDH1CKEN |SDH1 Controller Clock Enable Bit 164 * | | |0 = SDH1 clock Disabled. 165 * | | |1 = SDH1 clock Enabled. 166 * |[18] |PDMA1CKEN |PDMA1 Clock Enable Bit 167 * | | |0 = PDMA1 clock Disabled. 168 * | | |1 = PDMA1 clock Enabled. 169 * |[19] |TRACECKEN |TRACE Clock Enable Bit 170 * | | |0 = TRACE clock Disabled. 171 * | | |1 = TRACE clock Enabled. 172 * |[24] |GPACKEN |GPIOA Clock Enable Bit 173 * | | |0 = GPIOA clock Disabled. 174 * | | |1 = GPIOA clock Enabled. 175 * |[25] |GPBCKEN |GPIOB Clock Enable Bit 176 * | | |0 = GPIOB clock Disabled. 177 * | | |1 = GPIOB clock Enabled. 178 * |[26] |GPCCKEN |GPIOC Clock Enable Bit 179 * | | |0 = GPIOC clock Disabled. 180 * | | |1 = GPIOC clock Enabled. 181 * |[27] |GPDCKEN |GPIOD Clock Enable Bit 182 * | | |0 = GPIOD clock Disabled. 183 * | | |1 = GPIOD clock Enabled. 184 * |[28] |GPECKEN |GPIOE Clock Enable Bit 185 * | | |0 = GPIOE clock Disabled. 186 * | | |1 = GPIOE clock Enabled. 187 * |[29] |GPFCKEN |GPIOF Clock Enable Bit 188 * | | |0 = GPIOF clock Disabled. 189 * | | |1 = GPIOF clock Enabled. 190 * |[30] |GPGCKEN |GPIOG Clock Enable Bit 191 * | | |0 = GPIOG clock Disabled. 192 * | | |1 = GPIOG clock Enabled. 193 * |[31] |GPHCKEN |GPIOH Clock Enable Bit 194 * | | |0 = GPIOH clock Disabled. 195 * | | |1 = GPIOH clock Enabled. 196 * @var CLK_T::APBCLK0 197 * Offset: 0x08 APB Devices Clock Enable Control Register 0 198 * --------------------------------------------------------------------------------------------------- 199 * |Bits |Field |Descriptions 200 * | :----: | :----: | :---- | 201 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 202 * | | |0 = Watchdog timer clock Disabled. 203 * | | |1 = Watchdog timer clock Enabled. 204 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 205 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 206 * | | |This bit is used to control the RTC APB clock only. 207 * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). 208 * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). 209 * | | |0 = RTC clock Disabled. 210 * | | |1 = RTC clock Enabled. 211 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 212 * | | |0 = Timer0 clock Disabled. 213 * | | |1 = Timer0 clock Enabled. 214 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 215 * | | |0 = Timer1 clock Disabled. 216 * | | |1 = Timer1 clock Enabled. 217 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 218 * | | |0 = Timer2 clock Disabled. 219 * | | |1 = Timer2 clock Enabled. 220 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 221 * | | |0 = Timer3 clock Disabled. 222 * | | |1 = Timer3 clock Enabled. 223 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 224 * | | |0 = CLKO clock Disabled. 225 * | | |1 = CLKO clock Enabled. 226 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 227 * | | |0 = Analog comparator 0/1 clock Disabled. 228 * | | |1 = Analog comparator 0/1 clock Enabled. 229 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 230 * | | |0 = I2C0 clock Disabled. 231 * | | |1 = I2C0 clock Enabled. 232 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 233 * | | |0 = I2C1 clock Disabled. 234 * | | |1 = I2C1 clock Enabled. 235 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 236 * | | |0 = I2C2 clock Disabled. 237 * | | |1 = I2C2 clock Enabled. 238 * |[11] |I2C3CKEN |I2C3 Clock Enable Bit 239 * | | |0 = I2C3 clock Disabled. 240 * | | |1 = I2C3 clock Enabled. 241 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 242 * | | |0 = QSPI0 clock Disabled. 243 * | | |1 = QSPI0 clock Enabled. 244 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 245 * | | |0 = SPI0 clock Disabled. 246 * | | |1 = SPI0 clock Enabled. 247 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 248 * | | |0 = SPI1 clock Disabled. 249 * | | |1 = SPI1 clock Enabled. 250 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 251 * | | |0 = SPI2 clock Disabled. 252 * | | |1 = SPI2 clock Enabled. 253 * |[16] |UART0CKEN |UART0 Clock Enable Bit 254 * | | |0 = UART0 clock Disabled. 255 * | | |1 = UART0 clock Enabled. 256 * |[17] |UART1CKEN |UART1 Clock Enable Bit 257 * | | |0 = UART1 clock Disabled. 258 * | | |1 = UART1 clock Enabled. 259 * |[18] |UART2CKEN |UART2 Clock Enable Bit 260 * | | |0 = UART2 clock Disabled. 261 * | | |1 = UART2 clock Enabled. 262 * |[19] |UART3CKEN |UART3 Clock Enable Bit 263 * | | |0 = UART3 clock Disabled. 264 * | | |1 = UART3 clock Enabled. 265 * |[20] |UART4CKEN |UART4 Clock Enable Bit 266 * | | |0 = UART4 clock Disabled. 267 * | | |1 = UART4 clock Enabled. 268 * |[21] |UART5CKEN |UART5 Clock Enable Bit 269 * | | |0 = UART5 clock Disabled. 270 * | | |1 = UART5 clock Enabled. 271 * |[22] |UART6CKEN |UART6 Clock Enable Bit 272 * | | |0 = UART6 clock Disabled. 273 * | | |1 = UART6 clock Enabled. 274 * |[23] |UART7CKEN |UART7 Clock Enable Bit 275 * | | |0 = UART7 clock Disabled. 276 * | | |1 = UART7 clock Enabled. 277 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 278 * | | |0 = USB OTG clock Disabled. 279 * | | |1 = USB OTG clock Enabled. 280 * |[27] |USBDCKEN |USB Device Clock Enable Bit 281 * | | |0 = USB device clock Disabled. 282 * | | |1 = USB device clock Enabled. 283 * |[28] |EADC0CKEN |EADC0 Clock Enable Bit 284 * | | |0 = EADC0 clock Disabled. 285 * | | |1 = EADC0 clock Enabled. 286 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 287 * | | |0 = I2S0 clock Disabled. 288 * | | |1 = I2S0 clock Enabled. 289 * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit 290 * | | |0 = HSUSB OTG clock Disabled. 291 * | | |1 = HSUSB OTG clock Enabled. 292 * @var CLK_T::APBCLK1 293 * Offset: 0x0C APB Devices Clock Enable Control Register 1 294 * --------------------------------------------------------------------------------------------------- 295 * |Bits |Field |Descriptions 296 * | :----: | :----: | :---- | 297 * |[0] |SC0CKEN |SC0 Clock Enable Bit 298 * | | |0 = SC0 clock Disabled. 299 * | | |1 = SC0 clock Enabled. 300 * |[1] |SC1CKEN |SC1 Clock Enable Bit 301 * | | |0 = SC1 clock Disabled. 302 * | | |1 = SC1 clock Enabled. 303 * |[2] |SC2CKEN |SC2 Clock Enable Bit 304 * | | |0 = SC2 clock Disabled. 305 * | | |1 = SC2 clock Enabled. 306 * |[3] |I2C4CKEN |I2C4 Clock Enable Bit 307 * | | |0 = I2C4 clock Disabled. 308 * | | |1 = I2C4 clock Enabled. 309 * |[4] |QSPI1CKEN |QSPI1 Clock Enable Bit 310 * | | |0 = QSPI1 clock Disabled. 311 * | | |1 = QSPI1 clock Enabled. 312 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 313 * | | |0 = SPI3 clock Disabled. 314 * | | |1 = SPI3 clock Enabled. 315 * |[7] |SPI4CKEN |SPI4 Clock Enable Bit 316 * | | |0 = SPI4 clock Disabled. 317 * | | |1 = SPI4 clock Enabled. 318 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 319 * | | |0 = USCI0 clock Disabled. 320 * | | |1 = USCI0 clock Enabled. 321 * |[10] |PSIOCKEN |PSIO Clock Enable Bit 322 * | | |0 = PSIO clock Disabled. 323 * | | |1 = PSIO clock Enabled. 324 * |[12] |DACCKEN |DAC Clock Enable Bit 325 * | | |0 = DAC clock Disabled. 326 * | | |1 = DAC clock Enabled. 327 * |[13] |ECAP2CKEN |ECAP2 Clock Enable Bit 328 * | | |0 = ECAP2 clock Disabled. 329 * | | |1 = ECAP2 clock Enabled. 330 * |[14] |ECAP3CKEN |ECAP3 Clock Enable Bit 331 * | | |0 = ECAP3 clock Disabled. 332 * | | |1 = ECAP3 clock Enabled. 333 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 334 * | | |0 = EPWM0 clock Disabled. 335 * | | |1 = EPWM0 clock Enabled. 336 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 337 * | | |0 = EPWM1 clock Disabled. 338 * | | |1 = EPWM1 clock Enabled. 339 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 340 * | | |0 = BPWM0 clock Disabled. 341 * | | |1 = BPWM0 clock Enabled. 342 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 343 * | | |0 = BPWM1 clock Disabled. 344 * | | |1 = BPWM1 clock Enabled. 345 * |[20] |EQEI2CKEN |EQEI2 Clock Enable Bit 346 * | | |0 = EQEI2 clock Disabled. 347 * | | |1 = EQEI2 clock Enabled. 348 * |[21] |EQEI3CKEN |EQEI3 Clock Enable Bit 349 * | | |0 = EQEI3 clock Disabled. 350 * | | |1 = EQEI3 clock Enabled. 351 * |[22] |EQEI0CKEN |EQEI0 Clock Enable Bit 352 * | | |0 = EQEI0 clock Disabled. 353 * | | |1 = EQEI0 clock Enabled. 354 * |[23] |EQEI1CKEN |EQEI1 Clock Enable Bit 355 * | | |0 = EQEI1 clock Disabled. 356 * | | |1 = EQEI1 clock Enabled. 357 * |[25] |TRNGCKEN |TRNG Clock Enable Bit 358 * | | |0 = TRNG clock Disabled. 359 * | | |1 = TRNG clock Enabled. 360 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 361 * | | |0 = ECAP0 clock Disabled. 362 * | | |1 = ECAP0 clock Enabled. 363 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 364 * | | |0 = ECAP1 clock Disabled. 365 * | | |1 = ECAP1 clock Enabled. 366 * |[29] |I2S1CKEN |I2S1 Clock Enable Bit 367 * | | |0 = I2S1 clock Disabled. 368 * | | |1 = I2S1 clock Enabled. 369 * |[31] |EADC1CKEN |EADC1 Clock Enable Bit 370 * | | |0 = EADC1 clock Disabled. 371 * | | |1 = EADC1 clock Enabled. 372 * @var CLK_T::CLKSEL0 373 * Offset: 0x10 Clock Source Select Control Register 0 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 378 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 379 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 380 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 381 * | | |010 = Clock source from PLL 382 * | | |011 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 383 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 384 * | | |Others = Reserved. 385 * | | |Note: Theses bits are write protected. Refer to the SYS_REGLCTL register. 386 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) 387 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 388 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 389 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 390 * | | |010 = Clock source from HXT/2. 391 * | | |011 = Clock source from HCLK/2. 392 * | | |111 = Clock source from HIRC/2. 393 * | | |Note 1: If SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick needs to enable STCKEN(CLK_AHBCLK0[4]). 394 * | | |SysTick clock source must less than or equal to HCLK/2. 395 * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. 396 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 397 * | | |0 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 398 * | | |1 = Clock source from PLL/2. 399 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 400 * |[11:10] |EADC0SEL |EADC0 Clock Source Selection (Write Protect) 401 * | | |00 = Clock source from PLLFN/2. 402 * | | |01 = Clock source from PLL/2. 403 * | | |10 = Clock source from HCLK. 404 * | | |11 = Reserved. 405 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 406 * |[13:12] |EADC1SEL |EADC1 Clock Source Selection (Write Protect) 407 * | | |00 = Clock source from PLLFN/2. 408 * | | |01 = Clock source from PLL/2. 409 * | | |10 = Clock source from HCLK. 410 * | | |11 = Reserved. 411 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 412 * |[15:14] |EADC2SEL |EADC2 Clock Source Selection (Write Protect) 413 * | | |00 = Clock source from PLLFN/2. 414 * | | |01 = Clock source from PLL/2. 415 * | | |10 = Clock source from HCLK. 416 * | | |11 = Reserved. 417 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 418 * |[17:16] |CCAPSEL |CCAP Sensor Clock Source Selection (Write Protect) 419 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 420 * | | |01 = Clock source from PLL/2. 421 * | | |10 = Clock source from HCLK. 422 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 423 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 424 * |[21:20] |SDH0SEL |SDH0 Clock Source Selection (Write Protect) 425 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 426 * | | |01 = Clock source from PLL/2 clock. 427 * | | |10 = Clock source from HCLK. 428 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 429 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 430 * |[23:22] |SDH1SEL |SDH1 Clock Source Selection (Write Protect) 431 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 432 * | | |01 = Clock source from PLL/2 clock. 433 * | | |10 = Clock source from HCLK. 434 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 435 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 436 * |[25:24] |CANFD0SEL |CANFD0 Clock Source Selection (Write Protect) 437 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 438 * | | |01 = Clock source from PLL/2 clock. 439 * | | |10 = Clock source from HCLK. 440 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 441 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 442 * |[27:26] |CANFD1SEL |CANFD1 Clock Source Selection (Write Protect) 443 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 444 * | | |01 = Clock source from PLL/2 clock. 445 * | | |10 = Clock source from HCLK. 446 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 447 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 448 * |[29:28] |CANFD2SEL |CANFD2 Clock Source Selection (Write Protect) 449 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 450 * | | |01 = Clock source from PLL/2 clock. 451 * | | |10 = Clock source from HCLK. 452 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 453 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 454 * |[31:30] |CANFD3SEL |CANFD3 Clock Source Selection (Write Protect) 455 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 456 * | | |01 = Clock source from PLL/2 clock. 457 * | | |10 = Clock source from HCLK. 458 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 459 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 460 * @var CLK_T::CLKSEL1 461 * Offset: 0x14 Clock Source Select Control Register 1 462 * --------------------------------------------------------------------------------------------------- 463 * |Bits |Field |Descriptions 464 * | :----: | :----: | :---- | 465 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 466 * | | |00 = Reserved. 467 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 468 * | | |10 = Clock source from HCLK/2048. 469 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 470 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 471 * |[6:4] |CLKOSEL |Clock Output Clock Source Selection 472 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 473 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 474 * | | |010 = Clock source from HCLK. 475 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 476 * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 477 * | | |101 = Clock source from PLLFN/2. 478 * | | |110 = Clock source from PLL/2. 479 * | | |111 = Reserved. 480 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 481 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 482 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 483 * | | |010 = Clock source from PCLK0. 484 * | | |011 = Clock source from external clock TM0 pin. 485 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 486 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 487 * | | |Others = Reserved. 488 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 489 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 490 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 491 * | | |010 = Clock source from PCLK0. 492 * | | |011 = Clock source from external clock TM1 pin. 493 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 494 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 495 * | | |Others = Reserved. 496 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 497 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 498 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 499 * | | |010 = Clock source from PCLK1. 500 * | | |011 = Clock source from external clock TM2 pin. 501 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 502 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 503 * | | |Others = Reserved. 504 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 505 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 506 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 507 * | | |010 = Clock source from PCLK1. 508 * | | |011 = Clock source from external clock TM3 pin. 509 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 510 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 511 * | | |Others = Reserved. 512 * |[25:24] |UART0SEL |UART0 Clock Source Selection 513 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 514 * | | |01 = Clock source from PLL/2. 515 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 516 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 517 * |[27:26] |UART1SEL |UART1 Clock Source Selection 518 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 519 * | | |01 = Clock source from PLL/2. 520 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 521 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 522 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection 523 * | | |10 = Clock source from HCLK/2048. 524 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 525 * | | |Others = Reserved. 526 * @var CLK_T::CLKSEL2 527 * Offset: 0x18 Clock Source Select Control Register 2 528 * --------------------------------------------------------------------------------------------------- 529 * |Bits |Field |Descriptions 530 * | :----: | :----: | :---- | 531 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection 532 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 533 * | | |0 = Clock source from HCLK. 534 * | | |1 = Clock source from PCLK0. 535 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection 536 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 537 * | | |0 = Clock source from HCLK. 538 * | | |1 = Clock source from PCLK1. 539 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 540 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 541 * | | |01 = Clock source from PLL/2. 542 * | | |10 = Clock source from PCLK0. 543 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 544 * |[6:4] |SPI0SEL |SPI0 Clock Source Selection 545 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 546 * | | |001 = Clock source from PLL/2. 547 * | | |010 = Clock source from PCLK1. 548 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 549 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 550 * | | |101 = Clock source from PLLFN/2. 551 * | | |Others = Reserved. 552 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection 553 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 554 * | | |0 = Clock source from HCLK. 555 * | | |1 = Clock source from PCLK0. 556 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection 557 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 558 * | | |0 = Clock source from HCLK. 559 * | | |1 = Clock source from PCLK1. 560 * |[11:10] |QSPI1SEL |QSPI1 Clock Source Selection 561 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 562 * | | |01 = Clock source from PLL/2. 563 * | | |10 = Clock source from PCLK1. 564 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 565 * |[14:12] |SPI1SEL |SPI1 Clock Source Selection 566 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 567 * | | |001 = Clock source from PLL/2. 568 * | | |010 = Clock source from PCLK0. 569 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 570 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 571 * | | |101 = Clock source from PLLFN/2. 572 * | | |Others = Reserved. 573 * |[18:16] |I2S1SEL |I2S1 Clock Source Selection 574 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 575 * | | |001 = Clock source from PLL/2. 576 * | | |010 = Clock source from PCLK1. 577 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 578 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 579 * | | |101 = Clock source from PLLFN/2. 580 * | | |Others = Reserved. 581 * |[21:20] |UART8SEL |UART8 Clock Source Selection 582 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 583 * | | |01 = Clock source from PLL/2. 584 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 585 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 586 * |[23:22] |UART9SEL |UART9 Clock Source Selection 587 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 588 * | | |01 = Clock source from PLL/2. 589 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 590 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 591 * |[27] |TRNGSEL |TRNG Clock Source Selection 592 * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 593 * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 594 * |[30:28] |PSIOSEL |PSIO Clock Source Selection 595 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 596 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 597 * | | |010 = Clock source from PCLK1. 598 * | | |011 = Clock source from PLL/2. 599 * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 600 * | | |101 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 601 * | | |Others = Reserved. 602 * @var CLK_T::CLKSEL3 603 * Offset: 0x1C Clock Source Select Control Register 3 604 * --------------------------------------------------------------------------------------------------- 605 * |Bits |Field |Descriptions 606 * | :----: | :----: | :---- | 607 * |[1:0] |SC0SEL |SC0 Clock Source Selection 608 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 609 * | | |01 = Clock source from PLL/2. 610 * | | |10 = Clock source from PCLK0. 611 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 612 * |[3:2] |SC1SEL |SC0 Clock Source Selection 613 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 614 * | | |01 = Clock source from PLL/2. 615 * | | |10 = Clock source from PCLK1. 616 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 617 * |[5:4] |SC2SEL |SC2 Clock Source Selection 618 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 619 * | | |01 = Clock source from PLL/2. 620 * | | |10 = Clock source from PCLK0. 621 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 622 * |[7:6] |KPISEL |KPI Clock Source Selection 623 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 624 * | | |01 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 625 * | | |10 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 626 * | | |11 = Reserved. 627 * |[11:9] |SPI2SEL |SPI2 Clock Source Selection 628 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 629 * | | |001 = Clock source from PLL/2. 630 * | | |010 = Clock source from PCLK1. 631 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 632 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 633 * | | |101 = Clock source from PLLFN/2. 634 * | | |Others = Reserved. 635 * |[14:12] |SPI3SEL |SPI3 Clock Source Selection 636 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 637 * | | |001 = Clock source from PLL/2. 638 * | | |010 = Clock source from PCLK0. 639 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 640 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 641 * | | |101 = Clock source from PLLFN/2. 642 * | | |Others = Reserved. 643 * |[18:16] |I2S0SEL |I2S0 Clock Source Selection 644 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 645 * | | |001 = Clock source from PLL/2. 646 * | | |010 = Clock source from PCLK0. 647 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 648 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 649 * | | |101 = Clock source from PLLFN/2. 650 * | | |Others = Reserved. 651 * |[21:20] |UART6SEL |UART6 Clock Source Selection 652 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 653 * | | |01 = Clock source from PLL/2. 654 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 655 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 656 * |[23:22] |UART7SEL |UART7 Clock Source Selection 657 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 658 * | | |01 = Clock source from PLL/2. 659 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 660 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 661 * |[25:24] |UART2SEL |UART2 Clock Source Selection 662 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 663 * | | |01 = Clock source from PLL/2. 664 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 665 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 666 * |[27:26] |UART3SEL |UART3 Clock Source Selection 667 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 668 * | | |01 = Clock source from PLL/2. 669 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 670 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 671 * |[29:28] |UART4SEL |UART4 Clock Source Selection 672 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 673 * | | |01 = Clock source from PLL/2. 674 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 675 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 676 * |[31:30] |UART5SEL |UART5 Clock Source Selection 677 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 678 * | | |01 = Clock source from PLL/2. 679 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 680 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 681 * @var CLK_T::CLKDIV0 682 * Offset: 0x20 Clock Divider Number Register 0 683 * --------------------------------------------------------------------------------------------------- 684 * |Bits |Field |Descriptions 685 * | :----: | :----: | :---- | 686 * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source 687 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 688 * |[7:4] |USBDIV |USB Clock Divide Number from PLL/2 Clock 689 * | | |USB clock frequency = ((PLL frequency)/2) / (USBDIV + 1). 690 * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source 691 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 692 * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source 693 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 694 * |[23:16] |EADC0DIV |EADC0 Clock Divide Number from EADC0 Clock Source 695 * | | |EADC0 clock frequency = (EADC0 clock source frequency) / (EADC0DIV + 1). 696 * |[31:24] |SDH0DIV |SDH0 Clock Divide Number from SDH0 Clock Source 697 * | | |SDH0 clock frequency = (SDH0 clock source frequency) / (SDH0DIV + 1). 698 * @var CLK_T::CLKDIV1 699 * Offset: 0x24 Clock Divider Number Register 1 700 * --------------------------------------------------------------------------------------------------- 701 * |Bits |Field |Descriptions 702 * | :----: | :----: | :---- | 703 * |[7:0] |SC0DIV |SC0 Clock Divide Number from SC0 Clock Source 704 * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). 705 * |[15:8] |SC1DIV |SC1 Clock Divide Number from SC1 Clock Source 706 * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). 707 * |[23:16] |SC2DIV |SC2 Clock Divide Number from SC2 Clock Source 708 * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). 709 * |[31:24] |PSIODIV |PSIO Clock Divide Number from PSIO Clock Source 710 * | | |PSIO clock frequency = (PSIO clock source frequency) / (PSIODIV + 1). 711 * @var CLK_T::CLKDIV2 712 * Offset: 0x28 Clock Divider Number Register 2 713 * --------------------------------------------------------------------------------------------------- 714 * |Bits |Field |Descriptions 715 * | :----: | :----: | :---- | 716 * |[3:0] |I2S0DIV |I2S0 Clock Divide Number from I2S0 Clock Source 717 * | | |I2S0 clock frequency = (I2S0 clock source frequency) / (I2S0DIV + 1). 718 * |[7:4] |I2S1DIV |I2S1 Clock Divide Number from I2S1 Clock Source 719 * | | |I2S1 clock frequency = (I2S1 clock source frequency) / (I2S1DIV + 1). 720 * |[15:8] |KPIDIV |KPI Clock Divide Number from KPI Clock Source 721 * | | |KPI clock frequency = (KPI clock source frequency) / (KPIDIV + 1). 722 * |[31:24] |EADC1DIV |EADC1 Clock Divide Number from EADC1 Clock Source 723 * | | |EADC1 clock frequency = (EADC1 clock source frequency) / (EADC1DIV + 1). 724 * @var CLK_T::CLKDIV3 725 * Offset: 0x2C Clock Divider Number Register 3 726 * --------------------------------------------------------------------------------------------------- 727 * |Bits |Field |Descriptions 728 * | :----: | :----: | :---- | 729 * |[15:8] |VSENSEDIV |Video Pixel Clock Divide Number from CCAP Sensor Clock Source 730 * | | |Video pixel clock frequency = (CCAP sensor clock source frequency) / (VSENSEDIV + 1). 731 * |[23:16] |EMAC0DIV |EMAC0 Clock Divide Number form HCLK 732 * | | |EMAC0 MDCLK clock frequency = (HCLK) / (EMAC0DIV + 1). 733 * |[31:24] |SDH1DIV |SDH1 Clock Divide Number from SDH1 Clock Source 734 * | | |SDH1 clock frequency = (SDH1 clock source frequency) / (SDH1DIV + 1). 735 * @var CLK_T::CLKDIV4 736 * Offset: 0x30 Clock Divider Number Register 4 737 * --------------------------------------------------------------------------------------------------- 738 * |Bits |Field |Descriptions 739 * | :----: | :----: | :---- | 740 * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source 741 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 742 * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source 743 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 744 * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source 745 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 746 * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source 747 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 748 * |[19:16] |UART6DIV |UART6 Clock Divide Number from UART6 Clock Source 749 * | | |UART6 clock frequency = (UART6 clock source frequency) / (UART6DIV + 1). 750 * |[23:20] |UART7DIV |UART7 Clock Divide Number from UART7 Clock Source 751 * | | |UART7 clock frequency = (UART7 clock source frequency) / (UART7DIV + 1). 752 * @var CLK_T::PCLKDIV 753 * Offset: 0x34 APB Clock Divider Register 754 * --------------------------------------------------------------------------------------------------- 755 * |Bits |Field |Descriptions 756 * | :----: | :----: | :---- | 757 * |[2:0] |APB0DIV |APB0 Clock Divider 758 * | | |APB0 clock can be divided from HCLK. 759 * | | |000 = PCLK0 frequency is HCLK. 760 * | | |001 = PCLK0 frequency is HCLK/2. 761 * | | |010 = PCLK0 frequency is HCLK/4. 762 * | | |011 = PCLK0 frequency is HCLK/8. 763 * | | |100 = PCLK0 frequency is HCLK/16. 764 * | | |Others = Reserved. 765 * |[6:4] |APB1DIV |APB1 Clock Divider 766 * | | |APB1 clock can be divided from HCLK. 767 * | | |000 = PCLK1 frequency is HCLK. 768 * | | |001 = PCLK1 frequency is HCLK/2. 769 * | | |010 = PCLK1 frequency is HCLK/4. 770 * | | |011 = PCLK1 frequency is HCLK/8. 771 * | | |100 = PCLK1 frequency is HCLK/16. 772 * | | |Others = Reserved. 773 * @var CLK_T::APBCLK2 774 * Offset: 0x38 APB Devices Clock Enable Control Register 2 775 * --------------------------------------------------------------------------------------------------- 776 * |Bits |Field |Descriptions 777 * | :----: | :----: | :---- | 778 * |[0] |KPICKEN |KPI Clock Enable Bit 779 * | | |0 = KPI clock Disabled. 780 * | | |1 = KPI clock Enabled. 781 * |[6] |EADC2CKEN |EADC2 Clock Enable Bit 782 * | | |0 = EADC2 clock Disabled. 783 * | | |1 = EADC2 clock Enabled. 784 * |[7] |ACMP23CKEN|Analog Comparator 2/3 Clock Enable Bit 785 * | | |0 = Analog Comparator 2/3 clock Disabled. 786 * | | |1 = Analog Comparator 2/3 clock Enabled. 787 * |[8] |SPI5CKEN |SPI5 Clock Enable Bit 788 * | | |0 = SPI5 clock Disabled. 789 * | | |1 = SPI5 clock Enabled. 790 * |[9] |SPI6CKEN |SPI6 Clock Enable Bit 791 * | | |0 = SPI6 clock Disabled. 792 * | | |1 = SPI6 clock Enabled. 793 * |[10] |SPI7CKEN |SPI7 Clock Enable Bit 794 * | | |0 = SPI7 clock Disabled. 795 * | | |1 = SPI7 clock Enabled. 796 * |[11] |SPI8CKEN |SPI8 Clock Enable Bit 797 * | | |0 = SPI8 clock Disabled. 798 * | | |1 = SPI8 clock Enabled. 799 * |[12] |SPI9CKEN |SPI9 Clock Enable Bit 800 * | | |0 = SPI9 clock Disabled. 801 * | | |1 = SPI9 clock Enabled. 802 * |[13] |SPI10CKEN |SPI10 Clock Enable Bit 803 * | | |0 = SPI10 clock Disabled. 804 * | | |1 = SPI10 clock Enabled. 805 * |[16] |UART8CKEN |UART8 Clock Enable Bit 806 * | | |0 = UART8 clock Disabled. 807 * | | |1 = UART8 clock Enabled. 808 * |[17] |UART9CKEN |UART9 Clock Enable Bit 809 * | | |0 = UART9 clock Disabled. 810 * | | |1 = UART9 clock Enabled. 811 * @var CLK_T::CLKDIV5 812 * Offset: 0x3C Clock Divider Number Register 5 813 * --------------------------------------------------------------------------------------------------- 814 * |Bits |Field |Descriptions 815 * | :----: | :----: | :---- | 816 * |[3:0] |CANFD0DIV |CANFD0 Clock Divide Number from CANFD0 Clock Source 817 * | | |CANFD0 clock frequency = (CANFD0 clock source frequency) / (CANFD0DIV + 1). 818 * |[7:4] |CANFD1DIV |CANFD1 Clock Divide Number from CANFD1 Clock Source 819 * | | |CANFD1 clock frequency = (CANFD1 clock source frequency) / (CANFD1DIV + 1). 820 * |[11:8] |CANFD2DIV |CANFD2 Clock Divide Number from CANFD2 Clock Source 821 * | | |CANFD2 clock frequency = (CANFD2 clock source frequency) / (CANFD2DIV + 1). 822 * |[15:12] |CANFD3DIV |CANFD3 Clock Divide Number from CANFD3 Clock Source 823 * | | |CANFD3 clock frequency = (CANFD3 clock source frequency) / (CANFD3DIV + 1). 824 * |[19:16] |UART8DIV |UART6 Clock Divide Number from UART8 Clock Source 825 * | | |UART6 clock frequency = (UART8 clock source frequency) / (UART8DIV + 1). 826 * |[23:20] |UART9DIV |UART7 Clock Divide Number from UART9 Clock Source 827 * | | |UART7 clock frequency = (UART9 clock source frequency) / (UART9DIV + 1). 828 * |[31:24] |EADC2DIV |EADC2 Clock Divide Number from EADC2 Clock Source 829 * | | |EADC2 clock frequency = (EADC2 clock source frequency) / (EADC2DIV + 1). 830 * @var CLK_T::PLLCTL 831 * Offset: 0x40 PLL Control Register 832 * --------------------------------------------------------------------------------------------------- 833 * |Bits |Field |Descriptions 834 * | :----: | :----: | :---- | 835 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 836 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 837 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 838 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 839 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 840 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 841 * |[16] |PD |Power-down Mode (Write Protect) 842 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 843 * | | |0 = PLL is in normal mode. 844 * | | |1 = PLL is in Power-down mode (default). 845 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 846 * |[17] |BP |PLL Bypass Control (Write Protect) 847 * | | |0 = PLL is in normal mode (default). 848 * | | |1 = PLL clock output is same as PLL input clock FIN. 849 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 850 * |[18] |OE |PLL FOUT Enable Control (Write Protect) 851 * | | |0 = PLL FOUT Enabled. 852 * | | |1 = PLL FOUT is fixed low. 853 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 854 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 855 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 856 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 857 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 858 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 859 * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). 860 * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). 861 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 862 * @var CLK_T::PLLFNCTL0 863 * Offset: 0x48 PLLFN Control Register 0 864 * --------------------------------------------------------------------------------------------------- 865 * |Bits |Field |Descriptions 866 * | :----: | :----: | :---- | 867 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 868 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 869 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 870 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 871 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 872 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 873 * |[27:16] |FRDIV |PLL Fractional Divider Control (Write Protect) 874 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 875 * @var CLK_T::PLLFNCTL1 876 * Offset: 0x4C PLLFN Control Register 1 877 * --------------------------------------------------------------------------------------------------- 878 * |Bits |Field |Descriptions 879 * | :----: | :----: | :---- | 880 * |[27] |STBSEL |PLL Stable Counter Selection (Write Protect) 881 * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). 882 * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). 883 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 884 * |[28] |PD |Power-down Mode (Write Protect) 885 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 886 * | | |0 = PLL is in normal mode. 887 * | | |1 = PLL is in Power-down mode (default). 888 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 889 * |[29] |BP |PLL Bypass Control (Write Protect) 890 * | | |0 = PLL is in normal mode (default). 891 * | | |1 = PLL clock output is same as PLL input clock FIN. 892 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 893 * |[30] |OE |PLL FOUT Enable Control (Write Protect) 894 * | | |0 = PLL FOUT Enabled. 895 * | | |1 = PLL FOUT is fixed low. 896 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 897 * |[31] |PLLSRC |PLL Source Clock Selection (Write Protect) 898 * | | |0 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). 899 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 900 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 901 * @var CLK_T::STATUS 902 * Offset: 0x50 Clock Status Monitor Register 903 * --------------------------------------------------------------------------------------------------- 904 * |Bits |Field |Descriptions 905 * | :----: | :----: | :---- | 906 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 907 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 908 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 909 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 910 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 911 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 912 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 913 * | | |0 = Internal PLL clock is not stable or disabled. 914 * | | |1 = Internal PLL clock is stable and enabled. 915 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 916 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 917 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 918 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 919 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 920 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 921 * |[6] |HIRC48MSTB|HIRC48M Clock Source Stable Flag (Read Only) 922 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is not stable or disabled. 923 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is stable and enabled. 924 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 925 * | | |This bit is updated when software switches system clock source 926 * | | |If switch target clock is stable, this bit will be set to 0 927 * | | |If switch target clock is not stable, this bit will be set to 1. 928 * | | |0 = Clock switching success. 929 * | | |1 = Clock switching failure. 930 * | | |Note: This bit is read only. 931 * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 932 * |[10] |PLLFNSTB |Internal PLLFN Clock Source Stable Flag 933 * | | |0 = Internal PLLFN clock is not stable or disabled. 934 * | | |1 = Internal PLLFN clock is stable. 935 * | | |Note: This bit is read only. 936 * @var CLK_T::AHBCLK1 937 * Offset: 0x58 AHB Devices Clock Enable Control Register 1 938 * --------------------------------------------------------------------------------------------------- 939 * |Bits |Field |Descriptions 940 * | :----: | :----: | :---- | 941 * |[20] |CANFD0CKEN|CANFD0 Clock Enable Bit 942 * | | |0 = CANFD0 clock Disabled. 943 * | | |1 = CANFD0 clock Enabled. 944 * |[21] |CANFD1CKEN|CANFD1 Clock Enable Bit 945 * | | |0 = CANFD1 clock Disabled. 946 * | | |1 = CANFD1 clock Enabled. 947 * |[22] |CANFD2CKEN|CANFD2 Clock Enable Bit 948 * | | |0 = CANFD2 clock Disabled. 949 * | | |1 = CANFD2 clock Enabled. 950 * |[23] |CANFD3CKEN|CANFD3 Clock Enable Bit 951 * | | |0 = CANFD3 clock Disabled. 952 * | | |1 = CANFD3 clock Enabled. 953 * |[24] |GPICKEN |GPIOI Clock Enable Bit 954 * | | |0 = GPIOI clock Disabled. 955 * | | |1 = GPIOI clock Enabled. 956 * |[25] |GPJCKEN |GPIOJ Clock Enable Bit 957 * | | |0 = GPIOJ clock Disabled. 958 * | | |1 = GPIOJ clock Enabled. 959 * |[28] |BMCCKEN |BMC Clock Enable Bit 960 * | | |0 = BMC clock Disabled. 961 * | | |1 = BMC clock Enabled. 962 * @var CLK_T::CLKSEL4 963 * Offset: 0x5C Clock Source Select Control Register 4 964 * --------------------------------------------------------------------------------------------------- 965 * |Bits |Field |Descriptions 966 * | :----: | :----: | :---- | 967 * |[2:0] |SPI4SEL |SPI4 Clock Source Selection 968 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 969 * | | |001 = Clock source from PLL/2. 970 * | | |010 = Clock source from PCLK1. 971 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 972 * | | |Others = Reserved. 973 * |[6:4] |SPI5SEL |SPI5 Clock Source Selection 974 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 975 * | | |001 = Clock source from PLL/2. 976 * | | |010 = Clock source from PCLK0. 977 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 978 * | | |Others = Reserved. 979 * |[10:8] |SPI6SEL |SPI6 Clock Source Selection 980 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 981 * | | |001 = Clock source from PLL/2. 982 * | | |010 = Clock source from PCLK1. 983 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 984 * | | |Others = Reserved. 985 * |[14:12] |SPI7SEL |SPI7 Clock Source Selection 986 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 987 * | | |001 = Clock source from PLL/2. 988 * | | |010 = Clock source from PCLK1. 989 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 990 * | | |Others = Reserved. 991 * |[18:16] |SPI8SEL |SPI8 Clock Source Selection 992 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 993 * | | |001 = Clock source from PLL/2. 994 * | | |010 = Clock source from PCLK0. 995 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 996 * | | |Others = Reserved. 997 * |[22:20] |SPI9SEL |SPI9 Clock Source Selection 998 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 999 * | | |001 = Clock source from PLL/2. 1000 * | | |010 = Clock source from PCLK1. 1001 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 1002 * | | |Others = Reserved. 1003 * |[26:24] |SPI10SEL |SPI10 Clock Source Selection 1004 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 1005 * | | |001 = Clock source from PLL/2. 1006 * | | |010 = Clock source from PCLK1. 1007 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 1008 * | | |Others = Reserved. 1009 * @var CLK_T::CLKOCTL 1010 * Offset: 0x60 Clock Output Control Register 1011 * --------------------------------------------------------------------------------------------------- 1012 * |Bits |Field |Descriptions 1013 * | :----: | :----: | :---- | 1014 * |[3:0] |FREQSEL |Clock Output Frequency Selection 1015 * | | |The formula of output frequency is Fout = Fin/2^(N+1). 1016 * | | |Fin is the input clock frequency. 1017 * | | |Fout is the frequency of divider output clock. 1018 * | | |N is the 4-bit value of FREQSEL[3:0]. 1019 * |[4] |CLKOEN |Clock Output Enable Bit 1020 * | | |0 = Clock Output function Disabled. 1021 * | | |1 = Clock Output function Enabled. 1022 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 1023 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 1024 * | | |1 = Clock Output will output clock with source frequency. 1025 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 1026 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 1027 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 1028 * @var CLK_T::CLKDCTL 1029 * Offset: 0x70 Clock Fail Detector Control Register 1030 * --------------------------------------------------------------------------------------------------- 1031 * |Bits |Field |Descriptions 1032 * | :----: | :----: | :---- | 1033 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 1034 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 1035 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 1036 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 1037 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 1038 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 1039 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 1040 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 1041 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 1042 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 1043 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 1044 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 1045 * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit 1046 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. 1047 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. 1048 * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit 1049 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. 1050 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. 1051 * |[18] |HXTFQASW |HXT Clock Frequency Range Detector Event Auto Switch Enable Bit 1052 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will not switch to HIRC automatically. 1053 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will switch to HIRC automatically. 1054 * | | |Note: This bit should be set before HXTFQDEN(CLK_CLKDCTL[16]). 1055 * @var CLK_T::CLKDSTS 1056 * Offset: 0x74 Clock Fail Detector Status Register 1057 * --------------------------------------------------------------------------------------------------- 1058 * |Bits |Field |Descriptions 1059 * | :----: | :----: | :---- | 1060 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) 1061 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 1062 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 1063 * | | |Note 1: Write 1 to clear the bit to 0. 1064 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1065 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) 1066 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 1067 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 1068 * | | |Note 1: Write 1 to clear the bit to 0. 1069 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1070 * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) 1071 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. 1072 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 1073 * | | |Note 1: Write 1 to clear the bit to 0. 1074 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1075 * @var CLK_T::CDUPB 1076 * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register 1077 * --------------------------------------------------------------------------------------------------- 1078 * |Bits |Field |Descriptions 1079 * | :----: | :----: | :---- | 1080 * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value 1081 * | | |The bits define the maximum value of frequency range detector window. 1082 * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 1083 * @var CLK_T::CDLOWB 1084 * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register 1085 * --------------------------------------------------------------------------------------------------- 1086 * |Bits |Field |Descriptions 1087 * | :----: | :----: | :---- | 1088 * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value 1089 * | | |The bits define the minimum value of frequency range detector window. 1090 * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 1091 * @var CLK_T::STOPREQ 1092 * Offset: 0x80 Clock Stop Request Register 1093 * --------------------------------------------------------------------------------------------------- 1094 * |Bits |Field |Descriptions 1095 * | :----: | :----: | :---- | 1096 * |[0] |CANFD0STR |CANFD0 Clock Stop Request 1097 * | | |This bit is used to stop CANFD0 clock. 1098 * | | |0 = CANFD0 clock is not stoped by this bit. (default) 1099 * | | |1 = Set this bit and check the CANFD0STA(CLK_STOPACK[0]) is 1, then CANFD0 clock stop. 1100 * |[1] |CANFD1STR |CANFD1 Clock Stop Request 1101 * | | |This bit is used to stop CANFD1 clock. 1102 * | | |0 = CANFD1 clock is not stoped by this bit. (default) 1103 * | | |1 = Set this bit and check the CANFD1STA(CLK_STOPACK[1]) is 1, then CANFD1 clock stop. 1104 * |[2] |CANFD2STR |CANFD2 Clock Stop Request 1105 * | | |This bit is used to stop CANFD2 clock. 1106 * | | |0 = CANFD2 clock is not stoped by this bit. (default) 1107 * | | |1 = Set this bit and check the CANFD2STA(CLK_STOPACK[2]) is 1, then CANFD2 clock stop. 1108 * |[3] |CANFD3STR |CANFD3 Clock Stop Request 1109 * | | |This bit is used to stop CANFD3 clock. 1110 * | | |0 = CANFD3 clock is not stoped by this bit. (default) 1111 * | | |1 = Set this bit and check the CANFD3STA(CLK_STOPACK[3]) is 1, then CANFD3 clock stop. 1112 * @var CLK_T::STOPACK 1113 * Offset: 0x84 Clock Stop Acknowledge Register 1114 * --------------------------------------------------------------------------------------------------- 1115 * |Bits |Field |Descriptions 1116 * | :----: | :----: | :---- | 1117 * |[0] |CANFD0STA |CANFD0 Clock Stop Acknowledge (Read Only) 1118 * | | |This bit is used to check CANFD0 clock stop by setting CANFD0STR(CLK_STOPREQ[0]). 1119 * | | |0 = CANFD0 clock not stoped. 1120 * | | |1 = CANFD0 clock stoped. 1121 * |[1] |CANFD1STA |CANFD1 Clock Stop Acknowledge (Read Only) 1122 * | | |This bit is used to check CANFD1 clock stop by setting CANFD1STR(CLK_STOPREQ[1]). 1123 * | | |0 = CANFD1 clock not stoped. 1124 * | | |1 = CANFD1 clock stoped. 1125 * |[2] |CANFD2STA |CANFD2 Clock Stop Acknowledge (Read Only) 1126 * | | |This bit is used to check CANFD2 clock stop by setting CANFD2STR(CLK_STOPREQ[2]). 1127 * | | |0 = CANFD2 clock not stoped. 1128 * | | |1 = CANFD2 clock stoped. 1129 * |[3] |CAN3STACK |CANFD3 Clock Stop Acknowledge (Read Only) 1130 * | | |This bit is used to check CANFD3 clock stop by setting CANFD3STR(CLK_STOPREQ[3]). 1131 * | | |0 = CANFD3 clock not stoped. 1132 * | | |1 = CANFD3 clock stoped. 1133 * @var CLK_T::PMUCTL 1134 * Offset: 0x90 Power Manager Control Register 1135 * --------------------------------------------------------------------------------------------------- 1136 * |Bits |Field |Descriptions 1137 * | :----: | :----: | :---- | 1138 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 1139 * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. 1140 * | | |000 = Normal Power-down mode is selected (NPD). 1141 * | | |001 = Low leakage Power-down mode is selected (LLPD). 1142 * | | |010 = Fast wake-up Power-down mode is selected (FWPD). 1143 * | | |011 = Reserved. 1144 * | | |100 = Standby Power-down mode is selected (SPD). 1145 * | | |101 = Reserved. 1146 * | | |110 = Deep Power-down mode is selected (DPD). 1147 * | | |111 = Reserved. 1148 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1149 * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable Bit (Write Protect) 1150 * | | |0= When GPIO enters deep power-down mode, all I/O status are tri-state. 1151 * | | |1= When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status. 1152 * | | |After chip was woken up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] to release I/O hold status. 1153 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1154 * |[6:4] |SRETSEL |SRAM Retention Range Select Bit (Write Protect) 1155 * | | |Select SRAM retention range when chip enter SPD mode. 1156 * | | |000 = No SRAM retention. 1157 * | | |001 = 16K SRAM retention when chip enter SPD mode. 1158 * | | |010 = 32K SRAM retention when chip enter SPD mode. 1159 * | | |011 = 64K SRAM retention when chip enter SPD mode. 1160 * | | |100 = 128K SRAM retention when chip enter SPD mode. (default) 1161 * | | |101 = 256K SRAM retention when chip enter SPD mode. 1162 * | | |Others = Reserved. 1163 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1164 * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) 1165 * | | |0 = Wake-up timer disabled at DPD/SPD mode. 1166 * | | |1 = Wake-up timer enabled at DPD/SPD mode. 1167 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1168 * |[12:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 1169 * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 1170 * | | |0000 = Time-out interval is 128 LIRC clocks (12.8 ms). 1171 * | | |0001 = Time-out interval is 256 LIRC clocks (25.6 ms). 1172 * | | |0010 = Time-out interval is 512 LIRC clocks (51.2 ms). 1173 * | | |0011 = Time-out interval is 1024 LIRC clocks (102.4ms). 1174 * | | |0100 = Time-out interval is 4096 LIRC clocks (409.6ms). 1175 * | | |0101 = Time-out interval is 8192 LIRC clocks (819.2ms). 1176 * | | |0110 = Time-out interval is 16384 LIRC clocks (1638.4ms). 1177 * | | |0111 = Time-out interval is 65536 LIRC clocks (6553.6ms). 1178 * | | |1000 = Time-out interval is 131072 LIRC clocks (13107.2ms). 1179 * | | |1001 = Time-out interval is 262144 LIRC clocks (26214.4ms). 1180 * | | |1010 = Time-out interval is 524288 LIRC clocks (52428.8ms). 1181 * | | |1011 = Time-out interval is 1048576 LIRC clocks (104857.6ms). 1182 * | | |Others = Time-out interval is 128 LIRC clocks (12.8ms). 1183 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1184 * |[17:16] |WKPINEN0 |Wake-up Pin0 Enable Bit (Write Protect) 1185 * | | |This is control register for GPC.0 to wake-up pin. 1186 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1187 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1188 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1189 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1190 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1191 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect) 1192 * | | |0 = ACMP wake-up disabled at Standby Power-down mode. 1193 * | | |1 = ACMP wake-up enabled at Standby Power-down mode. 1194 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 1195 * | | |Note 2: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection, the filter clock is LIRC in ACMP SPD mode wakeup function. 1196 * |[22] |VBUSWKEN |VBUS Wake-up Enable Bit (Write Protect) 1197 * | | |0 = VBUS transition wake-up disabled at Deep Power-down mode. 1198 * | | |1 = VBUS transition wake-up enabled at Deep Power-down mode. 1199 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1200 * |[23] |RTCWKEN |RTC Wake-up Enable Bit (Write Protect) 1201 * | | |0 = RTC wake-up disabled at Deep Power-down mode or Standby Power-down mode. 1202 * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. 1203 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1204 * |[25:24] |WKPINEN1 |Wake-up Pin1 Enable Bit (Write Protect) 1205 * | | |This is control register for GPB.0 to wake-up pin. 1206 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1207 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1208 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1209 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1210 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1211 * |[27:26] |WKPINEN2 |Wake-up Pin2 Enable Bit (Write Protect) 1212 * | | |This is control register for GPB.2 to wake-up pin. 1213 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1214 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1215 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1216 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1217 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1218 * |[29:28] |WKPINEN3 |Wake-up Pin3 Enable Bit (Write Protect) 1219 * | | |This is control register for GPB.12 to wake-up pin. 1220 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1221 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1222 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1223 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1224 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1225 * |[31:30] |WKPINEN4 |Wake-up Pin4 Enable Bit (Write Protect) 1226 * | | |This is control register for GPF.6 to wake-up pin. 1227 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1228 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1229 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1230 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1231 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 1232 * | | |Note 2: Setting IOCTLSEL(RTC_LXTCTL[8]) to avoid GPF.6 unexpected falling edge. 1233 * @var CLK_T::PMUSTS 1234 * Offset: 0x94 Power Manager Status Register 1235 * --------------------------------------------------------------------------------------------------- 1236 * |Bits |Field |Descriptions 1237 * | :----: | :----: | :---- | 1238 * |[0] |PINWK0 |Pin0 Wake-up Flag (Read Only) 1239 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). 1240 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1241 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 1242 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. 1243 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1244 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 1245 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. 1246 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1247 * |[3] |PINWK1 |Pin1 Wake-up Flag (Read Only) 1248 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). 1249 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1250 * |[4] |PINWK2 |Pin2 Wake-up Flag (Read Only) 1251 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). 1252 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1253 * |[5] |PINWK3 |Pin3 Wake-up Flag (Read Only) 1254 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). 1255 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1256 * |[6] |PINWK4 |Pin4 Wake-up Flag (Read Only) 1257 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). 1258 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1259 * |[7] |VBUSWK |VBUS Wake-up Flag( Read Only) 1260 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). 1261 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1262 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 1263 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. 1264 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1265 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 1266 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. 1267 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1268 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 1269 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. 1270 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1271 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 1272 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. 1273 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1274 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 1275 * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. 1276 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1277 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 1278 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. 1279 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1280 * |[15] |RSTWK |RST pin Wake-up Flag (Read Only) 1281 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RST pin trigger happened. 1282 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1283 * |[16] |ACMPWK0 |ACMP0 Wake-up Flag (Read Only) 1284 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP0 transition. 1285 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1286 * |[17] |ACMPWK1 |ACMP1 Wake-up Flag (Read Only) 1287 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP1 transition. 1288 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1289 * |[18] |ACMPWK2 |ACMP2 Wake-up Flag (Read Only) 1290 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP2 transition. 1291 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1292 * |[19] |ACMPWK3 |ACMP3 Wake-up Flag (Read Only) 1293 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP3 transition. 1294 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1295 * |[31] |CLRWK |Clear Wake-up Flag 1296 * | | |0 = No clear. 1297 * | | |1= Clear all wake-up flag. 1298 * | | |Note: This bit is auto cleared by hardware. 1299 * @var CLK_T::SWKDBCTL 1300 * Offset: 0x9C GPIO Standby Power-down Wake-up De-bounce Control Register 1301 * --------------------------------------------------------------------------------------------------- 1302 * |Bits |Field |Descriptions 1303 * | :----: | :----: | :---- | 1304 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 1305 * | | |0000 = Sample wake-up input once per 1 clock. 1306 * | | |0001 = Sample wake-up input once per 2 clocks. 1307 * | | |0010 = Sample wake-up input once per 4 clocks. 1308 * | | |0011 = Sample wake-up input once per 8 clocks. 1309 * | | |0100 = Sample wake-up input once per 16 clocks. 1310 * | | |0101 = Sample wake-up input once per 32 clocks. 1311 * | | |0110 = Sample wake-up input once per 64 clocks. 1312 * | | |0111 = Sample wake-up input once per 128 clocks. 1313 * | | |1000 = Sample wake-up input once per 256 clocks. 1314 * | | |1001 = Sample wake-up input once per 2*256 clocks. 1315 * | | |1010 = Sample wake-up input once per 4*256 clocks. 1316 * | | |1011 = Sample wake-up input once per 8*256 clocks. 1317 * | | |1100 = Sample wake-up input once per 16*256 clocks. 1318 * | | |1101 = Sample wake-up input once per 32*256 clocks. 1319 * | | |1110 = Sample wake-up input once per 64*256 clocks. 1320 * | | |1111 = Sample wake-up input once per 128*256 clocks.. 1321 * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1322 * @var CLK_T::PASWKCTL 1323 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 1324 * --------------------------------------------------------------------------------------------------- 1325 * |Bits |Field |Descriptions 1326 * | :----: | :----: | :---- | 1327 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1328 * | | |0 = GPA group pin wake-up function Disabled. 1329 * | | |1 = GPA group pin wake-up function Enabled. 1330 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1331 * | | |0 = GPA group pin rising edge wake-up function Disabled. 1332 * | | |1 = GPA group pin rising edge wake-up function Enabled. 1333 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1334 * | | |0 = GPA group pin falling edge wake-up function Disabled. 1335 * | | |1 = GPA group pin falling edge wake-up function Enabled. 1336 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 1337 * | | |0000 = GPA.0 wake-up function Enabled. 1338 * | | |0001 = GPA.1 wake-up function Enabled. 1339 * | | |0010 = GPA.2 wake-up function Enabled. 1340 * | | |0011 = GPA.3 wake-up function Enabled. 1341 * | | |0100 = GPA.4 wake-up function Enabled. 1342 * | | |0101 = GPA.5 wake-up function Enabled. 1343 * | | |0110 = GPA.6 wake-up function Enabled. 1344 * | | |0111 = GPA.7 wake-up function Enabled. 1345 * | | |1000 = GPA.8 wake-up function Enabled. 1346 * | | |1001 = GPA.9 wake-up function Enabled. 1347 * | | |1010 = GPA.10 wake-up function Enabled. 1348 * | | |1011 = GPA.11 wake-up function Enabled. 1349 * | | |1100 = GPA.12 wake-up function Enabled. 1350 * | | |1101 = GPA.13 wake-up function Enabled. 1351 * | | |1110 = GPA.14 wake-up function Enabled. 1352 * | | |1111 = GPA.15 wake-up function Enabled. 1353 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 1354 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1355 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1356 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1357 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1358 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1359 * | | |The de-bounce function is valid only for edge triggered. 1360 * @var CLK_T::PBSWKCTL 1361 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 1362 * --------------------------------------------------------------------------------------------------- 1363 * |Bits |Field |Descriptions 1364 * | :----: | :----: | :---- | 1365 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1366 * | | |0 = GPB group pin wake-up function Disabled. 1367 * | | |1 = GPB group pin wake-up function Enabled. 1368 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1369 * | | |0 = GPB group pin rising edge wake-up function Disabled. 1370 * | | |1 = GPB group pin rising edge wake-up function Enabled. 1371 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1372 * | | |0 = GPB group pin falling edge wake-up function Disabled. 1373 * | | |1 = GPB group pin falling edge wake-up function Enabled. 1374 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 1375 * | | |0000 = GPB.0 wake-up function Enabled. 1376 * | | |0001 = GPB.1 wake-up function Enabled. 1377 * | | |0010 = GPB.2 wake-up function Enabled. 1378 * | | |0011 = GPB.3 wake-up function Enabled. 1379 * | | |0100 = GPB.4 wake-up function Enabled. 1380 * | | |0101 = GPB.5 wake-up function Enabled. 1381 * | | |0110 = GPB.6 wake-up function Enabled. 1382 * | | |0111 = GPB.7 wake-up function Enabled. 1383 * | | |1000 = GPB.8 wake-up function Enabled. 1384 * | | |1001 = GPB.9 wake-up function Enabled. 1385 * | | |1010 = GPB.10 wake-up function Enabled. 1386 * | | |1011 = GPB.11 wake-up function Enabled. 1387 * | | |1100 = GPB.12 wake-up function Enabled. 1388 * | | |1101 = GPB.13 wake-up function Enabled. 1389 * | | |1110 = GPB.14 wake-up function Enabled. 1390 * | | |1111 = GPB.15 wake-up function Enabled. 1391 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 1392 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1393 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1394 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. (LIRC) 1395 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1396 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1397 * | | |The de-bounce function is valid only for edge triggered. 1398 * @var CLK_T::PCSWKCTL 1399 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 1400 * --------------------------------------------------------------------------------------------------- 1401 * |Bits |Field |Descriptions 1402 * | :----: | :----: | :---- | 1403 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1404 * | | |0 = GPC group pin wake-up function Disabled. 1405 * | | |1 = GPC group pin wake-up function Enabled. 1406 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1407 * | | |0 = GPC group pin rising edge wake-up function Disabled. 1408 * | | |1 = GPC group pin rising edge wake-up function Enabled. 1409 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1410 * | | |0 = GPC group pin falling edge wake-up function Disabled. 1411 * | | |1 = GPC group pin falling edge wake-up function Enabled. 1412 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 1413 * | | |0000 = GPC.0 wake-up function Enabled. 1414 * | | |0001 = GPC.1 wake-up function Enabled. 1415 * | | |0010 = GPC.2 wake-up function Enabled. 1416 * | | |0011 = GPC.3 wake-up function Enabled. 1417 * | | |0100 = GPC.4 wake-up function Enabled. 1418 * | | |0101 = GPC.5 wake-up function Enabled. 1419 * | | |0110 = GPC.6 wake-up function Enabled. 1420 * | | |0111 = GPC.7 wake-up function Enabled. 1421 * | | |1000 = GPC.8 wake-up function Enabled. 1422 * | | |1001 = GPC.9 wake-up function Enabled. 1423 * | | |1010 = GPC.10 wake-up function Enabled. 1424 * | | |1011 = GPC.11 wake-up function Enabled. 1425 * | | |1100 = GPC.12 wake-up function Enabled. 1426 * | | |1101 = GPC.13 wake-up function Enabled. 1427 * | | |1110 = GPC.14 wake-up function Enabled. 1428 * | | |1111 = GPC.15 wake-up function Enabled. 1429 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 1430 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1431 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1432 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1433 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1434 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1435 * | | |Note: The de-bounce function is valid only for edge triggered. 1436 * @var CLK_T::PDSWKCTL 1437 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 1438 * --------------------------------------------------------------------------------------------------- 1439 * |Bits |Field |Descriptions 1440 * | :----: | :----: | :---- | 1441 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1442 * | | |0 = GPD group pin wake-up function Disabled. 1443 * | | |1 = GPD group pin wake-up function Enabled. 1444 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1445 * | | |0 = GPD group pin rising edge wake-up function Disabled. 1446 * | | |1 = GPD group pin rising edge wake-up function Enabled. 1447 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1448 * | | |0 = GPD group pin falling edge wake-up function Disabled. 1449 * | | |1 = GPD group pin falling edge wake-up function Enabled. 1450 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 1451 * | | |0000 = GPD.0 wake-up function Enabled. 1452 * | | |0001 = GPD.1 wake-up function Enabled. 1453 * | | |0010 = GPD.2 wake-up function Enabled. 1454 * | | |0011 = GPD.3 wake-up function Enabled. 1455 * | | |0100 = GPD.4 wake-up function Enabled. 1456 * | | |0101 = GPD.5 wake-up function Enabled. 1457 * | | |0110 = GPD.6 wake-up function Enabled. 1458 * | | |0111 = GPD.7 wake-up function Enabled. 1459 * | | |1000 = GPD.8 wake-up function Enabled. 1460 * | | |1001 = GPD.9 wake-up function Enabled. 1461 * | | |1010 = GPD.10 wake-up function Enabled. 1462 * | | |1011 = GPD.11 wake-up function Enabled. 1463 * | | |1100 = GPD.12 wake-up function Enabled. 1464 * | | |1101 = GPD.13 wake-up function Enabled. 1465 * | | |1110 = GPD.14 wake-up function Enabled. 1466 * | | |1111 = GPD.15 wake-up function Enabled. 1467 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 1468 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1469 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1470 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1471 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1472 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1473 * | | |Note: The de-bounce function is valid only for edge triggered. 1474 * @var CLK_T::IOPDCTL 1475 * Offset: 0xB0 GPIO Standby Power-down Control Register 1476 * --------------------------------------------------------------------------------------------------- 1477 * |Bits |Field |Descriptions 1478 * | :----: | :----: | :---- | 1479 * |[0] |IOHR |GPIO Hold Release 1480 * | | |When GPIO enters deep power-down mode or standby power-down mode, all I/O status are hold to keep normal operating status. 1481 * | | |After chip is woken up from deep power-down mode or standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. 1482 * | | |Note: This bit is auto cleared by hardware. 1483 */ 1484 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 1485 __IO uint32_t AHBCLK0; /*!< [0x0004] AHB Devices Clock Enable Control Register 0 */ 1486 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 1487 __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ 1488 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 1489 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 1490 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 1491 __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ 1492 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 1493 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 1494 __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */ 1495 __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ 1496 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 1497 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 1498 __IO uint32_t APBCLK2; /*!< [0x0038] APB Devices Clock Enable Control Register 2 */ 1499 __IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 */ 1500 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 1501 __I uint32_t RESERVE0[1]; 1502 __IO uint32_t PLLFNCTL0; /*!< [0x0048] PLLFN Control Register 0 */ 1503 __IO uint32_t PLLFNCTL1; /*!< [0x004c] PLLFN Control Register 1 */ 1504 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 1505 __I uint32_t RESERVE1[1]; 1506 __IO uint32_t AHBCLK1; /*!< [0x0058] AHB Devices Clock Enable Control Register 1 */ 1507 __IO uint32_t CLKSEL4; /*!< [0x005c] Clock Source Select Control Register 4 */ 1508 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 1509 __I uint32_t RESERVE3[3]; 1510 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 1511 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 1512 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ 1513 __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ 1514 __IO uint32_t STOPREQ; /*!< [0x0080] Clock Stop Request Register */ 1515 __I uint32_t STOPACK; /*!< [0x0084] Clock Stop Acknowledge Register */ 1516 __I uint32_t RESERVE4[2]; 1517 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 1518 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 1519 __I uint32_t RESERVE5[1]; 1520 __IO uint32_t SWKDBCTL; /*!< [0x009c] GPIO Standby Power-down Wake-up De-bounce Control Register */ 1521 __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ 1522 __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ 1523 __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ 1524 __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ 1525 __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ 1526 1527 } CLK_T; 1528 #endif 1529 1530 /** 1531 @addtogroup CLK_CONST CLK Bit Field Definition 1532 Constant Definitions for CLK Controller 1533 @{ */ 1534 1535 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 1536 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 1537 1538 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 1539 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1540 1541 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1542 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1543 1544 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1545 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1546 1547 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ 1548 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ 1549 1550 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1551 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1552 1553 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1554 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1555 1556 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1557 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1558 1559 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1560 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1561 1562 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1563 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1564 1565 #define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ 1566 #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ 1567 1568 #define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ 1569 #define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ 1570 1571 #define CLK_PWRCTL_HXTMD_Pos (31) /*!< CLK_T::PWRCTL: HXTMD Position */ 1572 #define CLK_PWRCTL_HXTMD_Msk (0x1ul << CLK_PWRCTL_HXTMD_Pos) /*!< CLK_T::PWRCTL: HXTMD Mask */ 1573 1574 #define CLK_AHBCLK0_PDMA0CKEN_Pos (1) /*!< CLK_T::AHBCLK0: PDMA0CKEN Position */ 1575 #define CLK_AHBCLK0_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA0CKEN Mask */ 1576 1577 #define CLK_AHBCLK0_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK0: ISPCKEN Position */ 1578 #define CLK_AHBCLK0_ISPCKEN_Msk (0x1ul << CLK_AHBCLK0_ISPCKEN_Pos) /*!< CLK_T::AHBCLK0: ISPCKEN Mask */ 1579 1580 #define CLK_AHBCLK0_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK0: EBICKEN Position */ 1581 #define CLK_AHBCLK0_EBICKEN_Msk (0x1ul << CLK_AHBCLK0_EBICKEN_Pos) /*!< CLK_T::AHBCLK0: EBICKEN Mask */ 1582 1583 #define CLK_AHBCLK0_STCKEN_Pos (4) /*!< CLK_T::AHBCLK0: STCKEN Position */ 1584 #define CLK_AHBCLK0_STCKEN_Msk (0x1ul << CLK_AHBCLK0_STCKEN_Pos) /*!< CLK_T::AHBCLK0: STCKEN Mask */ 1585 1586 #define CLK_AHBCLK0_EMAC0CKEN_Pos (5) /*!< CLK_T::AHBCLK0: EMAC0CKEN Position */ 1587 #define CLK_AHBCLK0_EMAC0CKEN_Msk (0x1ul << CLK_AHBCLK0_EMAC0CKEN_Pos) /*!< CLK_T::AHBCLK0: EMAC0CKEN Mask */ 1588 1589 #define CLK_AHBCLK0_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK0: SDH0CKEN Position */ 1590 #define CLK_AHBCLK0_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH0CKEN Mask */ 1591 1592 #define CLK_AHBCLK0_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK0: CRCCKEN Position */ 1593 #define CLK_AHBCLK0_CRCCKEN_Msk (0x1ul << CLK_AHBCLK0_CRCCKEN_Pos) /*!< CLK_T::AHBCLK0: CRCCKEN Mask */ 1594 1595 #define CLK_AHBCLK0_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK0: CCAPCKEN Position */ 1596 #define CLK_AHBCLK0_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK0_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK0: CCAPCKEN Mask */ 1597 1598 #define CLK_AHBCLK0_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK0: SENCKEN Position */ 1599 #define CLK_AHBCLK0_SENCKEN_Msk (0x1ul << CLK_AHBCLK0_SENCKEN_Pos) /*!< CLK_T::AHBCLK0: SENCKEN Mask */ 1600 1601 #define CLK_AHBCLK0_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Position */ 1602 #define CLK_AHBCLK0_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK0_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Mask */ 1603 1604 #define CLK_AHBCLK0_HBICKEN_Pos (11) /*!< CLK_T::AHBCLK0: HBICKEN Position */ 1605 #define CLK_AHBCLK0_HBICKEN_Msk (0x1ul << CLK_AHBCLK0_HBICKEN_Pos) /*!< CLK_T::AHBCLK0: HBICKEN Mask */ 1606 1607 #define CLK_AHBCLK0_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK0: CRPTCKEN Position */ 1608 #define CLK_AHBCLK0_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK0_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK0: CRPTCKEN Mask */ 1609 1610 #define CLK_AHBCLK0_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK0: KSCKEN Position */ 1611 #define CLK_AHBCLK0_KSCKEN_Msk (0x1ul << CLK_AHBCLK0_KSCKEN_Pos) /*!< CLK_T::AHBCLK0: KSCKEN Mask */ 1612 1613 #define CLK_AHBCLK0_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK0: SPIMCKEN Position */ 1614 #define CLK_AHBCLK0_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK0_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK0: SPIMCKEN Mask */ 1615 1616 #define CLK_AHBCLK0_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK0: FMCIDLE Position */ 1617 #define CLK_AHBCLK0_FMCIDLE_Msk (0x1ul << CLK_AHBCLK0_FMCIDLE_Pos) /*!< CLK_T::AHBCLK0: FMCIDLE Mask */ 1618 1619 #define CLK_AHBCLK0_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK0: USBHCKEN Position */ 1620 #define CLK_AHBCLK0_USBHCKEN_Msk (0x1ul << CLK_AHBCLK0_USBHCKEN_Pos) /*!< CLK_T::AHBCLK0: USBHCKEN Mask */ 1621 1622 #define CLK_AHBCLK0_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK0: SDH1CKEN Position */ 1623 #define CLK_AHBCLK0_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH1CKEN Mask */ 1624 1625 #define CLK_AHBCLK0_PDMA1CKEN_Pos (18) /*!< CLK_T::AHBCLK0: PDMA1CKEN Position */ 1626 #define CLK_AHBCLK0_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA1CKEN Mask */ 1627 1628 #define CLK_AHBCLK0_TRACECKEN_Pos (19) /*!< CLK_T::AHBCLK0: TRACECKEN Position */ 1629 #define CLK_AHBCLK0_TRACECKEN_Msk (0x1ul << CLK_AHBCLK0_TRACECKEN_Pos) /*!< CLK_T::AHBCLK0: TRACECKEN Mask */ 1630 1631 #define CLK_AHBCLK0_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK0: GPACKEN Position */ 1632 #define CLK_AHBCLK0_GPACKEN_Msk (0x1ul << CLK_AHBCLK0_GPACKEN_Pos) /*!< CLK_T::AHBCLK0: GPACKEN Mask */ 1633 1634 #define CLK_AHBCLK0_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK0: GPBCKEN Position */ 1635 #define CLK_AHBCLK0_GPBCKEN_Msk (0x1ul << CLK_AHBCLK0_GPBCKEN_Pos) /*!< CLK_T::AHBCLK0: GPBCKEN Mask */ 1636 1637 #define CLK_AHBCLK0_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK0: GPCCKEN Position */ 1638 #define CLK_AHBCLK0_GPCCKEN_Msk (0x1ul << CLK_AHBCLK0_GPCCKEN_Pos) /*!< CLK_T::AHBCLK0: GPCCKEN Mask */ 1639 1640 #define CLK_AHBCLK0_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK0: GPDCKEN Position */ 1641 #define CLK_AHBCLK0_GPDCKEN_Msk (0x1ul << CLK_AHBCLK0_GPDCKEN_Pos) /*!< CLK_T::AHBCLK0: GPDCKEN Mask */ 1642 1643 #define CLK_AHBCLK0_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK0: GPECKEN Position */ 1644 #define CLK_AHBCLK0_GPECKEN_Msk (0x1ul << CLK_AHBCLK0_GPECKEN_Pos) /*!< CLK_T::AHBCLK0: GPECKEN Mask */ 1645 1646 #define CLK_AHBCLK0_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK0: GPFCKEN Position */ 1647 #define CLK_AHBCLK0_GPFCKEN_Msk (0x1ul << CLK_AHBCLK0_GPFCKEN_Pos) /*!< CLK_T::AHBCLK0: GPFCKEN Mask */ 1648 1649 #define CLK_AHBCLK0_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK0: GPGCKEN Position */ 1650 #define CLK_AHBCLK0_GPGCKEN_Msk (0x1ul << CLK_AHBCLK0_GPGCKEN_Pos) /*!< CLK_T::AHBCLK0: GPGCKEN Mask */ 1651 1652 #define CLK_AHBCLK0_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK0: GPHCKEN Position */ 1653 #define CLK_AHBCLK0_GPHCKEN_Msk (0x1ul << CLK_AHBCLK0_GPHCKEN_Pos) /*!< CLK_T::AHBCLK0: GPHCKEN Mask */ 1654 1655 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 1656 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 1657 1658 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1659 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1660 1661 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1662 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1663 1664 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1665 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1666 1667 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1668 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1669 1670 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1671 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1672 1673 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1674 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1675 1676 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1677 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1678 1679 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1680 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1681 1682 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1683 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1684 1685 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1686 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1687 1688 #define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK_T::APBCLK0: I2C3CKEN Position */ 1689 #define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK_T::APBCLK0: I2C3CKEN Mask */ 1690 1691 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1692 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1693 1694 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1695 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1696 1697 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1698 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1699 1700 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1701 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1702 1703 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1704 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1705 1706 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1707 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1708 1709 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1710 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1711 1712 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1713 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1714 1715 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1716 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1717 1718 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1719 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1720 1721 #define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ 1722 #define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ 1723 1724 #define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ 1725 #define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ 1726 1727 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1728 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1729 1730 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1731 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1732 1733 #define CLK_APBCLK0_EADC0CKEN_Pos (28) /*!< CLK_T::APBCLK0: EADC0CKEN Position */ 1734 #define CLK_APBCLK0_EADC0CKEN_Msk (0x1ul << CLK_APBCLK0_EADC0CKEN_Pos) /*!< CLK_T::APBCLK0: EADC0CKEN Mask */ 1735 1736 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 1737 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 1738 1739 #define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ 1740 #define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ 1741 1742 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 1743 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 1744 1745 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 1746 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 1747 1748 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 1749 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 1750 1751 #define CLK_APBCLK1_I2C4CKEN_Pos (3) /*!< CLK_T::APBCLK1: I2C4CKEN Position */ 1752 #define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK_T::APBCLK1: I2C4CKEN Mask */ 1753 1754 #define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ 1755 #define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ 1756 1757 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1758 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1759 1760 #define CLK_APBCLK1_SPI4CKEN_Pos (7) /*!< CLK_T::APBCLK1: SPI4CKEN Position */ 1761 #define CLK_APBCLK1_SPI4CKEN_Msk (0x1ul << CLK_APBCLK1_SPI4CKEN_Pos) /*!< CLK_T::APBCLK1: SPI4CKEN Mask */ 1762 1763 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1764 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1765 1766 #define CLK_APBCLK1_PSIOCKEN_Pos (10) /*!< CLK_T::APBCLK1: PSIOCKEN Position */ 1767 #define CLK_APBCLK1_PSIOCKEN_Msk (0x1ul << CLK_APBCLK1_PSIOCKEN_Pos) /*!< CLK_T::APBCLK1: PSIOCKEN Mask */ 1768 1769 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 1770 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 1771 1772 #define CLK_APBCLK1_ECAP2CKEN_Pos (13) /*!< CLK_T::APBCLK1: ECAP2CKEN Position */ 1773 #define CLK_APBCLK1_ECAP2CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP2CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP2CKEN Mask */ 1774 1775 #define CLK_APBCLK1_ECAP3CKEN_Pos (14) /*!< CLK_T::APBCLK1: ECAP3CKEN Position */ 1776 #define CLK_APBCLK1_ECAP3CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP3CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP3CKEN Mask */ 1777 1778 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1779 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1780 1781 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1782 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1783 1784 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 1785 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 1786 1787 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 1788 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 1789 1790 #define CLK_APBCLK1_EQEI2CKEN_Pos (20) /*!< CLK_T::APBCLK1: EQEI2CKEN Position */ 1791 #define CLK_APBCLK1_EQEI2CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI2CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI2CKEN Mask */ 1792 1793 #define CLK_APBCLK1_EQEI3CKEN_Pos (21) /*!< CLK_T::APBCLK1: EQEI3CKEN Position */ 1794 #define CLK_APBCLK1_EQEI3CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI3CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI3CKEN Mask */ 1795 1796 #define CLK_APBCLK1_EQEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: EQEI0CKEN Position */ 1797 #define CLK_APBCLK1_EQEI0CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI0CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI0CKEN Mask */ 1798 1799 #define CLK_APBCLK1_EQEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: EQEI1CKEN Position */ 1800 #define CLK_APBCLK1_EQEI1CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI1CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI1CKEN Mask */ 1801 1802 #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ 1803 #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ 1804 1805 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1806 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1807 1808 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1809 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1810 1811 #define CLK_APBCLK1_I2S1CKEN_Pos (29) /*!< CLK_T::APBCLK1: I2S1CKEN Position */ 1812 #define CLK_APBCLK1_I2S1CKEN_Msk (0x1ul << CLK_APBCLK1_I2S1CKEN_Pos) /*!< CLK_T::APBCLK1: I2S1CKEN Mask */ 1813 1814 #define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */ 1815 #define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */ 1816 1817 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 1818 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 1819 1820 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1821 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1822 1823 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ 1824 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ 1825 1826 #define CLK_CLKSEL0_EADC0SEL_Pos (10) /*!< CLK_T::CLKSEL0: EADC0SEL Position */ 1827 #define CLK_CLKSEL0_EADC0SEL_Msk (0x3ul << CLK_CLKSEL0_EADC0SEL_Pos) /*!< CLK_T::CLKSEL0: EADC0SEL Mask */ 1828 1829 #define CLK_CLKSEL0_EADC1SEL_Pos (12) /*!< CLK_T::CLKSEL0: EADC1SEL Position */ 1830 #define CLK_CLKSEL0_EADC1SEL_Msk (0x3ul << CLK_CLKSEL0_EADC1SEL_Pos) /*!< CLK_T::CLKSEL0: EADC1SEL Mask */ 1831 1832 #define CLK_CLKSEL0_EADC2SEL_Pos (14) /*!< CLK_T::CLKSEL0: EADC2SEL Position */ 1833 #define CLK_CLKSEL0_EADC2SEL_Msk (0x3ul << CLK_CLKSEL0_EADC2SEL_Pos) /*!< CLK_T::CLKSEL0: EADC2SEL Mask */ 1834 1835 #define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */ 1836 #define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */ 1837 1838 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 1839 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 1840 1841 #define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ 1842 #define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ 1843 1844 #define CLK_CLKSEL0_CANFD0SEL_Pos (24) /*!< CLK_T::CLKSEL0: CANFD0SEL Position */ 1845 #define CLK_CLKSEL0_CANFD0SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD0SEL Mask */ 1846 1847 #define CLK_CLKSEL0_CANFD1SEL_Pos (26) /*!< CLK_T::CLKSEL0: CANFD1SEL Position */ 1848 #define CLK_CLKSEL0_CANFD1SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD1SEL Mask */ 1849 1850 #define CLK_CLKSEL0_CANFD2SEL_Pos (28) /*!< CLK_T::CLKSEL0: CANFD2SEL Position */ 1851 #define CLK_CLKSEL0_CANFD2SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD2SEL Mask */ 1852 1853 #define CLK_CLKSEL0_CANFD3SEL_Pos (30) /*!< CLK_T::CLKSEL0: CANFD3SEL Position */ 1854 #define CLK_CLKSEL0_CANFD3SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD3SEL Mask */ 1855 1856 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 1857 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 1858 1859 #define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1860 #define CLK_CLKSEL1_CLKOSEL_Msk (0x7ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1861 1862 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1863 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1864 1865 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1866 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1867 1868 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1869 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1870 1871 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1872 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1873 1874 #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ 1875 #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ 1876 1877 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ 1878 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ 1879 1880 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1881 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1882 1883 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1884 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1885 1886 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1887 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1888 1889 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1890 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1891 1892 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1893 #define CLK_CLKSEL2_SPI0SEL_Msk (0x7ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1894 1895 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 1896 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 1897 1898 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 1899 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 1900 1901 #define CLK_CLKSEL2_QSPI1SEL_Pos (10) /*!< CLK_T::CLKSEL2: QSPI1SEL Position */ 1902 #define CLK_CLKSEL2_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI1SEL Mask */ 1903 1904 #define CLK_CLKSEL2_SPI1SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1905 #define CLK_CLKSEL2_SPI1SEL_Msk (0x7ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1906 1907 #define CLK_CLKSEL2_I2S1SEL_Pos (16) /*!< CLK_T::CLKSEL2: I2S1SEL Position */ 1908 #define CLK_CLKSEL2_I2S1SEL_Msk (0x7ul << CLK_CLKSEL2_I2S1SEL_Pos) /*!< CLK_T::CLKSEL2: I2S1SEL Mask */ 1909 1910 #define CLK_CLKSEL2_UART8SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART8SEL Position */ 1911 #define CLK_CLKSEL2_UART8SEL_Msk (0x3ul << CLK_CLKSEL2_UART8SEL_Pos) /*!< CLK_T::CLKSEL2: UART8SEL Mask */ 1912 1913 #define CLK_CLKSEL2_UART9SEL_Pos (22) /*!< CLK_T::CLKSEL2: UART9SEL Position */ 1914 #define CLK_CLKSEL2_UART9SEL_Msk (0x3ul << CLK_CLKSEL2_UART9SEL_Pos) /*!< CLK_T::CLKSEL2: UART9SEL Mask */ 1915 1916 #define CLK_CLKSEL2_TRNGSEL_Pos (27) /*!< CLK_T::CLKSEL2: TRNGSEL Position */ 1917 #define CLK_CLKSEL2_TRNGSEL_Msk (0x1ul << CLK_CLKSEL2_TRNGSEL_Pos) /*!< CLK_T::CLKSEL2: TRNGSEL Mask */ 1918 1919 #define CLK_CLKSEL2_PSIOSEL_Pos (28) /*!< CLK_T::CLKSEL2: PSIOSEL Position */ 1920 #define CLK_CLKSEL2_PSIOSEL_Msk (0x7ul << CLK_CLKSEL2_PSIOSEL_Pos) /*!< CLK_T::CLKSEL2: PSIOSEL Mask */ 1921 1922 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 1923 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 1924 1925 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 1926 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 1927 1928 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 1929 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 1930 1931 #define CLK_CLKSEL3_KPISEL_Pos (6) /*!< CLK_T::CLKSEL3: KPISEL Position */ 1932 #define CLK_CLKSEL3_KPISEL_Msk (0x3ul << CLK_CLKSEL3_KPISEL_Pos) /*!< CLK_T::CLKSEL3: KPISEL Mask */ 1933 1934 #define CLK_CLKSEL3_SPI2SEL_Pos (9) /*!< CLK_T::CLKSEL3: SPI2SEL Position */ 1935 #define CLK_CLKSEL3_SPI2SEL_Msk (0x7ul << CLK_CLKSEL3_SPI2SEL_Pos) /*!< CLK_T::CLKSEL3: SPI2SEL Mask */ 1936 1937 #define CLK_CLKSEL3_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL3: SPI3SEL Position */ 1938 #define CLK_CLKSEL3_SPI3SEL_Msk (0x7ul << CLK_CLKSEL3_SPI3SEL_Pos) /*!< CLK_T::CLKSEL3: SPI3SEL Mask */ 1939 1940 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 1941 #define CLK_CLKSEL3_I2S0SEL_Msk (0x7ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 1942 1943 #define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */ 1944 #define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */ 1945 1946 #define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */ 1947 #define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */ 1948 1949 #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ 1950 #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ 1951 1952 #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ 1953 #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ 1954 1955 #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 1956 #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 1957 1958 #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 1959 #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 1960 1961 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 1962 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 1963 1964 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1965 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1966 1967 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1968 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1969 1970 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1971 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1972 1973 #define CLK_CLKDIV0_EADC0DIV_Pos (16) /*!< CLK_T::CLKDIV0: EADC0DIV Position */ 1974 #define CLK_CLKDIV0_EADC0DIV_Msk (0xfful << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLK_T::CLKDIV0: EADC0DIV Mask */ 1975 1976 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 1977 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 1978 1979 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 1980 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 1981 1982 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 1983 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 1984 1985 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 1986 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 1987 1988 #define CLK_CLKDIV1_PSIODIV_Pos (24) /*!< CLK_T::CLKDIV1: PSIODIV Position */ 1989 #define CLK_CLKDIV1_PSIODIV_Msk (0xfful << CLK_CLKDIV1_PSIODIV_Pos) /*!< CLK_T::CLKDIV1: PSIODIV Mask */ 1990 1991 #define CLK_CLKDIV2_I2S0DIV_Pos (0) /*!< CLK_T::CLKDIV2: I2S0DIV Position */ 1992 #define CLK_CLKDIV2_I2S0DIV_Msk (0xful << CLK_CLKDIV2_I2S0DIV_Pos) /*!< CLK_T::CLKDIV2: I2S0DIV Mask */ 1993 1994 #define CLK_CLKDIV2_I2S1DIV_Pos (4) /*!< CLK_T::CLKDIV2: I2S1DIV Position */ 1995 #define CLK_CLKDIV2_I2S1DIV_Msk (0xful << CLK_CLKDIV2_I2S1DIV_Pos) /*!< CLK_T::CLKDIV2: I2S1DIV Mask */ 1996 1997 #define CLK_CLKDIV2_KPIDIV_Pos (8) /*!< CLK_T::CLKDIV2: KPIDIV Position */ 1998 #define CLK_CLKDIV2_KPIDIV_Msk (0xfful << CLK_CLKDIV2_KPIDIV_Pos) /*!< CLK_T::CLKDIV2: KPIDIV Mask */ 1999 2000 #define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */ 2001 #define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */ 2002 2003 #define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */ 2004 #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */ 2005 2006 #define CLK_CLKDIV3_EMAC0DIV_Pos (16) /*!< CLK_T::CLKDIV3: EMAC0DIV Position */ 2007 #define CLK_CLKDIV3_EMAC0DIV_Msk (0xfful << CLK_CLKDIV3_EMAC0DIV_Pos) /*!< CLK_T::CLKDIV3: EMAC0DIV Mask */ 2008 2009 #define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ 2010 #define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ 2011 2012 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 2013 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 2014 2015 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 2016 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 2017 2018 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 2019 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 2020 2021 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 2022 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 2023 2024 #define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ 2025 #define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ 2026 2027 #define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ 2028 #define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ 2029 2030 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 2031 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 2032 2033 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 2034 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 2035 2036 #define CLK_APBCLK2_KPICKEN_Pos (0) /*!< CLK_T::APBCLK2: KPICKEN Position */ 2037 #define CLK_APBCLK2_KPICKEN_Msk (0x1ul << CLK_APBCLK2_KPICKEN_Pos) /*!< CLK_T::APBCLK2: KPICKEN Mask */ 2038 2039 #define CLK_APBCLK2_EADC2CKEN_Pos (6) /*!< CLK_T::APBCLK2: EADC2CKEN Position */ 2040 #define CLK_APBCLK2_EADC2CKEN_Msk (0x1ul << CLK_APBCLK2_EADC2CKEN_Pos) /*!< CLK_T::APBCLK2: EADC2CKEN Mask */ 2041 2042 #define CLK_APBCLK2_ACMP23CKEN_Pos (7) /*!< CLK_T::APBCLK2: ACMP23CKEN Position */ 2043 #define CLK_APBCLK2_ACMP23CKEN_Msk (0x1ul << CLK_APBCLK2_ACMP23CKEN_Pos) /*!< CLK_T::APBCLK2: ACMP23CKEN Mask */ 2044 2045 #define CLK_APBCLK2_SPI5CKEN_Pos (8) /*!< CLK_T::APBCLK2: SPI5CKEN Position */ 2046 #define CLK_APBCLK2_SPI5CKEN_Msk (0x1ul << CLK_APBCLK2_SPI5CKEN_Pos) /*!< CLK_T::APBCLK2: SPI5CKEN Mask */ 2047 2048 #define CLK_APBCLK2_SPI6CKEN_Pos (9) /*!< CLK_T::APBCLK2: SPI6CKEN Position */ 2049 #define CLK_APBCLK2_SPI6CKEN_Msk (0x1ul << CLK_APBCLK2_SPI6CKEN_Pos) /*!< CLK_T::APBCLK2: SPI6CKEN Mask */ 2050 2051 #define CLK_APBCLK2_SPI7CKEN_Pos (10) /*!< CLK_T::APBCLK2: SPI7CKEN Position */ 2052 #define CLK_APBCLK2_SPI7CKEN_Msk (0x1ul << CLK_APBCLK2_SPI7CKEN_Pos) /*!< CLK_T::APBCLK2: SPI7CKEN Mask */ 2053 2054 #define CLK_APBCLK2_SPI8CKEN_Pos (11) /*!< CLK_T::APBCLK2: SPI8CKEN Position */ 2055 #define CLK_APBCLK2_SPI8CKEN_Msk (0x1ul << CLK_APBCLK2_SPI8CKEN_Pos) /*!< CLK_T::APBCLK2: SPI8CKEN Mask */ 2056 2057 #define CLK_APBCLK2_SPI9CKEN_Pos (12) /*!< CLK_T::APBCLK2: SPI9CKEN Position */ 2058 #define CLK_APBCLK2_SPI9CKEN_Msk (0x1ul << CLK_APBCLK2_SPI9CKEN_Pos) /*!< CLK_T::APBCLK2: SPI9CKEN Mask */ 2059 2060 #define CLK_APBCLK2_SPI10CKEN_Pos (13) /*!< CLK_T::APBCLK2: SPI10CKEN Position */ 2061 #define CLK_APBCLK2_SPI10CKEN_Msk (0x1ul << CLK_APBCLK2_SPI10CKEN_Pos) /*!< CLK_T::APBCLK2: SPI10CKEN Mask */ 2062 2063 #define CLK_APBCLK2_UART8CKEN_Pos (16) /*!< CLK_T::APBCLK2: UART8CKEN Position */ 2064 #define CLK_APBCLK2_UART8CKEN_Msk (0x1ul << CLK_APBCLK2_UART8CKEN_Pos) /*!< CLK_T::APBCLK2: UART8CKEN Mask */ 2065 2066 #define CLK_APBCLK2_UART9CKEN_Pos (17) /*!< CLK_T::APBCLK2: UART9CKEN Position */ 2067 #define CLK_APBCLK2_UART9CKEN_Msk (0x1ul << CLK_APBCLK2_UART9CKEN_Pos) /*!< CLK_T::APBCLK2: UART9CKEN Mask */ 2068 2069 #define CLK_CLKDIV5_CANFD0DIV_Pos (0) /*!< CLK_T::CLKDIV5: CANFD0DIV Position */ 2070 #define CLK_CLKDIV5_CANFD0DIV_Msk (0xful << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD0DIV Mask */ 2071 2072 #define CLK_CLKDIV5_CANFD1DIV_Pos (4) /*!< CLK_T::CLKDIV5: CANFD1DIV Position */ 2073 #define CLK_CLKDIV5_CANFD1DIV_Msk (0xful << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD1DIV Mask */ 2074 2075 #define CLK_CLKDIV5_CANFD2DIV_Pos (8) /*!< CLK_T::CLKDIV5: CANFD2DIV Position */ 2076 #define CLK_CLKDIV5_CANFD2DIV_Msk (0xful << CLK_CLKDIV5_CANFD2DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD2DIV Mask */ 2077 2078 #define CLK_CLKDIV5_CANFD3DIV_Pos (12) /*!< CLK_T::CLKDIV5: CANFD3DIV Position */ 2079 #define CLK_CLKDIV5_CANFD3DIV_Msk (0xful << CLK_CLKDIV5_CANFD3DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD3DIV Mask */ 2080 2081 #define CLK_CLKDIV5_UART8DIV_Pos (16) /*!< CLK_T::CLKDIV5: UART8DIV Position */ 2082 #define CLK_CLKDIV5_UART8DIV_Msk (0xful << CLK_CLKDIV5_UART8DIV_Pos) /*!< CLK_T::CLKDIV5: UART8DIV Mask */ 2083 2084 #define CLK_CLKDIV5_UART9DIV_Pos (20) /*!< CLK_T::CLKDIV5: UART9DIV Position */ 2085 #define CLK_CLKDIV5_UART9DIV_Msk (0xful << CLK_CLKDIV5_UART9DIV_Pos) /*!< CLK_T::CLKDIV5: UART9DIV Mask */ 2086 2087 #define CLK_CLKDIV5_EADC2DIV_Pos (24) /*!< CLK_T::CLKDIV5: EADC2DIV Position */ 2088 #define CLK_CLKDIV5_EADC2DIV_Msk (0xfful << CLK_CLKDIV5_EADC2DIV_Pos) /*!< CLK_T::CLKDIV5: EADC2DIV Mask */ 2089 2090 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 2091 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 2092 2093 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 2094 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 2095 2096 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 2097 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 2098 2099 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 2100 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 2101 2102 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 2103 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 2104 2105 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 2106 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 2107 2108 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 2109 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 2110 2111 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 2112 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 2113 2114 #define CLK_PLLFNCTL0_FBDIV_Pos (0) /*!< CLK_T::PLLFNCTL0: FBDIV Position */ 2115 #define CLK_PLLFNCTL0_FBDIV_Msk (0x1fful << CLK_PLLFNCTL0_FBDIV_Pos) /*!< CLK_T::PLLFNCTL0: FBDIV Mask */ 2116 2117 #define CLK_PLLFNCTL0_INDIV_Pos (9) /*!< CLK_T::PLLFNCTL0: INDIV Position */ 2118 #define CLK_PLLFNCTL0_INDIV_Msk (0x1ful << CLK_PLLFNCTL0_INDIV_Pos) /*!< CLK_T::PLLFNCTL0: INDIV Mask */ 2119 2120 #define CLK_PLLFNCTL0_OUTDIV_Pos (14) /*!< CLK_T::PLLFNCTL0: OUTDIV Position */ 2121 #define CLK_PLLFNCTL0_OUTDIV_Msk (0x3ul << CLK_PLLFNCTL0_OUTDIV_Pos) /*!< CLK_T::PLLFNCTL0: OUTDIV Mask */ 2122 2123 #define CLK_PLLFNCTL0_FRDIV_Pos (16) /*!< CLK_T::PLLFNCTL0: FRDIV Position */ 2124 #define CLK_PLLFNCTL0_FRDIV_Msk (0xffful << CLK_PLLFNCTL0_FRDIV_Pos) /*!< CLK_T::PLLFNCTL0: FRDIV Mask */ 2125 2126 #define CLK_PLLFNCTL1_STBSEL_Pos (27) /*!< CLK_T::PLLFNCTL1: STBSEL Position */ 2127 #define CLK_PLLFNCTL1_STBSEL_Msk (0x1ul << CLK_PLLFNCTL1_STBSEL_Pos) /*!< CLK_T::PLLFNCTL1: STBSEL Mask */ 2128 2129 #define CLK_PLLFNCTL1_PD_Pos (28) /*!< CLK_T::PLLFNCTL1: PD Position */ 2130 #define CLK_PLLFNCTL1_PD_Msk (0x1ul << CLK_PLLFNCTL1_PD_Pos) /*!< CLK_T::PLLFNCTL1: PD Mask */ 2131 2132 #define CLK_PLLFNCTL1_BP_Pos (29) /*!< CLK_T::PLLFNCTL1: BP Position */ 2133 #define CLK_PLLFNCTL1_BP_Msk (0x1ul << CLK_PLLFNCTL1_BP_Pos) /*!< CLK_T::PLLFNCTL1: BP Mask */ 2134 2135 #define CLK_PLLFNCTL1_OE_Pos (30) /*!< CLK_T::PLLFNCTL1: OE Position */ 2136 #define CLK_PLLFNCTL1_OE_Msk (0x1ul << CLK_PLLFNCTL1_OE_Pos) /*!< CLK_T::PLLFNCTL1: OE Mask */ 2137 2138 #define CLK_PLLFNCTL1_PLLSRC_Pos (31) /*!< CLK_T::PLLFNCTL1: PLLSRC Position */ 2139 #define CLK_PLLFNCTL1_PLLSRC_Msk (0x1ul << CLK_PLLFNCTL1_PLLSRC_Pos) /*!< CLK_T::PLLFNCTL1: PLLSRC Mask */ 2140 2141 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 2142 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 2143 2144 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 2145 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 2146 2147 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 2148 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 2149 2150 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 2151 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 2152 2153 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 2154 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 2155 2156 #define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */ 2157 #define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */ 2158 2159 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 2160 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 2161 2162 #define CLK_STATUS_PLLFNSTB_Pos (10) /*!< CLK_T::STATUS: PLLFNSTB Position */ 2163 #define CLK_STATUS_PLLFNSTB_Msk (0x1ul << CLK_STATUS_PLLFNSTB_Pos) /*!< CLK_T::STATUS: PLLFNSTB Mask */ 2164 2165 #define CLK_AHBCLK1_CANFD0CKEN_Pos (20) /*!< CLK_T::AHBCLK1: CANFD0CKEN Position */ 2166 #define CLK_AHBCLK1_CANFD0CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD0CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD0CKEN Mask */ 2167 2168 #define CLK_AHBCLK1_CANFD1CKEN_Pos (21) /*!< CLK_T::AHBCLK1: CANFD1CKEN Position */ 2169 #define CLK_AHBCLK1_CANFD1CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD1CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD1CKEN Mask */ 2170 2171 #define CLK_AHBCLK1_CANFD2CKEN_Pos (22) /*!< CLK_T::AHBCLK1: CANFD2CKEN Position */ 2172 #define CLK_AHBCLK1_CANFD2CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD2CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD2CKEN Mask */ 2173 2174 #define CLK_AHBCLK1_CANFD3CKEN_Pos (23) /*!< CLK_T::AHBCLK1: CANFD3CKEN Position */ 2175 #define CLK_AHBCLK1_CANFD3CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD3CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD3CKEN Mask */ 2176 2177 #define CLK_AHBCLK1_GPICKEN_Pos (24) /*!< CLK_T::AHBCLK1: GPICKEN Position */ 2178 #define CLK_AHBCLK1_GPICKEN_Msk (0x1ul << CLK_AHBCLK1_GPICKEN_Pos) /*!< CLK_T::AHBCLK1: GPICKEN Mask */ 2179 2180 #define CLK_AHBCLK1_GPJCKEN_Pos (25) /*!< CLK_T::AHBCLK1: GPJCKEN Position */ 2181 #define CLK_AHBCLK1_GPJCKEN_Msk (0x1ul << CLK_AHBCLK1_GPJCKEN_Pos) /*!< CLK_T::AHBCLK1: GPJCKEN Mask */ 2182 2183 #define CLK_AHBCLK1_BMCCKEN_Pos (28) /*!< CLK_T::AHBCLK1: BMCCKEN Position */ 2184 #define CLK_AHBCLK1_BMCCKEN_Msk (0x1ul << CLK_AHBCLK1_BMCCKEN_Pos) /*!< CLK_T::AHBCLK1: BMCCKEN Mask */ 2185 2186 #define CLK_CLKSEL4_SPI4SEL_Pos (0) /*!< CLK_T::CLKSEL4: SPI4SEL Position */ 2187 #define CLK_CLKSEL4_SPI4SEL_Msk (0x7ul << CLK_CLKSEL4_SPI4SEL_Pos) /*!< CLK_T::CLKSEL4: SPI4SEL Mask */ 2188 2189 #define CLK_CLKSEL4_SPI5SEL_Pos (4) /*!< CLK_T::CLKSEL4: SPI5SEL Position */ 2190 #define CLK_CLKSEL4_SPI5SEL_Msk (0x7ul << CLK_CLKSEL4_SPI5SEL_Pos) /*!< CLK_T::CLKSEL4: SPI5SEL Mask */ 2191 2192 #define CLK_CLKSEL4_SPI6SEL_Pos (8) /*!< CLK_T::CLKSEL4: SPI6SEL Position */ 2193 #define CLK_CLKSEL4_SPI6SEL_Msk (0x7ul << CLK_CLKSEL4_SPI6SEL_Pos) /*!< CLK_T::CLKSEL4: SPI6SEL Mask */ 2194 2195 #define CLK_CLKSEL4_SPI7SEL_Pos (12) /*!< CLK_T::CLKSEL4: SPI7SEL Position */ 2196 #define CLK_CLKSEL4_SPI7SEL_Msk (0x7ul << CLK_CLKSEL4_SPI7SEL_Pos) /*!< CLK_T::CLKSEL4: SPI7SEL Mask */ 2197 2198 #define CLK_CLKSEL4_SPI8SEL_Pos (16) /*!< CLK_T::CLKSEL4: SPI8SEL Position */ 2199 #define CLK_CLKSEL4_SPI8SEL_Msk (0x7ul << CLK_CLKSEL4_SPI8SEL_Pos) /*!< CLK_T::CLKSEL4: SPI8SEL Mask */ 2200 2201 #define CLK_CLKSEL4_SPI9SEL_Pos (20) /*!< CLK_T::CLKSEL4: SPI9SEL Position */ 2202 #define CLK_CLKSEL4_SPI9SEL_Msk (0x7ul << CLK_CLKSEL4_SPI9SEL_Pos) /*!< CLK_T::CLKSEL4: SPI9SEL Mask */ 2203 2204 #define CLK_CLKSEL4_SPI10SEL_Pos (24) /*!< CLK_T::CLKSEL4: SPI10SEL Position */ 2205 #define CLK_CLKSEL4_SPI10SEL_Msk (0x7ul << CLK_CLKSEL4_SPI10SEL_Pos) /*!< CLK_T::CLKSEL4: SPI10SEL Mask */ 2206 2207 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 2208 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 2209 2210 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 2211 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 2212 2213 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 2214 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 2215 2216 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 2217 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 2218 2219 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 2220 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 2221 2222 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 2223 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 2224 2225 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 2226 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 2227 2228 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 2229 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 2230 2231 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 2232 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 2233 2234 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 2235 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 2236 2237 #define CLK_CLKDCTL_HXTFQASW_Pos (18) /*!< CLK_T::CLKDCTL: HXTFQASW Position */ 2238 #define CLK_CLKDCTL_HXTFQASW_Msk (0x1ul << CLK_CLKDCTL_HXTFQASW_Pos) /*!< CLK_T::CLKDCTL: HXTFQASW Mask */ 2239 2240 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 2241 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 2242 2243 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 2244 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 2245 2246 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 2247 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 2248 2249 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 2250 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 2251 2252 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 2253 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 2254 2255 #define CLK_STOPREQ_CANFD0STR_Pos (0) /*!< CLK_T::STOPREQ: CANFD0STR Position */ 2256 #define CLK_STOPREQ_CANFD0STR_Msk (0x1ul << CLK_STOPREQ_CANFD0STR_Pos) /*!< CLK_T::STOPREQ: CANFD0STR Mask */ 2257 2258 #define CLK_STOPREQ_CANFD1STR_Pos (1) /*!< CLK_T::STOPREQ: CANFD1STR Position */ 2259 #define CLK_STOPREQ_CANFD1STR_Msk (0x1ul << CLK_STOPREQ_CANFD1STR_Pos) /*!< CLK_T::STOPREQ: CANFD1STR Mask */ 2260 2261 #define CLK_STOPREQ_CANFD2STR_Pos (2) /*!< CLK_T::STOPREQ: CANFD2STR Position */ 2262 #define CLK_STOPREQ_CANFD2STR_Msk (0x1ul << CLK_STOPREQ_CANFD2STR_Pos) /*!< CLK_T::STOPREQ: CANFD2STR Mask */ 2263 2264 #define CLK_STOPREQ_CANFD3STR_Pos (3) /*!< CLK_T::STOPREQ: CANFD3STR Position */ 2265 #define CLK_STOPREQ_CANFD3STR_Msk (0x1ul << CLK_STOPREQ_CANFD3STR_Pos) /*!< CLK_T::STOPREQ: CANFD3STR Mask */ 2266 2267 #define CLK_STOPACK_CANFD0STA_Pos (0) /*!< CLK_T::STOPACK: CANFD0STA Position */ 2268 #define CLK_STOPACK_CANFD0STA_Msk (0x1ul << CLK_STOPACK_CANFD0STA_Pos) /*!< CLK_T::STOPACK: CANFD0STA Mask */ 2269 2270 #define CLK_STOPACK_CANFD1STA_Pos (1) /*!< CLK_T::STOPACK: CANFD1STA Position */ 2271 #define CLK_STOPACK_CANFD1STA_Msk (0x1ul << CLK_STOPACK_CANFD1STA_Pos) /*!< CLK_T::STOPACK: CANFD1STA Mask */ 2272 2273 #define CLK_STOPACK_CANFD2STA_Pos (2) /*!< CLK_T::STOPACK: CANFD2STA Position */ 2274 #define CLK_STOPACK_CANFD2STA_Msk (0x1ul << CLK_STOPACK_CANFD2STA_Pos) /*!< CLK_T::STOPACK: CANFD2STA Mask */ 2275 2276 #define CLK_STOPACK_CANFD3STA_Pos (3) /*!< CLK_T::STOPACK: CANFD3STA Position */ 2277 #define CLK_STOPACK_CANFD3STA_Msk (0x1ul << CLK_STOPACK_CANFD3STA_Pos) /*!< CLK_T::STOPACK: CANFD3STA Mask */ 2278 2279 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 2280 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 2281 2282 #define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */ 2283 #define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */ 2284 2285 #define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */ 2286 #define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ 2287 2288 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 2289 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 2290 2291 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 2292 #define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 2293 2294 #define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ 2295 #define CLK_PMUCTL_WKPINEN0_Msk (0x3ul << CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ 2296 2297 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 2298 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 2299 2300 #define CLK_PMUCTL_VBUSWKEN_Pos (22) /*!< CLK_T::PMUCTL: VBUSWKEN Position */ 2301 #define CLK_PMUCTL_VBUSWKEN_Msk (0x1ul << CLK_PMUCTL_VBUSWKEN_Pos) /*!< CLK_T::PMUCTL: VBUSWKEN Mask */ 2302 2303 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 2304 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 2305 2306 #define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ 2307 #define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ 2308 2309 #define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ 2310 #define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ 2311 2312 #define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ 2313 #define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ 2314 2315 #define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ 2316 #define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ 2317 2318 #define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ 2319 #define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ 2320 2321 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 2322 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 2323 2324 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 2325 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 2326 2327 #define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ 2328 #define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ 2329 2330 #define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ 2331 #define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ 2332 2333 #define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ 2334 #define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ 2335 2336 #define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ 2337 #define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ 2338 2339 #define CLK_PMUSTS_VBUSWK_Pos (7) /*!< CLK_T::PMUSTS: VBUSWK Position */ 2340 #define CLK_PMUSTS_VBUSWK_Msk (0x1ul << CLK_PMUSTS_VBUSWK_Pos) /*!< CLK_T::PMUSTS: VBUSWK Mask */ 2341 2342 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 2343 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 2344 2345 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 2346 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 2347 2348 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 2349 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 2350 2351 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 2352 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 2353 2354 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 2355 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 2356 2357 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 2358 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 2359 2360 #define CLK_PMUSTS_RSTWK_Pos (15) /*!< CLK_T::PMUSTS: RSTWK Position */ 2361 #define CLK_PMUSTS_RSTWK_Msk (0x1ul << CLK_PMUSTS_RSTWK_Pos) /*!< CLK_T::PMUSTS: RSTWK Mask */ 2362 2363 #define CLK_PMUSTS_ACMPWK0_Pos (16) /*!< CLK_T::PMUSTS: ACMPWK0 Position */ 2364 #define CLK_PMUSTS_ACMPWK0_Msk (0x1ul << CLK_PMUSTS_ACMPWK0_Pos) /*!< CLK_T::PMUSTS: ACMPWK0 Mask */ 2365 2366 #define CLK_PMUSTS_ACMPWK1_Pos (17) /*!< CLK_T::PMUSTS: ACMPWK1 Position */ 2367 #define CLK_PMUSTS_ACMPWK1_Msk (0x1ul << CLK_PMUSTS_ACMPWK1_Pos) /*!< CLK_T::PMUSTS: ACMPWK1 Mask */ 2368 2369 #define CLK_PMUSTS_ACMPWK2_Pos (18) /*!< CLK_T::PMUSTS: ACMPWK2 Position */ 2370 #define CLK_PMUSTS_ACMPWK2_Msk (0x1ul << CLK_PMUSTS_ACMPWK2_Pos) /*!< CLK_T::PMUSTS: ACMPWK2 Mask */ 2371 2372 #define CLK_PMUSTS_ACMPWK3_Pos (19) /*!< CLK_T::PMUSTS: ACMPWK3 Position */ 2373 #define CLK_PMUSTS_ACMPWK3_Msk (0x1ul << CLK_PMUSTS_ACMPWK3_Pos) /*!< CLK_T::PMUSTS: ACMPWK3 Mask */ 2374 2375 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 2376 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 2377 2378 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 2379 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 2380 2381 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 2382 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 2383 2384 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 2385 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 2386 2387 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 2388 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 2389 2390 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 2391 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 2392 2393 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 2394 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 2395 2396 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 2397 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 2398 2399 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 2400 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 2401 2402 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 2403 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 2404 2405 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 2406 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 2407 2408 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 2409 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 2410 2411 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 2412 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 2413 2414 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 2415 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 2416 2417 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 2418 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 2419 2420 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 2421 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 2422 2423 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 2424 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 2425 2426 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 2427 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 2428 2429 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 2430 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 2431 2432 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 2433 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 2434 2435 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 2436 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 2437 2438 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 2439 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 2440 2441 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 2442 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 2443 2444 2445 /**@}*/ /* CLK_CONST */ 2446 /**@}*/ /* end of CLK register group */ 2447 /**@}*/ /* end of REGISTER group */ 2448 2449 #if defined ( __CC_ARM ) 2450 #pragma no_anon_unions 2451 #endif 2452 2453 #endif /* __CLK_REG_H__ */ 2454
