1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIO_H__
35 #define NRF_GPIO_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #ifndef NRF_P0
44 #define NRF_P0 NRF_GPIO
45 #endif
46
47 #define GPIO_PORT_NUM(periph_name, prefix, i, _) i,
48 #define GPIO_REG(periph_name, prefix, i, _) NRFX_CONCAT(NRF_, periph_name, prefix, i),
49 #define GPIO_NUM_OF_PINS(periph_name, prefix, i, _) \
50 NRFX_CONCAT(periph_name, prefix, i, _PIN_NUM)
51
52 #define GPIO_PORT_NUM_LIST {NRFX_FOREACH_PRESENT(P, GPIO_PORT_NUM, (), (), _)}
53 #define GPIO_REG_LIST {NRFX_FOREACH_PRESENT(P, GPIO_REG, (), (), _)}
54 #define NUMBER_OF_PINS (NRFX_FOREACH_PRESENT(P, GPIO_NUM_OF_PINS, (+), (0), _))
55
56 #if !defined(GPIO_REG_LIST)
57 #error "Not supported."
58 #endif
59
60 #if defined(GPIO_PIN_CNF_DRIVE0_Msk)
61 #define GPIO_PIN_CNF_DRIVE1_OFFSET (GPIO_PIN_CNF_DRIVE1_Pos - GPIO_PIN_CNF_DRIVE0_Pos)
62 #endif
63
64 #if defined(NRF52820_XXAA)
65 #include <nrf_erratas.h>
66 #endif
67
68 /*
69 * Macro for generating case code blocks that return token NRF_<periph_name><prefix><i>
70 * for case value equal to <i>.
71 *
72 * Used by NRF_INTERNAL_GPIO_PORT_EXTRACT.
73 */
74 #define NRF_INTERNAL_GPIO_PORT_EXTRACT_1(periph_name, prefix, i, port) \
75 case i: \
76 port = NRFX_CONCAT(NRF_, periph_name, prefix, i); \
77 break;
78
79 /*
80 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_port_decode.
81 * It allows extracting the port number relative to the decoded pin.
82 */
83 #define NRF_INTERNAL_GPIO_PORT_EXTRACT(port) \
84 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_EXTRACT_1, (), (), port)
85
86 /*
87 * Macro for generating case code blocks that set mask to <periph_name><prefix><i>_FEATURE_PINS_PRESENT
88 * for case value equal to <i>.
89 *
90 * Used by NRF_INTERNAL_GPIO_PORT_MASK_SET.
91 */
92 #define NRF_INTERNAL_GPIO_PORT_MASK_SET_1(periph_name, prefix, i, mask) \
93 case i: \
94 mask = NRFX_CONCAT(periph_name, prefix, i, _FEATURE_PINS_PRESENT); \
95 break;
96
97 /*
98 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_present_check.
99 * It allows setting the mask to a value associated with the specific port.
100 */
101 #define NRF_INTERNAL_GPIO_PORT_MASK_SET(mask) \
102 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_MASK_SET_1, (), (), mask)
103
104 /**
105 * @defgroup nrf_gpio_hal GPIO HAL
106 * @{
107 * @ingroup nrf_gpio
108 * @brief Hardware access layer for managing the GPIO peripheral.
109 */
110
111 #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
112 /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
113 #define NRF_GPIO_LATCH_PRESENT
114 #endif
115
116 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(GPIO_PIN_CNF_CTRLSEL_Msk) \
117 || defined(__NRFX_DOXYGEN__)
118 /** @brief Presence of MCU/Subsystem control selection. */
119 #define NRF_GPIO_HAS_SEL 1
120 #else
121 #define NRF_GPIO_HAS_SEL 0
122 #endif
123
124 #if defined(GPIO_PIN_CNF_CTRLSEL_Msk) || defined(__NRFX_DOXYGEN__)
125 /** @brief Presence of MCU/Subsystem control selection for multiple peripherals. */
126 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 1
127 #else
128 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 0
129 #endif
130
131 #if defined(GPIO_PIN_CNF_CLOCKPIN_Msk) || defined(__NRFX_DOXYGEN__)
132 /** @brief Presence of clock pin enable. */
133 #define NRF_GPIO_HAS_CLOCKPIN 1
134 #else
135 #define NRF_GPIO_HAS_CLOCKPIN 0
136 #endif
137
138 #if defined(GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk) || defined(__NRFX_DOXYGEN__)
139 /** @brief Presence of drive control for impedance. */
140 #define NRF_GPIO_HAS_PORT_IMPEDANCE 1
141 #else
142 #define NRF_GPIO_HAS_PORT_IMPEDANCE 0
143 #endif
144
145 #if defined(GPIO_RETAIN_ResetValue) || defined(__NRFX_DOXYGEN__)
146 /** @brief Presence of register retention. */
147 #define NRF_GPIO_HAS_RETENTION 1
148 #else
149 #define NRF_GPIO_HAS_RETENTION 0
150 #endif
151
152 #if (defined(GPIO_RETAINSET_ResetValue) && defined(GPIO_RETAINCLR_ResetValue)) || \
153 defined(__NRFX_DOXYGEN__)
154 /** @brief Presence of register retention set/clear. */
155 #define NRF_GPIO_HAS_RETENTION_SETCLEAR 1
156 #else
157 #define NRF_GPIO_HAS_RETENTION_SETCLEAR 0
158 #endif
159
160 #if defined(GPIO_DETECTMODE_DETECTMODE_Msk) || defined(__NRFX_DOXYGEN__)
161 /** @brief Presence of detect mode. */
162 #define NRF_GPIO_HAS_DETECT_MODE 1
163 #else
164 #define NRF_GPIO_HAS_DETECT_MODE 0
165 #endif
166
167 /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
168 #define NRF_GPIO_PIN_MAP(port, pin) NRF_PIN_PORT_TO_PIN_NUMBER(pin, port)
169
170 #if NRF_GPIO_HAS_PORT_IMPEDANCE
171 /** @brief Mask of all impedances. */
172 #define NRF_GPIO_PORT_IMPEDANCE_ALL_MASK (GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk | \
173 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk | \
174 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk | \
175 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk | \
176 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk | \
177 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk)
178 #endif
179
180 /** @brief Pin direction definitions. */
181 typedef enum
182 {
183 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
184 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
185 } nrf_gpio_pin_dir_t;
186
187 /** @brief Connection of input buffer. */
188 typedef enum
189 {
190 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
191 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
192 } nrf_gpio_pin_input_t;
193
194 /**
195 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
196 * configuration.
197 */
198 typedef enum
199 {
200 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
201 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
202 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
203 } nrf_gpio_pin_pull_t;
204
205 /** @brief Enumerator used for selecting output drive mode. */
206 typedef enum
207 {
208 #if defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
209 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
210 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
211 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
212 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
213 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
214 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
215 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
216 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
217 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
218 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
219 #endif
220 #else
221 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE0_S0 |
222 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
223 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE0_H0 |
224 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
225 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE0_S0 |
226 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
227 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE0_H0 |
228 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
229 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE0_D0 |
230 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
231 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE0_D0 |
232 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
233 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE0_S0 |
234 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
235 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE0_H0 |
236 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
237 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE0_E0 |
238 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
239 #endif // defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
240 } nrf_gpio_pin_drive_t;
241
242 /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
243 typedef enum
244 {
245 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
246 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
247 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
248 } nrf_gpio_pin_sense_t;
249
250 #if NRF_GPIO_HAS_SEL
251 /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
252 typedef enum
253 {
254 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
255 NRF_GPIO_PIN_SEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
256 NRF_GPIO_PIN_SEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
257 NRF_GPIO_PIN_SEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
258 #endif
259 #if defined(GPIO_PIN_CNF_MCUSEL_TND) || defined(__NRFX_DOXYGEN__)
260 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
261 #elif defined(GPIO_PIN_CNF_CTRLSEL_TND)
262 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_CTRLSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
263 #endif
264 #if defined(GPIO_PIN_CNF_CTRLSEL_GPIO) || defined(__NRFX_DOXYGEN__)
265 NRF_GPIO_PIN_SEL_GPIO = GPIO_PIN_CNF_CTRLSEL_GPIO, ///< Pin controlled by GPIO or peripherals with configurable pins.
266 #endif
267 #if defined(GPIO_PIN_CNF_CTRLSEL_VPR) || defined(__NRFX_DOXYGEN__)
268 NRF_GPIO_PIN_SEL_VPR = GPIO_PIN_CNF_CTRLSEL_VPR, ///< Pin controlled by VPR.
269 #endif
270 #if defined(GPIO_PIN_CNF_CTRLSEL_GRTC) || defined(__NRFX_DOXYGEN__)
271 NRF_GPIO_PIN_SEL_GRTC = GPIO_PIN_CNF_CTRLSEL_GRTC, ///< Pin controlled by GRTC peripheral.
272 #endif
273 #if defined(NRF_GPIO_PIN_SEL_EXT)
274 NRF_GPIO_PIN_SEL_EXT
275 #endif
276 } nrf_gpio_pin_sel_t;
277 #endif // NRF_GPIO_HAS_SEL
278
279 #if NRF_GPIO_HAS_PORT_IMPEDANCE
280 /** @brief Port impedance enable mask. */
281 typedef enum
282 {
283 NRF_GPIO_PORT_IMPEDANCE_50_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk, ///< Enable 50 Ohm impedance.
284 NRF_GPIO_PORT_IMPEDANCE_100_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk, ///< Enable 100 Ohm impedance.
285 NRF_GPIO_PORT_IMPEDANCE_200_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk, ///< Enable 200 Ohm impedance.
286 NRF_GPIO_PORT_IMPEDANCE_400_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk, ///< Enable 400 Ohm impedance.
287 NRF_GPIO_PORT_IMPEDANCE_800_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk, ///< Enable 800 Ohm impedance.
288 NRF_GPIO_PORT_IMPEDANCE_1600_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk, ///< Enable 1600 Ohm impedance.
289 } nrf_gpio_port_impedance_mask_t;
290 #endif
291
292 #if NRF_GPIO_HAS_RETENTION
293 /** @brief Retention enable mask. */
294 typedef enum
295 {
296 #if defined(GPIO_RETAIN_APPLICAION_Msk) || defined(__NRFX_DOXYGEN__)
297 NRF_GPIO_RETAIN_APPLICATION_MASK = GPIO_RETAIN_APPLICAION_Msk, ///< Enable retention for GPIO registers for Application domain
298 #endif
299 #if defined(GPIO_RETAIN_RADIOCORE_Msk) || defined(__NRFX_DOXYGEN__)
300 NRF_GPIO_RETAIN_NETWORK_MASK = GPIO_RETAIN_RADIOCORE_Msk, ///< Enable retention for GPIO registers for Radio core
301 #endif
302 #if defined(GPIO_RETAIN_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
303 NRF_GPIO_RETAIN_PIN0_MASK = GPIO_RETAIN_PIN0_Msk, ///< Enable retention for pin 0.
304 NRF_GPIO_RETAIN_PIN1_MASK = GPIO_RETAIN_PIN1_Msk, ///< Enable retention for pin 1.
305 NRF_GPIO_RETAIN_PIN2_MASK = GPIO_RETAIN_PIN2_Msk, ///< Enable retention for pin 2.
306 NRF_GPIO_RETAIN_PIN3_MASK = GPIO_RETAIN_PIN3_Msk, ///< Enable retention for pin 3.
307 NRF_GPIO_RETAIN_PIN4_MASK = GPIO_RETAIN_PIN4_Msk, ///< Enable retention for pin 4.
308 NRF_GPIO_RETAIN_PIN5_MASK = GPIO_RETAIN_PIN5_Msk, ///< Enable retention for pin 5.
309 NRF_GPIO_RETAIN_PIN6_MASK = GPIO_RETAIN_PIN6_Msk, ///< Enable retention for pin 6.
310 NRF_GPIO_RETAIN_PIN7_MASK = GPIO_RETAIN_PIN7_Msk, ///< Enable retention for pin 7.
311 NRF_GPIO_RETAIN_PIN8_MASK = GPIO_RETAIN_PIN8_Msk, ///< Enable retention for pin 8.
312 NRF_GPIO_RETAIN_PIN9_MASK = GPIO_RETAIN_PIN9_Msk, ///< Enable retention for pin 9.
313 NRF_GPIO_RETAIN_PIN10_MASK = GPIO_RETAIN_PIN10_Msk, ///< Enable retention for pin 10.
314 NRF_GPIO_RETAIN_PIN11_MASK = GPIO_RETAIN_PIN11_Msk, ///< Enable retention for pin 11.
315 NRF_GPIO_RETAIN_PIN12_MASK = GPIO_RETAIN_PIN12_Msk, ///< Enable retention for pin 12.
316 NRF_GPIO_RETAIN_PIN13_MASK = GPIO_RETAIN_PIN13_Msk, ///< Enable retention for pin 13.
317 NRF_GPIO_RETAIN_PIN14_MASK = GPIO_RETAIN_PIN14_Msk, ///< Enable retention for pin 14.
318 NRF_GPIO_RETAIN_PIN15_MASK = GPIO_RETAIN_PIN15_Msk, ///< Enable retention for pin 15.
319 NRF_GPIO_RETAIN_PIN16_MASK = GPIO_RETAIN_PIN16_Msk, ///< Enable retention for pin 16.
320 NRF_GPIO_RETAIN_PIN17_MASK = GPIO_RETAIN_PIN17_Msk, ///< Enable retention for pin 17.
321 NRF_GPIO_RETAIN_PIN18_MASK = GPIO_RETAIN_PIN18_Msk, ///< Enable retention for pin 18.
322 NRF_GPIO_RETAIN_PIN19_MASK = GPIO_RETAIN_PIN19_Msk, ///< Enable retention for pin 19.
323 NRF_GPIO_RETAIN_PIN20_MASK = GPIO_RETAIN_PIN20_Msk, ///< Enable retention for pin 20.
324 NRF_GPIO_RETAIN_PIN21_MASK = GPIO_RETAIN_PIN21_Msk, ///< Enable retention for pin 21.
325 NRF_GPIO_RETAIN_PIN22_MASK = GPIO_RETAIN_PIN22_Msk, ///< Enable retention for pin 22.
326 NRF_GPIO_RETAIN_PIN23_MASK = GPIO_RETAIN_PIN23_Msk, ///< Enable retention for pin 23.
327 NRF_GPIO_RETAIN_PIN24_MASK = GPIO_RETAIN_PIN24_Msk, ///< Enable retention for pin 24.
328 NRF_GPIO_RETAIN_PIN25_MASK = GPIO_RETAIN_PIN25_Msk, ///< Enable retention for pin 25.
329 NRF_GPIO_RETAIN_PIN26_MASK = GPIO_RETAIN_PIN26_Msk, ///< Enable retention for pin 26.
330 NRF_GPIO_RETAIN_PIN27_MASK = GPIO_RETAIN_PIN27_Msk, ///< Enable retention for pin 27.
331 NRF_GPIO_RETAIN_PIN28_MASK = GPIO_RETAIN_PIN28_Msk, ///< Enable retention for pin 28.
332 NRF_GPIO_RETAIN_PIN29_MASK = GPIO_RETAIN_PIN29_Msk, ///< Enable retention for pin 29.
333 NRF_GPIO_RETAIN_PIN30_MASK = GPIO_RETAIN_PIN30_Msk, ///< Enable retention for pin 30.
334 NRF_GPIO_RETAIN_PIN31_MASK = GPIO_RETAIN_PIN31_Msk, ///< Enable retention for pin 31.
335 #endif
336 #if defined(NRF_GPIO_RETAIN_EXT)
337 NRF_GPIO_RETAIN_EXT
338 #endif
339 } nrf_gpio_retain_mask_t;
340 #endif
341
342 /**
343 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
344 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
345 *
346 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
347 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
348 *
349 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
350 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
351 */
352 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
353
354 /**
355 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
356 * This function can be used to configure pin range as simple input.
357 *
358 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
359 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
360 *
361 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured.
362 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured.
363 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
364 */
365 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
366 uint32_t pin_range_end,
367 nrf_gpio_pin_pull_t pull_config);
368
369 /**
370 * @brief Pin configuration function.
371 *
372 * The main pin configuration function.
373 * This function allows to set any aspect in PIN_CNF register.
374 *
375 * @param pin_number Specifies the pin number.
376 * @param dir Pin direction.
377 * @param input Connect or disconnect the input buffer.
378 * @param pull Pull configuration.
379 * @param drive Drive configuration.
380 * @param sense Pin sensing mechanism.
381 */
382 NRF_STATIC_INLINE void nrf_gpio_cfg(
383 uint32_t pin_number,
384 nrf_gpio_pin_dir_t dir,
385 nrf_gpio_pin_input_t input,
386 nrf_gpio_pin_pull_t pull,
387 nrf_gpio_pin_drive_t drive,
388 nrf_gpio_pin_sense_t sense);
389
390 /**
391 * @brief Function for reconfiguring pin.
392 *
393 * @note This function selectively updates fields in PIN_CNF register. Reconfiguration
394 * is performed in single register write. Fields for which new configuration is
395 * not provided remain unchanged.
396 *
397 * @param pin_number Specifies the pin number.
398 * @param p_dir Pin direction. If NULL, previous setting remains.
399 * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains.
400 * @param p_pull Pull configuration. If NULL, previous setting remains.
401 * @param p_drive Drive configuration. If NULL, previous setting remains.
402 * @param p_sense Pin sensing mechanism. If NULL, previous setting remains.
403 */
404 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
405 const nrf_gpio_pin_dir_t * p_dir,
406 const nrf_gpio_pin_input_t * p_input,
407 const nrf_gpio_pin_pull_t * p_pull,
408 const nrf_gpio_pin_drive_t * p_drive,
409 const nrf_gpio_pin_sense_t * p_sense);
410
411 /**
412 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
413 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
414 *
415 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
416 *
417 * @param pin_number Specifies the pin number.
418 */
419 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
420
421 /**
422 * @brief Function for configuring the given GPIO pin number from a given port as output, hiding inner details.
423 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
424 *
425 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
426 *
427 * @param p_reg Pointer to the structure of registers of the peripheral.
428 * @param pin_number Specifies the relative pin number.
429 */
430 NRF_STATIC_INLINE void nrf_gpio_port_pin_output_set(NRF_GPIO_Type * p_reg, uint32_t pin_number);
431
432 /**
433 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
434 * This function can be used to configure a pin as simple input.
435 *
436 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
437 *
438 * @param pin_number Specifies the pin number.
439 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
440 */
441 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
442
443 /**
444 * @brief Function for configuring the given GPIO pin number from a given port as input, hiding inner details.
445 * This function can be used to configure a pin as simple input.
446 *
447 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
448 *
449 * @param p_reg Pointer to the structure of registers of the peripheral.
450 * @param pin_number Specifies the relative pin number.
451 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
452 */
453 NRF_STATIC_INLINE void nrf_gpio_port_pin_input_set(NRF_GPIO_Type * p_reg,
454 uint32_t pin_number,
455 nrf_gpio_pin_pull_t pull_config);
456
457 /**
458 * @brief Function for resetting pin configuration to its default state.
459 *
460 * @param pin_number Specifies the pin number.
461 */
462 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
463
464 /**
465 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
466 *
467 * @param pin_number Specifies the pin number.
468 *
469 */
470 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
471
472 /**
473 * @brief Function for disconnecting input for the given GPIO.
474 *
475 * @param pin_number Specifies the pin number.
476 */
477 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
478
479 /**
480 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
481 * This function can be used to configure pin range as simple input.
482 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
483 *
484 * @param pin_number Specifies the pin number.
485 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
486 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
487 */
488 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
489 nrf_gpio_pin_pull_t pull_config,
490 nrf_gpio_pin_sense_t sense_config);
491
492 /**
493 * @brief Function for configuring sense level for the given GPIO.
494 *
495 * @param pin_number Specifies the pin number.
496 * @param sense_config Sense configuration.
497 */
498 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
499 nrf_gpio_pin_sense_t sense_config);
500
501 /**
502 * @brief Function for setting the direction for a GPIO pin.
503 *
504 * @param pin_number Specifies the pin number for which to set the direction.
505 * @param direction Specifies the direction.
506 */
507 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
508
509 /**
510 * @brief Function for setting a GPIO pin.
511 *
512 * @param pin_number Specifies the pin number to be set.
513 */
514 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
515
516 /**
517 * @brief Function for clearing a GPIO pin.
518 *
519 * @param pin_number Specifies the pin number to clear.
520 */
521 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
522
523 /**
524 * @brief Function for toggling a GPIO pin.
525 *
526 * @param pin_number Specifies the pin number to toggle.
527 */
528 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
529
530 /**
531 * @brief Function for writing a value to a GPIO pin.
532 *
533 * @param pin_number Specifies the pin number to write.
534 * @param value Specifies the value to be written to the pin.
535 * @arg 0 Clears the pin.
536 * @arg >=1 Sets the pin.
537 */
538 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
539
540 /**
541 * @brief Function for writing a value to a GPIO pin of a given port.
542 *
543 * @param p_reg Pointer to the structure of registers of the peripheral.
544 * @param pin_number Specifies the relative pin number to write.
545 * @param value Specifies the value to be written to the pin.
546 * @arg 0 Clears the pin.
547 * @arg >=1 Sets the pin.
548 */
549 NRF_STATIC_INLINE void nrf_gpio_port_pin_write(NRF_GPIO_Type * p_reg,
550 uint32_t pin_number,
551 uint32_t value);
552
553 /**
554 * @brief Function for reading the input level of a GPIO pin.
555 *
556 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
557 *
558 * @param pin_number Specifies the pin number to read.
559 *
560 * @return 0 if the pin input level is low. Positive value if the pin is high.
561 */
562 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
563
564 /**
565 * @brief Function for reading the input level of a GPIO pin of a given port.
566 *
567 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
568 *
569 * @param p_reg Pointer to the structure of registers of the peripheral.
570 * @param pin_number Specifies the relative pin number to read.
571 *
572 * @return False if the pin input level is low. True if the pin is high.
573 */
574 NRF_STATIC_INLINE bool nrf_gpio_port_pin_read(NRF_GPIO_Type const * p_reg, uint32_t pin_number);
575
576 /**
577 * @brief Function for reading the output level of a GPIO pin.
578 *
579 * @param pin_number Specifies the pin number to read.
580 *
581 * @return 0 if the pin output level is low. Positive value if pin output is high.
582 */
583 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
584
585 /**
586 * @brief Function for reading the sense configuration of a GPIO pin.
587 *
588 * @param pin_number Specifies the pin number to read.
589 *
590 * @return Sense configuration.
591 */
592 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
593
594 /**
595 * @brief Function for reading the direction configuration of a GPIO pin.
596 *
597 * @param pin_number Specifies the pin number to read.
598 *
599 * @return Direction configuration.
600 */
601 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
602
603 /**
604 * @brief Function for reading the status of GPIO pin input buffer.
605 *
606 * @param pin_number Pin number to be read.
607 *
608 * @retval Input buffer configuration.
609 */
610 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
611
612 /**
613 * @brief Function for reading the pull configuration of a GPIO pin.
614 *
615 * @param pin_number Specifies the pin number to read.
616 *
617 * @retval Pull configuration.
618 */
619 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
620
621 /**
622 * @brief Function for setting output direction on the selected pins on the given port.
623 *
624 * @param p_reg Pointer to the structure of registers of the peripheral.
625 * @param out_mask Mask specifying the pins to set as output.
626 */
627 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
628
629 /**
630 * @brief Function for setting input direction on selected pins on a given port.
631 *
632 * @param p_reg Pointer to the structure of registers of the peripheral.
633 * @param in_mask Mask that specifies the pins to be set as input.
634 */
635 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
636
637 /**
638 * @brief Function for writing the direction configuration of the GPIO pins in the given port.
639 *
640 * @warning This register is retained when retention is enabled.
641 *
642 * @param p_reg Pointer to the structure of registers of the peripheral.
643 * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
644 */
645 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
646
647 /**
648 * @brief Function for reading the direction configuration of a GPIO port.
649 *
650 * @warning This register is retained when retention is enabled.
651 *
652 * @param p_reg Pointer to the structure of registers of the peripheral.
653 *
654 * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
655 */
656 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
657
658 /**
659 * @brief Function for reading the input signals of the GPIO pins on the given port.
660 *
661 * @param p_reg Pointer to the peripheral registers structure.
662 *
663 * @return Port input values.
664 */
665 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
666
667 /**
668 * @brief Function for reading the output signals of the GPIO pins on the given port.
669 *
670 * @warning This register is retained when retention is enabled.
671 *
672 * @param p_reg Pointer to the peripheral registers structure.
673 *
674 * @return Port output values.
675 */
676 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
677
678 /**
679 * @brief Function for writing the GPIO pins output on a given port.
680 *
681 * @warning This register is retained when retention is enabled.
682 *
683 * @param p_reg Pointer to the structure of registers of the peripheral.
684 * @param value Output port mask.
685 */
686 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
687
688 /**
689 * @brief Function for setting high level on selected the GPIO pins on the given port.
690 *
691 * @param p_reg Pointer to the structure of registers of the peripheral.
692 * @param set_mask Mask with pins to be set as logical high level.
693 */
694 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
695
696 /**
697 * @brief Function for setting low level on selected the GPIO pins on the given port.
698 *
699 * @param p_reg Pointer to the structure of registers of the peripheral.
700 * @param clr_mask Mask with pins to be set as logical low level.
701 */
702 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
703
704 /**
705 * @brief Function for reading pin state of multiple consecutive ports.
706 *
707 * @param start_port Index of the first port to read.
708 * @param length Number of ports to read.
709 * @param p_masks Pointer to output array where port states will be stored.
710 */
711 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
712 uint32_t length,
713 uint32_t * p_masks);
714
715 #if NRF_GPIO_HAS_PORT_IMPEDANCE
716 /**
717 * @brief Function for setting the impedance matching of the pins on the given port.
718 *
719 * @note Each bit sets certain impedance and have them in parallel when more than one bit is set.
720 * High impedance is set for the pin when all bits are disabled.
721 * When all bits are enabled, the resulting impedance is about 25 Ohm.
722 *
723 * @warning This register is retained when retention is enabled.
724 *
725 * @param p_reg Pointer to the structure of registers of the peripheral.
726 * @param mask Mask of impedances to be set, created using @ref nrf_gpio_port_impedance_mask_t.
727 */
728 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask);
729
730 /**
731 * @brief Function for geting the impedance matching of the pins on the given port.
732 *
733 * @warning This register is retained when retention is enabled.
734 *
735 * @param p_reg Pointer to the structure of registers of the peripheral.
736 *
737 * @return Mask of impedances set, created using @ref nrf_gpio_port_impedance_mask_t.
738 */
739 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg);
740 #endif
741
742 #if NRF_GPIO_HAS_RETENTION
743 /**
744 * @brief Function for setting the retention of the registers.
745 *
746 * @param p_reg Pointer to the structure of registers of the peripheral.
747 * @param mask Mask of retention domains to be enabled, created using @ref nrf_gpio_retain_mask_t.
748 */
749 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask);
750
751 /**
752 * @brief Function for geting the retention setting of the registers.
753 *
754 * @param p_reg Pointer to the structure of registers of the peripheral.
755 *
756 * @return Mask of retention domains set, created using @ref nrf_gpio_retain_mask_t.
757 */
758 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg);
759
760 /**
761 * @brief Function for checking the retention setting of a pin.
762 *
763 * @param pin_number Pin number.
764 *
765 * @retval true If pin is retained.
766 * @retval false If pin is not retained.
767 */
768 NRF_STATIC_INLINE bool nrf_gpio_pin_retain_check(uint32_t pin_number);
769 #endif
770
771 #if NRF_GPIO_HAS_RETENTION_SETCLEAR
772 /**
773 * @brief Function for enabling the retention of the registers.
774 *
775 * @param p_reg Pointer to the structure of registers of the peripheral.
776 * @param mask Mask of pins to have retention enabled, created using @ref nrf_gpio_retain_mask_t.
777 */
778 NRF_STATIC_INLINE void nrf_gpio_port_retain_enable(NRF_GPIO_Type * p_reg, uint32_t mask);
779
780 /**
781 * @brief Function for disabling the retention of the registers.
782 *
783 * @param p_reg Pointer to the structure of registers of the peripheral.
784 * @param mask Mask of pins to have retention be disabled, created using @ref nrf_gpio_retain_mask_t.
785 */
786 NRF_STATIC_INLINE void nrf_gpio_port_retain_disable(NRF_GPIO_Type * p_reg, uint32_t mask);
787
788 /**
789 * @brief Function for enabling the retention of a pin.
790 *
791 * @param pin_number Pin number.
792 */
793 NRF_STATIC_INLINE void nrf_gpio_pin_retain_enable(uint32_t pin_number);
794
795 /**
796 * @brief Function for disabling the retention of a pin.
797 *
798 * @param pin_number Pin number.
799 */
800 NRF_STATIC_INLINE void nrf_gpio_pin_retain_disable(uint32_t pin_number);
801 #endif
802
803
804 #if NRF_GPIO_HAS_DETECT_MODE
805 /**
806 * @brief Function for setting the latched detect behaviour.
807 *
808 * @param p_reg Pointer to the structure of registers of the peripheral.
809 * @param enable True if the latched LDETECT behaviour is to be used, false if DETECT is to be
810 * directly connected to PIN DETECT signals.
811 */
812 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable);
813
814 /**
815 * @brief Function for checking the latched detect behaviour.
816 *
817 * @param p_reg Pointer to the structure of registers of the peripheral.
818 *
819 * @retval true Latched LDETECT behaviour is used.
820 * @retval false DETECT is directly connected to PIN DETECT signals.
821 */
822 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg);
823 #endif
824
825 #if defined(NRF_GPIO_LATCH_PRESENT)
826 /**
827 * @brief Function for reading latch state of multiple consecutive ports.
828 *
829 * @warning This register is retained when retention is enabled.
830 *
831 * @param start_port Index of the first port to read.
832 * @param length Number of ports to read.
833 * @param p_masks Pointer to output array where latch states will be stored.
834 */
835 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
836 uint32_t length,
837 uint32_t * p_masks);
838
839 /**
840 * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
841 *
842 * @warning This register is retained when retention is enabled.
843 *
844 * @param start_port Index of the first port to read and clear.
845 * @param length Number of ports to read and clear.
846 * @param p_masks Pointer to output array where latch states will be stored.
847 */
848 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
849 uint32_t length,
850 uint32_t * p_masks);
851
852 /**
853 * @brief Function for reading latch state of single pin.
854 *
855 * @warning This register is retained when retention is enabled.
856 *
857 * @param pin_number Pin number.
858 *
859 * @return 0 if latch is not set. Positive value otherwise.
860 */
861 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
862
863 /**
864 * @brief Function for clearing latch state of a single pin.
865 *
866 * @warning This register is retained when retention is enabled.
867 *
868 * @param pin_number Pin number.
869 */
870 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
871 #endif // defined(NRF_GPIO_LATCH_PRESENT)
872
873 #if NRF_GPIO_HAS_SEL
874 /**
875 * @brief Function for selecting the MCU or Subsystem to control a GPIO pin.
876 *
877 * @warning This register is retained when retention is enabled.
878 *
879 * @param pin_number Pin_number.
880 * @param ctrl MCU/Subsystem to control the pin.
881 */
882 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl);
883 #endif
884
885 #if NRF_GPIO_HAS_CLOCKPIN
886 /**
887 * @brief Function for setting whether the clock should be enabled for the specified GPIO pin.
888 *
889 * @warning This register is retained when retention is enabled.
890 *
891 * @param[in] pin_number Pin number.
892 * @param[in] enable True if clock is to be enabled, false otherwise.
893 */
894 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable);
895
896 /**
897 * @brief Function for getting the clock enable setting for the specified GPIO pin.
898 *
899 * @warning This register is retained when retention is enabled.
900 *
901 * @param[in] pin_number Pin number.
902 *
903 * @retval true Clock is enabled.
904 * @retval false Clock is disabled.
905 */
906 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number);
907 #endif
908
909 /**
910 * @brief Function for checking if provided pin is present on the MCU.
911 *
912 * @param[in] pin_number Number of the pin to be checked.
913 *
914 * @retval true Pin is present.
915 * @retval false Pin is not present.
916 */
917 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
918
919 /**
920 * @brief Function for extracting port number and the relative pin number
921 * from the absolute pin number.
922 *
923 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
924 * that is relative to the port.
925 *
926 * @return Port number.
927 */
928 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
929
930 /**
931 * @brief Function for extracting port and the relative pin number from the absolute pin number.
932 *
933 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
934 * that is relative to the port.
935 *
936 * @return Pointer to port register set.
937 */
938 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin);
939
940 #ifndef NRF_DECLARE_ONLY
941
nrf_gpio_pin_port_decode(uint32_t * p_pin)942 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
943 {
944 NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
945
946 NRF_GPIO_Type * p_port = NULL;
947
948 switch (nrf_gpio_pin_port_number_extract(p_pin))
949 {
950 NRF_INTERNAL_GPIO_PORT_EXTRACT(p_port);
951
952 default:
953 NRFX_ASSERT(0);
954 }
955 return p_port;
956 }
957
958
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)959 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
960 {
961 for (; pin_range_start <= pin_range_end; pin_range_start++)
962 {
963 nrf_gpio_cfg_output(pin_range_start);
964 }
965 }
966
967
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)968 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
969 uint32_t pin_range_end,
970 nrf_gpio_pin_pull_t pull_config)
971 {
972 for (; pin_range_start <= pin_range_end; pin_range_start++)
973 {
974 nrf_gpio_cfg_input(pin_range_start, pull_config);
975 }
976 }
977
978
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)979 NRF_STATIC_INLINE void nrf_gpio_cfg(
980 uint32_t pin_number,
981 nrf_gpio_pin_dir_t dir,
982 nrf_gpio_pin_input_t input,
983 nrf_gpio_pin_pull_t pull,
984 nrf_gpio_pin_drive_t drive,
985 nrf_gpio_pin_sense_t sense)
986 {
987 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
988 uint32_t cnf = reg->PIN_CNF[pin_number];
989
990 uint32_t to_update = GPIO_PIN_CNF_DIR_Msk |
991 GPIO_PIN_CNF_INPUT_Msk |
992 GPIO_PIN_CNF_PULL_Msk |
993 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
994 GPIO_PIN_CNF_DRIVE_Msk |
995 #else
996 GPIO_PIN_CNF_DRIVE0_Msk |
997 GPIO_PIN_CNF_DRIVE1_Msk |
998 #endif
999 GPIO_PIN_CNF_SENSE_Msk;
1000
1001 /* Clear fields that will be updated. */
1002 cnf &= ~to_update;
1003 cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
1004 ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
1005 ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
1006 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
1007 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
1008 #else
1009 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE0_Pos) |
1010 #endif
1011 ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
1012
1013 reg->PIN_CNF[pin_number] = cnf;
1014 }
1015
nrf_gpio_reconfigure(uint32_t pin_number,const nrf_gpio_pin_dir_t * p_dir,const nrf_gpio_pin_input_t * p_input,const nrf_gpio_pin_pull_t * p_pull,const nrf_gpio_pin_drive_t * p_drive,const nrf_gpio_pin_sense_t * p_sense)1016 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
1017 const nrf_gpio_pin_dir_t * p_dir,
1018 const nrf_gpio_pin_input_t * p_input,
1019 const nrf_gpio_pin_pull_t * p_pull,
1020 const nrf_gpio_pin_drive_t * p_drive,
1021 const nrf_gpio_pin_sense_t * p_sense)
1022 {
1023 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1024 uint32_t cnf = reg->PIN_CNF[pin_number];
1025 uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) |
1026 (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
1027 (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) |
1028 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
1029 (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
1030 #else
1031 (p_drive ? (GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk) : 0) |
1032 #endif
1033 (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
1034
1035 /* Clear fields that will be updated. */
1036 cnf &= ~to_update;
1037 cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) |
1038 ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
1039 ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) |
1040 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
1041 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
1042 #else
1043 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE0_Pos) |
1044 #endif
1045 ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
1046
1047 reg->PIN_CNF[pin_number] = cnf;
1048 }
1049
nrf_gpio_cfg_output(uint32_t pin_number)1050 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
1051 {
1052 nrf_gpio_cfg(
1053 pin_number,
1054 NRF_GPIO_PIN_DIR_OUTPUT,
1055 NRF_GPIO_PIN_INPUT_DISCONNECT,
1056 NRF_GPIO_PIN_NOPULL,
1057 NRF_GPIO_PIN_S0S1,
1058 NRF_GPIO_PIN_NOSENSE);
1059 }
1060
nrf_gpio_port_pin_output_set(NRF_GPIO_Type * p_reg,uint32_t pin_number)1061 NRF_STATIC_INLINE void nrf_gpio_port_pin_output_set(NRF_GPIO_Type * p_reg, uint32_t pin_number)
1062 {
1063 uint32_t cnf = ((uint32_t)NRF_GPIO_PIN_DIR_OUTPUT << GPIO_PIN_CNF_DIR_Pos) |
1064 ((uint32_t)NRF_GPIO_PIN_INPUT_DISCONNECT << GPIO_PIN_CNF_INPUT_Pos) |
1065 ((uint32_t)NRF_GPIO_PIN_NOPULL << GPIO_PIN_CNF_PULL_Pos) |
1066 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
1067 ((uint32_t)NRF_GPIO_PIN_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
1068 #else
1069 ((uint32_t)NRF_GPIO_PIN_S0S1 << GPIO_PIN_CNF_DRIVE0_Pos) |
1070 #endif
1071 ((uint32_t)NRF_GPIO_PIN_NOSENSE << GPIO_PIN_CNF_SENSE_Pos);
1072 p_reg->PIN_CNF[pin_number] = cnf;
1073 }
1074
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)1075 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
1076 {
1077 nrf_gpio_cfg(
1078 pin_number,
1079 NRF_GPIO_PIN_DIR_INPUT,
1080 NRF_GPIO_PIN_INPUT_CONNECT,
1081 pull_config,
1082 NRF_GPIO_PIN_S0S1,
1083 NRF_GPIO_PIN_NOSENSE);
1084 }
1085
nrf_gpio_port_pin_input_set(NRF_GPIO_Type * p_reg,uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)1086 NRF_STATIC_INLINE void nrf_gpio_port_pin_input_set(NRF_GPIO_Type * p_reg,
1087 uint32_t pin_number,
1088 nrf_gpio_pin_pull_t pull_config)
1089 {
1090 uint32_t cnf = ((uint32_t)NRF_GPIO_PIN_DIR_INPUT << GPIO_PIN_CNF_DIR_Pos) |
1091 ((uint32_t)NRF_GPIO_PIN_INPUT_CONNECT << GPIO_PIN_CNF_INPUT_Pos) |
1092 ((uint32_t)pull_config << GPIO_PIN_CNF_PULL_Pos) |
1093 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
1094 ((uint32_t)NRF_GPIO_PIN_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) |
1095 #else
1096 ((uint32_t)NRF_GPIO_PIN_S0S1 << GPIO_PIN_CNF_DRIVE0_Pos) |
1097 #endif
1098 ((uint32_t)NRF_GPIO_PIN_NOSENSE << GPIO_PIN_CNF_SENSE_Pos);
1099 p_reg->PIN_CNF[pin_number] = cnf;
1100 }
1101
1102
nrf_gpio_cfg_default(uint32_t pin_number)1103 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
1104 {
1105 nrf_gpio_cfg(
1106 pin_number,
1107 NRF_GPIO_PIN_DIR_INPUT,
1108 NRF_GPIO_PIN_INPUT_DISCONNECT,
1109 NRF_GPIO_PIN_NOPULL,
1110 NRF_GPIO_PIN_S0S1,
1111 NRF_GPIO_PIN_NOSENSE);
1112 }
1113
1114
nrf_gpio_cfg_watcher(uint32_t pin_number)1115 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
1116 {
1117 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT;
1118
1119 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
1120 }
1121
1122
nrf_gpio_input_disconnect(uint32_t pin_number)1123 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
1124 {
1125 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT;
1126
1127 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
1128 }
1129
1130
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)1131 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
1132 nrf_gpio_pin_pull_t pull_config,
1133 nrf_gpio_pin_sense_t sense_config)
1134 {
1135 nrf_gpio_cfg(
1136 pin_number,
1137 NRF_GPIO_PIN_DIR_INPUT,
1138 NRF_GPIO_PIN_INPUT_CONNECT,
1139 pull_config,
1140 NRF_GPIO_PIN_S0S1,
1141 sense_config);
1142 }
1143
1144
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)1145 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
1146 nrf_gpio_pin_sense_t sense_config)
1147 {
1148 nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
1149 }
1150
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)1151 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
1152 {
1153 if (direction == NRF_GPIO_PIN_DIR_INPUT)
1154 {
1155 nrf_gpio_cfg(
1156 pin_number,
1157 NRF_GPIO_PIN_DIR_INPUT,
1158 NRF_GPIO_PIN_INPUT_CONNECT,
1159 NRF_GPIO_PIN_NOPULL,
1160 NRF_GPIO_PIN_S0S1,
1161 NRF_GPIO_PIN_NOSENSE);
1162 }
1163 else
1164 {
1165 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1166 reg->DIRSET = (1UL << pin_number);
1167 }
1168 }
1169
1170
nrf_gpio_pin_set(uint32_t pin_number)1171 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
1172 {
1173 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1174
1175 nrf_gpio_port_out_set(reg, 1UL << pin_number);
1176 }
1177
1178
nrf_gpio_pin_clear(uint32_t pin_number)1179 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
1180 {
1181 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1182
1183 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
1184 }
1185
1186
nrf_gpio_pin_toggle(uint32_t pin_number)1187 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
1188 {
1189 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1190 uint32_t pins_state = reg->OUT;
1191
1192 reg->OUTSET = (~pins_state & (1UL << pin_number));
1193 reg->OUTCLR = (pins_state & (1UL << pin_number));
1194 }
1195
1196
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)1197 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
1198 {
1199 if (value == 0)
1200 {
1201 nrf_gpio_pin_clear(pin_number);
1202 }
1203 else
1204 {
1205 nrf_gpio_pin_set(pin_number);
1206 }
1207 }
1208
nrf_gpio_port_pin_write(NRF_GPIO_Type * p_reg,uint32_t pin_number,uint32_t value)1209 NRF_STATIC_INLINE void nrf_gpio_port_pin_write(NRF_GPIO_Type * p_reg,
1210 uint32_t pin_number,
1211 uint32_t value)
1212 {
1213 if (value == 0)
1214 {
1215 nrf_gpio_port_out_clear(p_reg, 1UL << pin_number);
1216 }
1217 else
1218 {
1219 nrf_gpio_port_out_set(p_reg, 1UL << pin_number);
1220 }
1221 }
1222
1223
nrf_gpio_pin_read(uint32_t pin_number)1224 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
1225 {
1226 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1227
1228 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
1229 }
1230
nrf_gpio_port_pin_read(NRF_GPIO_Type const * p_reg,uint32_t pin_number)1231 NRF_STATIC_INLINE bool nrf_gpio_port_pin_read(NRF_GPIO_Type const * p_reg, uint32_t pin_number)
1232 {
1233 return ((nrf_gpio_port_in_read(p_reg) >> pin_number) & 1UL);
1234 }
1235
nrf_gpio_pin_out_read(uint32_t pin_number)1236 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
1237 {
1238 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1239
1240 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
1241 }
1242
1243
nrf_gpio_pin_sense_get(uint32_t pin_number)1244 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
1245 {
1246 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1247
1248 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
1249 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
1250 }
1251
1252
nrf_gpio_pin_dir_get(uint32_t pin_number)1253 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
1254 {
1255 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1256
1257 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
1258 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
1259 }
1260
nrf_gpio_pin_input_get(uint32_t pin_number)1261 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
1262 {
1263 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1264
1265 return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
1266 GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
1267 }
1268
nrf_gpio_pin_pull_get(uint32_t pin_number)1269 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
1270 {
1271 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1272
1273 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
1274 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
1275 }
1276
1277
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)1278 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
1279 {
1280 p_reg->DIRSET = out_mask;
1281 }
1282
1283
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)1284 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
1285 {
1286 p_reg->DIRCLR = in_mask;
1287 }
1288
1289
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)1290 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
1291 {
1292 p_reg->DIR = value;
1293 }
1294
1295
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)1296 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
1297 {
1298 return p_reg->DIR;
1299 }
1300
1301
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)1302 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
1303 {
1304 return p_reg->IN;
1305 }
1306
1307
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)1308 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
1309 {
1310 return p_reg->OUT;
1311 }
1312
1313
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)1314 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
1315 {
1316 p_reg->OUT = value;
1317 }
1318
1319
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)1320 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
1321 {
1322 p_reg->OUTSET = set_mask;
1323 }
1324
1325
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)1326 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
1327 {
1328 p_reg->OUTCLR = clr_mask;
1329 }
1330
1331
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1332 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
1333 uint32_t length,
1334 uint32_t * p_masks)
1335 {
1336 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1337
1338 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
1339 uint32_t i;
1340
1341 for (i = start_port; i < (start_port + length); i++)
1342 {
1343 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
1344 p_masks++;
1345 }
1346 }
1347
1348 #if NRF_GPIO_HAS_PORT_IMPEDANCE
nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg,uint32_t mask)1349 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1350 {
1351 p_reg->PORTCNF.DRIVECTRL = ((p_reg->PORTCNF.DRIVECTRL & ~NRF_GPIO_PORT_IMPEDANCE_ALL_MASK) |
1352 (mask & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK));
1353 }
1354
nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)1355 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)
1356 {
1357 return p_reg->PORTCNF.DRIVECTRL & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK;
1358 }
1359 #endif
1360
1361 #if NRF_GPIO_HAS_RETENTION
nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg,uint32_t mask)1362 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1363 {
1364 p_reg->RETAIN = mask;
1365 }
1366
nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)1367 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)
1368 {
1369 return p_reg->RETAIN;
1370 }
1371
nrf_gpio_pin_retain_check(uint32_t pin_number)1372 NRF_STATIC_INLINE bool nrf_gpio_pin_retain_check(uint32_t pin_number)
1373 {
1374 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1375
1376 return (nrf_gpio_port_retain_get(reg) & (1UL << pin_number)) != 0U;
1377 }
1378 #endif
1379
1380 #if NRF_GPIO_HAS_RETENTION_SETCLEAR
nrf_gpio_port_retain_enable(NRF_GPIO_Type * p_reg,uint32_t mask)1381 NRF_STATIC_INLINE void nrf_gpio_port_retain_enable(NRF_GPIO_Type * p_reg, uint32_t mask)
1382 {
1383 p_reg->RETAINSET = mask;
1384 }
1385
nrf_gpio_port_retain_disable(NRF_GPIO_Type * p_reg,uint32_t mask)1386 NRF_STATIC_INLINE void nrf_gpio_port_retain_disable(NRF_GPIO_Type * p_reg, uint32_t mask)
1387 {
1388 p_reg->RETAINCLR = mask;
1389 }
1390
nrf_gpio_pin_retain_enable(uint32_t pin_number)1391 NRF_STATIC_INLINE void nrf_gpio_pin_retain_enable(uint32_t pin_number)
1392 {
1393 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1394
1395 nrf_gpio_port_retain_enable(reg, 1UL << pin_number);
1396 }
1397
nrf_gpio_pin_retain_disable(uint32_t pin_number)1398 NRF_STATIC_INLINE void nrf_gpio_pin_retain_disable(uint32_t pin_number)
1399 {
1400 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1401
1402 nrf_gpio_port_retain_disable(reg, 1UL << pin_number);
1403 }
1404 #endif
1405
1406 #if NRF_GPIO_HAS_DETECT_MODE
nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg,bool enable)1407 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable)
1408 {
1409 p_reg->DETECTMODE = (enable ? GPIO_DETECTMODE_DETECTMODE_LDETECT :
1410 GPIO_DETECTMODE_DETECTMODE_Default);
1411 }
1412
nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)1413 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)
1414 {
1415 return (p_reg->DETECTMODE == GPIO_DETECTMODE_DETECTMODE_LDETECT);
1416 }
1417 #endif
1418
1419 #if defined(NRF_GPIO_LATCH_PRESENT)
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1420 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
1421 uint32_t length,
1422 uint32_t * p_masks)
1423 {
1424 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1425 uint32_t i;
1426
1427 for (i = start_port; i < (start_port + length); i++)
1428 {
1429 *p_masks = gpio_regs[i]->LATCH;
1430 p_masks++;
1431 }
1432 }
1433
nrf_gpio_latches_read_and_clear(uint32_t start_port,uint32_t length,uint32_t * p_masks)1434 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
1435 uint32_t length,
1436 uint32_t * p_masks)
1437 {
1438 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1439 uint32_t i;
1440
1441 for (i = start_port; i < (start_port + length); i++)
1442 {
1443 *p_masks = gpio_regs[i]->LATCH;
1444
1445 // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
1446 gpio_regs[i]->LATCH = *p_masks;
1447
1448 p_masks++;
1449 }
1450 }
1451
nrf_gpio_pin_latch_get(uint32_t pin_number)1452 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
1453 {
1454 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1455
1456 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
1457 }
1458
1459
nrf_gpio_pin_latch_clear(uint32_t pin_number)1460 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
1461 {
1462 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1463
1464 reg->LATCH = (1 << pin_number);
1465 }
1466 #endif // defined(NRF_GPIO_LATCH_PRESENT)
1467
1468 #if NRF_GPIO_HAS_SEL
nrf_gpio_pin_control_select(uint32_t pin_number,nrf_gpio_pin_sel_t ctrl)1469 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
1470 {
1471 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1472 #if defined(GPIO_PIN_CNF_MCUSEL_Msk)
1473 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
1474 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
1475 #else
1476 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CTRLSEL_Msk;
1477 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_CTRLSEL_Pos);
1478 #endif
1479 }
1480 #endif // NRF_GPIO_HAS_SEL
1481
1482 #if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(uint32_t pin_number,bool enable)1483 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable)
1484 {
1485 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1486
1487 reg->PIN_CNF[pin_number] = ((reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CLOCKPIN_Msk) |
1488 ((enable ? GPIO_PIN_CNF_CLOCKPIN_Enabled :
1489 GPIO_PIN_CNF_CLOCKPIN_Disabled) << GPIO_PIN_CNF_CLOCKPIN_Pos));
1490 }
1491
nrf_gpio_pin_clock_check(uint32_t pin_number)1492 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number)
1493 {
1494 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1495
1496 return (((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_CLOCKPIN_Msk) >> GPIO_PIN_CNF_CLOCKPIN_Pos)
1497 == GPIO_PIN_CNF_CLOCKPIN_Enabled);
1498 }
1499 #endif
1500
nrf_gpio_pin_present_check(uint32_t pin_number)1501 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
1502 {
1503 uint32_t port = pin_number >> 5;
1504 uint32_t mask = 0;
1505
1506 switch (port)
1507 {
1508 NRF_INTERNAL_GPIO_PORT_MASK_SET(mask);
1509
1510 default:
1511 return false;
1512 }
1513
1514 #ifdef P0_FEATURE_PINS_PRESENT
1515 #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1516 /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
1517 * on the nRF52833 DK:
1518 * - P0.11 - Button 1
1519 * - P0.12 - Button 2
1520 * - P0.13 - LED 1
1521 * - P0.24 - Button 3
1522 * - P0.25 - Button 4
1523 */
1524 mask |= 0x03003800;
1525 #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1526 #endif
1527
1528 pin_number &= 0x1F;
1529
1530 return (mask & (1UL << pin_number)) ? true : false;
1531 }
1532
nrf_gpio_pin_port_number_extract(uint32_t * p_pin)1533 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
1534 {
1535 uint32_t pin_number = *p_pin;
1536 *p_pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
1537
1538 return NRF_PIN_NUMBER_TO_PORT(pin_number);
1539 }
1540
1541 #endif // NRF_DECLARE_ONLY
1542
1543 /** @} */
1544
1545 #ifdef __cplusplus
1546 }
1547 #endif
1548
1549 #endif // NRF_GPIO_H__
1550
