1 /* 2 * Copyright (c) 2016 - 2025, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, this 11 * list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived from this 19 * software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef NRFX_QSPI_H__ 35 #define NRFX_QSPI_H__ 36 37 #include <nrfx.h> 38 #include <hal/nrf_qspi.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /** 45 * @defgroup nrfx_qspi QSPI driver 46 * @{ 47 * @ingroup nrf_qspi 48 * @brief Quad Serial Peripheral Interface (QSPI) peripheral driver. 49 */ 50 51 /** @brief QSPI driver instance configuration structure. */ 52 typedef struct 53 { 54 uint32_t xip_offset; ///< Address offset into the external memory for Execute in Place operation. 55 nrf_qspi_pins_t pins; ///< Pin configuration structure. 56 nrf_qspi_prot_conf_t prot_if; ///< Protocol layer interface configuration structure. 57 nrf_qspi_phy_conf_t phy_if; ///< Physical layer interface configuration structure. 58 uint32_t timeout; ///< Time in milliseconds used in timeout counter. 59 uint8_t irq_priority; ///< Interrupt priority. 60 bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. 61 /**< When set to true, the driver does not modify 62 * any GPIO parameters of the used pins. Those 63 * parameters are supposed to be configured 64 * externally before the driver is initialized. */ 65 bool skip_psel_cfg; ///< Skip pin selection configuration. 66 /**< When set to true, the driver does not modify 67 * pin select registers in the peripheral. 68 * Those registers are supposed to be set up 69 * externally before the driver is initialized. 70 * @note When both GPIO configuration and pin 71 * selection are to be skipped, the structure 72 * fields that specify pins can be omitted, 73 * as they are ignored anyway. */ 74 } nrfx_qspi_config_t; 75 76 /** 77 * @brief QSPI instance default configuration. 78 * 79 * This configuration sets up QSPI with the following options: 80 * - no offset for address in the external memory for Execute in Place operation 81 * - single data line 82 * - FAST_READ opcode for reading 83 * - PP opcode for writing 84 * - 24 bit addressing mode 85 * - Deep Power-down disabled 86 * - clock frequency: 2 MHz for nRF52 Series, 6 MHz for nRF53 Series 87 * - SCK delay 5 clock ticks 88 * - 500 milliseconds operation timeout 89 * - mode 0 (data captured on the clock rising edge and transmitted on a falling edge. Clock base level is '0') 90 * 91 * @param[in] _pin_sck Pin for clock signal. 92 * @param[in] _pin_csn Pin for chip select signal. 93 * @param[in] _pin_io0 Pin 0 for I/O data. 94 * @param[in] _pin_io1 Pin 1 for I/O data. 95 * @param[in] _pin_io2 Pin 2 for I/O data. 96 * @param[in] _pin_io3 Pin 3 for I/O data. 97 */ 98 #define NRFX_QSPI_DEFAULT_CONFIG(_pin_sck, _pin_csn, _pin_io0, \ 99 _pin_io1, _pin_io2, _pin_io3) \ 100 { \ 101 .xip_offset = 0, \ 102 .pins = { \ 103 .sck_pin = _pin_sck, \ 104 .csn_pin = _pin_csn, \ 105 .io0_pin = _pin_io0, \ 106 .io1_pin = _pin_io1, \ 107 .io2_pin = _pin_io2, \ 108 .io3_pin = _pin_io3 \ 109 }, \ 110 .prot_if = { \ 111 .readoc = NRF_QSPI_READOC_FASTREAD, \ 112 .writeoc = NRF_QSPI_WRITEOC_PP, \ 113 .addrmode = NRF_QSPI_ADDRMODE_24BIT, \ 114 .dpmconfig = false, \ 115 }, \ 116 .phy_if = { \ 117 .sck_delay = 0x05, \ 118 .dpmen = false, \ 119 .spi_mode = NRF_QSPI_MODE_0, \ 120 .sck_freq = NRF_QSPI_FREQ_DIV16, \ 121 }, \ 122 .timeout = 500, \ 123 .irq_priority = (uint8_t)NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ 124 } 125 126 /** @brief QSPI custom instruction helper with the default configuration. */ 127 #define NRFX_QSPI_DEFAULT_CINSTR(opc, len) \ 128 { \ 129 .opcode = (opc), \ 130 .length = (len), \ 131 .io2_level = false, \ 132 .io3_level = false, \ 133 .wipwait = false, \ 134 .wren = false \ 135 } 136 137 /** 138 * @brief QSPI master driver event types, passed to the handler routine provided 139 * during initialization. 140 */ 141 typedef enum 142 { 143 NRFX_QSPI_EVENT_DONE, /**< Transfer done. */ 144 } nrfx_qspi_evt_t; 145 146 /** 147 * @brief QSPI master driver extended event types, 148 * obtained using @ref nrfx_qspi_event_extended_get() function. 149 */ 150 typedef enum 151 { 152 NRFX_QSPI_EVENT_NONE, /**< No event occurence. */ 153 NRFX_QSPI_EVENT_WRITE_DONE, /**< Write done. */ 154 NRFX_QSPI_EVENT_READ_DONE, /**< Read done. */ 155 NRFX_QSPI_EVENT_ERASE_DONE, /**< Erase done. */ 156 } nrfx_qspi_evt_ext_type_t; 157 158 /** @brief QSPI driver erase event data. */ 159 typedef struct 160 { 161 uint32_t addr; /**< Erase start address. */ 162 nrf_qspi_erase_len_t len; /**< Erase length. */ 163 } nrfx_qspi_evt_ext_erase_t; 164 165 /** @brief QSPI driver transfer event data. */ 166 typedef struct 167 { 168 void * p_buffer; /**< Pointer to the data buffer associated with transfer. */ 169 size_t size; /**< Data buffer size. */ 170 uint32_t addr; /**< Transfer start address. */ 171 } nrfx_qspi_evt_ext_xfer_t; 172 173 /** @brief QSPI driver extended event structure. */ 174 typedef struct 175 { 176 nrfx_qspi_evt_ext_type_t type; ///< Extended event type. 177 union 178 { 179 nrfx_qspi_evt_ext_xfer_t xfer; ///< Data for write or read transfer event. 180 nrfx_qspi_evt_ext_erase_t erase; ///< Data for erase event. 181 } data; ///< Union to store event data. 182 } nrfx_qspi_evt_ext_t; 183 184 /** @brief QSPI driver event handler type. */ 185 typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context); 186 187 /** 188 * @brief Function for initializing the QSPI driver instance. 189 * 190 * This function configures the peripheral and its interrupts. 191 * 192 * @note The function does not activate the peripheral instance. The activation is done during the first 193 * transfer after initialization or when calling @ref nrfx_qspi_activate function. 194 * The activation process starts the internal clocks, and the QSPI peripheral tries to read 195 * the status byte to check the busy bit. Reading the status byte is done in a simple poll 196 * and wait mechanism. If the busy bit is set, this indicates issues with the external memory 197 * device. As a result, transfer functions return @ref NRFX_ERROR_TIMEOUT. 198 * 199 * In case of issues: 200 * - Check the connection. 201 * - Make sure that the memory device does not perform other operations like erasing or writing. 202 * - Check if there is a short circuit. 203 * 204 * @param[in] p_config Pointer to the structure with the initial configuration. 205 * @param[in] handler Event handler provided by the user. If NULL, transfers 206 * will be performed in blocking mode. 207 * @param[in] p_context Pointer to context. Use in the interrupt handler. 208 * 209 * @warning On nRF5340, only the dedicated pins with @ref NRF_GPIO_PIN_SEL_PERIPHERAL configuration 210 * are supported. See the chapter <a href=@nRF5340pinAssignmentsURL>Pin assignments</a> 211 * in the Product Specification. 212 * 213 * @retval NRFX_SUCCESS Initialization was successful. 214 * @retval NRFX_ERROR_ALREADY The driver is already initialized. 215 * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized. 216 * Deprecated - use @ref NRFX_ERROR_ALREADY instead. 217 * @retval NRFX_ERROR_INVALID_PARAM The pin configuration was incorrect. 218 */ 219 nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, 220 nrfx_qspi_handler_t handler, 221 void * p_context); 222 223 /** 224 * @brief Function for reconfiguring the QSPI driver instance. 225 * 226 * @param[in] p_config Pointer to the structure with the configuration. 227 * 228 * @warning The function deactivates the peripheral instance. The activation is done during the first 229 * transfer after reconfiguration or when calling @ref nrfx_qspi_activate function. 230 * 231 * @retval NRFX_SUCCESS Reconfiguration was successful. 232 * @retval NRFX_ERROR_BUSY The driver is during transaction. 233 * @retval NRFX_ERROR_TIMEOUT External memory is busy or there are connection issues. 234 * @retval NRFX_ERROR_INVALID_STATE The driver is uninitialized. 235 * @retval NRFX_ERROR_INVALID_PARAM The pin configuration was incorrect. 236 */ 237 nrfx_err_t nrfx_qspi_reconfigure(nrfx_qspi_config_t const * p_config); 238 239 /** 240 * @brief Function for uninitializing the QSPI driver instance. 241 * 242 * @note If a custom instruction long transfer is ongoing when the function is called, 243 * the transfer will be interrupted. 244 */ 245 void nrfx_qspi_uninit(void); 246 247 /** 248 * @brief Function for activating the QSPI driver instance. 249 * 250 * @param[in] wait True if activation is to be in blocking mode, false otherwise. 251 * 252 * @retval NRFX_SUCCESS The driver instance has been activated. 253 * @retval NRFX_ERROR_ALREADY The driver is already activated. 254 * @retval NRFX_ERROR_TIMEOUT External memory is busy, or there are connection issues. 255 */ 256 nrfx_err_t nrfx_qspi_activate(bool wait); 257 258 /** 259 * @brief Function for deactivating the QSPI driver instance. 260 * 261 * @note If a custom instruction long transfer is ongoing when the function is called, 262 * the transfer will be interrupted. 263 * 264 * @retval NRFX_SUCCESS The driver instance has been activated. 265 * @retval NRFX_ERROR_BUSY The driver is during transaction. 266 */ 267 nrfx_err_t nrfx_qspi_deactivate(void); 268 269 /** 270 * @brief Function for checking if the QSPI driver is initialized. 271 * 272 * @retval true Driver is already initialized. 273 * @retval false Driver is not initialized. 274 */ 275 bool nrfx_qspi_init_check(void); 276 277 /** 278 * @brief Function for reading data from the QSPI memory. 279 * 280 * @note If that is the first operation after activation of driver initialization has been triggered, 281 * the activation process starts the internal clocks and the QSPI peripheral tries to read 282 * the status byte to check the busy bit. Reading the status byte is done in a simple poll 283 * and wait mechanism. If the busy bit is set, this indicates that the memory may not be ready yet. 284 * As a result, the function returns @ref NRFX_ERROR_TIMEOUT. 285 * 286 * Write, read, and erase operations check memory device busy state before starting the operation. 287 * If the memory is busy, the resulting action depends on the mode in which the read operation is used: 288 * - blocking mode (without handler) - a delay occurs until the last operation runs and 289 * until the operation data is being read. 290 * - interrupt mode (with handler) - event emission occurs after the last operation 291 * and reading of data are finished. 292 * In interrupt mode read operations can be double-buffered by calling the function again. 293 * To utilize double-buffering feature, @ref NRF_QSPI_TASK_READSTART needs to be triggered 294 * on @ref NRF_QSPI_EVENT_READY externally (for example by using the PPI/DPPI). 295 * 296 * @param[out] p_rx_buffer Pointer to the receive buffer. 297 * @param[in] rx_buffer_length Size of the data to read. 298 * @param[in] src_address Address in memory to read from. 299 * 300 * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation 301 * was commissioned (handler mode). 302 * @retval NRFX_ERROR_BUSY The driver currently handles another operation. 303 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 304 * @retval NRFX_ERROR_INVALID_ADDR The provided buffer is not placed in the Data RAM region 305 * or its address is not aligned to a 32-bit word. 306 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 307 * due to the current configuration of clocks. 308 * Refer to the errata document for more information. 309 */ 310 nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, 311 size_t rx_buffer_length, 312 uint32_t src_address); 313 314 /** 315 * @brief Function for writing data to QSPI memory. 316 * 317 * @note Refer to the note for @ref nrfx_qspi_read. 318 * 319 * Write, read, and erase operations check memory device busy state before starting the operation. 320 * If the memory is busy, the resulting action depends on the mode in which the write operation is used: 321 * - blocking mode (without handler) - a delay occurs until the last operation runs or 322 * until the operation data is being sent. 323 * - interrupt mode (with handler) - event emission occurs after the last operation 324 * and sending of operation data are finished. 325 * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check 326 * after executing the write function. 327 * Remember that an incoming event signalizes only that data was sent to the memory device and the peripheral 328 * before the write operation checked if memory was busy. 329 * In interrupt mode write operations can be double-buffered by calling the function again. 330 * To utilize double-buffering feature, @ref NRF_QSPI_TASK_WRITESTART needs to be triggered 331 * on @ref NRF_QSPI_EVENT_READY externally (for example by using the PPI/DPPI). 332 * 333 * @param[in] p_tx_buffer Pointer to the writing buffer. 334 * @param[in] tx_buffer_length Size of the data to write. 335 * @param[in] dst_address Address in memory to write to. 336 * 337 * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation 338 * was commissioned (handler mode). 339 * @retval NRFX_ERROR_BUSY The driver currently handles other operation. 340 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 341 * @retval NRFX_ERROR_INVALID_ADDR The provided buffer is not placed in the Data RAM region 342 * or its address is not aligned to a 32-bit word. 343 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 344 * due to the current configuration of clocks. 345 * Refer to the errata document for more information. 346 */ 347 nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, 348 size_t tx_buffer_length, 349 uint32_t dst_address); 350 351 /** 352 * @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip. 353 * 354 * @note Refer to the note for @ref nrfx_qspi_read. 355 * 356 * Write, read, and erase operations check memory device busy state before starting the operation. 357 * If the memory is busy, the resulting action depends on the mode in which the erase operation is used: 358 * - blocking mode (without handler) - a delay occurs until the last operation runs or 359 * until the operation data is being sent. 360 * - interrupt mode (with handler) - event emission occurs after the last operation 361 * and sending of operation data are finished. 362 * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check 363 * after executing the erase function. 364 * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral 365 * before the erase operation checked if memory was busy. 366 * 367 * @param[in] length Size of data to erase. See @ref nrf_qspi_erase_len_t. 368 * @param[in] start_address Memory address to start erasing. If chip erase is performed, address 369 * field is ommited. 370 * 371 * @retval NRFX_SUCCESS The operation was successful (blocking mode) or operation 372 * was commissioned (handler mode). 373 * @retval NRFX_ERROR_BUSY The driver currently handles another operation. 374 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 375 * @retval NRFX_ERROR_INVALID_ADDR The provided start address is not aligned to a 32-bit word. 376 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 377 * due to the current configuration of clocks. 378 * Refer to the errata document for more information. 379 */ 380 nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, 381 uint32_t start_address); 382 383 /** 384 * @brief Function for starting an erase operation of the whole chip. 385 * 386 * @note Refer to the note for @ref nrfx_qspi_read. 387 * 388 * @retval NRFX_SUCCESS The operation was successful (blocking mode) or 389 * commissioned (handler mode). 390 * @retval NRFX_ERROR_BUSY The driver currently is handling another operation. 391 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 392 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 393 * due to the current configuration of clocks. 394 * Refer to the errata document for more information. 395 */ 396 nrfx_err_t nrfx_qspi_chip_erase(void); 397 398 /** 399 * @brief Function for getting the extended event associated with finished operation. 400 * 401 * @return Pointer to the extended event associated with finished operation. 402 */ 403 nrfx_qspi_evt_ext_t const * nrfx_qspi_event_extended_get(void); 404 405 /** 406 * @brief Function for checking whether any write or read data transfer is buffered. 407 * 408 * @return True if there is a transfer buffered, false otherwise. 409 */ 410 bool nrfx_qspi_xfer_buffered_check(void); 411 412 /** 413 * @brief Function for getting the current driver status and status byte of memory device with 414 * testing WIP (write in progress) bit. 415 * 416 * @retval NRFX_SUCCESS The driver and memory are ready to handle a new operation. 417 * @retval NRFX_ERROR_BUSY The driver currently is handling another operation. 418 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 419 * due to the current configuration of clocks. 420 * Refer to the errata document for more information. 421 */ 422 nrfx_err_t nrfx_qspi_mem_busy_check(void); 423 424 /** 425 * @brief Function for signaling premature operation timeout. 426 * 427 * The function provides a mechanism that can cause premature timeout when the driver is waiting for 428 * the READY event. This allows to use external source of the timeout. If the driver is initialized 429 * with a handler, it will not process the event generated for the transfer. 430 */ 431 void nrfx_qspi_timeout_signal(void); 432 433 /** 434 * @brief Function for sending operation code, sending data, and receiving data from the memory device. 435 * 436 * @note Refer to the note for @ref nrfx_qspi_read. 437 * 438 * Use this function to transfer configuration data to memory and to receive data from memory. 439 * Pointers can be addresses from flash memory. 440 * This function is a synchronous function and should be used only if necessary. 441 * 442 * @note Please note that the @ref NRFX_QSPI_DEFAULT_CINSTR macro provides default values 443 * for the @p io2_level and @p io3_level fields that cause the IO2 and IO3 lines 444 * to be kept low during the custom instruction transfer. Such configuration may not 445 * be suitable in certain circumstances and memory devices can interpret such levels 446 * of those lines as active WP# and HOLD#/RESET# signals, respectively. Hence, it is 447 * safer to use a configuration that will keep the lines high during the transfer. 448 * 449 * @param[in] p_config Pointer to the structure with opcode and transfer configuration. 450 * @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted. 451 * @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive. 452 * 453 * @retval NRFX_SUCCESS The operation was successful. 454 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 455 * @retval NRFX_ERROR_BUSY The driver currently handles other operation. 456 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 457 * due to the current configuration of clocks. 458 * Refer to the errata document for more information. 459 */ 460 nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, 461 void const * p_tx_buffer, 462 void * p_rx_buffer); 463 464 /** 465 * @brief Function for sending operation code and data to the memory device with simpler configuration. 466 * 467 * @note Refer to the note for @ref nrfx_qspi_read. 468 * 469 * Use this function to transfer configuration data to memory and to receive data from memory. 470 * This function is a synchronous function and should be used only if necessary. 471 * 472 * @param[in] opcode Operation code. Sending first. 473 * @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t. 474 * @param[in] p_tx_buffer Pointer to input data array. 475 * 476 * @retval NRFX_SUCCESS The operation was successful. 477 * @retval NRFX_ERROR_BUSY The driver currently handles another operation. 478 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 479 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 480 * due to the current configuration of clocks. 481 * Refer to the errata document for more information. 482 */ 483 nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, 484 nrf_qspi_cinstr_len_t length, 485 void const * p_tx_buffer); 486 487 /** 488 * @brief Function for starting the custom instruction long frame mode. 489 * 490 * @note Refer to the note for @ref nrfx_qspi_read. 491 * 492 * The long frame mode is a mechanism that allows for arbitrary byte length custom instructions. 493 * Use this function to initiate a custom transaction by sending custom instruction opcode. 494 * To send and receive data, use @ref nrfx_qspi_lfm_xfer. 495 * 496 * @note Please note that the @ref NRFX_QSPI_DEFAULT_CINSTR macro provides default values 497 * for the @p io2_level and @p io3_level fields that cause the IO2 and IO3 lines 498 * to be kept low during the custom instruction transfer. Such configuration may not 499 * be suitable in certain circumstances and memory devices can interpret such levels 500 * of those lines as active WP# and HOLD#/RESET# signals, respectively. Hence, it is 501 * safer to use a configuration that will keep the lines high during the transfer. 502 * 503 * @param[in] p_config Pointer to the structure with custom instruction opcode and transfer 504 * configuration. Transfer length must be set to @ref NRF_QSPI_CINSTR_LEN_1B. 505 * 506 * @retval NRFX_SUCCESS Operation was successful. 507 * @retval NRFX_ERROR_BUSY Driver currently handles other operation. 508 * @retval NRFX_ERROR_TIMEOUT The external memory is busy, or there are connection issues. 509 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 510 * due to the current configuration of clocks. 511 * Refer to the errata document for more information. 512 */ 513 nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config); 514 515 /** 516 * @brief Function for sending and receiving data in the custom instruction long frame mode. 517 * 518 * @note Refer to the note for @ref nrfx_qspi_read. 519 * 520 * Both specified buffers must be at least @p transfer_length bytes in size. 521 * 522 * @param[in] p_tx_buffer Pointer to the array with data to send. 523 * Can be NULL if there is nothing to send. 524 * @param[out] p_rx_buffer Pointer to the array for receiving data. 525 * Can be NULL if there is nothing to receive. 526 * @param[in] transfer_length Number of bytes to send and receive. 527 * @param[in] finalize True if custom instruction long frame mode is to be finalized 528 * after this transfer. 529 * 530 * @retval NRFX_SUCCESS Operation was successful. 531 * @retval NRFX_ERROR_TIMEOUT External memory is busy or there are connection issues. 532 * Long frame mode becomes deactivated. 533 * @retval NRFX_ERROR_FORBIDDEN The operation could trigger nRF5340 anomaly 159 534 * due to the current configuration of clocks. 535 * Refer to the errata document for more information. 536 */ 537 nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer, 538 void * p_rx_buffer, 539 size_t transfer_length, 540 bool finalize); 541 542 #if NRF_QSPI_HAS_XIP_ENC || defined(__NRFX_DOXYGEN__) 543 /** 544 * @brief Function for setting the XIP encryption. 545 * 546 * @param[in] p_config XIP encryption configuration structure. 547 * To disable encryption, pass NULL pointer as argument. 548 * 549 * @retval NRFX_SUCCESS Operation was successful. 550 * @retval NRFX_ERROR_BUSY Driver currently handles other operation. 551 */ 552 nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config); 553 #endif 554 555 #if NRF_QSPI_HAS_DMA_ENC || defined(__NRFX_DOXYGEN__) 556 /** 557 * @brief Function for setting the EasyDMA encryption. 558 * 559 * @param[in] p_config DMA encryption configuration structure. 560 * To disable encryption, pass NULL pointer as argument. 561 * 562 * @retval NRFX_SUCCESS Operation was successful. 563 * @retval NRFX_ERROR_BUSY Driver currently handles other operation. 564 */ 565 nrfx_err_t nrfx_qspi_dma_encrypt(nrf_qspi_encryption_t const * p_config); 566 #endif 567 568 /** @} */ 569 570 571 void nrfx_qspi_irq_handler(void); 572 573 574 #ifdef __cplusplus 575 } 576 #endif 577 578 #endif // NRFX_QSPI_H__ 579
