1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF9230_ENGA_RADIOCORE_H 36 #define NRF9230_ENGA_RADIOCORE_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_RADIOCORE /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 53 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 54 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 55 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No 56 Match*/ 57 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 58 related Fault*/ 59 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 60 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 61 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 62 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 63 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 64 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 65 /* ============================================== Processor Specific Interrupts ============================================== */ 66 SPU000_IRQn = 0, /*!< 0 SPU000 */ 67 MPC_IRQn = 1, /*!< 1 MPC */ 68 MVDMA_IRQn = 3, /*!< 3 MVDMA */ 69 SPU010_IRQn = 16, /*!< 16 SPU010 */ 70 WDT010_IRQn = 19, /*!< 19 WDT010 */ 71 WDT011_IRQn = 20, /*!< 20 WDT011 */ 72 SPU020_IRQn = 32, /*!< 32 SPU020 */ 73 EGU020_IRQn = 37, /*!< 37 EGU020 */ 74 TIMER020_IRQn = 40, /*!< 40 TIMER020 */ 75 TIMER021_IRQn = 41, /*!< 41 TIMER021 */ 76 TIMER022_IRQn = 42, /*!< 42 TIMER022 */ 77 RTC_IRQn = 43, /*!< 43 RTC */ 78 RADIO_0_IRQn = 44, /*!< 44 RADIO_0 */ 79 RADIO_1_IRQn = 45, /*!< 45 RADIO_1 */ 80 SPU030_IRQn = 48, /*!< 48 SPU030 */ 81 VPR_IRQn = 52, /*!< 52 VPR */ 82 AAR030_CCM030_IRQn = 58, /*!< 58 AAR030_CCM030 */ 83 ECB030_IRQn = 59, /*!< 59 ECB030 */ 84 AAR031_CCM031_IRQn = 60, /*!< 60 AAR031_CCM031 */ 85 ECB031_IRQn = 61, /*!< 61 ECB031 */ 86 IPCT_0_IRQn = 64, /*!< 64 IPCT_0 */ 87 IPCT_1_IRQn = 65, /*!< 65 IPCT_1 */ 88 SWI0_IRQn = 88, /*!< 88 SWI0 */ 89 SWI1_IRQn = 89, /*!< 89 SWI1 */ 90 SWI2_IRQn = 90, /*!< 90 SWI2 */ 91 SWI3_IRQn = 91, /*!< 91 SWI3 */ 92 SWI4_IRQn = 92, /*!< 92 SWI4 */ 93 SWI5_IRQn = 93, /*!< 93 SWI5 */ 94 SWI6_IRQn = 94, /*!< 94 SWI6 */ 95 SWI7_IRQn = 95, /*!< 95 SWI7 */ 96 BELLBOARD_0_IRQn = 96, /*!< 96 BELLBOARD_0 */ 97 BELLBOARD_1_IRQn = 97, /*!< 97 BELLBOARD_1 */ 98 BELLBOARD_2_IRQn = 98, /*!< 98 BELLBOARD_2 */ 99 BELLBOARD_3_IRQn = 99, /*!< 99 BELLBOARD_3 */ 100 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 101 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 102 GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ 103 GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ 104 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 105 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 106 GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ 107 TBM_IRQn = 127, /*!< 127 TBM */ 108 USBHS_IRQn = 134, /*!< 134 USBHS */ 109 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 110 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 111 I3C120_IRQn = 211, /*!< 211 I3C120 */ 112 VPR121_IRQn = 212, /*!< 212 VPR121 */ 113 CAN120_IRQn = 216, /*!< 216 CAN120 */ 114 MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ 115 CAN121_IRQn = 219, /*!< 219 CAN121 */ 116 MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ 117 I3C121_IRQn = 222, /*!< 222 I3C121 */ 118 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 119 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 120 PWM120_IRQn = 228, /*!< 228 PWM120 */ 121 SPIS120_IRQn = 229, /*!< 229 SPIS120 */ 122 SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ 123 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 124 VPR130_IRQn = 264, /*!< 264 VPR130 */ 125 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 126 RTC130_IRQn = 296, /*!< 296 RTC130 */ 127 RTC131_IRQn = 297, /*!< 297 RTC131 */ 128 WDT131_IRQn = 299, /*!< 299 WDT131 */ 129 WDT132_IRQn = 300, /*!< 300 WDT132 */ 130 EGU130_IRQn = 301, /*!< 301 EGU130 */ 131 SAADC_IRQn = 386, /*!< 386 SAADC */ 132 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 133 TEMP_IRQn = 388, /*!< 388 TEMP */ 134 I2S130_IRQn = 402, /*!< 402 I2S130 */ 135 PDM_IRQn = 403, /*!< 403 PDM */ 136 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 137 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 138 I2S131_IRQn = 407, /*!< 407 I2S131 */ 139 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 140 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 141 PWM130_IRQn = 420, /*!< 420 PWM130 */ 142 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 143 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 144 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 145 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 146 PWM131_IRQn = 436, /*!< 436 PWM131 */ 147 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 148 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 149 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 150 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 151 PWM132_IRQn = 452, /*!< 452 PWM132 */ 152 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 153 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 154 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 155 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 156 PWM133_IRQn = 468, /*!< 468 PWM133 */ 157 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 158 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 159 } IRQn_Type; 160 161 /* ==================================================== Interrupt Aliases ==================================================== */ 162 #define AAR030_IRQn AAR030_CCM030_IRQn 163 #define AAR030_IRQHandler AAR030_CCM030_IRQHandler 164 #define CCM030_IRQn AAR030_CCM030_IRQn 165 #define CCM030_IRQHandler AAR030_CCM030_IRQHandler 166 #define AAR031_IRQn AAR031_CCM031_IRQn 167 #define AAR031_IRQHandler AAR031_CCM031_IRQHandler 168 #define CCM031_IRQn AAR031_CCM031_IRQn 169 #define CCM031_IRQHandler AAR031_CCM031_IRQHandler 170 #define SPIM120_IRQn SPIM120_UARTE120_IRQn 171 #define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler 172 #define UARTE120_IRQn SPIM120_UARTE120_IRQn 173 #define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler 174 #define COMP_IRQn COMP_LPCOMP_IRQn 175 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 176 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 177 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 178 #define SPIM130_IRQn SERIAL0_IRQn 179 #define SPIM130_IRQHandler SERIAL0_IRQHandler 180 #define SPIS130_IRQn SERIAL0_IRQn 181 #define SPIS130_IRQHandler SERIAL0_IRQHandler 182 #define TWIM130_IRQn SERIAL0_IRQn 183 #define TWIM130_IRQHandler SERIAL0_IRQHandler 184 #define TWIS130_IRQn SERIAL0_IRQn 185 #define TWIS130_IRQHandler SERIAL0_IRQHandler 186 #define UARTE130_IRQn SERIAL0_IRQn 187 #define UARTE130_IRQHandler SERIAL0_IRQHandler 188 #define SPIM131_IRQn SERIAL1_IRQn 189 #define SPIM131_IRQHandler SERIAL1_IRQHandler 190 #define SPIS131_IRQn SERIAL1_IRQn 191 #define SPIS131_IRQHandler SERIAL1_IRQHandler 192 #define TWIM131_IRQn SERIAL1_IRQn 193 #define TWIM131_IRQHandler SERIAL1_IRQHandler 194 #define TWIS131_IRQn SERIAL1_IRQn 195 #define TWIS131_IRQHandler SERIAL1_IRQHandler 196 #define UARTE131_IRQn SERIAL1_IRQn 197 #define UARTE131_IRQHandler SERIAL1_IRQHandler 198 #define SPIM132_IRQn SERIAL2_IRQn 199 #define SPIM132_IRQHandler SERIAL2_IRQHandler 200 #define SPIS132_IRQn SERIAL2_IRQn 201 #define SPIS132_IRQHandler SERIAL2_IRQHandler 202 #define TWIM132_IRQn SERIAL2_IRQn 203 #define TWIM132_IRQHandler SERIAL2_IRQHandler 204 #define TWIS132_IRQn SERIAL2_IRQn 205 #define TWIS132_IRQHandler SERIAL2_IRQHandler 206 #define UARTE132_IRQn SERIAL2_IRQn 207 #define UARTE132_IRQHandler SERIAL2_IRQHandler 208 #define SPIM133_IRQn SERIAL3_IRQn 209 #define SPIM133_IRQHandler SERIAL3_IRQHandler 210 #define SPIS133_IRQn SERIAL3_IRQn 211 #define SPIS133_IRQHandler SERIAL3_IRQHandler 212 #define TWIM133_IRQn SERIAL3_IRQn 213 #define TWIM133_IRQHandler SERIAL3_IRQHandler 214 #define TWIS133_IRQn SERIAL3_IRQn 215 #define TWIS133_IRQHandler SERIAL3_IRQHandler 216 #define UARTE133_IRQn SERIAL3_IRQn 217 #define UARTE133_IRQHandler SERIAL3_IRQHandler 218 #define SPIM134_IRQn SERIAL4_IRQn 219 #define SPIM134_IRQHandler SERIAL4_IRQHandler 220 #define SPIS134_IRQn SERIAL4_IRQn 221 #define SPIS134_IRQHandler SERIAL4_IRQHandler 222 #define TWIM134_IRQn SERIAL4_IRQn 223 #define TWIM134_IRQHandler SERIAL4_IRQHandler 224 #define TWIS134_IRQn SERIAL4_IRQn 225 #define TWIS134_IRQHandler SERIAL4_IRQHandler 226 #define UARTE134_IRQn SERIAL4_IRQn 227 #define UARTE134_IRQHandler SERIAL4_IRQHandler 228 #define SPIM135_IRQn SERIAL5_IRQn 229 #define SPIM135_IRQHandler SERIAL5_IRQHandler 230 #define SPIS135_IRQn SERIAL5_IRQn 231 #define SPIS135_IRQHandler SERIAL5_IRQHandler 232 #define TWIM135_IRQn SERIAL5_IRQn 233 #define TWIM135_IRQHandler SERIAL5_IRQHandler 234 #define TWIS135_IRQn SERIAL5_IRQn 235 #define TWIS135_IRQHandler SERIAL5_IRQHandler 236 #define UARTE135_IRQn SERIAL5_IRQn 237 #define UARTE135_IRQHandler SERIAL5_IRQHandler 238 #define SPIM136_IRQn SERIAL6_IRQn 239 #define SPIM136_IRQHandler SERIAL6_IRQHandler 240 #define SPIS136_IRQn SERIAL6_IRQn 241 #define SPIS136_IRQHandler SERIAL6_IRQHandler 242 #define TWIM136_IRQn SERIAL6_IRQn 243 #define TWIM136_IRQHandler SERIAL6_IRQHandler 244 #define TWIS136_IRQn SERIAL6_IRQn 245 #define TWIS136_IRQHandler SERIAL6_IRQHandler 246 #define UARTE136_IRQn SERIAL6_IRQn 247 #define UARTE136_IRQHandler SERIAL6_IRQHandler 248 #define SPIM137_IRQn SERIAL7_IRQn 249 #define SPIM137_IRQHandler SERIAL7_IRQHandler 250 #define SPIS137_IRQn SERIAL7_IRQn 251 #define SPIS137_IRQHandler SERIAL7_IRQHandler 252 #define TWIM137_IRQn SERIAL7_IRQn 253 #define TWIM137_IRQHandler SERIAL7_IRQHandler 254 #define TWIS137_IRQn SERIAL7_IRQn 255 #define TWIS137_IRQHandler SERIAL7_IRQHandler 256 #define UARTE137_IRQn SERIAL7_IRQn 257 #define UARTE137_IRQHandler SERIAL7_IRQHandler 258 259 /* =========================================================================================================================== */ 260 /* ================ Processor and Core Peripheral Section ================ */ 261 /* =========================================================================================================================== */ 262 263 /* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ 264 #define __CM33_REV r0p4 /*!< CM33 Core Revision */ 265 #define __DSP_PRESENT 1 /*!< DSP present or not */ 266 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 267 #define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 268 #define __MPU_PRESENT 1 /*!< MPU present */ 269 #define __FPU_PRESENT 1 /*!< FPU present */ 270 #define __FPU_DP 0 /*!< Double Precision FPU */ 271 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 272 #define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ 273 #define __SAUREGION_PRESENT 1 /*!< SAU present */ 274 #define __NUM_SAUREGIONS 4 /*!< Number of regions */ 275 276 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 277 #include "system_nrf.h" /*!< nrf9230_enga_radiocore System Library */ 278 279 #endif /*!< NRF_RADIOCORE */ 280 281 282 #ifdef NRF_RADIOCORE 283 284 #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE 285 #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE 286 #define NRF_OWNER NRF_OWNER_RADIOCORE 287 288 #endif /*!< NRF_RADIOCORE */ 289 290 291 /* ========================================= Start of section using anonymous unions ========================================= */ 292 293 #include "compiler_abstraction.h" 294 295 #if defined (__CC_ARM) 296 #pragma push 297 #pragma anon_unions 298 #elif defined (__ICCARM__) 299 #pragma language=extended 300 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 301 #pragma clang diagnostic push 302 #pragma clang diagnostic ignored "-Wc11-extensions" 303 #pragma clang diagnostic ignored "-Wreserved-id-macro" 304 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 305 #pragma clang diagnostic ignored "-Wnested-anon-types" 306 #elif defined (__GNUC__) 307 /* anonymous unions are enabled by default */ 308 #elif defined (__TMS470__) 309 /* anonymous unions are enabled by default */ 310 #elif defined (__TASKING__) 311 #pragma warning 586 312 #elif defined (__CSMC__) 313 /* anonymous unions are enabled by default */ 314 #else 315 #warning Unsupported compiler type 316 #endif 317 318 /* =========================================================================================================================== */ 319 /* ================ Peripheral Address Map ================ */ 320 /* =========================================================================================================================== */ 321 322 #define NRF_RADIOCORE_ICACHEDATA_S_BASE 0x03F00000UL 323 #define NRF_RADIOCORE_ICACHEINFO_S_BASE 0x03F10000UL 324 #define NRF_RADIOCORE_UICR_NS_BASE 0x0FFFA000UL 325 #define NRF_RADIOCORE_DCACHEDATA_S_BASE 0x23F00000UL 326 #define NRF_RADIOCORE_DCACHEINFO_S_BASE 0x23F10000UL 327 #define NRF_RADIOCORE_ETM_NS_BASE 0xE0041000UL 328 #define NRF_RADIOCORE_CTI_S_BASE 0xE0042000UL 329 #define NRF_RADIOCORE_CPUC_S_BASE 0xE0080000UL 330 #define NRF_RADIOCORE_ICACHE_S_BASE 0xE0082000UL 331 #define NRF_RADIOCORE_DCACHE_S_BASE 0xE0083000UL 332 #define NRF_RADIOCORE_SPU000_S_BASE 0x53000000UL 333 #define NRF_RADIOCORE_MPC_S_BASE 0x53001000UL 334 #define NRF_RADIOCORE_MVDMA_NS_BASE 0x43003000UL 335 #define NRF_RADIOCORE_MVDMA_S_BASE 0x53003000UL 336 #define NRF_RADIOCORE_RAMC000_NS_BASE 0x43004000UL 337 #define NRF_RADIOCORE_RAMC000_S_BASE 0x53004000UL 338 #define NRF_RADIOCORE_HSFLL_S_BASE 0x5300D000UL 339 #define NRF_RADIOCORE_LRCCONF000_S_BASE 0x5300E000UL 340 #define NRF_RADIOCORE_SPU010_S_BASE 0x53010000UL 341 #define NRF_RADIOCORE_MEMCONF_NS_BASE 0x43012000UL 342 #define NRF_RADIOCORE_MEMCONF_S_BASE 0x53012000UL 343 #define NRF_RADIOCORE_WDT010_NS_BASE 0x43013000UL 344 #define NRF_RADIOCORE_WDT010_S_BASE 0x53013000UL 345 #define NRF_RADIOCORE_WDT011_NS_BASE 0x43014000UL 346 #define NRF_RADIOCORE_WDT011_S_BASE 0x53014000UL 347 #define NRF_RADIOCORE_LRCCONF010_S_BASE 0x5301E000UL 348 #define NRF_RADIOCORE_RESETINFO_S_BASE 0x5301E000UL 349 #define NRF_RADIOCORE_SPU020_S_BASE 0x53020000UL 350 #define NRF_RADIOCORE_DPPIC020_NS_BASE 0x43022000UL 351 #define NRF_RADIOCORE_DPPIC020_S_BASE 0x53022000UL 352 #define NRF_RADIOCORE_PPIB020_S_BASE 0x53023000UL 353 #define NRF_RADIOCORE_EGU020_NS_BASE 0x43025000UL 354 #define NRF_RADIOCORE_EGU020_S_BASE 0x53025000UL 355 #define NRF_RADIOCORE_TIMER020_NS_BASE 0x43028000UL 356 #define NRF_RADIOCORE_TIMER020_S_BASE 0x53028000UL 357 #define NRF_RADIOCORE_TIMER021_NS_BASE 0x43029000UL 358 #define NRF_RADIOCORE_TIMER021_S_BASE 0x53029000UL 359 #define NRF_RADIOCORE_TIMER022_NS_BASE 0x4302A000UL 360 #define NRF_RADIOCORE_TIMER022_S_BASE 0x5302A000UL 361 #define NRF_RADIOCORE_RTC_NS_BASE 0x4302B000UL 362 #define NRF_RADIOCORE_RTC_S_BASE 0x5302B000UL 363 #define NRF_RADIOCORE_RADIO_NS_BASE 0x4302C000UL 364 #define NRF_RADIOCORE_RADIO_S_BASE 0x5302C000UL 365 #define NRF_RADIOCORE_LRCCONF020_S_BASE 0x5302E000UL 366 #define NRF_RADIOCORE_SPU030_S_BASE 0x53030000UL 367 #define NRF_RADIOCORE_PPIB030_S_BASE 0x53031000UL 368 #define NRF_RADIOCORE_VPR_NS_BASE 0x43034000UL 369 #define NRF_RADIOCORE_VPR_S_BASE 0x53034000UL 370 #define NRF_RADIOCORE_RAMC001_NS_BASE 0x43038000UL 371 #define NRF_RADIOCORE_RAMC001_S_BASE 0x53038000UL 372 #define NRF_RADIOCORE_AAR030_NS_BASE 0x4303A000UL 373 #define NRF_RADIOCORE_CCM030_NS_BASE 0x4303A000UL 374 #define NRF_RADIOCORE_AAR030_S_BASE 0x5303A000UL 375 #define NRF_RADIOCORE_CCM030_S_BASE 0x5303A000UL 376 #define NRF_RADIOCORE_ECB030_NS_BASE 0x4303B000UL 377 #define NRF_RADIOCORE_ECB030_S_BASE 0x5303B000UL 378 #define NRF_RADIOCORE_AAR031_NS_BASE 0x4303C000UL 379 #define NRF_RADIOCORE_CCM031_NS_BASE 0x4303C000UL 380 #define NRF_RADIOCORE_AAR031_S_BASE 0x5303C000UL 381 #define NRF_RADIOCORE_CCM031_S_BASE 0x5303C000UL 382 #define NRF_RADIOCORE_ECB031_NS_BASE 0x4303D000UL 383 #define NRF_RADIOCORE_ECB031_S_BASE 0x5303D000UL 384 #define NRF_RADIOCORE_IPCT_NS_BASE 0x43024000UL 385 #define NRF_RADIOCORE_IPCT_S_BASE 0x53024000UL 386 #define NRF_RADIOCORE_SWI0_NS_BASE 0x42058000UL 387 #define NRF_RADIOCORE_SWI1_NS_BASE 0x42059000UL 388 #define NRF_RADIOCORE_SWI2_NS_BASE 0x4205A000UL 389 #define NRF_RADIOCORE_SWI3_NS_BASE 0x4205B000UL 390 #define NRF_RADIOCORE_SWI4_NS_BASE 0x4205C000UL 391 #define NRF_RADIOCORE_SWI5_NS_BASE 0x4205D000UL 392 #define NRF_RADIOCORE_SWI6_NS_BASE 0x4205E000UL 393 #define NRF_RADIOCORE_SWI7_NS_BASE 0x4205F000UL 394 #define NRF_RADIOCORE_BELLBOARD_NS_BASE 0x4F09B000UL 395 #define NRF_RADIOCORE_BELLBOARD_S_BASE 0x5F09B000UL 396 397 /* =========================================================================================================================== */ 398 /* ================ Peripheral Declaration ================ */ 399 /* =========================================================================================================================== */ 400 401 #define NRF_RADIOCORE_ICACHEDATA_S ((NRF_ICACHEDATA_Type*) NRF_RADIOCORE_ICACHEDATA_S_BASE) 402 #define NRF_RADIOCORE_ICACHEINFO_S ((NRF_ICACHEINFO_Type*) NRF_RADIOCORE_ICACHEINFO_S_BASE) 403 #define NRF_RADIOCORE_UICR_NS ((NRF_UICR_Type*) NRF_RADIOCORE_UICR_NS_BASE) 404 #define NRF_RADIOCORE_DCACHEDATA_S ((NRF_DCACHEDATA_Type*) NRF_RADIOCORE_DCACHEDATA_S_BASE) 405 #define NRF_RADIOCORE_DCACHEINFO_S ((NRF_DCACHEINFO_Type*) NRF_RADIOCORE_DCACHEINFO_S_BASE) 406 #define NRF_RADIOCORE_ETM_NS ((NRF_ETM_Type*) NRF_RADIOCORE_ETM_NS_BASE) 407 #define NRF_RADIOCORE_CTI_S ((NRF_CTI_Type*) NRF_RADIOCORE_CTI_S_BASE) 408 #define NRF_RADIOCORE_CPUC_S ((NRF_CM33SS_Type*) NRF_RADIOCORE_CPUC_S_BASE) 409 #define NRF_RADIOCORE_ICACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_ICACHE_S_BASE) 410 #define NRF_RADIOCORE_DCACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_DCACHE_S_BASE) 411 #define NRF_RADIOCORE_SPU000_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU000_S_BASE) 412 #define NRF_RADIOCORE_MPC_S ((NRF_MPC_Type*) NRF_RADIOCORE_MPC_S_BASE) 413 #define NRF_RADIOCORE_MVDMA_NS ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_NS_BASE) 414 #define NRF_RADIOCORE_MVDMA_S ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_S_BASE) 415 #define NRF_RADIOCORE_RAMC000_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_NS_BASE) 416 #define NRF_RADIOCORE_RAMC000_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_S_BASE) 417 #define NRF_RADIOCORE_HSFLL_S ((NRF_HSFLL_Type*) NRF_RADIOCORE_HSFLL_S_BASE) 418 #define NRF_RADIOCORE_LRCCONF000_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF000_S_BASE) 419 #define NRF_RADIOCORE_SPU010_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU010_S_BASE) 420 #define NRF_RADIOCORE_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_NS_BASE) 421 #define NRF_RADIOCORE_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_S_BASE) 422 #define NRF_RADIOCORE_WDT010_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_NS_BASE) 423 #define NRF_RADIOCORE_WDT010_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_S_BASE) 424 #define NRF_RADIOCORE_WDT011_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_NS_BASE) 425 #define NRF_RADIOCORE_WDT011_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_S_BASE) 426 #define NRF_RADIOCORE_LRCCONF010_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF010_S_BASE) 427 #define NRF_RADIOCORE_RESETINFO_S ((NRF_RESETINFO_Type*) NRF_RADIOCORE_RESETINFO_S_BASE) 428 #define NRF_RADIOCORE_SPU020_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU020_S_BASE) 429 #define NRF_RADIOCORE_DPPIC020_NS ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_NS_BASE) 430 #define NRF_RADIOCORE_DPPIC020_S ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_S_BASE) 431 #define NRF_RADIOCORE_PPIB020_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB020_S_BASE) 432 #define NRF_RADIOCORE_EGU020_NS ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_NS_BASE) 433 #define NRF_RADIOCORE_EGU020_S ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_S_BASE) 434 #define NRF_RADIOCORE_TIMER020_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_NS_BASE) 435 #define NRF_RADIOCORE_TIMER020_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_S_BASE) 436 #define NRF_RADIOCORE_TIMER021_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_NS_BASE) 437 #define NRF_RADIOCORE_TIMER021_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_S_BASE) 438 #define NRF_RADIOCORE_TIMER022_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_NS_BASE) 439 #define NRF_RADIOCORE_TIMER022_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_S_BASE) 440 #define NRF_RADIOCORE_RTC_NS ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_NS_BASE) 441 #define NRF_RADIOCORE_RTC_S ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_S_BASE) 442 #define NRF_RADIOCORE_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_NS_BASE) 443 #define NRF_RADIOCORE_RADIO_S ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_S_BASE) 444 #define NRF_RADIOCORE_LRCCONF020_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF020_S_BASE) 445 #define NRF_RADIOCORE_SPU030_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU030_S_BASE) 446 #define NRF_RADIOCORE_PPIB030_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB030_S_BASE) 447 #define NRF_RADIOCORE_VPR_NS ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_NS_BASE) 448 #define NRF_RADIOCORE_VPR_S ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_S_BASE) 449 #define NRF_RADIOCORE_RAMC001_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_NS_BASE) 450 #define NRF_RADIOCORE_RAMC001_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_S_BASE) 451 #define NRF_RADIOCORE_AAR030_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_NS_BASE) 452 #define NRF_RADIOCORE_CCM030_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_NS_BASE) 453 #define NRF_RADIOCORE_AAR030_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_S_BASE) 454 #define NRF_RADIOCORE_CCM030_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_S_BASE) 455 #define NRF_RADIOCORE_ECB030_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_NS_BASE) 456 #define NRF_RADIOCORE_ECB030_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_S_BASE) 457 #define NRF_RADIOCORE_AAR031_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR031_NS_BASE) 458 #define NRF_RADIOCORE_CCM031_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM031_NS_BASE) 459 #define NRF_RADIOCORE_AAR031_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR031_S_BASE) 460 #define NRF_RADIOCORE_CCM031_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM031_S_BASE) 461 #define NRF_RADIOCORE_ECB031_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB031_NS_BASE) 462 #define NRF_RADIOCORE_ECB031_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB031_S_BASE) 463 #define NRF_RADIOCORE_IPCT_NS ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_NS_BASE) 464 #define NRF_RADIOCORE_IPCT_S ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_S_BASE) 465 #define NRF_RADIOCORE_SWI0_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI0_NS_BASE) 466 #define NRF_RADIOCORE_SWI1_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI1_NS_BASE) 467 #define NRF_RADIOCORE_SWI2_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI2_NS_BASE) 468 #define NRF_RADIOCORE_SWI3_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI3_NS_BASE) 469 #define NRF_RADIOCORE_SWI4_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI4_NS_BASE) 470 #define NRF_RADIOCORE_SWI5_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI5_NS_BASE) 471 #define NRF_RADIOCORE_SWI6_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI6_NS_BASE) 472 #define NRF_RADIOCORE_SWI7_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI7_NS_BASE) 473 #define NRF_RADIOCORE_BELLBOARD_NS ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_NS_BASE) 474 #define NRF_RADIOCORE_BELLBOARD_S ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_S_BASE) 475 476 /* =========================================================================================================================== */ 477 /* ================ TrustZone Remapping ================ */ 478 /* =========================================================================================================================== */ 479 480 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 481 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 482 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 483 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_NS 484 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_NS 485 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_NS 486 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_NS 487 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_NS 488 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_NS 489 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_NS 490 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_NS 491 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_NS 492 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_NS 493 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_NS 494 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_NS 495 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_NS 496 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_NS 497 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_NS 498 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_NS 499 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_NS 500 #define NRF_RADIOCORE_AAR031 NRF_RADIOCORE_AAR031_NS 501 #define NRF_RADIOCORE_CCM031 NRF_RADIOCORE_CCM031_NS 502 #define NRF_RADIOCORE_ECB031 NRF_RADIOCORE_ECB031_NS 503 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_NS 504 #define NRF_RADIOCORE_SWI0 NRF_RADIOCORE_SWI0_NS 505 #define NRF_RADIOCORE_SWI1 NRF_RADIOCORE_SWI1_NS 506 #define NRF_RADIOCORE_SWI2 NRF_RADIOCORE_SWI2_NS 507 #define NRF_RADIOCORE_SWI3 NRF_RADIOCORE_SWI3_NS 508 #define NRF_RADIOCORE_SWI4 NRF_RADIOCORE_SWI4_NS 509 #define NRF_RADIOCORE_SWI5 NRF_RADIOCORE_SWI5_NS 510 #define NRF_RADIOCORE_SWI6 NRF_RADIOCORE_SWI6_NS 511 #define NRF_RADIOCORE_SWI7 NRF_RADIOCORE_SWI7_NS 512 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_NS 513 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 514 #define NRF_RADIOCORE_ICACHEDATA NRF_RADIOCORE_ICACHEDATA_S 515 #define NRF_RADIOCORE_ICACHEINFO NRF_RADIOCORE_ICACHEINFO_S 516 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 517 #define NRF_RADIOCORE_DCACHEDATA NRF_RADIOCORE_DCACHEDATA_S 518 #define NRF_RADIOCORE_DCACHEINFO NRF_RADIOCORE_DCACHEINFO_S 519 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 520 #define NRF_RADIOCORE_CTI NRF_RADIOCORE_CTI_S 521 #define NRF_RADIOCORE_CPUC NRF_RADIOCORE_CPUC_S 522 #define NRF_RADIOCORE_ICACHE NRF_RADIOCORE_ICACHE_S 523 #define NRF_RADIOCORE_DCACHE NRF_RADIOCORE_DCACHE_S 524 #define NRF_RADIOCORE_SPU000 NRF_RADIOCORE_SPU000_S 525 #define NRF_RADIOCORE_MPC NRF_RADIOCORE_MPC_S 526 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_S 527 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_S 528 #define NRF_RADIOCORE_HSFLL NRF_RADIOCORE_HSFLL_S 529 #define NRF_RADIOCORE_LRCCONF000 NRF_RADIOCORE_LRCCONF000_S 530 #define NRF_RADIOCORE_SPU010 NRF_RADIOCORE_SPU010_S 531 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_S 532 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_S 533 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_S 534 #define NRF_RADIOCORE_LRCCONF010 NRF_RADIOCORE_LRCCONF010_S 535 #define NRF_RADIOCORE_RESETINFO NRF_RADIOCORE_RESETINFO_S 536 #define NRF_RADIOCORE_SPU020 NRF_RADIOCORE_SPU020_S 537 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_S 538 #define NRF_RADIOCORE_PPIB020 NRF_RADIOCORE_PPIB020_S 539 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_S 540 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_S 541 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_S 542 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_S 543 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_S 544 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_S 545 #define NRF_RADIOCORE_LRCCONF020 NRF_RADIOCORE_LRCCONF020_S 546 #define NRF_RADIOCORE_SPU030 NRF_RADIOCORE_SPU030_S 547 #define NRF_RADIOCORE_PPIB030 NRF_RADIOCORE_PPIB030_S 548 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_S 549 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_S 550 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_S 551 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_S 552 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_S 553 #define NRF_RADIOCORE_AAR031 NRF_RADIOCORE_AAR031_S 554 #define NRF_RADIOCORE_CCM031 NRF_RADIOCORE_CCM031_S 555 #define NRF_RADIOCORE_ECB031 NRF_RADIOCORE_ECB031_S 556 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_S 557 #define NRF_RADIOCORE_SWI0 NRF_RADIOCORE_SWI0_NS 558 #define NRF_RADIOCORE_SWI1 NRF_RADIOCORE_SWI1_NS 559 #define NRF_RADIOCORE_SWI2 NRF_RADIOCORE_SWI2_NS 560 #define NRF_RADIOCORE_SWI3 NRF_RADIOCORE_SWI3_NS 561 #define NRF_RADIOCORE_SWI4 NRF_RADIOCORE_SWI4_NS 562 #define NRF_RADIOCORE_SWI5 NRF_RADIOCORE_SWI5_NS 563 #define NRF_RADIOCORE_SWI6 NRF_RADIOCORE_SWI6_NS 564 #define NRF_RADIOCORE_SWI7 NRF_RADIOCORE_SWI7_NS 565 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_S 566 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 567 568 /* =========================================================================================================================== */ 569 /* ================ Local Domain Remapping ================ */ 570 /* =========================================================================================================================== */ 571 572 #ifdef NRF_RADIOCORE /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 573 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 574 #define NRF_UICR NRF_RADIOCORE_UICR 575 #define NRF_ETM NRF_RADIOCORE_ETM 576 #define NRF_MVDMA NRF_RADIOCORE_MVDMA 577 #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 578 #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF 579 #define NRF_WDT010 NRF_RADIOCORE_WDT010 580 #define NRF_WDT011 NRF_RADIOCORE_WDT011 581 #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 582 #define NRF_EGU020 NRF_RADIOCORE_EGU020 583 #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 584 #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 585 #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 586 #define NRF_RTC NRF_RADIOCORE_RTC 587 #define NRF_RADIO NRF_RADIOCORE_RADIO 588 #define NRF_VPR NRF_RADIOCORE_VPR 589 #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 590 #define NRF_AAR030 NRF_RADIOCORE_AAR030 591 #define NRF_CCM030 NRF_RADIOCORE_CCM030 592 #define NRF_ECB030 NRF_RADIOCORE_ECB030 593 #define NRF_AAR031 NRF_RADIOCORE_AAR031 594 #define NRF_CCM031 NRF_RADIOCORE_CCM031 595 #define NRF_ECB031 NRF_RADIOCORE_ECB031 596 #define NRF_IPCT NRF_RADIOCORE_IPCT 597 #define NRF_SWI0 NRF_RADIOCORE_SWI0 598 #define NRF_SWI1 NRF_RADIOCORE_SWI1 599 #define NRF_SWI2 NRF_RADIOCORE_SWI2 600 #define NRF_SWI3 NRF_RADIOCORE_SWI3 601 #define NRF_SWI4 NRF_RADIOCORE_SWI4 602 #define NRF_SWI5 NRF_RADIOCORE_SWI5 603 #define NRF_SWI6 NRF_RADIOCORE_SWI6 604 #define NRF_SWI7 NRF_RADIOCORE_SWI7 605 #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD 606 #else /*!< Remap all instances. */ 607 #define NRF_ICACHEDATA NRF_RADIOCORE_ICACHEDATA 608 #define NRF_ICACHEINFO NRF_RADIOCORE_ICACHEINFO 609 #define NRF_UICR NRF_RADIOCORE_UICR 610 #define NRF_DCACHEDATA NRF_RADIOCORE_DCACHEDATA 611 #define NRF_DCACHEINFO NRF_RADIOCORE_DCACHEINFO 612 #define NRF_ETM NRF_RADIOCORE_ETM 613 #define NRF_CTI NRF_RADIOCORE_CTI 614 #define NRF_CPUC NRF_RADIOCORE_CPUC 615 #define NRF_ICACHE NRF_RADIOCORE_ICACHE 616 #define NRF_DCACHE NRF_RADIOCORE_DCACHE 617 #define NRF_SPU000 NRF_RADIOCORE_SPU000 618 #define NRF_MPC NRF_RADIOCORE_MPC 619 #define NRF_MVDMA NRF_RADIOCORE_MVDMA 620 #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 621 #define NRF_HSFLL NRF_RADIOCORE_HSFLL 622 #define NRF_LRCCONF000 NRF_RADIOCORE_LRCCONF000 623 #define NRF_SPU010 NRF_RADIOCORE_SPU010 624 #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF 625 #define NRF_WDT010 NRF_RADIOCORE_WDT010 626 #define NRF_WDT011 NRF_RADIOCORE_WDT011 627 #define NRF_LRCCONF010 NRF_RADIOCORE_LRCCONF010 628 #define NRF_RESETINFO NRF_RADIOCORE_RESETINFO 629 #define NRF_SPU020 NRF_RADIOCORE_SPU020 630 #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 631 #define NRF_PPIB020 NRF_RADIOCORE_PPIB020 632 #define NRF_EGU020 NRF_RADIOCORE_EGU020 633 #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 634 #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 635 #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 636 #define NRF_RTC NRF_RADIOCORE_RTC 637 #define NRF_RADIO NRF_RADIOCORE_RADIO 638 #define NRF_LRCCONF020 NRF_RADIOCORE_LRCCONF020 639 #define NRF_SPU030 NRF_RADIOCORE_SPU030 640 #define NRF_PPIB030 NRF_RADIOCORE_PPIB030 641 #define NRF_VPR NRF_RADIOCORE_VPR 642 #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 643 #define NRF_AAR030 NRF_RADIOCORE_AAR030 644 #define NRF_CCM030 NRF_RADIOCORE_CCM030 645 #define NRF_ECB030 NRF_RADIOCORE_ECB030 646 #define NRF_AAR031 NRF_RADIOCORE_AAR031 647 #define NRF_CCM031 NRF_RADIOCORE_CCM031 648 #define NRF_ECB031 NRF_RADIOCORE_ECB031 649 #define NRF_IPCT NRF_RADIOCORE_IPCT 650 #define NRF_SWI0 NRF_RADIOCORE_SWI0 651 #define NRF_SWI1 NRF_RADIOCORE_SWI1 652 #define NRF_SWI2 NRF_RADIOCORE_SWI2 653 #define NRF_SWI3 NRF_RADIOCORE_SWI3 654 #define NRF_SWI4 NRF_RADIOCORE_SWI4 655 #define NRF_SWI5 NRF_RADIOCORE_SWI5 656 #define NRF_SWI6 NRF_RADIOCORE_SWI6 657 #define NRF_SWI7 NRF_RADIOCORE_SWI7 658 #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD 659 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 660 #endif /*!< NRF_RADIOCORE */ 661 662 /* ========================================== End of section using anonymous unions ========================================== */ 663 664 #if defined (__CC_ARM) 665 #pragma pop 666 #elif defined (__ICCARM__) 667 /* leave anonymous unions enabled */ 668 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 669 #pragma clang diagnostic pop 670 #elif defined (__GNUC__) 671 /* anonymous unions are enabled by default */ 672 #elif defined (__TMS470__) 673 /* anonymous unions are enabled by default */ 674 #elif defined (__TASKING__) 675 #pragma warning restore 676 #elif defined (__CSMC__) 677 /* anonymous unions are enabled by default */ 678 #endif 679 680 681 #ifdef __cplusplus 682 } 683 #endif 684 #endif /* NRF9230_ENGA_RADIOCORE_H */ 685 686
