1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF9230_ENGA_PPR_PERIPHERALS_H 36 #define NRF9230_ENGA_PPR_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*VPR CSR registers*/ 44 #define VPRCSR_PRESENT 1 45 #define VPRCSR_COUNT 1 46 47 #define VPRCSR_HARTNUM 11 /*!< HARTNUM: 11 */ 48 #define VPRCSR_MCLICBASERESET 0x5F909000 /*!< MCLICBASE: 0x5F909000 */ 49 #define VPRCSR_MULDIV 1 /*!< MULDIV: 1 */ 50 #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ 51 #define VPRCSR_DBG 1 /*!< DBG: 1 */ 52 #define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ 53 #define VPRCSR_BUSWIDTH 32 /*!< BUSWIDTH: 32 */ 54 #define VPRCSR_BKPT 1 /*!< BKPT: 1 */ 55 #define VPRCSR_VIOPINS 0x0000000F /*!< CSR VIOPINS value: 0x0000000F */ 56 #define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 57 #define VPRCSR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 58 #define VPRCSR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 59 #define VPRCSR_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ 60 #define VPRCSR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 61 #define VPRCSR_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 62 #define VPRCSR_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 63 #define VPRCSR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 64 #define VPRCSR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 65 #define VPRCSR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 66 #define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ 67 #define VPRCSR_CACHE_EN 0 /*!< (unspecified) */ 68 #define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ 69 #define VPRCSR_VPR_BUS_PRIO 0 /*!< (unspecified) */ 70 #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ 71 72 /*VPR CLIC registers*/ 73 #define CLIC_PRESENT 1 74 #define CLIC_COUNT 1 75 76 #define VPRCLIC_IRQ_COUNT 16 77 #define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ 78 #define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ 79 #define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ 80 #define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 81 #define VPRCLIC_CLIC_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 82 #define VPRCLIC_CLIC_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 83 #define VPRCLIC_CLIC_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ 84 #define VPRCLIC_COUNTER_IRQ_NUM 16 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 16 */ 85 #define VPRCLIC_CLIC_VPR_1_2 1 /*!< (unspecified) */ 86 87 /*VTIM CSR registers*/ 88 #define VTIM_PRESENT 1 89 #define VTIM_COUNT 1 90 91 /*Factory Information Configuration Registers*/ 92 #define FICR_PRESENT 1 93 #define FICR_COUNT 1 94 95 /*USBHSCORE*/ 96 #define USBHSCORE_PRESENT 1 97 #define USBHSCORE_COUNT 1 98 99 /*I3CCORE*/ 100 #define I3CCORE_PRESENT 1 101 #define I3CCORE_COUNT 2 102 103 /*DMU*/ 104 #define DMU_PRESENT 1 105 #define DMU_COUNT 2 106 107 /*MCAN*/ 108 #define MCAN_PRESENT 1 109 #define MCAN_COUNT 2 110 111 /*System Trace Macrocell data buffer*/ 112 #define STMDATA_PRESENT 1 113 #define STMDATA_COUNT 1 114 115 /*TDDCONF*/ 116 #define TDDCONF_PRESENT 1 117 #define TDDCONF_COUNT 1 118 119 #define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 0 /*!< (unspecified) */ 120 #define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 1 /*!< (unspecified) */ 121 122 /*System Trace Macrocell*/ 123 #define STM_PRESENT 1 124 #define STM_COUNT 1 125 126 /*Trace Port Interface Unit*/ 127 #define TPIU_PRESENT 1 128 #define TPIU_COUNT 1 129 130 /*Cross-Trigger Interface control*/ 131 #define CTI_PRESENT 1 132 #define CTI_COUNT 2 133 134 /*ATB Replicator module*/ 135 #define ATBREPLICATOR_PRESENT 1 136 #define ATBREPLICATOR_COUNT 4 137 138 /*ATB funnel module*/ 139 #define ATBFUNNEL_PRESENT 1 140 #define ATBFUNNEL_COUNT 4 141 142 /*GPIO Tasks and Events*/ 143 #define GPIOTE_PRESENT 1 144 #define GPIOTE_COUNT 2 145 146 #define GPIOTE130_IRQ_COUNT 2 147 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 148 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 149 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 150 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 151 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 152 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 153 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 154 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 155 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 156 #define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ 157 158 #define GPIOTE131_IRQ_COUNT 2 159 #define GPIOTE131_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 160 #define GPIOTE131_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 161 #define GPIOTE131_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 162 #define GPIOTE131_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 163 #define GPIOTE131_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 164 #define GPIOTE131_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 165 #define GPIOTE131_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 166 #define GPIOTE131_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 167 #define GPIOTE131_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 168 #define GPIOTE131_HAS_PORT_EVENT 1 /*!< (unspecified) */ 169 170 /*Global Real-time counter*/ 171 #define GRTC_PRESENT 1 172 #define GRTC_COUNT 1 173 174 #define GRTC_IRQ_COUNT 3 175 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 176 0..14*/ 177 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 178 0..14*/ 179 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 180 0..14*/ 181 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 182 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 183 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 184 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 185 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 186 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 187 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 188 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 189 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 190 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ 191 #define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ 192 #define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ 193 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 194 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 195 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 196 #define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ 197 #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ 198 #define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ 199 200 /*Trace buffer monitor*/ 201 #define TBM_PRESENT 1 202 #define TBM_COUNT 1 203 204 /*USBHS*/ 205 #define USBHS_PRESENT 1 206 #define USBHS_COUNT 1 207 208 /*External Memory Interface*/ 209 #define EXMIF_PRESENT 1 210 #define EXMIF_COUNT 1 211 212 /*BELLBOARD public registers*/ 213 #define BELLBOARDPUBLIC_PRESENT 1 214 #define BELLBOARDPUBLIC_COUNT 1 215 216 /*VPR peripheral registers*/ 217 #define VPRPUBLIC_PRESENT 1 218 #define VPRPUBLIC_COUNT 1 219 220 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 221 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 222 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 223 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 224 225 /*IPCT APB registers*/ 226 #define IPCT_PRESENT 1 227 #define IPCT_COUNT 2 228 229 #define IPCT120_IRQ_COUNT 1 230 231 #define IPCT130_IRQ_COUNT 1 232 233 /*MUTEX*/ 234 #define MUTEX_PRESENT 1 235 #define MUTEX_COUNT 2 236 237 /*I3C*/ 238 #define I3C_PRESENT 1 239 #define I3C_COUNT 2 240 241 /*VPR peripheral registers*/ 242 #define VPR_PRESENT 1 243 #define VPR_COUNT 2 244 245 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 246 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 247 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 248 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 249 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 250 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 251 #define VPR121_RETAINED 0 /*!< (unspecified) */ 252 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 253 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 254 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 255 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 256 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 257 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 258 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 259 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 260 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 261 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 262 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 263 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 264 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 265 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 266 267 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 268 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 269 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 270 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 271 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 272 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 273 #define VPR130_RETAINED 1 /*!< (unspecified) */ 274 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 275 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 276 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 277 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 278 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 279 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 280 #define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ 281 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 282 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 283 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 284 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 285 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 286 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 287 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 288 289 /*Controller Area Network*/ 290 #define CAN_PRESENT 1 291 #define CAN_COUNT 2 292 293 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 294 295 #define MVDMA_PRESENT 1 296 #define MVDMA_COUNT 2 297 298 #define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ 299 #define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ 300 #define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ 301 302 #define MVDMA121_COMPLETED_EVENT 1 /*!< (unspecified) */ 303 #define MVDMA121_DPPI_DISCONNECTED 1 /*!< (unspecified) */ 304 #define MVDMA121_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ 305 306 /*RAM Controller*/ 307 #define RAMC_PRESENT 1 308 #define RAMC_COUNT 2 309 310 #define RAMC122_ECC 0 /*!< (unspecified) */ 311 #define RAMC122_SEC 0 /*!< (unspecified) */ 312 313 #define RAMC123_ECC 0 /*!< (unspecified) */ 314 #define RAMC123_SEC 0 /*!< (unspecified) */ 315 316 /*Distributed programmable peripheral interconnect controller*/ 317 #define DPPIC_PRESENT 1 318 #define DPPIC_COUNT 8 319 320 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 321 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 322 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 323 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 324 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 325 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 326 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 327 328 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 329 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 330 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 331 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 332 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 333 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 334 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 335 336 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 337 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 338 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 339 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 340 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 341 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 342 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 343 344 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 345 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 346 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 347 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 348 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 349 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 350 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 351 352 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 353 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 354 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 355 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 356 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 357 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 358 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 359 360 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 361 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 362 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 363 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 364 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 365 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 366 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 367 368 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 369 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 370 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 371 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 372 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 373 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 374 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 375 376 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 377 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 378 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 379 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 380 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 381 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 382 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 383 384 /*Timer/Counter*/ 385 #define TIMER_PRESENT 1 386 #define TIMER_COUNT 10 387 388 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 389 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 390 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 391 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 392 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 393 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 394 #define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 395 #define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ 396 397 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 398 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 399 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 400 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 401 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 402 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 403 #define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 404 #define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ 405 406 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 407 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 408 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 409 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 410 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 411 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 412 #define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 413 #define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ 414 415 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 416 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 417 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 418 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 419 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 420 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 421 #define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 422 #define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ 423 424 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 425 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 426 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 427 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 428 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 429 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 430 #define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 431 #define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ 432 433 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 434 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 435 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 436 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 437 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 438 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 439 #define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 440 #define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ 441 442 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 443 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 444 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 445 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 446 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 447 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 448 #define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 449 #define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ 450 451 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 452 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 453 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 454 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 455 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 456 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 457 #define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 458 #define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ 459 460 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 461 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 462 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 463 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 464 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 465 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 466 #define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 467 #define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ 468 469 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 470 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 471 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 472 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 473 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 474 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 475 #define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 476 #define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ 477 478 /*Pulse width modulation unit*/ 479 #define PWM_PRESENT 1 480 #define PWM_COUNT 5 481 482 #define PWM120_IDLE_OUT 1 /*!< (unspecified) */ 483 #define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ 484 #define PWM120_FEATURES_V2 0 /*!< (unspecified) */ 485 #define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ 486 #define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 487 488 #define PWM130_IDLE_OUT 1 /*!< (unspecified) */ 489 #define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ 490 #define PWM130_FEATURES_V2 0 /*!< (unspecified) */ 491 #define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ 492 #define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 493 494 #define PWM131_IDLE_OUT 1 /*!< (unspecified) */ 495 #define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ 496 #define PWM131_FEATURES_V2 0 /*!< (unspecified) */ 497 #define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ 498 #define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 499 500 #define PWM132_IDLE_OUT 1 /*!< (unspecified) */ 501 #define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ 502 #define PWM132_FEATURES_V2 0 /*!< (unspecified) */ 503 #define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ 504 #define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 505 506 #define PWM133_IDLE_OUT 1 /*!< (unspecified) */ 507 #define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ 508 #define PWM133_FEATURES_V2 0 /*!< (unspecified) */ 509 #define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ 510 #define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 511 512 /*SPI Slave*/ 513 #define SPIS_PRESENT 1 514 #define SPIS_COUNT 9 515 516 #define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 517 #define SPIS120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 518 #define SPIS120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 519 #define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 520 521 #define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 522 #define SPIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 523 #define SPIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 524 #define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 525 526 #define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 527 #define SPIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 528 #define SPIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 529 #define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 530 531 #define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 532 #define SPIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 533 #define SPIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 534 #define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 535 536 #define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 537 #define SPIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 538 #define SPIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 539 #define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 540 541 #define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 542 #define SPIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 543 #define SPIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 544 #define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 545 546 #define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 547 #define SPIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 548 #define SPIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 549 #define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 550 551 #define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 552 #define SPIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 553 #define SPIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 554 #define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 555 556 #define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 557 #define SPIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 558 #define SPIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 559 #define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 560 561 /*Serial Peripheral Interface Master with EasyDMA*/ 562 #define SPIM_PRESENT 1 563 #define SPIM_COUNT 10 564 565 #define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 566 #define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ 567 #define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 568 #define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 569 #define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 570 #define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 571 #define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 572 #define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 573 #define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 574 #define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 575 #define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 576 #define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 577 #define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 578 #define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 579 #define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ 580 #define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 581 #define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 582 #define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 583 #define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 584 #define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 585 #define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 586 #define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 587 #define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 588 #define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 589 #define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 590 591 #define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 592 #define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ 593 #define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 594 #define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 595 #define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 596 #define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 597 #define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 598 #define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 599 #define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 600 #define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 601 #define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 602 #define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 603 #define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 604 #define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 605 #define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ 606 #define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 607 #define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 608 #define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 609 #define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 610 #define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 611 #define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 612 #define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 613 #define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 614 #define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 615 #define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 616 617 #define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 618 #define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ 619 #define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 620 #define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 621 #define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 622 #define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 623 #define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 624 #define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 625 #define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 626 #define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 627 #define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 628 #define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 629 #define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 630 #define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 631 #define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ 632 #define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 633 #define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 634 #define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 635 #define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 636 #define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 637 #define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 638 #define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 639 #define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 640 #define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 641 #define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 642 643 #define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 644 #define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ 645 #define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 646 #define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 647 #define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 648 #define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 649 #define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 650 #define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 651 #define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 652 #define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 653 #define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 654 #define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 655 #define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 656 #define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 657 #define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ 658 #define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 659 #define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 660 #define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 661 #define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 662 #define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 663 #define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 664 #define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 665 #define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 666 #define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 667 #define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 668 669 #define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 670 #define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ 671 #define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 672 #define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 673 #define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 674 #define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 675 #define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 676 #define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 677 #define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 678 #define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 679 #define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 680 #define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 681 #define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 682 #define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 683 #define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ 684 #define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 685 #define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 686 #define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 687 #define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 688 #define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 689 #define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 690 #define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 691 #define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 692 #define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 693 #define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 694 695 #define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 696 #define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ 697 #define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 698 #define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 699 #define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 700 #define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 701 #define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 702 #define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 703 #define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 704 #define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 705 #define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 706 #define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 707 #define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 708 #define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 709 #define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ 710 #define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 711 #define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 712 #define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 713 #define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 714 #define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 715 #define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 716 #define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 717 #define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 718 #define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 719 #define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 720 721 #define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 722 #define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ 723 #define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 724 #define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 725 #define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 726 #define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 727 #define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 728 #define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 729 #define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 730 #define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 731 #define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 732 #define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 733 #define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 734 #define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 735 #define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ 736 #define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 737 #define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 738 #define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 739 #define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 740 #define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 741 #define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 742 #define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 743 #define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 744 #define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 745 #define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 746 747 #define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 748 #define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ 749 #define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 750 #define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 751 #define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 752 #define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 753 #define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 754 #define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 755 #define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 756 #define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 757 #define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 758 #define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 759 #define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 760 #define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 761 #define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ 762 #define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 763 #define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 764 #define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 765 #define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 766 #define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 767 #define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 768 #define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 769 #define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 770 #define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 771 #define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 772 773 #define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 774 #define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ 775 #define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 776 #define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 777 #define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 778 #define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 779 #define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 780 #define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 781 #define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 782 #define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 783 #define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 784 #define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 785 #define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 786 #define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 787 #define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ 788 #define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 789 #define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 790 #define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 791 #define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 792 #define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 793 #define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 794 #define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 795 #define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 796 #define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 797 #define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 798 799 #define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 800 #define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ 801 #define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 802 #define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 803 #define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 804 #define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 805 #define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 806 #define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 807 #define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 808 #define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 809 #define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 810 #define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 811 #define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 812 #define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 813 #define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ 814 #define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 815 #define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 816 #define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 817 #define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 818 #define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 819 #define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 820 #define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 821 #define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 822 #define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 823 #define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 824 825 /*UART with EasyDMA*/ 826 #define UARTE_PRESENT 1 827 #define UARTE_COUNT 9 828 829 #define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 830 #define UARTE120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 831 #define UARTE120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 832 #define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 833 #define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 834 #define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ 835 #define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ 836 #define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 837 #define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 838 839 #define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 840 #define UARTE130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 841 #define UARTE130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 842 #define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 843 #define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 844 #define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 845 #define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ 846 #define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 847 #define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 848 849 #define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 850 #define UARTE131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 851 #define UARTE131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 852 #define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 853 #define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 854 #define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 855 #define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ 856 #define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 857 #define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 858 859 #define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 860 #define UARTE132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 861 #define UARTE132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 862 #define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 863 #define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 864 #define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 865 #define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ 866 #define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 867 #define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 868 869 #define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 870 #define UARTE133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 871 #define UARTE133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 872 #define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 873 #define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 874 #define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 875 #define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ 876 #define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 877 #define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 878 879 #define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 880 #define UARTE134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 881 #define UARTE134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 882 #define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 883 #define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 884 #define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 885 #define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ 886 #define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 887 #define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 888 889 #define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 890 #define UARTE135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 891 #define UARTE135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 892 #define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 893 #define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 894 #define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 895 #define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ 896 #define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 897 #define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 898 899 #define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 900 #define UARTE136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 901 #define UARTE136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 902 #define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 903 #define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 904 #define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 905 #define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ 906 #define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 907 #define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 908 909 #define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 910 #define UARTE137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 911 #define UARTE137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 912 #define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 913 #define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 914 #define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 915 #define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ 916 #define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 917 #define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 918 919 /*Real-time counter*/ 920 #define RTC_PRESENT 1 921 #define RTC_COUNT 2 922 923 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 924 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 925 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 926 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 927 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 928 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 929 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 930 931 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 932 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 933 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 934 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 935 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 936 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 937 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 938 939 /*Watchdog Timer*/ 940 #define WDT_PRESENT 1 941 #define WDT_COUNT 2 942 943 #define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ 944 #define WDT131_HAS_INTEN 0 /*!< (unspecified) */ 945 946 #define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ 947 #define WDT132_HAS_INTEN 0 /*!< (unspecified) */ 948 949 /*Event generator unit*/ 950 #define EGU_PRESENT 1 951 #define EGU_COUNT 1 952 953 #define EGU130_PEND 0 /*!< (unspecified) */ 954 #define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ 955 #define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ 956 #define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ 957 958 /*GPIO Port*/ 959 #define GPIO_PRESENT 1 960 #define GPIO_COUNT 10 961 962 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 963 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 964 #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ 965 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 966 #define P0_PIN_NUM_MAX 12 /*!< (unspecified) */ 967 #define P0_PIN_NUM_SIZE 13 /*!< (unspecified) */ 968 #define P0_FEATURE_PINS_PRESENT 0x00001FFFUL /*!< (unspecified) */ 969 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 970 #define P0_RETAIN 1 /*!< (unspecified) */ 971 #define P0_PWRCTRL 0 /*!< (unspecified) */ 972 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 973 #define P0_BIASCTRL 0 /*!< (unspecified) */ 974 975 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 976 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 977 #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ 978 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 979 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 980 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 981 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 982 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 983 #define P1_RETAIN 1 /*!< (unspecified) */ 984 #define P1_PWRCTRL 0 /*!< (unspecified) */ 985 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 986 #define P1_BIASCTRL 0 /*!< (unspecified) */ 987 988 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 989 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 990 #define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ 991 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 992 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 993 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 994 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 995 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 996 #define P2_RETAIN 1 /*!< (unspecified) */ 997 #define P2_PWRCTRL 0 /*!< (unspecified) */ 998 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 999 #define P2_BIASCTRL 0 /*!< (unspecified) */ 1000 1001 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1002 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1003 #define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1004 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 1005 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 1006 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 1007 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 1008 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 1009 #define P6_RETAIN 1 /*!< (unspecified) */ 1010 #define P6_PWRCTRL 0 /*!< (unspecified) */ 1011 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1012 #define P6_BIASCTRL 0 /*!< (unspecified) */ 1013 1014 #define P8_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1015 #define P8_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1016 #define P8_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1017 #define P8_PIN_NUM_MIN 0 /*!< (unspecified) */ 1018 #define P8_PIN_NUM_MAX 4 /*!< (unspecified) */ 1019 #define P8_PIN_NUM_SIZE 5 /*!< (unspecified) */ 1020 #define P8_FEATURE_PINS_PRESENT 0x0000001FUL /*!< (unspecified) */ 1021 #define P8_DRIVECTRL 1 /*!< (unspecified) */ 1022 #define P8_RETAIN 1 /*!< (unspecified) */ 1023 #define P8_PWRCTRL 0 /*!< (unspecified) */ 1024 #define P8_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1025 #define P8_BIASCTRL 0 /*!< (unspecified) */ 1026 1027 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1028 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1029 #define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1030 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 1031 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 1032 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 1033 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 1034 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 1035 #define P9_RETAIN 1 /*!< (unspecified) */ 1036 #define P9_PWRCTRL 1 /*!< (unspecified) */ 1037 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1038 #define P9_BIASCTRL 0 /*!< (unspecified) */ 1039 1040 #define P10_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1041 #define P10_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1042 #define P10_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1043 #define P10_PIN_NUM_MIN 0 /*!< (unspecified) */ 1044 #define P10_PIN_NUM_MAX 7 /*!< (unspecified) */ 1045 #define P10_PIN_NUM_SIZE 8 /*!< (unspecified) */ 1046 #define P10_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 1047 #define P10_DRIVECTRL 0 /*!< (unspecified) */ 1048 #define P10_RETAIN 1 /*!< (unspecified) */ 1049 #define P10_PWRCTRL 0 /*!< (unspecified) */ 1050 #define P10_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1051 #define P10_BIASCTRL 0 /*!< (unspecified) */ 1052 1053 #define P11_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1054 #define P11_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1055 #define P11_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1056 #define P11_PIN_NUM_MIN 0 /*!< (unspecified) */ 1057 #define P11_PIN_NUM_MAX 7 /*!< (unspecified) */ 1058 #define P11_PIN_NUM_SIZE 8 /*!< (unspecified) */ 1059 #define P11_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 1060 #define P11_DRIVECTRL 0 /*!< (unspecified) */ 1061 #define P11_RETAIN 1 /*!< (unspecified) */ 1062 #define P11_PWRCTRL 0 /*!< (unspecified) */ 1063 #define P11_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1064 #define P11_BIASCTRL 0 /*!< (unspecified) */ 1065 1066 #define P12_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1067 #define P12_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1068 #define P12_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1069 #define P12_PIN_NUM_MIN 0 /*!< (unspecified) */ 1070 #define P12_PIN_NUM_MAX 2 /*!< (unspecified) */ 1071 #define P12_PIN_NUM_SIZE 3 /*!< (unspecified) */ 1072 #define P12_FEATURE_PINS_PRESENT 0x00000007UL /*!< (unspecified) */ 1073 #define P12_DRIVECTRL 0 /*!< (unspecified) */ 1074 #define P12_RETAIN 1 /*!< (unspecified) */ 1075 #define P12_PWRCTRL 0 /*!< (unspecified) */ 1076 #define P12_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1077 #define P12_BIASCTRL 0 /*!< (unspecified) */ 1078 1079 #define P13_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1080 #define P13_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1081 #define P13_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1082 #define P13_PIN_NUM_MIN 0 /*!< (unspecified) */ 1083 #define P13_PIN_NUM_MAX 3 /*!< (unspecified) */ 1084 #define P13_PIN_NUM_SIZE 4 /*!< (unspecified) */ 1085 #define P13_FEATURE_PINS_PRESENT 0x0000000FUL /*!< (unspecified) */ 1086 #define P13_DRIVECTRL 0 /*!< (unspecified) */ 1087 #define P13_RETAIN 1 /*!< (unspecified) */ 1088 #define P13_PWRCTRL 0 /*!< (unspecified) */ 1089 #define P13_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1090 #define P13_BIASCTRL 0 /*!< (unspecified) */ 1091 1092 /*Analog to Digital Converter*/ 1093 #define SAADC_PRESENT 1 1094 #define SAADC_COUNT 1 1095 1096 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 1097 #define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ 1098 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1099 1100 /*Comparator*/ 1101 #define COMP_PRESENT 1 1102 #define COMP_COUNT 1 1103 1104 /*Low-power comparator*/ 1105 #define LPCOMP_PRESENT 1 1106 #define LPCOMP_COUNT 1 1107 1108 /*Temperature Sensor*/ 1109 #define TEMP_PRESENT 1 1110 #define TEMP_COUNT 1 1111 1112 /*Inter-IC Sound*/ 1113 #define I2S_PRESENT 1 1114 #define I2S_COUNT 2 1115 1116 /*Pulse Density Modulation (Digital Microphone) Interface*/ 1117 #define PDM_PRESENT 1 1118 #define PDM_COUNT 1 1119 1120 #define PDM_SAMPLE16 1 /*!< (unspecified) */ 1121 #define PDM_SAMPLE48 0 /*!< (unspecified) */ 1122 #define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1123 1124 /*Quadrature Decoder*/ 1125 #define QDEC_PRESENT 1 1126 #define QDEC_COUNT 2 1127 1128 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 1129 #define TWIM_PRESENT 1 1130 #define TWIM_COUNT 8 1131 1132 #define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1133 #define TWIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1134 #define TWIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1135 #define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1136 1137 #define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1138 #define TWIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1139 #define TWIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1140 #define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1141 1142 #define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1143 #define TWIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1144 #define TWIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1145 #define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1146 1147 #define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1148 #define TWIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1149 #define TWIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1150 #define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1151 1152 #define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1153 #define TWIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1154 #define TWIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1155 #define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1156 1157 #define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1158 #define TWIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1159 #define TWIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1160 #define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1161 1162 #define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1163 #define TWIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1164 #define TWIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1165 #define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1166 1167 #define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1168 #define TWIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1169 #define TWIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1170 #define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1171 1172 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 1173 #define TWIS_PRESENT 1 1174 #define TWIS_COUNT 8 1175 1176 #define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1177 #define TWIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1178 #define TWIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1179 #define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1180 1181 #define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1182 #define TWIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1183 #define TWIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1184 #define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1185 1186 #define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1187 #define TWIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1188 #define TWIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1189 #define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1190 1191 #define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1192 #define TWIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1193 #define TWIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1194 #define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1195 1196 #define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1197 #define TWIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1198 #define TWIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1199 #define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1200 1201 #define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1202 #define TWIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1203 #define TWIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1204 #define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1205 1206 #define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1207 #define TWIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1208 #define TWIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1209 #define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1210 1211 #define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1212 #define TWIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 1213 #define TWIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 1214 #define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1215 1216 1217 #ifdef __cplusplus 1218 } 1219 #endif 1220 #endif /* NRF9230_ENGA_PPR_PERIPHERALS_H */ 1221 1222
