1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF9230_ENGA_FLPR_H 36 #define NRF9230_ENGA_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 VPRTIM_IRQn = 32, /*!< 32 VPRTIM */ 86 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 87 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 88 GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ 89 GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ 90 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 91 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 92 GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ 93 TBM_IRQn = 127, /*!< 127 TBM */ 94 USBHS_IRQn = 134, /*!< 134 USBHS */ 95 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 96 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 97 I3C120_IRQn = 211, /*!< 211 I3C120 */ 98 VPR121_IRQn = 212, /*!< 212 VPR121 */ 99 CAN120_IRQn = 216, /*!< 216 CAN120 */ 100 MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ 101 CAN121_IRQn = 219, /*!< 219 CAN121 */ 102 MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ 103 I3C121_IRQn = 222, /*!< 222 I3C121 */ 104 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 105 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 106 PWM120_IRQn = 228, /*!< 228 PWM120 */ 107 SPIS120_IRQn = 229, /*!< 229 SPIS120 */ 108 SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ 109 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 110 VPR130_IRQn = 264, /*!< 264 VPR130 */ 111 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 112 RTC130_IRQn = 296, /*!< 296 RTC130 */ 113 RTC131_IRQn = 297, /*!< 297 RTC131 */ 114 WDT131_IRQn = 299, /*!< 299 WDT131 */ 115 WDT132_IRQn = 300, /*!< 300 WDT132 */ 116 EGU130_IRQn = 301, /*!< 301 EGU130 */ 117 SAADC_IRQn = 386, /*!< 386 SAADC */ 118 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 119 TEMP_IRQn = 388, /*!< 388 TEMP */ 120 I2S130_IRQn = 402, /*!< 402 I2S130 */ 121 PDM_IRQn = 403, /*!< 403 PDM */ 122 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 123 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 124 I2S131_IRQn = 407, /*!< 407 I2S131 */ 125 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 126 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 127 PWM130_IRQn = 420, /*!< 420 PWM130 */ 128 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 129 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 130 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 131 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 132 PWM131_IRQn = 436, /*!< 436 PWM131 */ 133 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 134 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 135 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 136 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 137 PWM132_IRQn = 452, /*!< 452 PWM132 */ 138 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 139 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 140 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 141 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 142 PWM133_IRQn = 468, /*!< 468 PWM133 */ 143 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 144 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 145 } IRQn_Type; 146 147 /* ==================================================== Interrupt Aliases ==================================================== */ 148 #define SPIM120_IRQn SPIM120_UARTE120_IRQn 149 #define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler 150 #define UARTE120_IRQn SPIM120_UARTE120_IRQn 151 #define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler 152 #define COMP_IRQn COMP_LPCOMP_IRQn 153 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 154 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 155 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 156 #define SPIM130_IRQn SERIAL0_IRQn 157 #define SPIM130_IRQHandler SERIAL0_IRQHandler 158 #define SPIS130_IRQn SERIAL0_IRQn 159 #define SPIS130_IRQHandler SERIAL0_IRQHandler 160 #define TWIM130_IRQn SERIAL0_IRQn 161 #define TWIM130_IRQHandler SERIAL0_IRQHandler 162 #define TWIS130_IRQn SERIAL0_IRQn 163 #define TWIS130_IRQHandler SERIAL0_IRQHandler 164 #define UARTE130_IRQn SERIAL0_IRQn 165 #define UARTE130_IRQHandler SERIAL0_IRQHandler 166 #define SPIM131_IRQn SERIAL1_IRQn 167 #define SPIM131_IRQHandler SERIAL1_IRQHandler 168 #define SPIS131_IRQn SERIAL1_IRQn 169 #define SPIS131_IRQHandler SERIAL1_IRQHandler 170 #define TWIM131_IRQn SERIAL1_IRQn 171 #define TWIM131_IRQHandler SERIAL1_IRQHandler 172 #define TWIS131_IRQn SERIAL1_IRQn 173 #define TWIS131_IRQHandler SERIAL1_IRQHandler 174 #define UARTE131_IRQn SERIAL1_IRQn 175 #define UARTE131_IRQHandler SERIAL1_IRQHandler 176 #define SPIM132_IRQn SERIAL2_IRQn 177 #define SPIM132_IRQHandler SERIAL2_IRQHandler 178 #define SPIS132_IRQn SERIAL2_IRQn 179 #define SPIS132_IRQHandler SERIAL2_IRQHandler 180 #define TWIM132_IRQn SERIAL2_IRQn 181 #define TWIM132_IRQHandler SERIAL2_IRQHandler 182 #define TWIS132_IRQn SERIAL2_IRQn 183 #define TWIS132_IRQHandler SERIAL2_IRQHandler 184 #define UARTE132_IRQn SERIAL2_IRQn 185 #define UARTE132_IRQHandler SERIAL2_IRQHandler 186 #define SPIM133_IRQn SERIAL3_IRQn 187 #define SPIM133_IRQHandler SERIAL3_IRQHandler 188 #define SPIS133_IRQn SERIAL3_IRQn 189 #define SPIS133_IRQHandler SERIAL3_IRQHandler 190 #define TWIM133_IRQn SERIAL3_IRQn 191 #define TWIM133_IRQHandler SERIAL3_IRQHandler 192 #define TWIS133_IRQn SERIAL3_IRQn 193 #define TWIS133_IRQHandler SERIAL3_IRQHandler 194 #define UARTE133_IRQn SERIAL3_IRQn 195 #define UARTE133_IRQHandler SERIAL3_IRQHandler 196 #define SPIM134_IRQn SERIAL4_IRQn 197 #define SPIM134_IRQHandler SERIAL4_IRQHandler 198 #define SPIS134_IRQn SERIAL4_IRQn 199 #define SPIS134_IRQHandler SERIAL4_IRQHandler 200 #define TWIM134_IRQn SERIAL4_IRQn 201 #define TWIM134_IRQHandler SERIAL4_IRQHandler 202 #define TWIS134_IRQn SERIAL4_IRQn 203 #define TWIS134_IRQHandler SERIAL4_IRQHandler 204 #define UARTE134_IRQn SERIAL4_IRQn 205 #define UARTE134_IRQHandler SERIAL4_IRQHandler 206 #define SPIM135_IRQn SERIAL5_IRQn 207 #define SPIM135_IRQHandler SERIAL5_IRQHandler 208 #define SPIS135_IRQn SERIAL5_IRQn 209 #define SPIS135_IRQHandler SERIAL5_IRQHandler 210 #define TWIM135_IRQn SERIAL5_IRQn 211 #define TWIM135_IRQHandler SERIAL5_IRQHandler 212 #define TWIS135_IRQn SERIAL5_IRQn 213 #define TWIS135_IRQHandler SERIAL5_IRQHandler 214 #define UARTE135_IRQn SERIAL5_IRQn 215 #define UARTE135_IRQHandler SERIAL5_IRQHandler 216 #define SPIM136_IRQn SERIAL6_IRQn 217 #define SPIM136_IRQHandler SERIAL6_IRQHandler 218 #define SPIS136_IRQn SERIAL6_IRQn 219 #define SPIS136_IRQHandler SERIAL6_IRQHandler 220 #define TWIM136_IRQn SERIAL6_IRQn 221 #define TWIM136_IRQHandler SERIAL6_IRQHandler 222 #define TWIS136_IRQn SERIAL6_IRQn 223 #define TWIS136_IRQHandler SERIAL6_IRQHandler 224 #define UARTE136_IRQn SERIAL6_IRQn 225 #define UARTE136_IRQHandler SERIAL6_IRQHandler 226 #define SPIM137_IRQn SERIAL7_IRQn 227 #define SPIM137_IRQHandler SERIAL7_IRQHandler 228 #define SPIS137_IRQn SERIAL7_IRQn 229 #define SPIS137_IRQHandler SERIAL7_IRQHandler 230 #define TWIM137_IRQn SERIAL7_IRQn 231 #define TWIM137_IRQHandler SERIAL7_IRQHandler 232 #define TWIS137_IRQn SERIAL7_IRQn 233 #define TWIS137_IRQHandler SERIAL7_IRQHandler 234 #define UARTE137_IRQn SERIAL7_IRQn 235 #define UARTE137_IRQHandler SERIAL7_IRQHandler 236 237 /* =========================================================================================================================== */ 238 /* ================ Processor and Core Peripheral Section ================ */ 239 /* =========================================================================================================================== */ 240 241 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 242 #define __VPR_REV 1.1 /*!< VPR Core Revision */ 243 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 244 #define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ 245 #define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ 246 #define __DSP_PRESENT 0 /*!< DSP present or not */ 247 #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 248 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 249 #define __MPU_PRESENT 1 /*!< MPU present */ 250 #define __FPU_PRESENT 0 /*!< FPU present */ 251 #define __FPU_DP 0 /*!< Double Precision FPU */ 252 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 253 254 #define NRF_VPR NRF_VPR121 /*!< VPR instance name */ 255 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 256 #include "system_nrf.h" /*!< nrf9230_enga_flpr System Library */ 257 258 #endif /*!< NRF_FLPR */ 259 260 261 #ifdef NRF_FLPR 262 263 #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST 264 #define NRF_PROCESSOR NRF_PROCESSOR_FLPR 265 #ifndef NRF_OWNER 266 #define NRF_OWNER NRF_OWNER_APPLICATION 267 #endif 268 269 #endif /*!< NRF_FLPR */ 270 271 272 /* ========================================= Start of section using anonymous unions ========================================= */ 273 274 #include "compiler_abstraction.h" 275 276 #if defined (__CC_ARM) 277 #pragma push 278 #pragma anon_unions 279 #elif defined (__ICCARM__) 280 #pragma language=extended 281 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 282 #pragma clang diagnostic push 283 #pragma clang diagnostic ignored "-Wc11-extensions" 284 #pragma clang diagnostic ignored "-Wreserved-id-macro" 285 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 286 #pragma clang diagnostic ignored "-Wnested-anon-types" 287 #elif defined (__GNUC__) 288 /* anonymous unions are enabled by default */ 289 #elif defined (__TMS470__) 290 /* anonymous unions are enabled by default */ 291 #elif defined (__TASKING__) 292 #pragma warning 586 293 #elif defined (__CSMC__) 294 /* anonymous unions are enabled by default */ 295 #else 296 #warning Unsupported compiler type 297 #endif 298 299 /* =========================================================================================================================== */ 300 /* ================ Peripheral Address Map ================ */ 301 /* =========================================================================================================================== */ 302 303 #define NRF_FLPR_VPRCLIC_BASE 0x5F8D5000UL 304 305 /* =========================================================================================================================== */ 306 /* ================ Peripheral Declaration ================ */ 307 /* =========================================================================================================================== */ 308 309 #define NRF_FLPR_VPRCLIC ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_BASE) 310 311 /* =========================================================================================================================== */ 312 /* ================ Local Domain Remapping ================ */ 313 /* =========================================================================================================================== */ 314 315 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 316 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 317 #endif /*!< NRF_FLPR */ 318 319 /* ========================================== End of section using anonymous unions ========================================== */ 320 321 #if defined (__CC_ARM) 322 #pragma pop 323 #elif defined (__ICCARM__) 324 /* leave anonymous unions enabled */ 325 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 326 #pragma clang diagnostic pop 327 #elif defined (__GNUC__) 328 /* anonymous unions are enabled by default */ 329 #elif defined (__TMS470__) 330 /* anonymous unions are enabled by default */ 331 #elif defined (__TASKING__) 332 #pragma warning restore 333 #elif defined (__CSMC__) 334 /* anonymous unions are enabled by default */ 335 #endif 336 337 338 #ifdef __cplusplus 339 } 340 #endif 341 #endif /* NRF9230_ENGA_FLPR_H */ 342 343
