1 /*
2 
3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF9160_BITS_H
36 #define __NRF9160_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: CC_HOST_RGF */
41 /* Description: CRYPTOCELL HOST_RGF interface */
42 
43 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
44 /* Description: AES hardware key select */
45 
46 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
47 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
48 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
49 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
50 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */
51 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */
52 
53 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
54 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
55 
56 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
57 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
58 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
59 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
60 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
61 
62 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
63 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
64 
65 /* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
66 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
67 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
68 
69 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
70 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
71 
72 /* Bits 31..0 : K_DR bits 63:32 */
73 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
74 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
75 
76 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
77 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
78 
79 /* Bits 31..0 : K_DR bits 95:64 */
80 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
81 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
82 
83 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
84 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
85 
86 /* Bits 31..0 : K_DR bits 127:96 */
87 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
88 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
89 
90 /* Register: CC_HOST_RGF_HOST_IOT_LCS */
91 /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */
92 
93 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
94 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
95 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
96 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
97 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
98 
99 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
100 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
101 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
102 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */
103 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */
104 
105 
106 /* Peripheral: CLOCK */
107 /* Description: Clock management 0 */
108 
109 /* Register: CLOCK_TASKS_HFCLKSTART */
110 /* Description: Start HFCLK source */
111 
112 /* Bit 0 : Start HFCLK source */
113 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
114 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
115 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
116 
117 /* Register: CLOCK_TASKS_HFCLKSTOP */
118 /* Description: Stop HFCLK source */
119 
120 /* Bit 0 : Stop HFCLK source */
121 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
122 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
123 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
124 
125 /* Register: CLOCK_TASKS_LFCLKSTART */
126 /* Description: Start LFCLK source */
127 
128 /* Bit 0 : Start LFCLK source */
129 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
130 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
131 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
132 
133 /* Register: CLOCK_TASKS_LFCLKSTOP */
134 /* Description: Stop LFCLK source */
135 
136 /* Bit 0 : Stop LFCLK source */
137 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
138 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
139 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
140 
141 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
142 /* Description: Subscribe configuration for task HFCLKSTART */
143 
144 /* Bit 31 :   */
145 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
146 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
147 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
148 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
149 
150 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
151 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
152 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
153 
154 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
155 /* Description: Subscribe configuration for task HFCLKSTOP */
156 
157 /* Bit 31 :   */
158 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
159 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
160 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
161 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
162 
163 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
164 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
165 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
166 
167 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
168 /* Description: Subscribe configuration for task LFCLKSTART */
169 
170 /* Bit 31 :   */
171 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
172 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
173 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
174 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
175 
176 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
177 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
178 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
179 
180 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
181 /* Description: Subscribe configuration for task LFCLKSTOP */
182 
183 /* Bit 31 :   */
184 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
185 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
186 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
187 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
188 
189 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
190 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
191 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
192 
193 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
194 /* Description: HFCLK oscillator started */
195 
196 /* Bit 0 : HFCLK oscillator started */
197 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
198 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
199 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
200 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
201 
202 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
203 /* Description: LFCLK started */
204 
205 /* Bit 0 : LFCLK started */
206 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
207 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
208 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
209 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
210 
211 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
212 /* Description: Publish configuration for event HFCLKSTARTED */
213 
214 /* Bit 31 :   */
215 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
216 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
217 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
218 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
219 
220 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */
221 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
222 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
223 
224 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
225 /* Description: Publish configuration for event LFCLKSTARTED */
226 
227 /* Bit 31 :   */
228 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
229 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
230 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
231 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
232 
233 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */
234 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
235 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
236 
237 /* Register: CLOCK_INTEN */
238 /* Description: Enable or disable interrupt */
239 
240 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
241 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
242 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
243 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
244 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
245 
246 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
247 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
248 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
249 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
250 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
251 
252 /* Register: CLOCK_INTENSET */
253 /* Description: Enable interrupt */
254 
255 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
256 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
257 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
258 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
259 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
260 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
261 
262 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
263 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
264 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
265 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
266 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
267 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
268 
269 /* Register: CLOCK_INTENCLR */
270 /* Description: Disable interrupt */
271 
272 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
273 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
274 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
275 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
276 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
277 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
278 
279 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
280 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
281 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
282 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
283 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
284 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
285 
286 /* Register: CLOCK_INTPEND */
287 /* Description: Pending interrupts */
288 
289 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
290 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
291 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
292 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
293 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
294 
295 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
296 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
297 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
298 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
299 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
300 
301 /* Register: CLOCK_HFCLKRUN */
302 /* Description: Status indicating that HFCLKSTART task has been triggered */
303 
304 /* Bit 0 : HFCLKSTART task triggered or not */
305 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
306 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
307 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
308 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
309 
310 /* Register: CLOCK_HFCLKSTAT */
311 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */
312 
313 /* Bit 16 : HFCLK state */
314 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
315 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
316 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */
317 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */
318 
319 /* Bit 0 : Active clock source */
320 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
321 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
322 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */
323 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */
324 
325 /* Register: CLOCK_LFCLKRUN */
326 /* Description: Status indicating that LFCLKSTART task has been triggered */
327 
328 /* Bit 0 : LFCLKSTART task triggered or not */
329 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
330 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
331 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
332 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
333 
334 /* Register: CLOCK_LFCLKSTAT */
335 /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */
336 
337 /* Bit 16 : LFCLK state */
338 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
339 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
340 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */
341 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */
342 
343 /* Bits 1..0 : Active clock source */
344 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
345 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
346 #define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */
347 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
348 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
349 
350 /* Register: CLOCK_LFCLKSRCCOPY */
351 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */
352 
353 /* Bits 1..0 : Clock source */
354 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
355 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
356 #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */
357 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
358 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
359 
360 /* Register: CLOCK_LFCLKSRC */
361 /* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */
362 
363 /* Bits 1..0 : Clock source */
364 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
365 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
366 #define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */
367 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
368 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
369 
370 
371 /* Peripheral: CRYPTOCELL */
372 /* Description: ARM TrustZone CryptoCell register interface */
373 
374 /* Register: CRYPTOCELL_ENABLE */
375 /* Description: Enable CRYPTOCELL subsystem */
376 
377 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
378 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
379 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
380 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
381 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */
382 
383 
384 /* Peripheral: CTRLAPPERI */
385 /* Description: Control access port */
386 
387 /* Register: CTRLAPPERI_MAILBOX_RXDATA */
388 /* Description: Data sent from the debugger to the CPU. */
389 
390 /* Bits 31..0 : Data received from debugger */
391 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
392 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
393 
394 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
395 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
396 
397 /* Bit 0 : Status of data in register RXDATA */
398 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
399 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
400 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */
401 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
402 
403 /* Register: CTRLAPPERI_MAILBOX_TXDATA */
404 /* Description: Data sent from the CPU to the debugger. */
405 
406 /* Bits 31..0 : Data sent to debugger */
407 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
408 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
409 
410 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
411 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
412 
413 /* Bit 0 : Status of data in register TXDATA */
414 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
415 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
416 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */
417 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
418 
419 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
420 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
421 
422 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
423 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
424 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
425 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
426 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
427 
428 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
429 /* Description: This register disables the ERASEPROTECT register and performs an  ERASEALL operation. */
430 
431 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
432 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
433 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
434 
435 
436 /* Peripheral: DPPIC */
437 /* Description: Distributed programmable peripheral interconnect controller 0 */
438 
439 /* Register: DPPIC_TASKS_CHG_EN */
440 /* Description: Description cluster: Enable channel group n */
441 
442 /* Bit 0 : Enable channel group n */
443 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
444 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
445 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
446 
447 /* Register: DPPIC_TASKS_CHG_DIS */
448 /* Description: Description cluster: Disable channel group n */
449 
450 /* Bit 0 : Disable channel group n */
451 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
452 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
453 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
454 
455 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
456 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
457 
458 /* Bit 31 :   */
459 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
460 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
461 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
462 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
463 
464 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
465 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
466 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
467 
468 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
469 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
470 
471 /* Bit 31 :   */
472 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
473 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
474 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
475 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
476 
477 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
478 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
479 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
480 
481 /* Register: DPPIC_CHEN */
482 /* Description: Channel enable register */
483 
484 /* Bit 15 : Enable or disable channel 15 */
485 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
486 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
487 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
488 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
489 
490 /* Bit 14 : Enable or disable channel 14 */
491 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
492 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
493 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
494 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
495 
496 /* Bit 13 : Enable or disable channel 13 */
497 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
498 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
499 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
500 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
501 
502 /* Bit 12 : Enable or disable channel 12 */
503 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
504 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
505 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
506 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
507 
508 /* Bit 11 : Enable or disable channel 11 */
509 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
510 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
511 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
512 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
513 
514 /* Bit 10 : Enable or disable channel 10 */
515 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
516 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
517 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
518 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
519 
520 /* Bit 9 : Enable or disable channel 9 */
521 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
522 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
523 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
524 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
525 
526 /* Bit 8 : Enable or disable channel 8 */
527 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
528 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
529 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
530 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
531 
532 /* Bit 7 : Enable or disable channel 7 */
533 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
534 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
535 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
536 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
537 
538 /* Bit 6 : Enable or disable channel 6 */
539 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
540 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
541 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
542 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
543 
544 /* Bit 5 : Enable or disable channel 5 */
545 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
546 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
547 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
548 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
549 
550 /* Bit 4 : Enable or disable channel 4 */
551 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
552 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
553 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
554 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
555 
556 /* Bit 3 : Enable or disable channel 3 */
557 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
558 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
559 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
560 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
561 
562 /* Bit 2 : Enable or disable channel 2 */
563 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
564 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
565 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
566 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
567 
568 /* Bit 1 : Enable or disable channel 1 */
569 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
570 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
571 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
572 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
573 
574 /* Bit 0 : Enable or disable channel 0 */
575 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
576 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
577 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
578 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
579 
580 /* Register: DPPIC_CHENSET */
581 /* Description: Channel enable set register */
582 
583 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
584 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
585 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
586 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */
587 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */
588 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
589 
590 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
591 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
592 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
593 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */
594 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */
595 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
596 
597 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
598 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
599 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
600 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */
601 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */
602 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
603 
604 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
605 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
606 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
607 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */
608 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */
609 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
610 
611 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
612 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
613 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
614 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */
615 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */
616 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
617 
618 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
619 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
620 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
621 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */
622 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */
623 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
624 
625 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
626 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
627 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
628 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */
629 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */
630 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
631 
632 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
633 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
634 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
635 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */
636 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */
637 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
638 
639 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
640 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
641 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
642 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */
643 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */
644 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
645 
646 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
647 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
648 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
649 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */
650 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */
651 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
652 
653 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
654 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
655 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
656 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */
657 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */
658 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
659 
660 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
661 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
662 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
663 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */
664 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */
665 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
666 
667 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
668 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
669 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
670 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */
671 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */
672 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
673 
674 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
675 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
676 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
677 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */
678 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */
679 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
680 
681 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
682 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
683 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
684 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */
685 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */
686 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
687 
688 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
689 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
690 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
691 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
692 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
693 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
694 
695 /* Register: DPPIC_CHENCLR */
696 /* Description: Channel enable clear register */
697 
698 /* Bit 15 : Channel 15 enable clear register.  Writing 0 has no effect. */
699 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
700 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
701 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */
702 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */
703 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */
704 
705 /* Bit 14 : Channel 14 enable clear register.  Writing 0 has no effect. */
706 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
707 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
708 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */
709 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */
710 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */
711 
712 /* Bit 13 : Channel 13 enable clear register.  Writing 0 has no effect. */
713 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
714 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
715 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */
716 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */
717 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */
718 
719 /* Bit 12 : Channel 12 enable clear register.  Writing 0 has no effect. */
720 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
721 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
722 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */
723 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */
724 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */
725 
726 /* Bit 11 : Channel 11 enable clear register.  Writing 0 has no effect. */
727 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
728 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
729 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */
730 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */
731 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */
732 
733 /* Bit 10 : Channel 10 enable clear register.  Writing 0 has no effect. */
734 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
735 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
736 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */
737 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */
738 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */
739 
740 /* Bit 9 : Channel 9 enable clear register.  Writing 0 has no effect. */
741 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
742 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
743 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */
744 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */
745 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */
746 
747 /* Bit 8 : Channel 8 enable clear register.  Writing 0 has no effect. */
748 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
749 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
750 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */
751 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */
752 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */
753 
754 /* Bit 7 : Channel 7 enable clear register.  Writing 0 has no effect. */
755 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
756 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
757 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */
758 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */
759 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */
760 
761 /* Bit 6 : Channel 6 enable clear register.  Writing 0 has no effect. */
762 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
763 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
764 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */
765 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */
766 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */
767 
768 /* Bit 5 : Channel 5 enable clear register.  Writing 0 has no effect. */
769 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
770 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
771 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */
772 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */
773 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */
774 
775 /* Bit 4 : Channel 4 enable clear register.  Writing 0 has no effect. */
776 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
777 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
778 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */
779 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */
780 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */
781 
782 /* Bit 3 : Channel 3 enable clear register.  Writing 0 has no effect. */
783 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
784 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
785 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */
786 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */
787 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */
788 
789 /* Bit 2 : Channel 2 enable clear register.  Writing 0 has no effect. */
790 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
791 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
792 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */
793 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */
794 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */
795 
796 /* Bit 1 : Channel 1 enable clear register.  Writing 0 has no effect. */
797 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
798 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
799 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */
800 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */
801 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */
802 
803 /* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
804 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
805 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
806 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
807 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
808 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
809 
810 /* Register: DPPIC_CHG */
811 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
812 
813 /* Bit 15 : Include or exclude channel 15 */
814 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
815 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
816 #define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */
817 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
818 
819 /* Bit 14 : Include or exclude channel 14 */
820 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
821 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
822 #define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */
823 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
824 
825 /* Bit 13 : Include or exclude channel 13 */
826 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
827 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
828 #define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */
829 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
830 
831 /* Bit 12 : Include or exclude channel 12 */
832 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
833 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
834 #define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */
835 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
836 
837 /* Bit 11 : Include or exclude channel 11 */
838 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
839 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
840 #define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */
841 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
842 
843 /* Bit 10 : Include or exclude channel 10 */
844 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
845 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
846 #define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */
847 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
848 
849 /* Bit 9 : Include or exclude channel 9 */
850 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
851 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
852 #define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */
853 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
854 
855 /* Bit 8 : Include or exclude channel 8 */
856 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
857 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
858 #define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */
859 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
860 
861 /* Bit 7 : Include or exclude channel 7 */
862 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
863 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
864 #define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */
865 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
866 
867 /* Bit 6 : Include or exclude channel 6 */
868 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
869 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
870 #define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */
871 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
872 
873 /* Bit 5 : Include or exclude channel 5 */
874 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
875 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
876 #define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */
877 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
878 
879 /* Bit 4 : Include or exclude channel 4 */
880 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
881 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
882 #define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */
883 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
884 
885 /* Bit 3 : Include or exclude channel 3 */
886 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
887 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
888 #define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */
889 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
890 
891 /* Bit 2 : Include or exclude channel 2 */
892 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
893 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
894 #define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */
895 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
896 
897 /* Bit 1 : Include or exclude channel 1 */
898 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
899 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
900 #define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */
901 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
902 
903 /* Bit 0 : Include or exclude channel 0 */
904 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
905 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
906 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
907 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
908 
909 
910 /* Peripheral: EGU */
911 /* Description: Event generator unit 0 */
912 
913 /* Register: EGU_TASKS_TRIGGER */
914 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
915 
916 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
917 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
918 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
919 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
920 
921 /* Register: EGU_SUBSCRIBE_TRIGGER */
922 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
923 
924 /* Bit 31 :   */
925 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
926 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
927 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
928 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
929 
930 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
931 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
932 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
933 
934 /* Register: EGU_EVENTS_TRIGGERED */
935 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
936 
937 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
938 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
939 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
940 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
941 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
942 
943 /* Register: EGU_PUBLISH_TRIGGERED */
944 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
945 
946 /* Bit 31 :   */
947 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
948 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
949 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
950 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
951 
952 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */
953 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
954 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
955 
956 /* Register: EGU_INTEN */
957 /* Description: Enable or disable interrupt */
958 
959 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
960 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
961 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
962 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
963 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
964 
965 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
966 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
967 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
968 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
969 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
970 
971 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
972 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
973 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
974 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
975 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
976 
977 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
978 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
979 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
980 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
981 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
982 
983 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
984 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
985 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
986 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
987 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
988 
989 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
990 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
991 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
992 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
993 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
994 
995 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
996 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
997 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
998 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
999 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1000 
1001 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1002 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1003 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1004 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1005 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1006 
1007 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1008 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1009 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1010 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1011 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1012 
1013 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1014 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1015 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1016 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1017 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1018 
1019 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1020 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1021 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1022 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1023 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1024 
1025 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1026 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1027 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1028 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1029 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1030 
1031 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1032 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1033 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1034 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1035 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1036 
1037 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1038 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1039 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1040 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1041 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1042 
1043 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1044 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1045 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1046 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1047 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1048 
1049 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1050 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1051 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1052 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1053 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1054 
1055 /* Register: EGU_INTENSET */
1056 /* Description: Enable interrupt */
1057 
1058 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1059 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1060 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1061 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1062 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1063 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1064 
1065 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1066 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1067 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1068 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1069 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1070 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1071 
1072 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1073 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1074 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1075 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1076 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1077 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1078 
1079 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1080 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1081 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1082 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1083 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1084 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1085 
1086 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1087 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1088 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1089 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1090 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1091 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1092 
1093 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1094 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1095 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1096 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1097 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1098 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1099 
1100 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1101 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1102 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1103 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1104 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1105 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1106 
1107 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1108 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1109 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1110 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1111 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1112 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1113 
1114 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1115 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1116 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1117 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1118 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1119 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1120 
1121 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1122 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1123 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1124 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1125 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1126 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1127 
1128 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1129 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1130 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1131 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1132 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1133 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1134 
1135 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1136 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1137 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1138 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1139 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1140 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1141 
1142 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1143 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1144 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1145 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1146 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1147 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1148 
1149 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1150 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1151 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1152 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1153 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1154 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1155 
1156 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1157 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1158 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1159 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1160 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1161 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1162 
1163 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1164 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1165 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1166 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1167 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1168 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1169 
1170 /* Register: EGU_INTENCLR */
1171 /* Description: Disable interrupt */
1172 
1173 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1174 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1175 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1176 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1177 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1178 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1179 
1180 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1181 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1182 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1183 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1184 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1185 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1186 
1187 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1188 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1189 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1190 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1191 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1192 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1193 
1194 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1195 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1196 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1197 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1198 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1199 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1200 
1201 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1202 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1203 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1204 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1205 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1206 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1207 
1208 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1209 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1210 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1211 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1212 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1213 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1214 
1215 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1216 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1217 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1218 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1219 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1220 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1221 
1222 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1223 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1224 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1225 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1226 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1227 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1228 
1229 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1230 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1231 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1232 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1233 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1234 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1235 
1236 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1237 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1238 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1239 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1240 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1241 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1242 
1243 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1244 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1245 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1246 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1247 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1248 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1249 
1250 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1251 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1252 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1253 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1254 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1255 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1256 
1257 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1258 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1259 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1260 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1261 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1262 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1263 
1264 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1265 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1266 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1267 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1268 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1269 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1270 
1271 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1272 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1273 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1274 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1275 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1276 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1277 
1278 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1279 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1280 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1281 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1282 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1283 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1284 
1285 
1286 /* Peripheral: FICR */
1287 /* Description: Factory Information Configuration Registers */
1288 
1289 /* Register: FICR_SIPINFO_PARTNO */
1290 /* Description: SIP part number */
1291 
1292 /* Bits 31..0 :   */
1293 #define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */
1294 #define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */
1295 #define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */
1296 
1297 /* Register: FICR_SIPINFO_HWREVISION */
1298 /* Description: Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A */
1299 
1300 /* Bits 7..0 :   */
1301 #define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */
1302 #define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */
1303 
1304 /* Register: FICR_SIPINFO_VARIANT */
1305 /* Description: Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */
1306 
1307 /* Bits 7..0 :   */
1308 #define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1309 #define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1310 
1311 /* Register: FICR_INFO_DEVICEID */
1312 /* Description: Description collection: Device identifier */
1313 
1314 /* Bits 31..0 : 64 bit unique device identifier */
1315 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1316 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1317 
1318 /* Register: FICR_INFO_PART */
1319 /* Description: Part code */
1320 
1321 /* Bits 31..0 : Part code */
1322 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1323 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1324 #define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */
1325 #define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */
1326 
1327 /* Register: FICR_INFO_VARIANT */
1328 /* Description: Part Variant, Hardware version and Production configuration */
1329 
1330 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1331 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1332 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1333 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
1334 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1335 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1336 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
1337 
1338 /* Register: FICR_INFO_PACKAGE */
1339 /* Description: Package option */
1340 
1341 /* Bits 31..0 : Package option */
1342 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1343 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1344 #define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */
1345 
1346 /* Register: FICR_INFO_RAM */
1347 /* Description: RAM variant */
1348 
1349 /* Bits 31..0 : RAM variant */
1350 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1351 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1352 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256  kByte RAM */
1353 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1354 
1355 /* Register: FICR_INFO_FLASH */
1356 /* Description: Flash variant */
1357 
1358 /* Bits 31..0 : Flash variant */
1359 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1360 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1361 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
1362 
1363 /* Register: FICR_INFO_CODEPAGESIZE */
1364 /* Description: Code memory page size */
1365 
1366 /* Bits 31..0 : Code memory page size */
1367 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1368 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1369 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4  kByte */
1370 
1371 /* Register: FICR_INFO_CODESIZE */
1372 /* Description: Code memory size */
1373 
1374 /* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */
1375 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1376 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1377 #define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */
1378 
1379 /* Register: FICR_INFO_DEVICETYPE */
1380 /* Description: Device type */
1381 
1382 /* Bits 31..0 : Device type */
1383 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
1384 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
1385 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */
1386 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
1387 
1388 /* Register: FICR_TRIMCNF_ADDR */
1389 /* Description: Description cluster: Address */
1390 
1391 /* Bits 31..0 : Address */
1392 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
1393 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
1394 
1395 /* Register: FICR_TRIMCNF_DATA */
1396 /* Description: Description cluster: Data */
1397 
1398 /* Bits 31..0 : Data */
1399 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
1400 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
1401 
1402 /* Register: FICR_TRNG90B_BYTES */
1403 /* Description: Amount of bytes for the required entropy bits */
1404 
1405 /* Bits 31..0 : Amount of bytes for the required entropy bits */
1406 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
1407 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
1408 
1409 /* Register: FICR_TRNG90B_RCCUTOFF */
1410 /* Description: Repetition counter cutoff */
1411 
1412 /* Bits 31..0 : Repetition counter cutoff */
1413 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
1414 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
1415 
1416 /* Register: FICR_TRNG90B_APCUTOFF */
1417 /* Description: Adaptive proportion cutoff */
1418 
1419 /* Bits 31..0 : Adaptive proportion cutoff */
1420 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
1421 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
1422 
1423 /* Register: FICR_TRNG90B_STARTUP */
1424 /* Description: Amount of bytes for the startup tests */
1425 
1426 /* Bits 31..0 : Amount of bytes for the startup tests */
1427 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
1428 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
1429 
1430 /* Register: FICR_TRNG90B_ROSC1 */
1431 /* Description: Sample count for ring oscillator 1 */
1432 
1433 /* Bits 31..0 : Sample count for ring oscillator 1 */
1434 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
1435 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
1436 
1437 /* Register: FICR_TRNG90B_ROSC2 */
1438 /* Description: Sample count for ring oscillator 2 */
1439 
1440 /* Bits 31..0 : Sample count for ring oscillator 2 */
1441 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
1442 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
1443 
1444 /* Register: FICR_TRNG90B_ROSC3 */
1445 /* Description: Sample count for ring oscillator 3 */
1446 
1447 /* Bits 31..0 : Sample count for ring oscillator 3 */
1448 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
1449 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
1450 
1451 /* Register: FICR_TRNG90B_ROSC4 */
1452 /* Description: Sample count for ring oscillator 4 */
1453 
1454 /* Bits 31..0 : Sample count for ring oscillator 4 */
1455 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
1456 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
1457 
1458 
1459 /* Peripheral: GPIOTE */
1460 /* Description: GPIO Tasks and Events 0 */
1461 
1462 /* Register: GPIOTE_TASKS_OUT */
1463 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1464 
1465 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1466 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1467 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1468 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1469 
1470 /* Register: GPIOTE_TASKS_SET */
1471 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1472 
1473 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1474 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1475 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1476 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1477 
1478 /* Register: GPIOTE_TASKS_CLR */
1479 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1480 
1481 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1482 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1483 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1484 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1485 
1486 /* Register: GPIOTE_SUBSCRIBE_OUT */
1487 /* Description: Description collection: Subscribe configuration for task OUT[n] */
1488 
1489 /* Bit 31 :   */
1490 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
1491 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
1492 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
1493 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
1494 
1495 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
1496 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1497 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1498 
1499 /* Register: GPIOTE_SUBSCRIBE_SET */
1500 /* Description: Description collection: Subscribe configuration for task SET[n] */
1501 
1502 /* Bit 31 :   */
1503 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
1504 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
1505 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
1506 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
1507 
1508 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
1509 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1510 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1511 
1512 /* Register: GPIOTE_SUBSCRIBE_CLR */
1513 /* Description: Description collection: Subscribe configuration for task CLR[n] */
1514 
1515 /* Bit 31 :   */
1516 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
1517 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
1518 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
1519 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
1520 
1521 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
1522 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1523 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1524 
1525 /* Register: GPIOTE_EVENTS_IN */
1526 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1527 
1528 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1529 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1530 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1531 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1532 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1533 
1534 /* Register: GPIOTE_EVENTS_PORT */
1535 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1536 
1537 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1538 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1539 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1540 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1541 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1542 
1543 /* Register: GPIOTE_PUBLISH_IN */
1544 /* Description: Description collection: Publish configuration for event IN[n] */
1545 
1546 /* Bit 31 :   */
1547 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
1548 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
1549 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
1550 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
1551 
1552 /* Bits 7..0 : DPPI channel that event IN[n] will publish to */
1553 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1554 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1555 
1556 /* Register: GPIOTE_PUBLISH_PORT */
1557 /* Description: Publish configuration for event PORT */
1558 
1559 /* Bit 31 :   */
1560 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
1561 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
1562 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
1563 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
1564 
1565 /* Bits 7..0 : DPPI channel that event PORT will publish to */
1566 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1567 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1568 
1569 /* Register: GPIOTE_INTENSET */
1570 /* Description: Enable interrupt */
1571 
1572 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1573 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1574 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
1575 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1576 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1577 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1578 
1579 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1580 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
1581 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
1582 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1583 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1584 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1585 
1586 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1587 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
1588 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
1589 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1590 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1591 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1592 
1593 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1594 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
1595 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
1596 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1597 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1598 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1599 
1600 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1601 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
1602 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
1603 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1604 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1605 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1606 
1607 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1608 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
1609 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
1610 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1611 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1612 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1613 
1614 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1615 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1616 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
1617 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1618 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1619 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1620 
1621 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1622 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
1623 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
1624 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1625 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1626 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1627 
1628 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1629 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
1630 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
1631 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1632 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1633 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1634 
1635 /* Register: GPIOTE_INTENCLR */
1636 /* Description: Disable interrupt */
1637 
1638 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1639 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
1640 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
1641 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1642 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1643 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1644 
1645 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1646 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
1647 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
1648 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1649 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1650 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1651 
1652 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1653 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
1654 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
1655 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1656 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1657 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1658 
1659 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1660 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
1661 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
1662 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1663 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1664 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1665 
1666 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1667 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
1668 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
1669 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1670 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1671 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1672 
1673 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1674 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
1675 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
1676 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1677 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1678 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1679 
1680 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1681 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
1682 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
1683 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1684 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1685 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1686 
1687 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1688 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
1689 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
1690 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1691 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1692 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1693 
1694 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1695 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
1696 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
1697 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1698 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1699 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1700 
1701 /* Register: GPIOTE_CONFIG */
1702 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
1703 
1704 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
1705 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
1706 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
1707 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
1708 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
1709 
1710 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
1711 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
1712 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
1713 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
1714 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
1715 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
1716 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
1717 
1718 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
1719 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
1720 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
1721 
1722 /* Bits 1..0 : Mode */
1723 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
1724 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
1725 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
1726 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
1727 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
1728 
1729 
1730 /* Peripheral: I2S */
1731 /* Description: Inter-IC Sound 0 */
1732 
1733 /* Register: I2S_TASKS_START */
1734 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1735 
1736 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1737 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
1738 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
1739 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
1740 
1741 /* Register: I2S_TASKS_STOP */
1742 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
1743 
1744 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
1745 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
1746 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
1747 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
1748 
1749 /* Register: I2S_SUBSCRIBE_START */
1750 /* Description: Subscribe configuration for task START */
1751 
1752 /* Bit 31 :   */
1753 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
1754 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
1755 #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
1756 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
1757 
1758 /* Bits 7..0 : DPPI channel that task START will subscribe to */
1759 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1760 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1761 
1762 /* Register: I2S_SUBSCRIBE_STOP */
1763 /* Description: Subscribe configuration for task STOP */
1764 
1765 /* Bit 31 :   */
1766 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
1767 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
1768 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
1769 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
1770 
1771 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
1772 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1773 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1774 
1775 /* Register: I2S_EVENTS_RXPTRUPD */
1776 /* Description: The RXD.PTR register has been copied to internal double-buffers.
1777       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
1778 
1779 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
1780       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
1781 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
1782 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
1783 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
1784 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
1785 
1786 /* Register: I2S_EVENTS_STOPPED */
1787 /* Description: I2S transfer stopped. */
1788 
1789 /* Bit 0 : I2S transfer stopped. */
1790 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
1791 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
1792 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
1793 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
1794 
1795 /* Register: I2S_EVENTS_TXPTRUPD */
1796 /* Description: The TDX.PTR register has been copied to internal double-buffers.
1797       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
1798 
1799 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
1800       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
1801 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
1802 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
1803 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
1804 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
1805 
1806 /* Register: I2S_PUBLISH_RXPTRUPD */
1807 /* Description: Publish configuration for event RXPTRUPD */
1808 
1809 /* Bit 31 :   */
1810 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
1811 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
1812 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1813 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1814 
1815 /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */
1816 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1817 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1818 
1819 /* Register: I2S_PUBLISH_STOPPED */
1820 /* Description: Publish configuration for event STOPPED */
1821 
1822 /* Bit 31 :   */
1823 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
1824 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
1825 #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
1826 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
1827 
1828 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
1829 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1830 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1831 
1832 /* Register: I2S_PUBLISH_TXPTRUPD */
1833 /* Description: Publish configuration for event TXPTRUPD */
1834 
1835 /* Bit 31 :   */
1836 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
1837 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
1838 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1839 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1840 
1841 /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */
1842 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1843 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1844 
1845 /* Register: I2S_INTEN */
1846 /* Description: Enable or disable interrupt */
1847 
1848 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
1849 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1850 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1851 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
1852 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
1853 
1854 /* Bit 2 : Enable or disable interrupt for event STOPPED */
1855 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1856 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1857 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
1858 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
1859 
1860 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
1861 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1862 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1863 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
1864 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
1865 
1866 /* Register: I2S_INTENSET */
1867 /* Description: Enable interrupt */
1868 
1869 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
1870 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1871 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1872 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1873 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1874 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
1875 
1876 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
1877 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1878 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1879 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1880 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1881 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
1882 
1883 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
1884 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1885 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1886 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1887 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1888 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
1889 
1890 /* Register: I2S_INTENCLR */
1891 /* Description: Disable interrupt */
1892 
1893 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
1894 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1895 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1896 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1897 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1898 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
1899 
1900 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
1901 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1902 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1903 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1904 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1905 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
1906 
1907 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
1908 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1909 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1910 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1911 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1912 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
1913 
1914 /* Register: I2S_ENABLE */
1915 /* Description: Enable I2S module. */
1916 
1917 /* Bit 0 : Enable I2S module. */
1918 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1919 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1920 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1921 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
1922 
1923 /* Register: I2S_CONFIG_MODE */
1924 /* Description: I2S mode. */
1925 
1926 /* Bit 0 : I2S mode. */
1927 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1928 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1929 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
1930 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
1931 
1932 /* Register: I2S_CONFIG_RXEN */
1933 /* Description: Reception (RX) enable. */
1934 
1935 /* Bit 0 : Reception (RX) enable. */
1936 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
1937 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
1938 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
1939 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
1940 
1941 /* Register: I2S_CONFIG_TXEN */
1942 /* Description: Transmission (TX) enable. */
1943 
1944 /* Bit 0 : Transmission (TX) enable. */
1945 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
1946 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
1947 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
1948 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
1949 
1950 /* Register: I2S_CONFIG_MCKEN */
1951 /* Description: Master clock generator enable. */
1952 
1953 /* Bit 0 : Master clock generator enable. */
1954 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
1955 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
1956 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
1957 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
1958 
1959 /* Register: I2S_CONFIG_MCKFREQ */
1960 /* Description: Master clock generator frequency. */
1961 
1962 /* Bits 31..0 : Master clock generator frequency. */
1963 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
1964 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
1965 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
1966 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
1967 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
1968 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
1969 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
1970 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
1971 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
1972 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
1973 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
1974 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
1975 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
1976 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
1977 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
1978 
1979 /* Register: I2S_CONFIG_RATIO */
1980 /* Description: MCK / LRCK ratio. */
1981 
1982 /* Bits 3..0 : MCK / LRCK ratio. */
1983 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
1984 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
1985 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
1986 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
1987 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
1988 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
1989 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
1990 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
1991 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
1992 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
1993 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
1994 
1995 /* Register: I2S_CONFIG_SWIDTH */
1996 /* Description: Sample width. */
1997 
1998 /* Bits 1..0 : Sample width. */
1999 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2000 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2001 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2002 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2003 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2004 
2005 /* Register: I2S_CONFIG_ALIGN */
2006 /* Description: Alignment of sample within a frame. */
2007 
2008 /* Bit 0 : Alignment of sample within a frame. */
2009 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2010 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2011 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2012 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2013 
2014 /* Register: I2S_CONFIG_FORMAT */
2015 /* Description: Frame format. */
2016 
2017 /* Bit 0 : Frame format. */
2018 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2019 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2020 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2021 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2022 
2023 /* Register: I2S_CONFIG_CHANNELS */
2024 /* Description: Enable channels. */
2025 
2026 /* Bits 1..0 : Enable channels. */
2027 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2028 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2029 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2030 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2031 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2032 
2033 /* Register: I2S_RXD_PTR */
2034 /* Description: Receive buffer RAM start address. */
2035 
2036 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2037 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2038 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2039 
2040 /* Register: I2S_TXD_PTR */
2041 /* Description: Transmit buffer RAM start address. */
2042 
2043 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2044 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2045 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2046 
2047 /* Register: I2S_RXTXD_MAXCNT */
2048 /* Description: Size of RXD and TXD buffers. */
2049 
2050 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2051 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2052 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2053 
2054 /* Register: I2S_PSEL_MCK */
2055 /* Description: Pin select for MCK signal. */
2056 
2057 /* Bit 31 : Connection */
2058 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2059 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2060 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2061 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2062 
2063 /* Bits 4..0 : Pin number */
2064 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2065 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2066 
2067 /* Register: I2S_PSEL_SCK */
2068 /* Description: Pin select for SCK signal. */
2069 
2070 /* Bit 31 : Connection */
2071 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2072 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2073 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2074 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2075 
2076 /* Bits 4..0 : Pin number */
2077 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2078 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2079 
2080 /* Register: I2S_PSEL_LRCK */
2081 /* Description: Pin select for LRCK signal. */
2082 
2083 /* Bit 31 : Connection */
2084 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2085 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2086 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2087 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2088 
2089 /* Bits 4..0 : Pin number */
2090 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2091 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2092 
2093 /* Register: I2S_PSEL_SDIN */
2094 /* Description: Pin select for SDIN signal. */
2095 
2096 /* Bit 31 : Connection */
2097 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2098 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2099 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2100 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2101 
2102 /* Bits 4..0 : Pin number */
2103 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2104 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2105 
2106 /* Register: I2S_PSEL_SDOUT */
2107 /* Description: Pin select for SDOUT signal. */
2108 
2109 /* Bit 31 : Connection */
2110 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2111 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2112 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2113 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2114 
2115 /* Bits 4..0 : Pin number */
2116 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2117 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2118 
2119 
2120 /* Peripheral: IPC */
2121 /* Description: Interprocessor communication 0 */
2122 
2123 /* Register: IPC_TASKS_SEND */
2124 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
2125 
2126 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
2127 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
2128 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
2129 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
2130 
2131 /* Register: IPC_SUBSCRIBE_SEND */
2132 /* Description: Description collection: Subscribe configuration for task SEND[n] */
2133 
2134 /* Bit 31 :   */
2135 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
2136 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
2137 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
2138 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
2139 
2140 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
2141 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2142 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2143 
2144 /* Register: IPC_EVENTS_RECEIVE */
2145 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
2146 
2147 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
2148 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
2149 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
2150 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
2151 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
2152 
2153 /* Register: IPC_PUBLISH_RECEIVE */
2154 /* Description: Description collection: Publish configuration for event RECEIVE[n] */
2155 
2156 /* Bit 31 :   */
2157 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
2158 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
2159 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
2160 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
2161 
2162 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */
2163 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2164 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2165 
2166 /* Register: IPC_INTEN */
2167 /* Description: Enable or disable interrupt */
2168 
2169 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
2170 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2171 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2172 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
2173 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
2174 
2175 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
2176 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2177 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2178 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
2179 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
2180 
2181 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
2182 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2183 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2184 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
2185 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
2186 
2187 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
2188 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2189 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2190 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
2191 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
2192 
2193 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
2194 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2195 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2196 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
2197 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
2198 
2199 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
2200 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2201 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2202 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
2203 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
2204 
2205 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
2206 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2207 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2208 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
2209 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
2210 
2211 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
2212 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2213 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2214 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
2215 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
2216 
2217 /* Register: IPC_INTENSET */
2218 /* Description: Enable interrupt */
2219 
2220 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
2221 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2222 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2223 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2224 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2225 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
2226 
2227 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
2228 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2229 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2230 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2231 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2232 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
2233 
2234 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
2235 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2236 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2237 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2238 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2239 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
2240 
2241 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
2242 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2243 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2244 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2245 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2246 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
2247 
2248 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
2249 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2250 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2251 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2252 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2253 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
2254 
2255 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
2256 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2257 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2258 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2259 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2260 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
2261 
2262 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
2263 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2264 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2265 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2266 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2267 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
2268 
2269 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
2270 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2271 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2272 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2273 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2274 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
2275 
2276 /* Register: IPC_INTENCLR */
2277 /* Description: Disable interrupt */
2278 
2279 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
2280 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2281 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2282 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2283 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2284 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
2285 
2286 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
2287 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2288 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2289 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2290 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2291 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
2292 
2293 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
2294 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2295 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2296 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2297 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2298 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
2299 
2300 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
2301 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2302 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2303 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2304 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2305 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
2306 
2307 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
2308 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2309 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2310 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2311 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2312 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
2313 
2314 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
2315 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2316 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2317 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2318 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2319 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
2320 
2321 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
2322 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2323 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2324 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2325 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2326 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
2327 
2328 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
2329 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2330 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2331 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2332 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2333 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
2334 
2335 /* Register: IPC_INTPEND */
2336 /* Description: Pending interrupts */
2337 
2338 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
2339 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2340 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2341 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
2342 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
2343 
2344 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
2345 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2346 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2347 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
2348 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
2349 
2350 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
2351 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2352 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2353 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
2354 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
2355 
2356 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
2357 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2358 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2359 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
2360 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
2361 
2362 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
2363 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2364 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2365 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
2366 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
2367 
2368 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
2369 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2370 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2371 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
2372 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
2373 
2374 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
2375 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2376 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2377 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
2378 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
2379 
2380 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
2381 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2382 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2383 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
2384 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
2385 
2386 /* Register: IPC_SEND_CNF */
2387 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */
2388 
2389 /* Bit 7 : Enable broadcasting on IPC channel 7 */
2390 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
2391 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
2392 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */
2393 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */
2394 
2395 /* Bit 6 : Enable broadcasting on IPC channel 6 */
2396 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
2397 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
2398 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */
2399 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */
2400 
2401 /* Bit 5 : Enable broadcasting on IPC channel 5 */
2402 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
2403 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
2404 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */
2405 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */
2406 
2407 /* Bit 4 : Enable broadcasting on IPC channel 4 */
2408 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
2409 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
2410 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */
2411 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */
2412 
2413 /* Bit 3 : Enable broadcasting on IPC channel 3 */
2414 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
2415 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
2416 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */
2417 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */
2418 
2419 /* Bit 2 : Enable broadcasting on IPC channel 2 */
2420 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2421 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
2422 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */
2423 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */
2424 
2425 /* Bit 1 : Enable broadcasting on IPC channel 1 */
2426 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2427 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
2428 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */
2429 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */
2430 
2431 /* Bit 0 : Enable broadcasting on IPC channel 0 */
2432 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
2433 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
2434 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */
2435 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */
2436 
2437 /* Register: IPC_RECEIVE_CNF */
2438 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
2439 
2440 /* Bit 7 : Enable subscription to IPC channel 7 */
2441 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
2442 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
2443 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */
2444 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */
2445 
2446 /* Bit 6 : Enable subscription to IPC channel 6 */
2447 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
2448 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
2449 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */
2450 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */
2451 
2452 /* Bit 5 : Enable subscription to IPC channel 5 */
2453 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
2454 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
2455 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */
2456 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */
2457 
2458 /* Bit 4 : Enable subscription to IPC channel 4 */
2459 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
2460 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
2461 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */
2462 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */
2463 
2464 /* Bit 3 : Enable subscription to IPC channel 3 */
2465 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
2466 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
2467 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */
2468 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */
2469 
2470 /* Bit 2 : Enable subscription to IPC channel 2 */
2471 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2472 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
2473 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */
2474 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */
2475 
2476 /* Bit 1 : Enable subscription to IPC channel 1 */
2477 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2478 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
2479 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */
2480 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */
2481 
2482 /* Bit 0 : Enable subscription to IPC channel 0 */
2483 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
2484 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
2485 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */
2486 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */
2487 
2488 /* Register: IPC_GPMEM */
2489 /* Description: Description collection: General purpose memory */
2490 
2491 /* Bits 31..0 : General purpose memory */
2492 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
2493 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
2494 
2495 
2496 /* Peripheral: KMU */
2497 /* Description: Key management unit 0 */
2498 
2499 /* Register: KMU_TASKS_PUSH_KEYSLOT */
2500 /* Description: Push a key slot over secure APB */
2501 
2502 /* Bit 0 : Push a key slot over secure APB */
2503 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
2504 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
2505 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
2506 
2507 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */
2508 /* Description: Key slot successfully pushed over secure APB */
2509 
2510 /* Bit 0 : Key slot successfully pushed over secure APB */
2511 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
2512 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
2513 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */
2514 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
2515 
2516 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */
2517 /* Description: Key slot has been revoked and cannot be tasked for selection */
2518 
2519 /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
2520 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
2521 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
2522 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */
2523 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */
2524 
2525 /* Register: KMU_EVENTS_KEYSLOT_ERROR */
2526 /* Description: No key slot selected, no destination address defined, or error during push operation */
2527 
2528 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
2529 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
2530 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
2531 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */
2532 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */
2533 
2534 /* Register: KMU_INTEN */
2535 /* Description: Enable or disable interrupt */
2536 
2537 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
2538 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2539 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2540 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */
2541 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
2542 
2543 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
2544 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2545 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2546 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */
2547 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
2548 
2549 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
2550 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2551 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2552 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */
2553 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
2554 
2555 /* Register: KMU_INTENSET */
2556 /* Description: Enable interrupt */
2557 
2558 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
2559 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2560 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2561 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2562 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2563 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
2564 
2565 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
2566 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2567 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2568 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2569 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2570 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
2571 
2572 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
2573 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2574 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2575 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2576 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2577 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
2578 
2579 /* Register: KMU_INTENCLR */
2580 /* Description: Disable interrupt */
2581 
2582 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
2583 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2584 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2585 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2586 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2587 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
2588 
2589 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
2590 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2591 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2592 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2593 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2594 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
2595 
2596 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
2597 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2598 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2599 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2600 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2601 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
2602 
2603 /* Register: KMU_INTPEND */
2604 /* Description: Pending interrupts */
2605 
2606 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
2607 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2608 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2609 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */
2610 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
2611 
2612 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
2613 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2614 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2615 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */
2616 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
2617 
2618 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
2619 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2620 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2621 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */
2622 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
2623 
2624 /* Register: KMU_STATUS */
2625 /* Description: Status bits for KMU operation */
2626 
2627 /* Bit 1 : Violation status */
2628 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
2629 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
2630 #define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */
2631 #define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */
2632 
2633 /* Bit 0 : Key slot ID successfully selected by the KMU */
2634 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
2635 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
2636 #define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */
2637 #define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
2638 
2639 /* Register: KMU_SELECTKEYSLOT */
2640 /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
2641 
2642 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
2643 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
2644 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
2645 
2646 
2647 /* Peripheral: NVMC */
2648 /* Description: Non-volatile memory controller 0 */
2649 
2650 /* Register: NVMC_READY */
2651 /* Description: Ready flag */
2652 
2653 /* Bit 0 : NVMC is ready or busy */
2654 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
2655 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
2656 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
2657 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
2658 
2659 /* Register: NVMC_READYNEXT */
2660 /* Description: Ready flag */
2661 
2662 /* Bit 0 : NVMC can accept a new write operation */
2663 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
2664 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
2665 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
2666 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
2667 
2668 /* Register: NVMC_CONFIG */
2669 /* Description: Configuration register */
2670 
2671 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
2672 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
2673 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
2674 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2675 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2676 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2677 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
2678 
2679 /* Register: NVMC_ERASEALL */
2680 /* Description: Register for erasing all non-volatile user memory */
2681 
2682 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */
2683 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
2684 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
2685 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
2686 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
2687 
2688 /* Register: NVMC_ERASEPAGEPARTIALCFG */
2689 /* Description: Register for partial erase configuration */
2690 
2691 /* Bits 6..0 : Duration of the partial erase in milliseconds */
2692 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
2693 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
2694 
2695 /* Register: NVMC_ICACHECNF */
2696 /* Description: I-code cache configuration register */
2697 
2698 /* Bit 8 : Cache profiling enable */
2699 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
2700 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
2701 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
2702 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
2703 
2704 /* Bit 0 : Cache enable */
2705 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
2706 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
2707 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
2708 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
2709 
2710 /* Register: NVMC_IHIT */
2711 /* Description: I-code cache hit counter */
2712 
2713 /* Bits 31..0 : Number of cache hits Write zero to clear */
2714 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
2715 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
2716 
2717 /* Register: NVMC_IMISS */
2718 /* Description: I-code cache miss counter */
2719 
2720 /* Bits 31..0 : Number of cache misses Write zero to clear */
2721 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
2722 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
2723 
2724 /* Register: NVMC_CONFIGNS */
2725 /* Description: Unspecified */
2726 
2727 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
2728 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
2729 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
2730 #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */
2731 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
2732 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
2733 
2734 /* Register: NVMC_WRITEUICRNS */
2735 /* Description: Non-secure APPROTECT enable register */
2736 
2737 /* Bits 31..4 : Key to write in order to validate the write operation */
2738 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
2739 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
2740 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */
2741 
2742 /* Bit 0 : Allow non-secure code to set APPROTECT */
2743 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
2744 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
2745 #define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
2746 
2747 
2748 /* Peripheral: GPIO */
2749 /* Description: GPIO Port 0 */
2750 
2751 /* Register: GPIO_OUT */
2752 /* Description: Write GPIO port */
2753 
2754 /* Bit 31 : Pin 31 */
2755 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2756 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2757 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
2758 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2759 
2760 /* Bit 30 : Pin 30 */
2761 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2762 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2763 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
2764 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2765 
2766 /* Bit 29 : Pin 29 */
2767 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2768 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2769 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
2770 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2771 
2772 /* Bit 28 : Pin 28 */
2773 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2774 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2775 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
2776 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2777 
2778 /* Bit 27 : Pin 27 */
2779 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2780 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2781 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
2782 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2783 
2784 /* Bit 26 : Pin 26 */
2785 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2786 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2787 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
2788 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2789 
2790 /* Bit 25 : Pin 25 */
2791 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2792 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2793 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
2794 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2795 
2796 /* Bit 24 : Pin 24 */
2797 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2798 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2799 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
2800 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2801 
2802 /* Bit 23 : Pin 23 */
2803 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2804 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2805 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
2806 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2807 
2808 /* Bit 22 : Pin 22 */
2809 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2810 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2811 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
2812 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2813 
2814 /* Bit 21 : Pin 21 */
2815 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2816 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2817 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
2818 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2819 
2820 /* Bit 20 : Pin 20 */
2821 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2822 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2823 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
2824 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2825 
2826 /* Bit 19 : Pin 19 */
2827 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2828 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2829 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
2830 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2831 
2832 /* Bit 18 : Pin 18 */
2833 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2834 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2835 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
2836 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2837 
2838 /* Bit 17 : Pin 17 */
2839 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2840 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2841 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
2842 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2843 
2844 /* Bit 16 : Pin 16 */
2845 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2846 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2847 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
2848 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2849 
2850 /* Bit 15 : Pin 15 */
2851 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2852 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2853 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
2854 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2855 
2856 /* Bit 14 : Pin 14 */
2857 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2858 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2859 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
2860 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2861 
2862 /* Bit 13 : Pin 13 */
2863 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2864 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2865 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
2866 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2867 
2868 /* Bit 12 : Pin 12 */
2869 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2870 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2871 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
2872 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2873 
2874 /* Bit 11 : Pin 11 */
2875 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2876 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2877 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
2878 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2879 
2880 /* Bit 10 : Pin 10 */
2881 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2882 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2883 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
2884 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2885 
2886 /* Bit 9 : Pin 9 */
2887 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2888 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2889 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
2890 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2891 
2892 /* Bit 8 : Pin 8 */
2893 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2894 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2895 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
2896 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2897 
2898 /* Bit 7 : Pin 7 */
2899 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2900 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2901 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
2902 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2903 
2904 /* Bit 6 : Pin 6 */
2905 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2906 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2907 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
2908 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2909 
2910 /* Bit 5 : Pin 5 */
2911 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2912 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2913 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
2914 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2915 
2916 /* Bit 4 : Pin 4 */
2917 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2918 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2919 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
2920 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2921 
2922 /* Bit 3 : Pin 3 */
2923 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2924 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2925 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
2926 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2927 
2928 /* Bit 2 : Pin 2 */
2929 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2930 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2931 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
2932 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2933 
2934 /* Bit 1 : Pin 1 */
2935 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2936 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2937 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
2938 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2939 
2940 /* Bit 0 : Pin 0 */
2941 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2942 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2943 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
2944 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2945 
2946 /* Register: GPIO_OUTSET */
2947 /* Description: Set individual bits in GPIO port */
2948 
2949 /* Bit 31 : Pin 31 */
2950 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2951 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2952 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2953 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2954 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2955 
2956 /* Bit 30 : Pin 30 */
2957 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2958 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2959 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2960 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2961 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2962 
2963 /* Bit 29 : Pin 29 */
2964 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2965 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2966 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2967 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2968 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2969 
2970 /* Bit 28 : Pin 28 */
2971 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2972 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2973 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2974 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2975 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2976 
2977 /* Bit 27 : Pin 27 */
2978 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2979 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2980 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2981 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2982 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2983 
2984 /* Bit 26 : Pin 26 */
2985 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2986 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2987 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2988 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2989 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2990 
2991 /* Bit 25 : Pin 25 */
2992 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2993 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2994 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2995 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2996 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2997 
2998 /* Bit 24 : Pin 24 */
2999 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3000 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3001 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
3002 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
3003 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3004 
3005 /* Bit 23 : Pin 23 */
3006 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3007 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3008 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
3009 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
3010 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3011 
3012 /* Bit 22 : Pin 22 */
3013 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3014 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3015 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
3016 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
3017 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3018 
3019 /* Bit 21 : Pin 21 */
3020 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3021 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3022 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
3023 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
3024 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3025 
3026 /* Bit 20 : Pin 20 */
3027 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3028 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3029 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
3030 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
3031 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3032 
3033 /* Bit 19 : Pin 19 */
3034 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3035 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3036 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
3037 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
3038 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3039 
3040 /* Bit 18 : Pin 18 */
3041 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3042 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3043 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
3044 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
3045 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3046 
3047 /* Bit 17 : Pin 17 */
3048 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3049 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3050 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
3051 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
3052 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3053 
3054 /* Bit 16 : Pin 16 */
3055 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3056 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3057 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
3058 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
3059 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3060 
3061 /* Bit 15 : Pin 15 */
3062 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3063 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3064 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
3065 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
3066 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3067 
3068 /* Bit 14 : Pin 14 */
3069 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3070 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3071 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
3072 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
3073 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3074 
3075 /* Bit 13 : Pin 13 */
3076 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3077 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3078 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
3079 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
3080 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3081 
3082 /* Bit 12 : Pin 12 */
3083 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3084 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3085 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
3086 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
3087 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3088 
3089 /* Bit 11 : Pin 11 */
3090 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3091 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3092 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
3093 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
3094 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3095 
3096 /* Bit 10 : Pin 10 */
3097 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3098 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3099 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
3100 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
3101 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3102 
3103 /* Bit 9 : Pin 9 */
3104 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3105 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3106 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
3107 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
3108 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3109 
3110 /* Bit 8 : Pin 8 */
3111 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3112 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3113 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
3114 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
3115 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3116 
3117 /* Bit 7 : Pin 7 */
3118 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3119 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3120 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
3121 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
3122 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3123 
3124 /* Bit 6 : Pin 6 */
3125 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3126 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3127 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
3128 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
3129 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3130 
3131 /* Bit 5 : Pin 5 */
3132 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3133 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3134 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
3135 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
3136 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3137 
3138 /* Bit 4 : Pin 4 */
3139 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3140 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3141 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
3142 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
3143 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3144 
3145 /* Bit 3 : Pin 3 */
3146 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3147 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3148 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
3149 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
3150 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3151 
3152 /* Bit 2 : Pin 2 */
3153 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3154 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3155 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
3156 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
3157 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3158 
3159 /* Bit 1 : Pin 1 */
3160 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3161 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3162 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
3163 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
3164 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3165 
3166 /* Bit 0 : Pin 0 */
3167 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3168 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3169 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
3170 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
3171 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3172 
3173 /* Register: GPIO_OUTCLR */
3174 /* Description: Clear individual bits in GPIO port */
3175 
3176 /* Bit 31 : Pin 31 */
3177 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3178 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3179 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
3180 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
3181 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3182 
3183 /* Bit 30 : Pin 30 */
3184 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3185 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3186 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
3187 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
3188 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3189 
3190 /* Bit 29 : Pin 29 */
3191 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3192 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3193 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
3194 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
3195 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3196 
3197 /* Bit 28 : Pin 28 */
3198 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3199 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3200 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
3201 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
3202 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3203 
3204 /* Bit 27 : Pin 27 */
3205 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3206 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3207 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
3208 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
3209 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3210 
3211 /* Bit 26 : Pin 26 */
3212 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3213 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3214 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
3215 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
3216 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3217 
3218 /* Bit 25 : Pin 25 */
3219 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3220 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3221 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
3222 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
3223 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3224 
3225 /* Bit 24 : Pin 24 */
3226 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3227 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3228 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
3229 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
3230 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3231 
3232 /* Bit 23 : Pin 23 */
3233 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3234 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3235 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
3236 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
3237 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3238 
3239 /* Bit 22 : Pin 22 */
3240 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3241 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3242 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
3243 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
3244 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3245 
3246 /* Bit 21 : Pin 21 */
3247 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3248 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3249 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
3250 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
3251 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3252 
3253 /* Bit 20 : Pin 20 */
3254 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3255 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3256 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
3257 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
3258 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3259 
3260 /* Bit 19 : Pin 19 */
3261 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3262 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3263 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
3264 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
3265 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3266 
3267 /* Bit 18 : Pin 18 */
3268 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3269 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3270 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
3271 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
3272 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3273 
3274 /* Bit 17 : Pin 17 */
3275 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3276 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3277 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
3278 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
3279 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3280 
3281 /* Bit 16 : Pin 16 */
3282 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3283 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3284 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
3285 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
3286 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3287 
3288 /* Bit 15 : Pin 15 */
3289 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3290 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3291 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
3292 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
3293 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3294 
3295 /* Bit 14 : Pin 14 */
3296 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3297 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3298 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
3299 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
3300 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3301 
3302 /* Bit 13 : Pin 13 */
3303 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3304 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3305 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
3306 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
3307 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3308 
3309 /* Bit 12 : Pin 12 */
3310 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3311 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3312 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
3313 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
3314 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3315 
3316 /* Bit 11 : Pin 11 */
3317 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3318 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3319 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
3320 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
3321 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3322 
3323 /* Bit 10 : Pin 10 */
3324 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3325 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3326 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
3327 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
3328 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3329 
3330 /* Bit 9 : Pin 9 */
3331 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3332 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3333 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
3334 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
3335 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3336 
3337 /* Bit 8 : Pin 8 */
3338 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3339 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3340 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
3341 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
3342 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3343 
3344 /* Bit 7 : Pin 7 */
3345 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3346 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3347 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
3348 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
3349 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3350 
3351 /* Bit 6 : Pin 6 */
3352 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3353 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3354 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
3355 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
3356 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3357 
3358 /* Bit 5 : Pin 5 */
3359 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3360 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3361 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
3362 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
3363 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3364 
3365 /* Bit 4 : Pin 4 */
3366 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3367 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3368 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
3369 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
3370 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3371 
3372 /* Bit 3 : Pin 3 */
3373 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3374 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3375 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
3376 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
3377 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3378 
3379 /* Bit 2 : Pin 2 */
3380 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3381 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3382 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
3383 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
3384 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3385 
3386 /* Bit 1 : Pin 1 */
3387 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3388 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3389 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
3390 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
3391 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3392 
3393 /* Bit 0 : Pin 0 */
3394 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3395 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3396 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
3397 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
3398 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3399 
3400 /* Register: GPIO_IN */
3401 /* Description: Read GPIO port */
3402 
3403 /* Bit 31 : Pin 31 */
3404 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3405 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3406 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
3407 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
3408 
3409 /* Bit 30 : Pin 30 */
3410 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3411 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3412 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
3413 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
3414 
3415 /* Bit 29 : Pin 29 */
3416 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3417 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3418 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
3419 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
3420 
3421 /* Bit 28 : Pin 28 */
3422 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3423 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3424 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
3425 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
3426 
3427 /* Bit 27 : Pin 27 */
3428 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3429 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3430 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
3431 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
3432 
3433 /* Bit 26 : Pin 26 */
3434 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3435 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3436 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
3437 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
3438 
3439 /* Bit 25 : Pin 25 */
3440 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3441 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3442 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
3443 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
3444 
3445 /* Bit 24 : Pin 24 */
3446 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3447 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3448 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
3449 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
3450 
3451 /* Bit 23 : Pin 23 */
3452 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3453 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3454 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
3455 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
3456 
3457 /* Bit 22 : Pin 22 */
3458 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3459 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3460 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
3461 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
3462 
3463 /* Bit 21 : Pin 21 */
3464 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3465 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3466 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
3467 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
3468 
3469 /* Bit 20 : Pin 20 */
3470 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3471 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3472 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
3473 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
3474 
3475 /* Bit 19 : Pin 19 */
3476 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3477 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3478 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
3479 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
3480 
3481 /* Bit 18 : Pin 18 */
3482 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3483 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3484 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
3485 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
3486 
3487 /* Bit 17 : Pin 17 */
3488 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3489 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3490 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
3491 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
3492 
3493 /* Bit 16 : Pin 16 */
3494 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3495 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3496 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
3497 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
3498 
3499 /* Bit 15 : Pin 15 */
3500 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3501 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3502 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
3503 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
3504 
3505 /* Bit 14 : Pin 14 */
3506 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3507 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3508 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
3509 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
3510 
3511 /* Bit 13 : Pin 13 */
3512 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3513 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3514 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
3515 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
3516 
3517 /* Bit 12 : Pin 12 */
3518 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3519 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3520 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
3521 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
3522 
3523 /* Bit 11 : Pin 11 */
3524 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3525 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3526 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
3527 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
3528 
3529 /* Bit 10 : Pin 10 */
3530 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3531 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3532 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
3533 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
3534 
3535 /* Bit 9 : Pin 9 */
3536 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3537 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3538 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
3539 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
3540 
3541 /* Bit 8 : Pin 8 */
3542 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3543 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3544 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
3545 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
3546 
3547 /* Bit 7 : Pin 7 */
3548 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3549 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3550 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
3551 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
3552 
3553 /* Bit 6 : Pin 6 */
3554 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3555 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3556 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
3557 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
3558 
3559 /* Bit 5 : Pin 5 */
3560 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3561 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3562 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
3563 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
3564 
3565 /* Bit 4 : Pin 4 */
3566 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3567 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3568 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
3569 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
3570 
3571 /* Bit 3 : Pin 3 */
3572 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3573 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3574 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
3575 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
3576 
3577 /* Bit 2 : Pin 2 */
3578 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3579 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3580 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
3581 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
3582 
3583 /* Bit 1 : Pin 1 */
3584 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3585 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3586 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
3587 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
3588 
3589 /* Bit 0 : Pin 0 */
3590 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3591 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3592 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
3593 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
3594 
3595 /* Register: GPIO_DIR */
3596 /* Description: Direction of GPIO pins */
3597 
3598 /* Bit 31 : Pin 31 */
3599 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3600 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3601 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
3602 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
3603 
3604 /* Bit 30 : Pin 30 */
3605 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3606 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3607 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
3608 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
3609 
3610 /* Bit 29 : Pin 29 */
3611 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3612 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3613 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
3614 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
3615 
3616 /* Bit 28 : Pin 28 */
3617 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3618 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3619 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
3620 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
3621 
3622 /* Bit 27 : Pin 27 */
3623 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3624 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3625 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
3626 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
3627 
3628 /* Bit 26 : Pin 26 */
3629 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3630 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3631 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
3632 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
3633 
3634 /* Bit 25 : Pin 25 */
3635 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3636 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3637 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
3638 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
3639 
3640 /* Bit 24 : Pin 24 */
3641 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3642 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3643 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
3644 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
3645 
3646 /* Bit 23 : Pin 23 */
3647 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3648 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3649 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
3650 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
3651 
3652 /* Bit 22 : Pin 22 */
3653 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3654 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3655 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
3656 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
3657 
3658 /* Bit 21 : Pin 21 */
3659 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3660 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3661 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
3662 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
3663 
3664 /* Bit 20 : Pin 20 */
3665 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3666 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3667 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
3668 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
3669 
3670 /* Bit 19 : Pin 19 */
3671 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3672 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3673 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
3674 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
3675 
3676 /* Bit 18 : Pin 18 */
3677 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3678 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3679 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
3680 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
3681 
3682 /* Bit 17 : Pin 17 */
3683 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3684 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3685 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
3686 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
3687 
3688 /* Bit 16 : Pin 16 */
3689 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3690 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3691 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
3692 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
3693 
3694 /* Bit 15 : Pin 15 */
3695 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3696 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3697 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
3698 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
3699 
3700 /* Bit 14 : Pin 14 */
3701 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3702 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3703 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
3704 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
3705 
3706 /* Bit 13 : Pin 13 */
3707 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3708 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3709 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
3710 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
3711 
3712 /* Bit 12 : Pin 12 */
3713 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3714 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3715 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
3716 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
3717 
3718 /* Bit 11 : Pin 11 */
3719 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3720 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3721 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
3722 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
3723 
3724 /* Bit 10 : Pin 10 */
3725 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3726 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3727 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
3728 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
3729 
3730 /* Bit 9 : Pin 9 */
3731 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3732 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3733 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
3734 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
3735 
3736 /* Bit 8 : Pin 8 */
3737 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3738 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3739 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
3740 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
3741 
3742 /* Bit 7 : Pin 7 */
3743 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3744 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3745 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
3746 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
3747 
3748 /* Bit 6 : Pin 6 */
3749 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3750 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3751 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
3752 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
3753 
3754 /* Bit 5 : Pin 5 */
3755 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3756 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3757 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
3758 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
3759 
3760 /* Bit 4 : Pin 4 */
3761 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3762 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3763 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
3764 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
3765 
3766 /* Bit 3 : Pin 3 */
3767 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3768 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3769 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
3770 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
3771 
3772 /* Bit 2 : Pin 2 */
3773 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3774 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3775 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
3776 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
3777 
3778 /* Bit 1 : Pin 1 */
3779 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3780 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3781 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
3782 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
3783 
3784 /* Bit 0 : Pin 0 */
3785 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3786 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3787 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
3788 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
3789 
3790 /* Register: GPIO_DIRSET */
3791 /* Description: DIR set register */
3792 
3793 /* Bit 31 : Set as output pin 31 */
3794 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3795 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3796 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3797 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3798 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3799 
3800 /* Bit 30 : Set as output pin 30 */
3801 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3802 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3803 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3804 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3805 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3806 
3807 /* Bit 29 : Set as output pin 29 */
3808 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3809 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3810 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3811 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3812 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3813 
3814 /* Bit 28 : Set as output pin 28 */
3815 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3816 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3817 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3818 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3819 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3820 
3821 /* Bit 27 : Set as output pin 27 */
3822 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3823 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3824 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3825 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3826 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3827 
3828 /* Bit 26 : Set as output pin 26 */
3829 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3830 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3831 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3832 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3833 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3834 
3835 /* Bit 25 : Set as output pin 25 */
3836 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3837 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3838 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3839 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3840 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3841 
3842 /* Bit 24 : Set as output pin 24 */
3843 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3844 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3845 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3846 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3847 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3848 
3849 /* Bit 23 : Set as output pin 23 */
3850 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3851 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3852 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3853 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3854 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3855 
3856 /* Bit 22 : Set as output pin 22 */
3857 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3858 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3859 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3860 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3861 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3862 
3863 /* Bit 21 : Set as output pin 21 */
3864 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3865 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3866 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3867 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3868 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3869 
3870 /* Bit 20 : Set as output pin 20 */
3871 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3872 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3873 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3874 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3875 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3876 
3877 /* Bit 19 : Set as output pin 19 */
3878 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3879 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3880 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3881 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3882 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3883 
3884 /* Bit 18 : Set as output pin 18 */
3885 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3886 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3887 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3888 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3889 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3890 
3891 /* Bit 17 : Set as output pin 17 */
3892 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3893 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3894 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3895 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3896 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3897 
3898 /* Bit 16 : Set as output pin 16 */
3899 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3900 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3901 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3902 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3903 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3904 
3905 /* Bit 15 : Set as output pin 15 */
3906 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3907 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3908 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3909 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3910 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3911 
3912 /* Bit 14 : Set as output pin 14 */
3913 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3914 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3915 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3916 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3917 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3918 
3919 /* Bit 13 : Set as output pin 13 */
3920 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3921 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3922 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3923 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3924 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3925 
3926 /* Bit 12 : Set as output pin 12 */
3927 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3928 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3929 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3930 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3931 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3932 
3933 /* Bit 11 : Set as output pin 11 */
3934 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3935 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3936 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3937 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3938 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3939 
3940 /* Bit 10 : Set as output pin 10 */
3941 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3942 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3943 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3944 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3945 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3946 
3947 /* Bit 9 : Set as output pin 9 */
3948 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3949 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3950 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3951 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3952 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3953 
3954 /* Bit 8 : Set as output pin 8 */
3955 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3956 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3957 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3958 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3959 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3960 
3961 /* Bit 7 : Set as output pin 7 */
3962 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3963 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3964 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3965 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3966 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3967 
3968 /* Bit 6 : Set as output pin 6 */
3969 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3970 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3971 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3972 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3973 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3974 
3975 /* Bit 5 : Set as output pin 5 */
3976 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3977 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3978 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3979 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3980 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3981 
3982 /* Bit 4 : Set as output pin 4 */
3983 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3984 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3985 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3986 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3987 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3988 
3989 /* Bit 3 : Set as output pin 3 */
3990 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3991 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3992 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3993 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3994 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3995 
3996 /* Bit 2 : Set as output pin 2 */
3997 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3998 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3999 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
4000 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
4001 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
4002 
4003 /* Bit 1 : Set as output pin 1 */
4004 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4005 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4006 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
4007 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
4008 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
4009 
4010 /* Bit 0 : Set as output pin 0 */
4011 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4012 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4013 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
4014 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
4015 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
4016 
4017 /* Register: GPIO_DIRCLR */
4018 /* Description: DIR clear register */
4019 
4020 /* Bit 31 : Set as input pin 31 */
4021 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4022 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4023 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
4024 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
4025 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4026 
4027 /* Bit 30 : Set as input pin 30 */
4028 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4029 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4030 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
4031 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
4032 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4033 
4034 /* Bit 29 : Set as input pin 29 */
4035 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4036 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4037 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
4038 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
4039 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4040 
4041 /* Bit 28 : Set as input pin 28 */
4042 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4043 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4044 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
4045 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
4046 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4047 
4048 /* Bit 27 : Set as input pin 27 */
4049 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4050 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4051 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
4052 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
4053 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4054 
4055 /* Bit 26 : Set as input pin 26 */
4056 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4057 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4058 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
4059 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
4060 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4061 
4062 /* Bit 25 : Set as input pin 25 */
4063 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4064 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4065 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
4066 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
4067 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4068 
4069 /* Bit 24 : Set as input pin 24 */
4070 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4071 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4072 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
4073 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
4074 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4075 
4076 /* Bit 23 : Set as input pin 23 */
4077 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4078 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4079 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
4080 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
4081 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4082 
4083 /* Bit 22 : Set as input pin 22 */
4084 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4085 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4086 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
4087 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
4088 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4089 
4090 /* Bit 21 : Set as input pin 21 */
4091 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4092 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4093 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
4094 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
4095 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4096 
4097 /* Bit 20 : Set as input pin 20 */
4098 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4099 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4100 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
4101 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
4102 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4103 
4104 /* Bit 19 : Set as input pin 19 */
4105 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4106 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4107 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
4108 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
4109 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4110 
4111 /* Bit 18 : Set as input pin 18 */
4112 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4113 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4114 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
4115 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
4116 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4117 
4118 /* Bit 17 : Set as input pin 17 */
4119 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4120 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4121 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
4122 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
4123 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4124 
4125 /* Bit 16 : Set as input pin 16 */
4126 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4127 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4128 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
4129 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
4130 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4131 
4132 /* Bit 15 : Set as input pin 15 */
4133 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4134 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4135 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
4136 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
4137 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4138 
4139 /* Bit 14 : Set as input pin 14 */
4140 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4141 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4142 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
4143 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
4144 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4145 
4146 /* Bit 13 : Set as input pin 13 */
4147 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4148 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4149 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
4150 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
4151 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4152 
4153 /* Bit 12 : Set as input pin 12 */
4154 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4155 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4156 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
4157 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
4158 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4159 
4160 /* Bit 11 : Set as input pin 11 */
4161 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4162 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4163 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
4164 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
4165 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4166 
4167 /* Bit 10 : Set as input pin 10 */
4168 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4169 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4170 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
4171 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
4172 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4173 
4174 /* Bit 9 : Set as input pin 9 */
4175 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4176 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4177 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
4178 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
4179 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4180 
4181 /* Bit 8 : Set as input pin 8 */
4182 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4183 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4184 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
4185 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
4186 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4187 
4188 /* Bit 7 : Set as input pin 7 */
4189 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4190 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4191 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
4192 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
4193 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4194 
4195 /* Bit 6 : Set as input pin 6 */
4196 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4197 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4198 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
4199 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
4200 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4201 
4202 /* Bit 5 : Set as input pin 5 */
4203 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4204 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4205 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
4206 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
4207 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4208 
4209 /* Bit 4 : Set as input pin 4 */
4210 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4211 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4212 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
4213 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
4214 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4215 
4216 /* Bit 3 : Set as input pin 3 */
4217 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4218 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4219 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
4220 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
4221 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4222 
4223 /* Bit 2 : Set as input pin 2 */
4224 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4225 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4226 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
4227 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
4228 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4229 
4230 /* Bit 1 : Set as input pin 1 */
4231 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4232 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4233 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
4234 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
4235 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4236 
4237 /* Bit 0 : Set as input pin 0 */
4238 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4239 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4240 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
4241 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
4242 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4243 
4244 /* Register: GPIO_LATCH */
4245 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
4246 
4247 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
4248 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4249 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4250 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
4251 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
4252 
4253 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
4254 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4255 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4256 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
4257 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
4258 
4259 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
4260 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4261 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4262 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
4263 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
4264 
4265 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
4266 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4267 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4268 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
4269 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
4270 
4271 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
4272 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4273 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4274 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
4275 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
4276 
4277 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
4278 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4279 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4280 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
4281 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
4282 
4283 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
4284 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4285 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4286 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
4287 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
4288 
4289 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
4290 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4291 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4292 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
4293 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
4294 
4295 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
4296 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4297 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4298 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
4299 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
4300 
4301 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
4302 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4303 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4304 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
4305 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
4306 
4307 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
4308 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4309 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4310 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
4311 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
4312 
4313 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
4314 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4315 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4316 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
4317 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
4318 
4319 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
4320 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4321 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4322 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
4323 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
4324 
4325 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
4326 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4327 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4328 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
4329 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
4330 
4331 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
4332 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4333 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4334 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
4335 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
4336 
4337 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
4338 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4339 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4340 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
4341 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
4342 
4343 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
4344 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4345 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4346 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
4347 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
4348 
4349 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
4350 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4351 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4352 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
4353 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
4354 
4355 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
4356 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4357 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4358 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
4359 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
4360 
4361 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
4362 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4363 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4364 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
4365 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
4366 
4367 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
4368 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4369 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4370 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
4371 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
4372 
4373 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
4374 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4375 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4376 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
4377 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
4378 
4379 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
4380 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4381 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4382 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
4383 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
4384 
4385 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
4386 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4387 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4388 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
4389 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
4390 
4391 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
4392 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4393 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4394 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
4395 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
4396 
4397 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
4398 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4399 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4400 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
4401 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
4402 
4403 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
4404 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4405 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4406 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
4407 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
4408 
4409 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
4410 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4411 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4412 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
4413 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
4414 
4415 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
4416 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4417 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4418 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
4419 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
4420 
4421 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
4422 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4423 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4424 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
4425 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
4426 
4427 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
4428 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4429 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4430 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
4431 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
4432 
4433 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
4434 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4435 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4436 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
4437 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
4438 
4439 /* Register: GPIO_DETECTMODE */
4440 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
4441 
4442 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
4443 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
4444 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
4445 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
4446 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
4447 
4448 /* Register: GPIO_DETECTMODE_SEC */
4449 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
4450 
4451 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
4452 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
4453 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
4454 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
4455 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
4456 
4457 /* Register: GPIO_PIN_CNF */
4458 /* Description: Description collection: Configuration of GPIO pins */
4459 
4460 /* Bits 17..16 : Pin sensing mechanism */
4461 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
4462 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
4463 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
4464 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
4465 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
4466 
4467 /* Bits 10..8 : Drive configuration */
4468 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
4469 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
4470 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
4471 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
4472 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
4473 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
4474 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
4475 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
4476 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
4477 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
4478 
4479 /* Bits 3..2 : Pull configuration */
4480 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
4481 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
4482 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
4483 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
4484 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
4485 
4486 /* Bit 1 : Connect or disconnect input buffer */
4487 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
4488 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
4489 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
4490 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
4491 
4492 /* Bit 0 : Pin direction. Same physical register as DIR register */
4493 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
4494 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
4495 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
4496 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
4497 
4498 
4499 /* Peripheral: PDM */
4500 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */
4501 
4502 /* Register: PDM_TASKS_START */
4503 /* Description: Starts continuous PDM transfer */
4504 
4505 /* Bit 0 : Starts continuous PDM transfer */
4506 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
4507 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
4508 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
4509 
4510 /* Register: PDM_TASKS_STOP */
4511 /* Description: Stops PDM transfer */
4512 
4513 /* Bit 0 : Stops PDM transfer */
4514 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
4515 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
4516 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4517 
4518 /* Register: PDM_SUBSCRIBE_START */
4519 /* Description: Subscribe configuration for task START */
4520 
4521 /* Bit 31 :   */
4522 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
4523 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
4524 #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
4525 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
4526 
4527 /* Bits 7..0 : DPPI channel that task START will subscribe to */
4528 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4529 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4530 
4531 /* Register: PDM_SUBSCRIBE_STOP */
4532 /* Description: Subscribe configuration for task STOP */
4533 
4534 /* Bit 31 :   */
4535 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
4536 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
4537 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
4538 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4539 
4540 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
4541 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4542 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4543 
4544 /* Register: PDM_EVENTS_STARTED */
4545 /* Description: PDM transfer has started */
4546 
4547 /* Bit 0 : PDM transfer has started */
4548 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
4549 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
4550 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
4551 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4552 
4553 /* Register: PDM_EVENTS_STOPPED */
4554 /* Description: PDM transfer has finished */
4555 
4556 /* Bit 0 : PDM transfer has finished */
4557 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
4558 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
4559 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
4560 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
4561 
4562 /* Register: PDM_EVENTS_END */
4563 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
4564 
4565 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
4566 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
4567 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
4568 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
4569 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
4570 
4571 /* Register: PDM_PUBLISH_STARTED */
4572 /* Description: Publish configuration for event STARTED */
4573 
4574 /* Bit 31 :   */
4575 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
4576 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
4577 #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
4578 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
4579 
4580 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
4581 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4582 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4583 
4584 /* Register: PDM_PUBLISH_STOPPED */
4585 /* Description: Publish configuration for event STOPPED */
4586 
4587 /* Bit 31 :   */
4588 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
4589 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
4590 #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
4591 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
4592 
4593 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
4594 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4595 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4596 
4597 /* Register: PDM_PUBLISH_END */
4598 /* Description: Publish configuration for event END */
4599 
4600 /* Bit 31 :   */
4601 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
4602 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
4603 #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
4604 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
4605 
4606 /* Bits 7..0 : DPPI channel that event END will publish to */
4607 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4608 #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4609 
4610 /* Register: PDM_INTEN */
4611 /* Description: Enable or disable interrupt */
4612 
4613 /* Bit 2 : Enable or disable interrupt for event END */
4614 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
4615 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
4616 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
4617 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
4618 
4619 /* Bit 1 : Enable or disable interrupt for event STOPPED */
4620 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4621 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4622 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
4623 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
4624 
4625 /* Bit 0 : Enable or disable interrupt for event STARTED */
4626 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4627 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4628 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4629 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4630 
4631 /* Register: PDM_INTENSET */
4632 /* Description: Enable interrupt */
4633 
4634 /* Bit 2 : Write '1' to enable interrupt for event END */
4635 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
4636 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
4637 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
4638 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4639 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
4640 
4641 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
4642 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4643 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4644 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4645 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4646 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4647 
4648 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
4649 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4650 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4651 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4652 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4653 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
4654 
4655 /* Register: PDM_INTENCLR */
4656 /* Description: Disable interrupt */
4657 
4658 /* Bit 2 : Write '1' to disable interrupt for event END */
4659 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
4660 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
4661 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4662 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4663 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
4664 
4665 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
4666 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4667 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4668 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4669 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4670 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4671 
4672 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
4673 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4674 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4675 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4676 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4677 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4678 
4679 /* Register: PDM_ENABLE */
4680 /* Description: PDM module enable register */
4681 
4682 /* Bit 0 : Enable or disable PDM module */
4683 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4684 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4685 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4686 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4687 
4688 /* Register: PDM_PDMCLKCTRL */
4689 /* Description: PDM clock generator control */
4690 
4691 /* Bits 31..0 : PDM_CLK frequency configuration. */
4692 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
4693 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
4694 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
4695 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
4696 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
4697 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
4698 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
4699 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
4700 
4701 /* Register: PDM_MODE */
4702 /* Description: Defines the routing of the connected PDM microphones' signals */
4703 
4704 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
4705 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
4706 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
4707 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
4708 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
4709 
4710 /* Bit 0 : Mono or stereo operation */
4711 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
4712 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
4713 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
4714 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
4715 
4716 /* Register: PDM_GAINL */
4717 /* Description: Left output gain adjustment */
4718 
4719 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
4720 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
4721 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
4722 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
4723 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
4724 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
4725 
4726 /* Register: PDM_GAINR */
4727 /* Description: Right output gain adjustment */
4728 
4729 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
4730 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
4731 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
4732 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
4733 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
4734 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
4735 
4736 /* Register: PDM_RATIO */
4737 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
4738 
4739 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
4740 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
4741 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
4742 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
4743 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
4744 
4745 /* Register: PDM_PSEL_CLK */
4746 /* Description: Pin number configuration for PDM CLK signal */
4747 
4748 /* Bit 31 : Connection */
4749 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4750 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4751 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
4752 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4753 
4754 /* Bits 4..0 : Pin number */
4755 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
4756 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
4757 
4758 /* Register: PDM_PSEL_DIN */
4759 /* Description: Pin number configuration for PDM DIN signal */
4760 
4761 /* Bit 31 : Connection */
4762 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4763 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4764 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
4765 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
4766 
4767 /* Bits 4..0 : Pin number */
4768 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
4769 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
4770 
4771 /* Register: PDM_SAMPLE_PTR */
4772 /* Description: RAM address pointer to write samples to with EasyDMA */
4773 
4774 /* Bits 31..0 : Address to write PDM samples to over DMA */
4775 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
4776 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
4777 
4778 /* Register: PDM_SAMPLE_MAXCNT */
4779 /* Description: Number of samples to allocate memory for in EasyDMA mode */
4780 
4781 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
4782 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
4783 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
4784 
4785 
4786 /* Peripheral: POWER */
4787 /* Description: Power control 0 */
4788 
4789 /* Register: POWER_TASKS_CONSTLAT */
4790 /* Description: Enable constant latency mode. */
4791 
4792 /* Bit 0 : Enable constant latency mode. */
4793 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
4794 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
4795 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
4796 
4797 /* Register: POWER_TASKS_LOWPWR */
4798 /* Description: Enable low power mode (variable latency) */
4799 
4800 /* Bit 0 : Enable low power mode (variable latency) */
4801 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
4802 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
4803 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
4804 
4805 /* Register: POWER_SUBSCRIBE_CONSTLAT */
4806 /* Description: Subscribe configuration for task CONSTLAT */
4807 
4808 /* Bit 31 :   */
4809 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
4810 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
4811 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
4812 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
4813 
4814 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
4815 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4816 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4817 
4818 /* Register: POWER_SUBSCRIBE_LOWPWR */
4819 /* Description: Subscribe configuration for task LOWPWR */
4820 
4821 /* Bit 31 :   */
4822 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
4823 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
4824 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
4825 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
4826 
4827 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
4828 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4829 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4830 
4831 /* Register: POWER_EVENTS_POFWARN */
4832 /* Description: Power failure warning */
4833 
4834 /* Bit 0 : Power failure warning */
4835 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
4836 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
4837 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
4838 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
4839 
4840 /* Register: POWER_EVENTS_SLEEPENTER */
4841 /* Description: CPU entered WFI/WFE sleep */
4842 
4843 /* Bit 0 : CPU entered WFI/WFE sleep */
4844 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
4845 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
4846 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
4847 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
4848 
4849 /* Register: POWER_EVENTS_SLEEPEXIT */
4850 /* Description: CPU exited WFI/WFE sleep */
4851 
4852 /* Bit 0 : CPU exited WFI/WFE sleep */
4853 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
4854 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
4855 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
4856 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
4857 
4858 /* Register: POWER_PUBLISH_POFWARN */
4859 /* Description: Publish configuration for event POFWARN */
4860 
4861 /* Bit 31 :   */
4862 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
4863 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
4864 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
4865 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
4866 
4867 /* Bits 7..0 : DPPI channel that event POFWARN will publish to */
4868 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4869 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4870 
4871 /* Register: POWER_PUBLISH_SLEEPENTER */
4872 /* Description: Publish configuration for event SLEEPENTER */
4873 
4874 /* Bit 31 :   */
4875 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
4876 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
4877 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
4878 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
4879 
4880 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */
4881 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4882 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4883 
4884 /* Register: POWER_PUBLISH_SLEEPEXIT */
4885 /* Description: Publish configuration for event SLEEPEXIT */
4886 
4887 /* Bit 31 :   */
4888 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
4889 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
4890 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
4891 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
4892 
4893 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */
4894 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4895 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4896 
4897 /* Register: POWER_INTEN */
4898 /* Description: Enable or disable interrupt */
4899 
4900 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
4901 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4902 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4903 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
4904 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
4905 
4906 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
4907 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4908 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4909 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
4910 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
4911 
4912 /* Bit 2 : Enable or disable interrupt for event POFWARN */
4913 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4914 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4915 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
4916 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
4917 
4918 /* Register: POWER_INTENSET */
4919 /* Description: Enable interrupt */
4920 
4921 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
4922 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4923 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4924 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4925 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4926 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4927 
4928 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
4929 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4930 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4931 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4932 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4933 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4934 
4935 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4936 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4937 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4938 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4939 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4940 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4941 
4942 /* Register: POWER_INTENCLR */
4943 /* Description: Disable interrupt */
4944 
4945 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
4946 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4947 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4948 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4949 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4950 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4951 
4952 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
4953 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4954 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4955 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4956 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4957 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4958 
4959 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4960 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4961 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4962 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4963 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4964 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4965 
4966 /* Register: POWER_RESETREAS */
4967 /* Description: Reset reason */
4968 
4969 /* Bit 18 : Reset triggered through CTRL-AP */
4970 #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */
4971 #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
4972 #define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */
4973 #define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
4974 
4975 /* Bit 17 : Reset from CPU lock-up detected */
4976 #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */
4977 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
4978 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
4979 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
4980 
4981 /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */
4982 #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */
4983 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
4984 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
4985 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
4986 
4987 /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */
4988 #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */
4989 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
4990 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
4991 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
4992 
4993 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */
4994 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */
4995 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
4996 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
4997 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
4998 
4999 /* Bit 1 : Reset from global watchdog detected */
5000 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
5001 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
5002 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
5003 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
5004 
5005 /* Bit 0 : Reset from pin reset detected */
5006 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
5007 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
5008 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
5009 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
5010 
5011 /* Register: POWER_POWERSTATUS */
5012 /* Description: Modem domain power status */
5013 
5014 /* Bit 0 : LTE modem domain status */
5015 #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */
5016 #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */
5017 #define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */
5018 #define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */
5019 
5020 /* Register: POWER_GPREGRET */
5021 /* Description: Description collection: General purpose retention register */
5022 
5023 /* Bits 7..0 : General purpose retention register */
5024 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
5025 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
5026 
5027 /* Register: POWER_LTEMODEM_STARTN */
5028 /* Description: Start LTE modem */
5029 
5030 /* Bit 0 : Start LTE modem */
5031 #define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */
5032 #define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */
5033 #define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */
5034 #define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */
5035 
5036 /* Register: POWER_LTEMODEM_FORCEOFF */
5037 /* Description: Force off LTE modem */
5038 
5039 /* Bit 0 : Force off LTE modem */
5040 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
5041 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
5042 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */
5043 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */
5044 
5045 
5046 /* Peripheral: PWM */
5047 /* Description: Pulse width modulation unit 0 */
5048 
5049 /* Register: PWM_TASKS_STOP */
5050 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
5051 
5052 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
5053 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5054 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5055 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5056 
5057 /* Register: PWM_TASKS_SEQSTART */
5058 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
5059 
5060 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
5061 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
5062 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
5063 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
5064 
5065 /* Register: PWM_TASKS_NEXTSTEP */
5066 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
5067 
5068 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
5069 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
5070 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
5071 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
5072 
5073 /* Register: PWM_SUBSCRIBE_STOP */
5074 /* Description: Subscribe configuration for task STOP */
5075 
5076 /* Bit 31 :   */
5077 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5078 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5079 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5080 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5081 
5082 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5083 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5084 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5085 
5086 /* Register: PWM_SUBSCRIBE_SEQSTART */
5087 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
5088 
5089 /* Bit 31 :   */
5090 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
5091 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
5092 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
5093 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
5094 
5095 /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
5096 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5097 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5098 
5099 /* Register: PWM_SUBSCRIBE_NEXTSTEP */
5100 /* Description: Subscribe configuration for task NEXTSTEP */
5101 
5102 /* Bit 31 :   */
5103 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
5104 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
5105 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
5106 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
5107 
5108 /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
5109 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5110 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5111 
5112 /* Register: PWM_EVENTS_STOPPED */
5113 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
5114 
5115 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
5116 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
5117 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
5118 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
5119 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5120 
5121 /* Register: PWM_EVENTS_SEQSTARTED */
5122 /* Description: Description collection: First PWM period started on sequence n */
5123 
5124 /* Bit 0 : First PWM period started on sequence n */
5125 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
5126 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
5127 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
5128 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
5129 
5130 /* Register: PWM_EVENTS_SEQEND */
5131 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5132 
5133 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5134 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
5135 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
5136 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
5137 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
5138 
5139 /* Register: PWM_EVENTS_PWMPERIODEND */
5140 /* Description: Emitted at the end of each PWM period */
5141 
5142 /* Bit 0 : Emitted at the end of each PWM period */
5143 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
5144 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
5145 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
5146 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
5147 
5148 /* Register: PWM_EVENTS_LOOPSDONE */
5149 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5150 
5151 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5152 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
5153 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
5154 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
5155 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
5156 
5157 /* Register: PWM_PUBLISH_STOPPED */
5158 /* Description: Publish configuration for event STOPPED */
5159 
5160 /* Bit 31 :   */
5161 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
5162 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
5163 #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
5164 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
5165 
5166 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
5167 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5168 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5169 
5170 /* Register: PWM_PUBLISH_SEQSTARTED */
5171 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
5172 
5173 /* Bit 31 :   */
5174 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
5175 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
5176 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
5177 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
5178 
5179 /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */
5180 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5181 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5182 
5183 /* Register: PWM_PUBLISH_SEQEND */
5184 /* Description: Description collection: Publish configuration for event SEQEND[n] */
5185 
5186 /* Bit 31 :   */
5187 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
5188 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
5189 #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
5190 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
5191 
5192 /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */
5193 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5194 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5195 
5196 /* Register: PWM_PUBLISH_PWMPERIODEND */
5197 /* Description: Publish configuration for event PWMPERIODEND */
5198 
5199 /* Bit 31 :   */
5200 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
5201 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
5202 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
5203 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
5204 
5205 /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */
5206 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5207 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5208 
5209 /* Register: PWM_PUBLISH_LOOPSDONE */
5210 /* Description: Publish configuration for event LOOPSDONE */
5211 
5212 /* Bit 31 :   */
5213 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
5214 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
5215 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
5216 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
5217 
5218 /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */
5219 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5220 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5221 
5222 /* Register: PWM_SHORTS */
5223 /* Description: Shortcuts between local events and tasks */
5224 
5225 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
5226 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
5227 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
5228 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
5229 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5230 
5231 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
5232 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
5233 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
5234 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
5235 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5236 
5237 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
5238 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
5239 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
5240 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
5241 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5242 
5243 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
5244 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
5245 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
5246 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
5247 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5248 
5249 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
5250 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
5251 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
5252 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
5253 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5254 
5255 /* Register: PWM_INTEN */
5256 /* Description: Enable or disable interrupt */
5257 
5258 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
5259 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5260 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5261 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
5262 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5263 
5264 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
5265 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5266 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5267 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
5268 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5269 
5270 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5271 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5272 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5273 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
5274 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5275 
5276 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
5277 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5278 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5279 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
5280 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5281 
5282 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5283 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5284 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5285 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
5286 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5287 
5288 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5289 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5290 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5291 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
5292 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5293 
5294 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5295 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5296 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5297 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
5298 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5299 
5300 /* Register: PWM_INTENSET */
5301 /* Description: Enable interrupt */
5302 
5303 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
5304 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5305 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5306 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5307 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5308 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5309 
5310 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
5311 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5312 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5313 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5314 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5315 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5316 
5317 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
5318 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5319 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5320 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5321 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5322 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5323 
5324 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
5325 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5326 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5327 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5328 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5329 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5330 
5331 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
5332 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5333 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5334 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5335 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5336 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5337 
5338 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5339 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5340 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5341 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5342 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5343 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5344 
5345 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
5346 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5347 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5348 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5349 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5350 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5351 
5352 /* Register: PWM_INTENCLR */
5353 /* Description: Disable interrupt */
5354 
5355 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
5356 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5357 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5358 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5359 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5360 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5361 
5362 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
5363 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5364 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5365 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5366 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5367 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5368 
5369 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
5370 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5371 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5372 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5373 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5374 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5375 
5376 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
5377 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5378 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5379 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5380 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5381 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5382 
5383 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
5384 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5385 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5386 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5387 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5388 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5389 
5390 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5391 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5392 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5393 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5394 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5395 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5396 
5397 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
5398 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5399 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5400 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5401 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5402 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5403 
5404 /* Register: PWM_ENABLE */
5405 /* Description: PWM module enable register */
5406 
5407 /* Bit 0 : Enable or disable PWM module */
5408 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5409 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5410 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
5411 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5412 
5413 /* Register: PWM_MODE */
5414 /* Description: Selects operating mode of the wave counter */
5415 
5416 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
5417 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
5418 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
5419 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
5420 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
5421 
5422 /* Register: PWM_COUNTERTOP */
5423 /* Description: Value up to which the pulse generator counter counts */
5424 
5425 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
5426 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
5427 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
5428 
5429 /* Register: PWM_PRESCALER */
5430 /* Description: Configuration for PWM_CLK */
5431 
5432 /* Bits 2..0 : Prescaler of PWM_CLK */
5433 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5434 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5435 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
5436 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5437 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
5438 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
5439 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
5440 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
5441 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
5442 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
5443 
5444 /* Register: PWM_DECODER */
5445 /* Description: Configuration of the decoder */
5446 
5447 /* Bit 8 : Selects source for advancing the active sequence */
5448 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
5449 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
5450 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
5451 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
5452 
5453 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5454 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
5455 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
5456 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
5457 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
5458 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
5459 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
5460 
5461 /* Register: PWM_LOOP */
5462 /* Description: Number of playbacks of a loop */
5463 
5464 /* Bits 15..0 : Number of playbacks of pattern cycles */
5465 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
5466 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
5467 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
5468 
5469 /* Register: PWM_SEQ_PTR */
5470 /* Description: Description cluster: Beginning address in RAM of this sequence */
5471 
5472 /* Bits 31..0 : Beginning address in RAM of this sequence */
5473 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
5474 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
5475 
5476 /* Register: PWM_SEQ_CNT */
5477 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
5478 
5479 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
5480 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
5481 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
5482 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
5483 
5484 /* Register: PWM_SEQ_REFRESH */
5485 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
5486 
5487 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
5488 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
5489 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
5490 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
5491 
5492 /* Register: PWM_SEQ_ENDDELAY */
5493 /* Description: Description cluster: Time added after the sequence */
5494 
5495 /* Bits 23..0 : Time added after the sequence in PWM periods */
5496 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
5497 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
5498 
5499 /* Register: PWM_PSEL_OUT */
5500 /* Description: Description collection: Output pin select for PWM channel n */
5501 
5502 /* Bit 31 : Connection */
5503 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5504 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5505 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
5506 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
5507 
5508 /* Bits 4..0 : Pin number */
5509 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
5510 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
5511 
5512 
5513 /* Peripheral: REGULATORS */
5514 /* Description: Voltage regulators control 0 */
5515 
5516 /* Register: REGULATORS_SYSTEMOFF */
5517 /* Description: System OFF register */
5518 
5519 /* Bit 0 : Enable System OFF mode */
5520 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
5521 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
5522 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
5523 
5524 /* Register: REGULATORS_EXTPOFCON */
5525 /* Description: External power failure warning configuration */
5526 
5527 /* Bit 0 : Enable or disable external power failure warning */
5528 #define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */
5529 #define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */
5530 #define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */
5531 #define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */
5532 
5533 /* Register: REGULATORS_DCDCEN */
5534 /* Description: Enable DC/DC mode of the main voltage regulator. */
5535 
5536 /* Bit 0 : Enable DC/DC converter */
5537 #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
5538 #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
5539 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */
5540 #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */
5541 
5542 
5543 /* Peripheral: RTC */
5544 /* Description: Real-time counter 0 */
5545 
5546 /* Register: RTC_TASKS_START */
5547 /* Description: Start RTC counter */
5548 
5549 /* Bit 0 : Start RTC counter */
5550 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5551 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5552 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5553 
5554 /* Register: RTC_TASKS_STOP */
5555 /* Description: Stop RTC counter */
5556 
5557 /* Bit 0 : Stop RTC counter */
5558 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5559 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5560 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5561 
5562 /* Register: RTC_TASKS_CLEAR */
5563 /* Description: Clear RTC counter */
5564 
5565 /* Bit 0 : Clear RTC counter */
5566 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
5567 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
5568 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
5569 
5570 /* Register: RTC_TASKS_TRIGOVRFLW */
5571 /* Description: Set counter to 0xFFFFF0 */
5572 
5573 /* Bit 0 : Set counter to 0xFFFFF0 */
5574 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
5575 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
5576 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
5577 
5578 /* Register: RTC_SUBSCRIBE_START */
5579 /* Description: Subscribe configuration for task START */
5580 
5581 /* Bit 31 :   */
5582 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5583 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5584 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5585 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5586 
5587 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5588 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5589 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5590 
5591 /* Register: RTC_SUBSCRIBE_STOP */
5592 /* Description: Subscribe configuration for task STOP */
5593 
5594 /* Bit 31 :   */
5595 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5596 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5597 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5598 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5599 
5600 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5601 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5602 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5603 
5604 /* Register: RTC_SUBSCRIBE_CLEAR */
5605 /* Description: Subscribe configuration for task CLEAR */
5606 
5607 /* Bit 31 :   */
5608 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
5609 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
5610 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
5611 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5612 
5613 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
5614 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5615 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5616 
5617 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
5618 /* Description: Subscribe configuration for task TRIGOVRFLW */
5619 
5620 /* Bit 31 :   */
5621 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5622 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5623 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
5624 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
5625 
5626 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
5627 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5628 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5629 
5630 /* Register: RTC_EVENTS_TICK */
5631 /* Description: Event on counter increment */
5632 
5633 /* Bit 0 : Event on counter increment */
5634 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
5635 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
5636 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
5637 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
5638 
5639 /* Register: RTC_EVENTS_OVRFLW */
5640 /* Description: Event on counter overflow */
5641 
5642 /* Bit 0 : Event on counter overflow */
5643 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
5644 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
5645 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
5646 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
5647 
5648 /* Register: RTC_EVENTS_COMPARE */
5649 /* Description: Description collection: Compare event on CC[n] match */
5650 
5651 /* Bit 0 : Compare event on CC[n] match */
5652 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
5653 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
5654 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
5655 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
5656 
5657 /* Register: RTC_PUBLISH_TICK */
5658 /* Description: Publish configuration for event TICK */
5659 
5660 /* Bit 31 :   */
5661 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
5662 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
5663 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
5664 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
5665 
5666 /* Bits 7..0 : DPPI channel that event TICK will publish to */
5667 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5668 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5669 
5670 /* Register: RTC_PUBLISH_OVRFLW */
5671 /* Description: Publish configuration for event OVRFLW */
5672 
5673 /* Bit 31 :   */
5674 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5675 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5676 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
5677 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
5678 
5679 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to */
5680 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5681 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5682 
5683 /* Register: RTC_PUBLISH_COMPARE */
5684 /* Description: Description collection: Publish configuration for event COMPARE[n] */
5685 
5686 /* Bit 31 :   */
5687 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
5688 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
5689 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
5690 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5691 
5692 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
5693 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5694 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5695 
5696 /* Register: RTC_INTENSET */
5697 /* Description: Enable interrupt */
5698 
5699 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
5700 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5701 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5702 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5703 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5704 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
5705 
5706 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
5707 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5708 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5709 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5710 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5711 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
5712 
5713 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
5714 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5715 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5716 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5717 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5718 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
5719 
5720 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5721 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5722 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5723 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5724 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5725 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5726 
5727 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
5728 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5729 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5730 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5731 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5732 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
5733 
5734 /* Bit 0 : Write '1' to enable interrupt for event TICK */
5735 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5736 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5737 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5738 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5739 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
5740 
5741 /* Register: RTC_INTENCLR */
5742 /* Description: Disable interrupt */
5743 
5744 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
5745 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5746 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5747 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5748 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5749 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5750 
5751 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
5752 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5753 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5754 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5755 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5756 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5757 
5758 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
5759 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5760 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5761 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5762 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5763 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5764 
5765 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5766 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5767 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5768 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5769 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5770 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5771 
5772 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
5773 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5774 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5775 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5776 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5777 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5778 
5779 /* Bit 0 : Write '1' to disable interrupt for event TICK */
5780 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5781 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5782 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5783 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5784 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
5785 
5786 /* Register: RTC_EVTEN */
5787 /* Description: Enable or disable event routing */
5788 
5789 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
5790 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5791 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5792 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
5793 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
5794 
5795 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
5796 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5797 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5798 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
5799 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
5800 
5801 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
5802 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5803 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5804 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
5805 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
5806 
5807 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
5808 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5809 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5810 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
5811 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
5812 
5813 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5814 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5815 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5816 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
5817 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
5818 
5819 /* Bit 0 : Enable or disable event routing for event TICK */
5820 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
5821 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
5822 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
5823 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
5824 
5825 /* Register: RTC_EVTENSET */
5826 /* Description: Enable event routing */
5827 
5828 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
5829 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5830 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5831 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5832 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5833 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
5834 
5835 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
5836 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5837 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5838 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5839 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5840 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
5841 
5842 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
5843 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5844 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5845 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5846 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5847 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
5848 
5849 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
5850 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5851 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5852 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5853 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5854 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
5855 
5856 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
5857 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5858 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5859 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5860 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5861 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
5862 
5863 /* Bit 0 : Write '1' to enable event routing for event TICK */
5864 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5865 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5866 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5867 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5868 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
5869 
5870 /* Register: RTC_EVTENCLR */
5871 /* Description: Disable event routing */
5872 
5873 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
5874 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5875 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5876 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5877 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5878 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5879 
5880 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
5881 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5882 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5883 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5884 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5885 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5886 
5887 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
5888 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5889 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5890 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5891 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5892 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5893 
5894 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
5895 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5896 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5897 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5898 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5899 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5900 
5901 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
5902 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5903 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5904 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5905 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5906 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5907 
5908 /* Bit 0 : Write '1' to disable event routing for event TICK */
5909 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5910 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5911 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5912 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5913 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
5914 
5915 /* Register: RTC_COUNTER */
5916 /* Description: Current counter value */
5917 
5918 /* Bits 23..0 : Counter value */
5919 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
5920 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
5921 
5922 /* Register: RTC_PRESCALER */
5923 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
5924 
5925 /* Bits 11..0 : Prescaler value */
5926 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5927 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5928 
5929 /* Register: RTC_CC */
5930 /* Description: Description collection: Compare register n */
5931 
5932 /* Bits 23..0 : Compare value */
5933 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
5934 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
5935 
5936 
5937 /* Peripheral: SAADC */
5938 /* Description: Analog to Digital Converter 0 */
5939 
5940 /* Register: SAADC_TASKS_START */
5941 /* Description: Start the ADC and prepare the result buffer in RAM */
5942 
5943 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
5944 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5945 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5946 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5947 
5948 /* Register: SAADC_TASKS_SAMPLE */
5949 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
5950 
5951 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
5952 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
5953 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
5954 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
5955 
5956 /* Register: SAADC_TASKS_STOP */
5957 /* Description: Stop the ADC and terminate any on-going conversion */
5958 
5959 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
5960 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5961 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5962 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5963 
5964 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
5965 /* Description: Starts offset auto-calibration */
5966 
5967 /* Bit 0 : Starts offset auto-calibration */
5968 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
5969 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
5970 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
5971 
5972 /* Register: SAADC_SUBSCRIBE_START */
5973 /* Description: Subscribe configuration for task START */
5974 
5975 /* Bit 31 :   */
5976 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5977 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5978 #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5979 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5980 
5981 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5982 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5983 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5984 
5985 /* Register: SAADC_SUBSCRIBE_SAMPLE */
5986 /* Description: Subscribe configuration for task SAMPLE */
5987 
5988 /* Bit 31 :   */
5989 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
5990 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
5991 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
5992 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
5993 
5994 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
5995 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5996 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5997 
5998 /* Register: SAADC_SUBSCRIBE_STOP */
5999 /* Description: Subscribe configuration for task STOP */
6000 
6001 /* Bit 31 :   */
6002 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
6003 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
6004 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
6005 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6006 
6007 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
6008 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6009 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6010 
6011 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
6012 /* Description: Subscribe configuration for task CALIBRATEOFFSET */
6013 
6014 /* Bit 31 :   */
6015 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
6016 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
6017 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
6018 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
6019 
6020 /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
6021 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6022 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6023 
6024 /* Register: SAADC_EVENTS_STARTED */
6025 /* Description: The ADC has started */
6026 
6027 /* Bit 0 : The ADC has started */
6028 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
6029 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
6030 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
6031 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6032 
6033 /* Register: SAADC_EVENTS_END */
6034 /* Description: The ADC has filled up the Result buffer */
6035 
6036 /* Bit 0 : The ADC has filled up the Result buffer */
6037 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6038 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6039 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6040 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6041 
6042 /* Register: SAADC_EVENTS_DONE */
6043 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
6044 
6045 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
6046 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
6047 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
6048 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
6049 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
6050 
6051 /* Register: SAADC_EVENTS_RESULTDONE */
6052 /* Description: A result is ready to get transferred to RAM. */
6053 
6054 /* Bit 0 : A result is ready to get transferred to RAM. */
6055 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
6056 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
6057 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
6058 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
6059 
6060 /* Register: SAADC_EVENTS_CALIBRATEDONE */
6061 /* Description: Calibration is complete */
6062 
6063 /* Bit 0 : Calibration is complete */
6064 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
6065 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
6066 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
6067 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
6068 
6069 /* Register: SAADC_EVENTS_STOPPED */
6070 /* Description: The ADC has stopped */
6071 
6072 /* Bit 0 : The ADC has stopped */
6073 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6074 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6075 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6076 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6077 
6078 /* Register: SAADC_EVENTS_CH_LIMITH */
6079 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
6080 
6081 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
6082 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
6083 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
6084 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
6085 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
6086 
6087 /* Register: SAADC_EVENTS_CH_LIMITL */
6088 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
6089 
6090 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
6091 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
6092 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
6093 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
6094 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
6095 
6096 /* Register: SAADC_PUBLISH_STARTED */
6097 /* Description: Publish configuration for event STARTED */
6098 
6099 /* Bit 31 :   */
6100 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
6101 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
6102 #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6103 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6104 
6105 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
6106 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6107 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6108 
6109 /* Register: SAADC_PUBLISH_END */
6110 /* Description: Publish configuration for event END */
6111 
6112 /* Bit 31 :   */
6113 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
6114 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
6115 #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6116 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6117 
6118 /* Bits 7..0 : DPPI channel that event END will publish to */
6119 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6120 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6121 
6122 /* Register: SAADC_PUBLISH_DONE */
6123 /* Description: Publish configuration for event DONE */
6124 
6125 /* Bit 31 :   */
6126 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
6127 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
6128 #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
6129 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
6130 
6131 /* Bits 7..0 : DPPI channel that event DONE will publish to */
6132 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6133 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6134 
6135 /* Register: SAADC_PUBLISH_RESULTDONE */
6136 /* Description: Publish configuration for event RESULTDONE */
6137 
6138 /* Bit 31 :   */
6139 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
6140 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
6141 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
6142 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
6143 
6144 /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */
6145 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6146 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6147 
6148 /* Register: SAADC_PUBLISH_CALIBRATEDONE */
6149 /* Description: Publish configuration for event CALIBRATEDONE */
6150 
6151 /* Bit 31 :   */
6152 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
6153 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
6154 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
6155 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
6156 
6157 /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */
6158 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6159 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6160 
6161 /* Register: SAADC_PUBLISH_STOPPED */
6162 /* Description: Publish configuration for event STOPPED */
6163 
6164 /* Bit 31 :   */
6165 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6166 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
6167 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6168 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6169 
6170 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
6171 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6172 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6173 
6174 /* Register: SAADC_PUBLISH_CH_LIMITH */
6175 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
6176 
6177 /* Bit 31 :   */
6178 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
6179 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
6180 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
6181 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
6182 
6183 /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */
6184 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6185 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6186 
6187 /* Register: SAADC_PUBLISH_CH_LIMITL */
6188 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
6189 
6190 /* Bit 31 :   */
6191 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
6192 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
6193 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
6194 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
6195 
6196 /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */
6197 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6198 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6199 
6200 /* Register: SAADC_INTEN */
6201 /* Description: Enable or disable interrupt */
6202 
6203 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
6204 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6205 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6206 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
6207 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
6208 
6209 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
6210 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6211 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6212 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
6213 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
6214 
6215 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
6216 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6217 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6218 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
6219 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
6220 
6221 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
6222 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6223 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6224 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
6225 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
6226 
6227 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
6228 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6229 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6230 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
6231 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
6232 
6233 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
6234 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6235 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6236 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
6237 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
6238 
6239 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
6240 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6241 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6242 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
6243 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
6244 
6245 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
6246 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6247 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6248 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
6249 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
6250 
6251 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
6252 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6253 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6254 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
6255 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
6256 
6257 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
6258 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6259 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6260 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
6261 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
6262 
6263 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
6264 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6265 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6266 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
6267 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
6268 
6269 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
6270 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6271 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6272 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
6273 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
6274 
6275 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
6276 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6277 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6278 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
6279 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
6280 
6281 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
6282 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6283 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6284 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
6285 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
6286 
6287 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
6288 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6289 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6290 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
6291 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
6292 
6293 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
6294 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6295 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6296 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
6297 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
6298 
6299 /* Bit 5 : Enable or disable interrupt for event STOPPED */
6300 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6301 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6302 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6303 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6304 
6305 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
6306 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6307 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6308 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
6309 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
6310 
6311 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
6312 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6313 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6314 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
6315 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
6316 
6317 /* Bit 2 : Enable or disable interrupt for event DONE */
6318 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
6319 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
6320 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
6321 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
6322 
6323 /* Bit 1 : Enable or disable interrupt for event END */
6324 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
6325 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
6326 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
6327 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
6328 
6329 /* Bit 0 : Enable or disable interrupt for event STARTED */
6330 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6331 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6332 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6333 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6334 
6335 /* Register: SAADC_INTENSET */
6336 /* Description: Enable interrupt */
6337 
6338 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
6339 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6340 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6341 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6342 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6343 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
6344 
6345 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
6346 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6347 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6348 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6349 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6350 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
6351 
6352 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
6353 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6354 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6355 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6356 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6357 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
6358 
6359 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
6360 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6361 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6362 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6363 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6364 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
6365 
6366 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
6367 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6368 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6369 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6370 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6371 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
6372 
6373 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
6374 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6375 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6376 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6377 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6378 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
6379 
6380 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
6381 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6382 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6383 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6384 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6385 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
6386 
6387 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
6388 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6389 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6390 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6391 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6392 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
6393 
6394 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
6395 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6396 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6397 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6398 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6399 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
6400 
6401 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
6402 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6403 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6404 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6405 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6406 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
6407 
6408 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
6409 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6410 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6411 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6412 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6413 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
6414 
6415 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
6416 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6417 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6418 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6419 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6420 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
6421 
6422 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
6423 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6424 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6425 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6426 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6427 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
6428 
6429 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
6430 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6431 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6432 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6433 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6434 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
6435 
6436 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
6437 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6438 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6439 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6440 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6441 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
6442 
6443 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
6444 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6445 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6446 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6447 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6448 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
6449 
6450 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
6451 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6452 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6453 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6454 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6455 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6456 
6457 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
6458 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6459 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6460 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6461 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6462 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
6463 
6464 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
6465 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6466 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6467 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6468 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6469 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
6470 
6471 /* Bit 2 : Write '1' to enable interrupt for event DONE */
6472 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
6473 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
6474 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
6475 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
6476 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
6477 
6478 /* Bit 1 : Write '1' to enable interrupt for event END */
6479 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
6480 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
6481 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6482 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6483 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
6484 
6485 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6486 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6487 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6488 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6489 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6490 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
6491 
6492 /* Register: SAADC_INTENCLR */
6493 /* Description: Disable interrupt */
6494 
6495 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
6496 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6497 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6498 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6499 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6500 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
6501 
6502 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
6503 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6504 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6505 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6506 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6507 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
6508 
6509 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
6510 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6511 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6512 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6513 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6514 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
6515 
6516 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
6517 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6518 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6519 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6520 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6521 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
6522 
6523 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
6524 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6525 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6526 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6527 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6528 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
6529 
6530 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
6531 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6532 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6533 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6534 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6535 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
6536 
6537 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
6538 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6539 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6540 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6541 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6542 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
6543 
6544 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
6545 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6546 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6547 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6548 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6549 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
6550 
6551 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
6552 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6553 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6554 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6555 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6556 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
6557 
6558 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
6559 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6560 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6561 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6562 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6563 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
6564 
6565 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
6566 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6567 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6568 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6569 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6570 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
6571 
6572 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
6573 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6574 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6575 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6576 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6577 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
6578 
6579 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
6580 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6581 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6582 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6583 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6584 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
6585 
6586 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
6587 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6588 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6589 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6590 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6591 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
6592 
6593 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
6594 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6595 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6596 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6597 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6598 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
6599 
6600 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
6601 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6602 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6603 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6604 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6605 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
6606 
6607 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
6608 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6609 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6610 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6611 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6612 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6613 
6614 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
6615 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6616 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6617 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6618 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6619 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
6620 
6621 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
6622 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6623 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6624 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6625 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6626 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
6627 
6628 /* Bit 2 : Write '1' to disable interrupt for event DONE */
6629 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
6630 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
6631 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
6632 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
6633 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
6634 
6635 /* Bit 1 : Write '1' to disable interrupt for event END */
6636 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
6637 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6638 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6639 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6640 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
6641 
6642 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6643 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6644 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6645 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6646 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6647 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6648 
6649 /* Register: SAADC_STATUS */
6650 /* Description: Status */
6651 
6652 /* Bit 0 : Status */
6653 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
6654 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
6655 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
6656 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */
6657 
6658 /* Register: SAADC_ENABLE */
6659 /* Description: Enable or disable ADC */
6660 
6661 /* Bit 0 : Enable or disable ADC */
6662 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6663 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6664 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
6665 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
6666 
6667 /* Register: SAADC_CH_PSELP */
6668 /* Description: Description cluster: Input positive pin selection for CH[n] */
6669 
6670 /* Bits 4..0 : Analog positive input channel */
6671 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
6672 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
6673 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
6674 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
6675 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
6676 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
6677 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
6678 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
6679 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
6680 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
6681 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
6682 #define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */
6683 
6684 /* Register: SAADC_CH_PSELN */
6685 /* Description: Description cluster: Input negative pin selection for CH[n] */
6686 
6687 /* Bits 4..0 : Analog negative input, enables differential channel */
6688 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
6689 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
6690 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
6691 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
6692 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
6693 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
6694 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
6695 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
6696 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
6697 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
6698 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
6699 #define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */
6700 
6701 /* Register: SAADC_CH_CONFIG */
6702 /* Description: Description cluster: Input configuration for CH[n] */
6703 
6704 /* Bit 24 : Enable burst mode */
6705 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
6706 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
6707 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
6708 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
6709 
6710 /* Bit 20 : Enable differential mode */
6711 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
6712 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
6713 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
6714 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
6715 
6716 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
6717 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
6718 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
6719 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
6720 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
6721 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
6722 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
6723 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
6724 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
6725 
6726 /* Bit 12 : Reference control */
6727 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
6728 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
6729 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
6730 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */
6731 
6732 /* Bits 10..8 : Gain control */
6733 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
6734 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
6735 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
6736 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
6737 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
6738 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
6739 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
6740 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
6741 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
6742 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
6743 
6744 /* Bits 5..4 : Negative channel resistor control */
6745 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
6746 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
6747 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
6748 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
6749 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
6750 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
6751 
6752 /* Bits 1..0 : Positive channel resistor control */
6753 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
6754 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
6755 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
6756 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
6757 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */
6758 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */
6759 
6760 /* Register: SAADC_CH_LIMIT */
6761 /* Description: Description cluster: High/low limits for event monitoring a channel */
6762 
6763 /* Bits 31..16 : High level limit */
6764 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
6765 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
6766 
6767 /* Bits 15..0 : Low level limit */
6768 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
6769 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
6770 
6771 /* Register: SAADC_RESOLUTION */
6772 /* Description: Resolution configuration */
6773 
6774 /* Bits 2..0 : Set the resolution */
6775 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
6776 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
6777 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
6778 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
6779 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
6780 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
6781 
6782 /* Register: SAADC_OVERSAMPLE */
6783 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
6784 
6785 /* Bits 3..0 : Oversample control */
6786 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
6787 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
6788 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
6789 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
6790 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
6791 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
6792 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
6793 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
6794 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
6795 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
6796 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
6797 
6798 /* Register: SAADC_SAMPLERATE */
6799 /* Description: Controls normal or continuous sample rate */
6800 
6801 /* Bit 12 : Select mode for sample rate control */
6802 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
6803 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
6804 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
6805 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
6806 
6807 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
6808 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
6809 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
6810 
6811 /* Register: SAADC_RESULT_PTR */
6812 /* Description: Data pointer */
6813 
6814 /* Bits 31..0 : Data pointer */
6815 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6816 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6817 
6818 /* Register: SAADC_RESULT_MAXCNT */
6819 /* Description: Maximum number of buffer words to transfer */
6820 
6821 /* Bits 14..0 : Maximum number of buffer words to transfer */
6822 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6823 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6824 
6825 /* Register: SAADC_RESULT_AMOUNT */
6826 /* Description: Number of buffer words transferred since last START */
6827 
6828 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
6829 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
6830 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
6831 
6832 
6833 /* Peripheral: SPIM */
6834 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
6835 
6836 /* Register: SPIM_TASKS_START */
6837 /* Description: Start SPI transaction */
6838 
6839 /* Bit 0 : Start SPI transaction */
6840 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6841 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6842 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6843 
6844 /* Register: SPIM_TASKS_STOP */
6845 /* Description: Stop SPI transaction */
6846 
6847 /* Bit 0 : Stop SPI transaction */
6848 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6849 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6850 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6851 
6852 /* Register: SPIM_TASKS_SUSPEND */
6853 /* Description: Suspend SPI transaction */
6854 
6855 /* Bit 0 : Suspend SPI transaction */
6856 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
6857 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
6858 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
6859 
6860 /* Register: SPIM_TASKS_RESUME */
6861 /* Description: Resume SPI transaction */
6862 
6863 /* Bit 0 : Resume SPI transaction */
6864 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
6865 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
6866 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
6867 
6868 /* Register: SPIM_SUBSCRIBE_START */
6869 /* Description: Subscribe configuration for task START */
6870 
6871 /* Bit 31 :   */
6872 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
6873 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
6874 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
6875 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
6876 
6877 /* Bits 7..0 : DPPI channel that task START will subscribe to */
6878 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6879 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6880 
6881 /* Register: SPIM_SUBSCRIBE_STOP */
6882 /* Description: Subscribe configuration for task STOP */
6883 
6884 /* Bit 31 :   */
6885 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
6886 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
6887 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
6888 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6889 
6890 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
6891 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6892 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6893 
6894 /* Register: SPIM_SUBSCRIBE_SUSPEND */
6895 /* Description: Subscribe configuration for task SUSPEND */
6896 
6897 /* Bit 31 :   */
6898 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
6899 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
6900 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
6901 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
6902 
6903 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
6904 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6905 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6906 
6907 /* Register: SPIM_SUBSCRIBE_RESUME */
6908 /* Description: Subscribe configuration for task RESUME */
6909 
6910 /* Bit 31 :   */
6911 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
6912 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
6913 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
6914 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
6915 
6916 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
6917 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6918 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6919 
6920 /* Register: SPIM_EVENTS_STOPPED */
6921 /* Description: SPI transaction has stopped */
6922 
6923 /* Bit 0 : SPI transaction has stopped */
6924 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6925 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6926 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6927 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6928 
6929 /* Register: SPIM_EVENTS_ENDRX */
6930 /* Description: End of RXD buffer reached */
6931 
6932 /* Bit 0 : End of RXD buffer reached */
6933 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
6934 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
6935 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
6936 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
6937 
6938 /* Register: SPIM_EVENTS_END */
6939 /* Description: End of RXD buffer and TXD buffer reached */
6940 
6941 /* Bit 0 : End of RXD buffer and TXD buffer reached */
6942 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6943 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6944 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6945 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6946 
6947 /* Register: SPIM_EVENTS_ENDTX */
6948 /* Description: End of TXD buffer reached */
6949 
6950 /* Bit 0 : End of TXD buffer reached */
6951 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
6952 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
6953 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
6954 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
6955 
6956 /* Register: SPIM_EVENTS_STARTED */
6957 /* Description: Transaction started */
6958 
6959 /* Bit 0 : Transaction started */
6960 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
6961 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
6962 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
6963 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6964 
6965 /* Register: SPIM_PUBLISH_STOPPED */
6966 /* Description: Publish configuration for event STOPPED */
6967 
6968 /* Bit 31 :   */
6969 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6970 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
6971 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6972 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6973 
6974 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
6975 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6976 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6977 
6978 /* Register: SPIM_PUBLISH_ENDRX */
6979 /* Description: Publish configuration for event ENDRX */
6980 
6981 /* Bit 31 :   */
6982 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
6983 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
6984 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
6985 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
6986 
6987 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
6988 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6989 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6990 
6991 /* Register: SPIM_PUBLISH_END */
6992 /* Description: Publish configuration for event END */
6993 
6994 /* Bit 31 :   */
6995 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
6996 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
6997 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6998 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6999 
7000 /* Bits 7..0 : DPPI channel that event END will publish to */
7001 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7002 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7003 
7004 /* Register: SPIM_PUBLISH_ENDTX */
7005 /* Description: Publish configuration for event ENDTX */
7006 
7007 /* Bit 31 :   */
7008 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
7009 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
7010 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
7011 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
7012 
7013 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */
7014 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7015 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7016 
7017 /* Register: SPIM_PUBLISH_STARTED */
7018 /* Description: Publish configuration for event STARTED */
7019 
7020 /* Bit 31 :   */
7021 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
7022 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
7023 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
7024 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
7025 
7026 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
7027 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7028 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7029 
7030 /* Register: SPIM_SHORTS */
7031 /* Description: Shortcuts between local events and tasks */
7032 
7033 /* Bit 17 : Shortcut between event END and task START */
7034 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
7035 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
7036 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
7037 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
7038 
7039 /* Register: SPIM_INTENSET */
7040 /* Description: Enable interrupt */
7041 
7042 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
7043 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
7044 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
7045 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7046 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7047 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
7048 
7049 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
7050 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
7051 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
7052 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7053 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7054 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
7055 
7056 /* Bit 6 : Write '1' to enable interrupt for event END */
7057 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
7058 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
7059 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7060 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7061 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
7062 
7063 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7064 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7065 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7066 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7067 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7068 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7069 
7070 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7071 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7072 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7073 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7074 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7075 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7076 
7077 /* Register: SPIM_INTENCLR */
7078 /* Description: Disable interrupt */
7079 
7080 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
7081 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
7082 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
7083 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7084 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7085 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7086 
7087 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
7088 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
7089 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
7090 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7091 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7092 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7093 
7094 /* Bit 6 : Write '1' to disable interrupt for event END */
7095 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
7096 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7097 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7098 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7099 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7100 
7101 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7102 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7103 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7104 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7105 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7106 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7107 
7108 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7109 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7110 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7111 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7112 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7113 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7114 
7115 /* Register: SPIM_ENABLE */
7116 /* Description: Enable SPIM */
7117 
7118 /* Bits 3..0 : Enable or disable SPIM */
7119 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7120 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7121 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
7122 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
7123 
7124 /* Register: SPIM_PSEL_SCK */
7125 /* Description: Pin select for SCK */
7126 
7127 /* Bit 31 : Connection */
7128 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7129 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7130 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7131 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7132 
7133 /* Bits 4..0 : Pin number */
7134 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7135 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7136 
7137 /* Register: SPIM_PSEL_MOSI */
7138 /* Description: Pin select for MOSI signal */
7139 
7140 /* Bit 31 : Connection */
7141 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7142 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7143 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7144 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7145 
7146 /* Bits 4..0 : Pin number */
7147 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7148 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7149 
7150 /* Register: SPIM_PSEL_MISO */
7151 /* Description: Pin select for MISO signal */
7152 
7153 /* Bit 31 : Connection */
7154 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7155 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7156 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7157 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7158 
7159 /* Bits 4..0 : Pin number */
7160 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7161 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7162 
7163 /* Register: SPIM_FREQUENCY */
7164 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7165 
7166 /* Bits 31..0 : SPI master data rate */
7167 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7168 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7169 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
7170 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
7171 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
7172 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7173 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7174 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7175 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7176 
7177 /* Register: SPIM_RXD_PTR */
7178 /* Description: Data pointer */
7179 
7180 /* Bits 31..0 : Data pointer */
7181 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7182 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7183 
7184 /* Register: SPIM_RXD_MAXCNT */
7185 /* Description: Maximum number of bytes in receive buffer */
7186 
7187 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7188 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7189 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7190 
7191 /* Register: SPIM_RXD_AMOUNT */
7192 /* Description: Number of bytes transferred in the last transaction */
7193 
7194 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7195 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7196 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7197 
7198 /* Register: SPIM_RXD_LIST */
7199 /* Description: EasyDMA list type */
7200 
7201 /* Bits 1..0 : List type */
7202 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7203 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7204 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7205 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7206 
7207 /* Register: SPIM_TXD_PTR */
7208 /* Description: Data pointer */
7209 
7210 /* Bits 31..0 : Data pointer */
7211 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7212 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7213 
7214 /* Register: SPIM_TXD_MAXCNT */
7215 /* Description: Maximum number of bytes in transmit buffer */
7216 
7217 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7218 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7219 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7220 
7221 /* Register: SPIM_TXD_AMOUNT */
7222 /* Description: Number of bytes transferred in the last transaction */
7223 
7224 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7225 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7226 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7227 
7228 /* Register: SPIM_TXD_LIST */
7229 /* Description: EasyDMA list type */
7230 
7231 /* Bits 1..0 : List type */
7232 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7233 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7234 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7235 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7236 
7237 /* Register: SPIM_CONFIG */
7238 /* Description: Configuration register */
7239 
7240 /* Bit 2 : Serial clock (SCK) polarity */
7241 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7242 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7243 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7244 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7245 
7246 /* Bit 1 : Serial clock (SCK) phase */
7247 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7248 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7249 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7250 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7251 
7252 /* Bit 0 : Bit order */
7253 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7254 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7255 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7256 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7257 
7258 /* Register: SPIM_ORC */
7259 /* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */
7260 
7261 /* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */
7262 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
7263 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
7264 
7265 
7266 /* Peripheral: SPIS */
7267 /* Description: SPI Slave 0 */
7268 
7269 /* Register: SPIS_TASKS_ACQUIRE */
7270 /* Description: Acquire SPI semaphore */
7271 
7272 /* Bit 0 : Acquire SPI semaphore */
7273 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
7274 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
7275 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
7276 
7277 /* Register: SPIS_TASKS_RELEASE */
7278 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
7279 
7280 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
7281 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
7282 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
7283 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
7284 
7285 /* Register: SPIS_SUBSCRIBE_ACQUIRE */
7286 /* Description: Subscribe configuration for task ACQUIRE */
7287 
7288 /* Bit 31 :   */
7289 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
7290 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
7291 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
7292 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
7293 
7294 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
7295 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7296 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7297 
7298 /* Register: SPIS_SUBSCRIBE_RELEASE */
7299 /* Description: Subscribe configuration for task RELEASE */
7300 
7301 /* Bit 31 :   */
7302 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
7303 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
7304 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
7305 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
7306 
7307 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
7308 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7309 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7310 
7311 /* Register: SPIS_EVENTS_END */
7312 /* Description: Granted transaction completed */
7313 
7314 /* Bit 0 : Granted transaction completed */
7315 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7316 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7317 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7318 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7319 
7320 /* Register: SPIS_EVENTS_ENDRX */
7321 /* Description: End of RXD buffer reached */
7322 
7323 /* Bit 0 : End of RXD buffer reached */
7324 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
7325 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
7326 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
7327 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
7328 
7329 /* Register: SPIS_EVENTS_ACQUIRED */
7330 /* Description: Semaphore acquired */
7331 
7332 /* Bit 0 : Semaphore acquired */
7333 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
7334 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
7335 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
7336 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
7337 
7338 /* Register: SPIS_PUBLISH_END */
7339 /* Description: Publish configuration for event END */
7340 
7341 /* Bit 31 :   */
7342 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
7343 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
7344 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
7345 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
7346 
7347 /* Bits 7..0 : DPPI channel that event END will publish to */
7348 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7349 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7350 
7351 /* Register: SPIS_PUBLISH_ENDRX */
7352 /* Description: Publish configuration for event ENDRX */
7353 
7354 /* Bit 31 :   */
7355 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
7356 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
7357 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
7358 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
7359 
7360 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
7361 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7362 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7363 
7364 /* Register: SPIS_PUBLISH_ACQUIRED */
7365 /* Description: Publish configuration for event ACQUIRED */
7366 
7367 /* Bit 31 :   */
7368 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
7369 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
7370 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
7371 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
7372 
7373 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */
7374 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7375 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7376 
7377 /* Register: SPIS_SHORTS */
7378 /* Description: Shortcuts between local events and tasks */
7379 
7380 /* Bit 2 : Shortcut between event END and task ACQUIRE */
7381 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
7382 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
7383 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
7384 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
7385 
7386 /* Register: SPIS_INTENSET */
7387 /* Description: Enable interrupt */
7388 
7389 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
7390 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7391 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7392 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7393 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7394 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
7395 
7396 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7397 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7398 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7399 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7400 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7401 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7402 
7403 /* Bit 1 : Write '1' to enable interrupt for event END */
7404 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
7405 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
7406 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7407 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7408 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
7409 
7410 /* Register: SPIS_INTENCLR */
7411 /* Description: Disable interrupt */
7412 
7413 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
7414 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7415 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7416 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7417 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7418 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
7419 
7420 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7421 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7422 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7423 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7424 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7425 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7426 
7427 /* Bit 1 : Write '1' to disable interrupt for event END */
7428 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
7429 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7430 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7431 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7432 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
7433 
7434 /* Register: SPIS_SEMSTAT */
7435 /* Description: Semaphore status register */
7436 
7437 /* Bits 1..0 : Semaphore status */
7438 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
7439 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
7440 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
7441 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
7442 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
7443 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
7444 
7445 /* Register: SPIS_STATUS */
7446 /* Description: Status from last transaction */
7447 
7448 /* Bit 1 : RX buffer overflow detected, and prevented */
7449 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
7450 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
7451 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
7452 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
7453 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
7454 
7455 /* Bit 0 : TX buffer over-read detected, and prevented */
7456 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
7457 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
7458 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
7459 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
7460 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
7461 
7462 /* Register: SPIS_ENABLE */
7463 /* Description: Enable SPI slave */
7464 
7465 /* Bits 3..0 : Enable or disable SPI slave */
7466 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7467 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7468 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
7469 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
7470 
7471 /* Register: SPIS_PSEL_SCK */
7472 /* Description: Pin select for SCK */
7473 
7474 /* Bit 31 : Connection */
7475 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7476 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7477 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7478 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7479 
7480 /* Bits 4..0 : Pin number */
7481 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7482 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7483 
7484 /* Register: SPIS_PSEL_MISO */
7485 /* Description: Pin select for MISO signal */
7486 
7487 /* Bit 31 : Connection */
7488 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7489 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7490 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7491 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7492 
7493 /* Bits 4..0 : Pin number */
7494 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7495 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7496 
7497 /* Register: SPIS_PSEL_MOSI */
7498 /* Description: Pin select for MOSI signal */
7499 
7500 /* Bit 31 : Connection */
7501 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7502 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7503 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7504 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7505 
7506 /* Bits 4..0 : Pin number */
7507 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7508 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7509 
7510 /* Register: SPIS_PSEL_CSN */
7511 /* Description: Pin select for CSN signal */
7512 
7513 /* Bit 31 : Connection */
7514 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7515 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7516 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
7517 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7518 
7519 /* Bits 4..0 : Pin number */
7520 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
7521 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
7522 
7523 /* Register: SPIS_RXD_PTR */
7524 /* Description: RXD data pointer */
7525 
7526 /* Bits 31..0 : RXD data pointer */
7527 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7528 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7529 
7530 /* Register: SPIS_RXD_MAXCNT */
7531 /* Description: Maximum number of bytes in receive buffer */
7532 
7533 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7534 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7535 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7536 
7537 /* Register: SPIS_RXD_AMOUNT */
7538 /* Description: Number of bytes received in last granted transaction */
7539 
7540 /* Bits 12..0 : Number of bytes received in the last granted transaction */
7541 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7542 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7543 
7544 /* Register: SPIS_RXD_LIST */
7545 /* Description: EasyDMA list type */
7546 
7547 /* Bits 1..0 : List type */
7548 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7549 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7550 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7551 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7552 
7553 /* Register: SPIS_TXD_PTR */
7554 /* Description: TXD data pointer */
7555 
7556 /* Bits 31..0 : TXD data pointer */
7557 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7558 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7559 
7560 /* Register: SPIS_TXD_MAXCNT */
7561 /* Description: Maximum number of bytes in transmit buffer */
7562 
7563 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7564 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7565 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7566 
7567 /* Register: SPIS_TXD_AMOUNT */
7568 /* Description: Number of bytes transmitted in last granted transaction */
7569 
7570 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */
7571 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7572 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7573 
7574 /* Register: SPIS_TXD_LIST */
7575 /* Description: EasyDMA list type */
7576 
7577 /* Bits 1..0 : List type */
7578 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7579 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7580 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7581 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7582 
7583 /* Register: SPIS_CONFIG */
7584 /* Description: Configuration register */
7585 
7586 /* Bit 2 : Serial clock (SCK) polarity */
7587 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7588 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7589 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7590 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7591 
7592 /* Bit 1 : Serial clock (SCK) phase */
7593 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7594 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7595 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7596 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7597 
7598 /* Bit 0 : Bit order */
7599 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7600 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7601 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7602 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7603 
7604 /* Register: SPIS_DEF */
7605 /* Description: Default character. Character clocked out in case of an ignored transaction. */
7606 
7607 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
7608 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
7609 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
7610 
7611 /* Register: SPIS_ORC */
7612 /* Description: Over-read character */
7613 
7614 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
7615 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
7616 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
7617 
7618 
7619 /* Peripheral: SPU */
7620 /* Description: System protection unit */
7621 
7622 /* Register: SPU_EVENTS_RAMACCERR */
7623 /* Description: A security violation has been detected for the RAM memory space */
7624 
7625 /* Bit 0 : A security violation has been detected for the RAM memory space */
7626 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
7627 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
7628 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */
7629 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */
7630 
7631 /* Register: SPU_EVENTS_FLASHACCERR */
7632 /* Description: A security violation has been detected for the flash memory space */
7633 
7634 /* Bit 0 : A security violation has been detected for the flash memory space */
7635 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
7636 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
7637 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */
7638 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */
7639 
7640 /* Register: SPU_EVENTS_PERIPHACCERR */
7641 /* Description: A security violation has been detected on one or several peripherals */
7642 
7643 /* Bit 0 : A security violation has been detected on one or several peripherals */
7644 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
7645 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
7646 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */
7647 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */
7648 
7649 /* Register: SPU_PUBLISH_RAMACCERR */
7650 /* Description: Publish configuration for event RAMACCERR */
7651 
7652 /* Bit 31 :   */
7653 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7654 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
7655 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7656 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7657 
7658 /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */
7659 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7660 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7661 
7662 /* Register: SPU_PUBLISH_FLASHACCERR */
7663 /* Description: Publish configuration for event FLASHACCERR */
7664 
7665 /* Bit 31 :   */
7666 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7667 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
7668 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7669 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7670 
7671 /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */
7672 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7673 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7674 
7675 /* Register: SPU_PUBLISH_PERIPHACCERR */
7676 /* Description: Publish configuration for event PERIPHACCERR */
7677 
7678 /* Bit 31 :   */
7679 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7680 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
7681 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7682 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7683 
7684 /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */
7685 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7686 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7687 
7688 /* Register: SPU_INTEN */
7689 /* Description: Enable or disable interrupt */
7690 
7691 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
7692 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7693 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7694 #define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */
7695 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
7696 
7697 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
7698 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7699 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7700 #define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */
7701 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
7702 
7703 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
7704 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7705 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7706 #define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */
7707 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
7708 
7709 /* Register: SPU_INTENSET */
7710 /* Description: Enable interrupt */
7711 
7712 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
7713 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7714 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7715 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7716 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7717 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
7718 
7719 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
7720 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7721 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7722 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7723 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7724 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
7725 
7726 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
7727 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7728 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7729 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7730 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7731 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
7732 
7733 /* Register: SPU_INTENCLR */
7734 /* Description: Disable interrupt */
7735 
7736 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
7737 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7738 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7739 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7740 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7741 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
7742 
7743 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
7744 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7745 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7746 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7747 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7748 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
7749 
7750 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
7751 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7752 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7753 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7754 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7755 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
7756 
7757 /* Register: SPU_CAP */
7758 /* Description: Show implemented features for the current device */
7759 
7760 /* Bit 0 : Show ARM TrustZone status */
7761 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
7762 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
7763 #define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */
7764 #define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */
7765 
7766 /* Register: SPU_EXTDOMAIN_PERM */
7767 /* Description: Description cluster: Access  for bus access generated from the external domain n List capabilities of the external domain  n */
7768 
7769 /* Bit 8 :   */
7770 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
7771 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
7772 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
7773 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
7774 
7775 /* Bit 4 : Peripheral security mapping */
7776 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
7777 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
7778 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
7779 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */
7780 
7781 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
7782 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
7783 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
7784 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
7785 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */
7786 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */
7787 
7788 /* Register: SPU_DPPI_PERM */
7789 /* Description: Description cluster: Select between secure and non-secure attribute  for the DPPI channels. */
7790 
7791 /* Bit 15 : Select secure attribute. */
7792 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
7793 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
7794 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */
7795 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */
7796 
7797 /* Bit 14 : Select secure attribute. */
7798 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
7799 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
7800 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */
7801 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */
7802 
7803 /* Bit 13 : Select secure attribute. */
7804 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
7805 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
7806 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */
7807 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */
7808 
7809 /* Bit 12 : Select secure attribute. */
7810 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
7811 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
7812 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */
7813 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */
7814 
7815 /* Bit 11 : Select secure attribute. */
7816 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
7817 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
7818 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */
7819 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */
7820 
7821 /* Bit 10 : Select secure attribute. */
7822 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
7823 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
7824 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */
7825 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */
7826 
7827 /* Bit 9 : Select secure attribute. */
7828 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
7829 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
7830 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */
7831 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */
7832 
7833 /* Bit 8 : Select secure attribute. */
7834 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
7835 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
7836 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */
7837 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */
7838 
7839 /* Bit 7 : Select secure attribute. */
7840 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
7841 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
7842 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */
7843 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */
7844 
7845 /* Bit 6 : Select secure attribute. */
7846 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
7847 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
7848 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */
7849 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */
7850 
7851 /* Bit 5 : Select secure attribute. */
7852 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
7853 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
7854 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */
7855 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */
7856 
7857 /* Bit 4 : Select secure attribute. */
7858 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
7859 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
7860 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */
7861 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */
7862 
7863 /* Bit 3 : Select secure attribute. */
7864 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
7865 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
7866 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */
7867 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */
7868 
7869 /* Bit 2 : Select secure attribute. */
7870 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
7871 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
7872 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */
7873 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */
7874 
7875 /* Bit 1 : Select secure attribute. */
7876 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
7877 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
7878 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */
7879 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */
7880 
7881 /* Bit 0 : Select secure attribute. */
7882 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
7883 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
7884 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */
7885 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */
7886 
7887 /* Register: SPU_DPPI_LOCK */
7888 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
7889 
7890 /* Bit 0 :   */
7891 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
7892 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
7893 #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */
7894 #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */
7895 
7896 /* Register: SPU_GPIOPORT_PERM */
7897 /* Description: Description cluster: Select between secure and non-secure attribute  for pins 0 to 31  of port n. */
7898 
7899 /* Bit 31 : Select secure attribute attribute for PIN 31. */
7900 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7901 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7902 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
7903 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
7904 
7905 /* Bit 30 : Select secure attribute attribute for PIN 30. */
7906 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7907 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7908 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
7909 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
7910 
7911 /* Bit 29 : Select secure attribute attribute for PIN 29. */
7912 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7913 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7914 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
7915 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
7916 
7917 /* Bit 28 : Select secure attribute attribute for PIN 28. */
7918 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7919 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7920 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
7921 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
7922 
7923 /* Bit 27 : Select secure attribute attribute for PIN 27. */
7924 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7925 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7926 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
7927 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
7928 
7929 /* Bit 26 : Select secure attribute attribute for PIN 26. */
7930 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7931 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7932 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
7933 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
7934 
7935 /* Bit 25 : Select secure attribute attribute for PIN 25. */
7936 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7937 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7938 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
7939 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
7940 
7941 /* Bit 24 : Select secure attribute attribute for PIN 24. */
7942 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7943 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7944 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
7945 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
7946 
7947 /* Bit 23 : Select secure attribute attribute for PIN 23. */
7948 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7949 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7950 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
7951 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
7952 
7953 /* Bit 22 : Select secure attribute attribute for PIN 22. */
7954 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7955 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7956 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
7957 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
7958 
7959 /* Bit 21 : Select secure attribute attribute for PIN 21. */
7960 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7961 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7962 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
7963 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
7964 
7965 /* Bit 20 : Select secure attribute attribute for PIN 20. */
7966 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7967 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7968 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
7969 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
7970 
7971 /* Bit 19 : Select secure attribute attribute for PIN 19. */
7972 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7973 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7974 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
7975 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
7976 
7977 /* Bit 18 : Select secure attribute attribute for PIN 18. */
7978 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7979 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7980 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
7981 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
7982 
7983 /* Bit 17 : Select secure attribute attribute for PIN 17. */
7984 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7985 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7986 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
7987 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
7988 
7989 /* Bit 16 : Select secure attribute attribute for PIN 16. */
7990 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7991 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7992 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
7993 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
7994 
7995 /* Bit 15 : Select secure attribute attribute for PIN 15. */
7996 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7997 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7998 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
7999 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
8000 
8001 /* Bit 14 : Select secure attribute attribute for PIN 14. */
8002 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8003 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8004 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
8005 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
8006 
8007 /* Bit 13 : Select secure attribute attribute for PIN 13. */
8008 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8009 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8010 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
8011 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
8012 
8013 /* Bit 12 : Select secure attribute attribute for PIN 12. */
8014 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8015 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8016 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
8017 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
8018 
8019 /* Bit 11 : Select secure attribute attribute for PIN 11. */
8020 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8021 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8022 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
8023 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
8024 
8025 /* Bit 10 : Select secure attribute attribute for PIN 10. */
8026 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8027 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8028 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
8029 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
8030 
8031 /* Bit 9 : Select secure attribute attribute for PIN 9. */
8032 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8033 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8034 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
8035 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
8036 
8037 /* Bit 8 : Select secure attribute attribute for PIN 8. */
8038 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8039 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8040 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
8041 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
8042 
8043 /* Bit 7 : Select secure attribute attribute for PIN 7. */
8044 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8045 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8046 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
8047 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
8048 
8049 /* Bit 6 : Select secure attribute attribute for PIN 6. */
8050 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8051 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8052 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
8053 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
8054 
8055 /* Bit 5 : Select secure attribute attribute for PIN 5. */
8056 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8057 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8058 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
8059 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
8060 
8061 /* Bit 4 : Select secure attribute attribute for PIN 4. */
8062 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8063 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8064 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
8065 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
8066 
8067 /* Bit 3 : Select secure attribute attribute for PIN 3. */
8068 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8069 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8070 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
8071 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
8072 
8073 /* Bit 2 : Select secure attribute attribute for PIN 2. */
8074 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8075 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8076 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
8077 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
8078 
8079 /* Bit 1 : Select secure attribute attribute for PIN 1. */
8080 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8081 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8082 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
8083 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
8084 
8085 /* Bit 0 : Select secure attribute attribute for PIN 0. */
8086 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8087 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8088 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
8089 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
8090 
8091 /* Register: SPU_GPIOPORT_LOCK */
8092 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
8093 
8094 /* Bit 0 :   */
8095 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
8096 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
8097 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */
8098 #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */
8099 
8100 /* Register: SPU_FLASHNSC_REGION */
8101 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */
8102 
8103 /* Bit 8 :   */
8104 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8105 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
8106 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
8107 #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8108 
8109 /* Bits 4..0 : Region number */
8110 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
8111 #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
8112 
8113 /* Register: SPU_FLASHNSC_SIZE */
8114 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8115 
8116 /* Bit 8 :   */
8117 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8118 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
8119 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
8120 #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8121 
8122 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8123 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
8124 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
8125 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
8126 #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
8127 #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
8128 #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
8129 #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
8130 #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
8131 #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
8132 #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
8133 #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
8134 
8135 /* Register: SPU_RAMNSC_REGION */
8136 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */
8137 
8138 /* Bit 8 :   */
8139 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8140 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
8141 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
8142 #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8143 
8144 /* Bits 4..0 : Region number */
8145 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
8146 #define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
8147 
8148 /* Register: SPU_RAMNSC_SIZE */
8149 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8150 
8151 /* Bit 8 :   */
8152 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8153 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
8154 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
8155 #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8156 
8157 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8158 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
8159 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
8160 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
8161 #define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
8162 #define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
8163 #define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
8164 #define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
8165 #define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
8166 #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
8167 #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
8168 #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
8169 
8170 /* Register: SPU_FLASHREGION_PERM */
8171 /* Description: Description cluster: Access permissions for flash region n */
8172 
8173 /* Bit 8 :   */
8174 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8175 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8176 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8177 #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8178 
8179 /* Bit 4 : Security attribute for flash region n */
8180 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8181 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8182 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */
8183 #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */
8184 
8185 /* Bit 2 : Configure read permissions for flash region n */
8186 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8187 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
8188 #define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */
8189 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
8190 
8191 /* Bit 1 : Configure write permission for flash region n */
8192 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8193 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
8194 #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */
8195 #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */
8196 
8197 /* Bit 0 : Configure instruction fetch permissions from flash region n */
8198 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
8199 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
8200 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */
8201 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */
8202 
8203 /* Register: SPU_RAMREGION_PERM */
8204 /* Description: Description cluster: Access permissions for RAM region n */
8205 
8206 /* Bit 8 :   */
8207 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8208 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8209 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8210 #define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8211 
8212 /* Bit 4 : Security attribute for RAM region n */
8213 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8214 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8215 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */
8216 #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */
8217 
8218 /* Bit 2 : Configure read permissions for RAM region n */
8219 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8220 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
8221 #define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */
8222 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
8223 
8224 /* Bit 1 : Configure write permission for RAM region n */
8225 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8226 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
8227 #define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */
8228 #define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */
8229 
8230 /* Bit 0 : Configure instruction fetch permissions from RAM region n */
8231 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
8232 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
8233 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */
8234 #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */
8235 
8236 /* Register: SPU_PERIPHID_PERM */
8237 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */
8238 
8239 /* Bit 31 : Indicate if a peripheral is present with ID n */
8240 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
8241 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
8242 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */
8243 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */
8244 
8245 /* Bit 8 :   */
8246 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8247 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8248 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8249 #define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8250 
8251 /* Bit 5 : Security attribution for the DMA transfer */
8252 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
8253 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
8254 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
8255 #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */
8256 
8257 /* Bit 4 : Peripheral security mapping */
8258 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8259 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8260 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
8261 #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */
8262 
8263 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
8264 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
8265 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
8266 #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */
8267 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
8268 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */
8269 
8270 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
8271 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
8272 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
8273 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
8274 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */
8275 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
8276 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */
8277 
8278 
8279 /* Peripheral: TAD */
8280 /* Description: Trace and debug control */
8281 
8282 /* Register: TAD_TASKS_CLOCKSTART */
8283 /* Description: Start all trace and debug clocks. */
8284 
8285 /* Bit 0 : Start all trace and debug clocks. */
8286 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */
8287 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */
8288 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */
8289 
8290 /* Register: TAD_TASKS_CLOCKSTOP */
8291 /* Description: Stop all trace and debug clocks. */
8292 
8293 /* Bit 0 : Stop all trace and debug clocks. */
8294 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */
8295 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */
8296 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */
8297 
8298 /* Register: TAD_ENABLE */
8299 /* Description: Enable debug domain and aquire selected GPIOs */
8300 
8301 /* Bit 0 :   */
8302 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8303 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8304 #define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */
8305 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
8306 
8307 /* Register: TAD_PSEL_TRACECLK */
8308 /* Description: Pin configuration for TRACECLK */
8309 
8310 /* Bit 31 : Connection */
8311 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8312 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8313 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */
8314 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8315 
8316 /* Bits 4..0 : Pin number */
8317 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
8318 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
8319 #define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */
8320 
8321 /* Register: TAD_PSEL_TRACEDATA0 */
8322 /* Description: Pin configuration for TRACEDATA[0] */
8323 
8324 /* Bit 31 : Connection */
8325 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8326 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8327 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */
8328 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */
8329 
8330 /* Bits 4..0 : Pin number */
8331 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
8332 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
8333 #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */
8334 
8335 /* Register: TAD_PSEL_TRACEDATA1 */
8336 /* Description: Pin configuration for TRACEDATA[1] */
8337 
8338 /* Bit 31 : Connection */
8339 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8340 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8341 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */
8342 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */
8343 
8344 /* Bits 4..0 : Pin number */
8345 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
8346 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
8347 #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */
8348 
8349 /* Register: TAD_PSEL_TRACEDATA2 */
8350 /* Description: Pin configuration for TRACEDATA[2] */
8351 
8352 /* Bit 31 : Connection */
8353 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8354 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8355 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */
8356 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */
8357 
8358 /* Bits 4..0 : Pin number */
8359 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
8360 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
8361 #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */
8362 
8363 /* Register: TAD_PSEL_TRACEDATA3 */
8364 /* Description: Pin configuration for TRACEDATA[3] */
8365 
8366 /* Bit 31 : Connection */
8367 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8368 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8369 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */
8370 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */
8371 
8372 /* Bits 4..0 : Pin number */
8373 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
8374 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
8375 #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */
8376 
8377 /* Register: TAD_TRACEPORTSPEED */
8378 /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */
8379 
8380 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
8381 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
8382 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
8383 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */
8384 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */
8385 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */
8386 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */
8387 
8388 
8389 /* Peripheral: TIMER */
8390 /* Description: Timer/Counter 0 */
8391 
8392 /* Register: TIMER_TASKS_START */
8393 /* Description: Start Timer */
8394 
8395 /* Bit 0 : Start Timer */
8396 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8397 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8398 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8399 
8400 /* Register: TIMER_TASKS_STOP */
8401 /* Description: Stop Timer */
8402 
8403 /* Bit 0 : Stop Timer */
8404 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8405 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8406 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8407 
8408 /* Register: TIMER_TASKS_COUNT */
8409 /* Description: Increment Timer (Counter mode only) */
8410 
8411 /* Bit 0 : Increment Timer (Counter mode only) */
8412 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
8413 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
8414 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
8415 
8416 /* Register: TIMER_TASKS_CLEAR */
8417 /* Description: Clear time */
8418 
8419 /* Bit 0 : Clear time */
8420 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
8421 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
8422 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8423 
8424 /* Register: TIMER_TASKS_SHUTDOWN */
8425 /* Description: Deprecated register - Shut down timer */
8426 
8427 /* Bit 0 : Deprecated field -  Shut down timer */
8428 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
8429 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
8430 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
8431 
8432 /* Register: TIMER_TASKS_CAPTURE */
8433 /* Description: Description collection: Capture Timer value to CC[n] register */
8434 
8435 /* Bit 0 : Capture Timer value to CC[n] register */
8436 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
8437 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
8438 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8439 
8440 /* Register: TIMER_SUBSCRIBE_START */
8441 /* Description: Subscribe configuration for task START */
8442 
8443 /* Bit 31 :   */
8444 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8445 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8446 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8447 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8448 
8449 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8450 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8451 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8452 
8453 /* Register: TIMER_SUBSCRIBE_STOP */
8454 /* Description: Subscribe configuration for task STOP */
8455 
8456 /* Bit 31 :   */
8457 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8458 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8459 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8460 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8461 
8462 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8463 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8464 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8465 
8466 /* Register: TIMER_SUBSCRIBE_COUNT */
8467 /* Description: Subscribe configuration for task COUNT */
8468 
8469 /* Bit 31 :   */
8470 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
8471 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
8472 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
8473 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
8474 
8475 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
8476 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8477 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8478 
8479 /* Register: TIMER_SUBSCRIBE_CLEAR */
8480 /* Description: Subscribe configuration for task CLEAR */
8481 
8482 /* Bit 31 :   */
8483 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
8484 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
8485 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
8486 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
8487 
8488 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
8489 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8490 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8491 
8492 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
8493 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
8494 
8495 /* Bit 31 :   */
8496 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
8497 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
8498 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
8499 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
8500 
8501 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
8502 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8503 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8504 
8505 /* Register: TIMER_SUBSCRIBE_CAPTURE */
8506 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
8507 
8508 /* Bit 31 :   */
8509 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
8510 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
8511 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
8512 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
8513 
8514 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
8515 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8516 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8517 
8518 /* Register: TIMER_EVENTS_COMPARE */
8519 /* Description: Description collection: Compare event on CC[n] match */
8520 
8521 /* Bit 0 : Compare event on CC[n] match */
8522 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
8523 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
8524 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
8525 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8526 
8527 /* Register: TIMER_PUBLISH_COMPARE */
8528 /* Description: Description collection: Publish configuration for event COMPARE[n] */
8529 
8530 /* Bit 31 :   */
8531 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
8532 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
8533 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
8534 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
8535 
8536 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
8537 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8538 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8539 
8540 /* Register: TIMER_SHORTS */
8541 /* Description: Shortcuts between local events and tasks */
8542 
8543 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
8544 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
8545 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
8546 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8547 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8548 
8549 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
8550 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
8551 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
8552 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8553 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8554 
8555 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
8556 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
8557 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
8558 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8559 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8560 
8561 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
8562 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
8563 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
8564 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8565 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8566 
8567 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
8568 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
8569 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
8570 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8571 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8572 
8573 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
8574 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
8575 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
8576 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8577 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8578 
8579 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
8580 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
8581 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
8582 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8583 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8584 
8585 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
8586 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
8587 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
8588 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8589 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8590 
8591 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
8592 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
8593 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
8594 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8595 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8596 
8597 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8598 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8599 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
8600 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8601 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8602 
8603 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8604 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8605 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
8606 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8607 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8608 
8609 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
8610 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
8611 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
8612 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8613 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8614 
8615 /* Register: TIMER_INTENSET */
8616 /* Description: Enable interrupt */
8617 
8618 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8619 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8620 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8621 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8622 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8623 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8624 
8625 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8626 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8627 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8628 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8629 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8630 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8631 
8632 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8633 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8634 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8635 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8636 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8637 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8638 
8639 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8640 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8641 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8642 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8643 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8644 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8645 
8646 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8647 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8648 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8649 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8650 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8651 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8652 
8653 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8654 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8655 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8656 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8657 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8658 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8659 
8660 /* Register: TIMER_INTENCLR */
8661 /* Description: Disable interrupt */
8662 
8663 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
8664 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8665 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8666 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8667 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8668 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8669 
8670 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
8671 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8672 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8673 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8674 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8675 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8676 
8677 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8678 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8679 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8680 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8681 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8682 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8683 
8684 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8685 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8686 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8687 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8688 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8689 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8690 
8691 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8692 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8693 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8694 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8695 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8696 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8697 
8698 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8699 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8700 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8701 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8702 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8703 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8704 
8705 /* Register: TIMER_MODE */
8706 /* Description: Timer mode selection */
8707 
8708 /* Bits 1..0 : Timer mode */
8709 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
8710 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
8711 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
8712 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
8713 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
8714 
8715 /* Register: TIMER_BITMODE */
8716 /* Description: Configure the number of bits used by the TIMER */
8717 
8718 /* Bits 1..0 : Timer bit width */
8719 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
8720 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
8721 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
8722 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
8723 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
8724 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
8725 
8726 /* Register: TIMER_PRESCALER */
8727 /* Description: Timer prescaler register */
8728 
8729 /* Bits 3..0 : Prescaler value */
8730 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8731 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8732 
8733 /* Register: TIMER_ONESHOTEN */
8734 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
8735 
8736 /* Bit 0 : Enable one-shot operation */
8737 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
8738 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
8739 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
8740 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
8741 
8742 /* Register: TIMER_CC */
8743 /* Description: Description collection: Capture/Compare register n */
8744 
8745 /* Bits 31..0 : Capture/Compare value */
8746 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
8747 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
8748 
8749 
8750 /* Peripheral: TWIM */
8751 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
8752 
8753 /* Register: TWIM_TASKS_STARTRX */
8754 /* Description: Start TWI receive sequence */
8755 
8756 /* Bit 0 : Start TWI receive sequence */
8757 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
8758 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
8759 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
8760 
8761 /* Register: TWIM_TASKS_STARTTX */
8762 /* Description: Start TWI transmit sequence */
8763 
8764 /* Bit 0 : Start TWI transmit sequence */
8765 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
8766 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
8767 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
8768 
8769 /* Register: TWIM_TASKS_STOP */
8770 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8771 
8772 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8773 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8774 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8775 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8776 
8777 /* Register: TWIM_TASKS_SUSPEND */
8778 /* Description: Suspend TWI transaction */
8779 
8780 /* Bit 0 : Suspend TWI transaction */
8781 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8782 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8783 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8784 
8785 /* Register: TWIM_TASKS_RESUME */
8786 /* Description: Resume TWI transaction */
8787 
8788 /* Bit 0 : Resume TWI transaction */
8789 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8790 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8791 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8792 
8793 /* Register: TWIM_SUBSCRIBE_STARTRX */
8794 /* Description: Subscribe configuration for task STARTRX */
8795 
8796 /* Bit 31 :   */
8797 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
8798 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
8799 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
8800 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
8801 
8802 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
8803 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8804 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8805 
8806 /* Register: TWIM_SUBSCRIBE_STARTTX */
8807 /* Description: Subscribe configuration for task STARTTX */
8808 
8809 /* Bit 31 :   */
8810 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
8811 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
8812 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
8813 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
8814 
8815 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
8816 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8817 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8818 
8819 /* Register: TWIM_SUBSCRIBE_STOP */
8820 /* Description: Subscribe configuration for task STOP */
8821 
8822 /* Bit 31 :   */
8823 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8824 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8825 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8826 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8827 
8828 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8829 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8830 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8831 
8832 /* Register: TWIM_SUBSCRIBE_SUSPEND */
8833 /* Description: Subscribe configuration for task SUSPEND */
8834 
8835 /* Bit 31 :   */
8836 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
8837 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
8838 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
8839 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
8840 
8841 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
8842 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8843 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8844 
8845 /* Register: TWIM_SUBSCRIBE_RESUME */
8846 /* Description: Subscribe configuration for task RESUME */
8847 
8848 /* Bit 31 :   */
8849 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
8850 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
8851 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
8852 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
8853 
8854 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
8855 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8856 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8857 
8858 /* Register: TWIM_EVENTS_STOPPED */
8859 /* Description: TWI stopped */
8860 
8861 /* Bit 0 : TWI stopped */
8862 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8863 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8864 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8865 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8866 
8867 /* Register: TWIM_EVENTS_ERROR */
8868 /* Description: TWI error */
8869 
8870 /* Bit 0 : TWI error */
8871 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
8872 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
8873 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
8874 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
8875 
8876 /* Register: TWIM_EVENTS_SUSPENDED */
8877 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
8878 
8879 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
8880 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
8881 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
8882 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
8883 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
8884 
8885 /* Register: TWIM_EVENTS_RXSTARTED */
8886 /* Description: Receive sequence started */
8887 
8888 /* Bit 0 : Receive sequence started */
8889 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
8890 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
8891 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8892 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
8893 
8894 /* Register: TWIM_EVENTS_TXSTARTED */
8895 /* Description: Transmit sequence started */
8896 
8897 /* Bit 0 : Transmit sequence started */
8898 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
8899 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
8900 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8901 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
8902 
8903 /* Register: TWIM_EVENTS_LASTRX */
8904 /* Description: Byte boundary, starting to receive the last byte */
8905 
8906 /* Bit 0 : Byte boundary, starting to receive the last byte */
8907 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
8908 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
8909 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
8910 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
8911 
8912 /* Register: TWIM_EVENTS_LASTTX */
8913 /* Description: Byte boundary, starting to transmit the last byte */
8914 
8915 /* Bit 0 : Byte boundary, starting to transmit the last byte */
8916 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
8917 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
8918 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
8919 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
8920 
8921 /* Register: TWIM_PUBLISH_STOPPED */
8922 /* Description: Publish configuration for event STOPPED */
8923 
8924 /* Bit 31 :   */
8925 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
8926 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
8927 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
8928 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8929 
8930 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
8931 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8932 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8933 
8934 /* Register: TWIM_PUBLISH_ERROR */
8935 /* Description: Publish configuration for event ERROR */
8936 
8937 /* Bit 31 :   */
8938 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
8939 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
8940 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
8941 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
8942 
8943 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
8944 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8945 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8946 
8947 /* Register: TWIM_PUBLISH_SUSPENDED */
8948 /* Description: Publish configuration for event SUSPENDED */
8949 
8950 /* Bit 31 :   */
8951 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
8952 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
8953 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
8954 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
8955 
8956 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */
8957 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8958 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8959 
8960 /* Register: TWIM_PUBLISH_RXSTARTED */
8961 /* Description: Publish configuration for event RXSTARTED */
8962 
8963 /* Bit 31 :   */
8964 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
8965 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
8966 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8967 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8968 
8969 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
8970 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8971 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8972 
8973 /* Register: TWIM_PUBLISH_TXSTARTED */
8974 /* Description: Publish configuration for event TXSTARTED */
8975 
8976 /* Bit 31 :   */
8977 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
8978 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
8979 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8980 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8981 
8982 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
8983 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8984 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8985 
8986 /* Register: TWIM_PUBLISH_LASTRX */
8987 /* Description: Publish configuration for event LASTRX */
8988 
8989 /* Bit 31 :   */
8990 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
8991 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
8992 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
8993 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
8994 
8995 /* Bits 7..0 : DPPI channel that event LASTRX will publish to */
8996 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8997 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8998 
8999 /* Register: TWIM_PUBLISH_LASTTX */
9000 /* Description: Publish configuration for event LASTTX */
9001 
9002 /* Bit 31 :   */
9003 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
9004 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
9005 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
9006 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
9007 
9008 /* Bits 7..0 : DPPI channel that event LASTTX will publish to */
9009 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9010 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9011 
9012 /* Register: TWIM_SHORTS */
9013 /* Description: Shortcuts between local events and tasks */
9014 
9015 /* Bit 12 : Shortcut between event LASTRX and task STOP */
9016 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
9017 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
9018 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
9019 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
9020 
9021 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
9022 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
9023 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
9024 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9025 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9026 
9027 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
9028 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
9029 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
9030 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
9031 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
9032 
9033 /* Bit 9 : Shortcut between event LASTTX and task STOP */
9034 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
9035 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
9036 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
9037 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
9038 
9039 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
9040 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
9041 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
9042 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9043 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9044 
9045 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
9046 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
9047 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
9048 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
9049 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
9050 
9051 /* Register: TWIM_INTEN */
9052 /* Description: Enable or disable interrupt */
9053 
9054 /* Bit 24 : Enable or disable interrupt for event LASTTX */
9055 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9056 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9057 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
9058 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
9059 
9060 /* Bit 23 : Enable or disable interrupt for event LASTRX */
9061 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9062 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9063 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
9064 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
9065 
9066 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9067 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9068 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9069 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9070 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9071 
9072 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9073 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9074 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9075 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9076 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9077 
9078 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
9079 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9080 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9081 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
9082 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
9083 
9084 /* Bit 9 : Enable or disable interrupt for event ERROR */
9085 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9086 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9087 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9088 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9089 
9090 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9091 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9092 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9093 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9094 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9095 
9096 /* Register: TWIM_INTENSET */
9097 /* Description: Enable interrupt */
9098 
9099 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
9100 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9101 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9102 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9103 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9104 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
9105 
9106 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
9107 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9108 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9109 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9110 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9111 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
9112 
9113 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9114 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9115 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9116 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9117 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9118 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9119 
9120 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9121 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9122 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9123 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9124 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9125 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9126 
9127 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9128 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9129 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9130 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9131 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9132 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9133 
9134 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9135 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9136 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9137 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9138 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9139 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
9140 
9141 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9142 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9143 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9144 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9145 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9146 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9147 
9148 /* Register: TWIM_INTENCLR */
9149 /* Description: Disable interrupt */
9150 
9151 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
9152 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9153 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9154 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9155 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9156 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
9157 
9158 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
9159 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9160 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9161 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9162 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9163 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9164 
9165 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9166 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9167 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9168 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9169 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9170 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9171 
9172 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9173 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9174 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9175 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9176 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9177 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9178 
9179 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9180 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9181 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9182 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9183 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9184 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9185 
9186 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9187 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9188 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9189 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9190 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9191 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9192 
9193 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9194 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9195 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9196 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9197 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9198 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9199 
9200 /* Register: TWIM_ERRORSRC */
9201 /* Description: Error source */
9202 
9203 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9204 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9205 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9206 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9207 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9208 
9209 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9210 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9211 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
9212 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
9213 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
9214 
9215 /* Bit 0 : Overrun error */
9216 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9217 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9218 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
9219 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
9220 
9221 /* Register: TWIM_ENABLE */
9222 /* Description: Enable TWIM */
9223 
9224 /* Bits 3..0 : Enable or disable TWIM */
9225 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9226 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9227 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9228 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9229 
9230 /* Register: TWIM_PSEL_SCL */
9231 /* Description: Pin select for SCL signal */
9232 
9233 /* Bit 31 : Connection */
9234 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9235 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9236 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9237 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9238 
9239 /* Bits 4..0 : Pin number */
9240 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9241 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9242 
9243 /* Register: TWIM_PSEL_SDA */
9244 /* Description: Pin select for SDA signal */
9245 
9246 /* Bit 31 : Connection */
9247 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9248 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9249 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9250 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9251 
9252 /* Bits 4..0 : Pin number */
9253 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9254 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9255 
9256 /* Register: TWIM_FREQUENCY */
9257 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9258 
9259 /* Bits 31..0 : TWI master clock frequency */
9260 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9261 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9262 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
9263 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9264 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
9265 
9266 /* Register: TWIM_RXD_PTR */
9267 /* Description: Data pointer */
9268 
9269 /* Bits 31..0 : Data pointer */
9270 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9271 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9272 
9273 /* Register: TWIM_RXD_MAXCNT */
9274 /* Description: Maximum number of bytes in receive buffer */
9275 
9276 /* Bits 12..0 : Maximum number of bytes in receive buffer */
9277 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9278 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9279 
9280 /* Register: TWIM_RXD_AMOUNT */
9281 /* Description: Number of bytes transferred in the last transaction */
9282 
9283 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9284 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9285 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9286 
9287 /* Register: TWIM_RXD_LIST */
9288 /* Description: EasyDMA list type */
9289 
9290 /* Bits 1..0 : List type */
9291 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9292 #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9293 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9294 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9295 
9296 /* Register: TWIM_TXD_PTR */
9297 /* Description: Data pointer */
9298 
9299 /* Bits 31..0 : Data pointer */
9300 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9301 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9302 
9303 /* Register: TWIM_TXD_MAXCNT */
9304 /* Description: Maximum number of bytes in transmit buffer */
9305 
9306 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
9307 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9308 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9309 
9310 /* Register: TWIM_TXD_AMOUNT */
9311 /* Description: Number of bytes transferred in the last transaction */
9312 
9313 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9314 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9315 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9316 
9317 /* Register: TWIM_TXD_LIST */
9318 /* Description: EasyDMA list type */
9319 
9320 /* Bits 1..0 : List type */
9321 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9322 #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9323 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9324 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9325 
9326 /* Register: TWIM_ADDRESS */
9327 /* Description: Address used in the TWI transfer */
9328 
9329 /* Bits 6..0 : Address used in the TWI transfer */
9330 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9331 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9332 
9333 
9334 /* Peripheral: TWIS */
9335 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
9336 
9337 /* Register: TWIS_TASKS_STOP */
9338 /* Description: Stop TWI transaction */
9339 
9340 /* Bit 0 : Stop TWI transaction */
9341 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9342 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9343 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9344 
9345 /* Register: TWIS_TASKS_SUSPEND */
9346 /* Description: Suspend TWI transaction */
9347 
9348 /* Bit 0 : Suspend TWI transaction */
9349 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9350 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9351 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9352 
9353 /* Register: TWIS_TASKS_RESUME */
9354 /* Description: Resume TWI transaction */
9355 
9356 /* Bit 0 : Resume TWI transaction */
9357 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9358 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9359 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9360 
9361 /* Register: TWIS_TASKS_PREPARERX */
9362 /* Description: Prepare the TWI slave to respond to a write command */
9363 
9364 /* Bit 0 : Prepare the TWI slave to respond to a write command */
9365 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
9366 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
9367 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
9368 
9369 /* Register: TWIS_TASKS_PREPARETX */
9370 /* Description: Prepare the TWI slave to respond to a read command */
9371 
9372 /* Bit 0 : Prepare the TWI slave to respond to a read command */
9373 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
9374 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
9375 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
9376 
9377 /* Register: TWIS_SUBSCRIBE_STOP */
9378 /* Description: Subscribe configuration for task STOP */
9379 
9380 /* Bit 31 :   */
9381 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9382 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9383 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9384 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9385 
9386 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9387 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9388 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9389 
9390 /* Register: TWIS_SUBSCRIBE_SUSPEND */
9391 /* Description: Subscribe configuration for task SUSPEND */
9392 
9393 /* Bit 31 :   */
9394 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
9395 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
9396 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
9397 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
9398 
9399 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
9400 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9401 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9402 
9403 /* Register: TWIS_SUBSCRIBE_RESUME */
9404 /* Description: Subscribe configuration for task RESUME */
9405 
9406 /* Bit 31 :   */
9407 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
9408 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
9409 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
9410 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
9411 
9412 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
9413 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9414 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9415 
9416 /* Register: TWIS_SUBSCRIBE_PREPARERX */
9417 /* Description: Subscribe configuration for task PREPARERX */
9418 
9419 /* Bit 31 :   */
9420 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
9421 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
9422 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
9423 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
9424 
9425 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
9426 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9427 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9428 
9429 /* Register: TWIS_SUBSCRIBE_PREPARETX */
9430 /* Description: Subscribe configuration for task PREPARETX */
9431 
9432 /* Bit 31 :   */
9433 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
9434 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
9435 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
9436 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
9437 
9438 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
9439 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9440 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9441 
9442 /* Register: TWIS_EVENTS_STOPPED */
9443 /* Description: TWI stopped */
9444 
9445 /* Bit 0 : TWI stopped */
9446 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9447 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9448 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9449 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9450 
9451 /* Register: TWIS_EVENTS_ERROR */
9452 /* Description: TWI error */
9453 
9454 /* Bit 0 : TWI error */
9455 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9456 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9457 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9458 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9459 
9460 /* Register: TWIS_EVENTS_RXSTARTED */
9461 /* Description: Receive sequence started */
9462 
9463 /* Bit 0 : Receive sequence started */
9464 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9465 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9466 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9467 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9468 
9469 /* Register: TWIS_EVENTS_TXSTARTED */
9470 /* Description: Transmit sequence started */
9471 
9472 /* Bit 0 : Transmit sequence started */
9473 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9474 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9475 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9476 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9477 
9478 /* Register: TWIS_EVENTS_WRITE */
9479 /* Description: Write command received */
9480 
9481 /* Bit 0 : Write command received */
9482 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
9483 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
9484 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
9485 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
9486 
9487 /* Register: TWIS_EVENTS_READ */
9488 /* Description: Read command received */
9489 
9490 /* Bit 0 : Read command received */
9491 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
9492 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
9493 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
9494 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
9495 
9496 /* Register: TWIS_PUBLISH_STOPPED */
9497 /* Description: Publish configuration for event STOPPED */
9498 
9499 /* Bit 31 :   */
9500 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
9501 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
9502 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
9503 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9504 
9505 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
9506 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9507 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9508 
9509 /* Register: TWIS_PUBLISH_ERROR */
9510 /* Description: Publish configuration for event ERROR */
9511 
9512 /* Bit 31 :   */
9513 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
9514 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
9515 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
9516 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
9517 
9518 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
9519 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9520 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9521 
9522 /* Register: TWIS_PUBLISH_RXSTARTED */
9523 /* Description: Publish configuration for event RXSTARTED */
9524 
9525 /* Bit 31 :   */
9526 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9527 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9528 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9529 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9530 
9531 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
9532 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9533 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9534 
9535 /* Register: TWIS_PUBLISH_TXSTARTED */
9536 /* Description: Publish configuration for event TXSTARTED */
9537 
9538 /* Bit 31 :   */
9539 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9540 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9541 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9542 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9543 
9544 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
9545 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9546 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9547 
9548 /* Register: TWIS_PUBLISH_WRITE */
9549 /* Description: Publish configuration for event WRITE */
9550 
9551 /* Bit 31 :   */
9552 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
9553 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
9554 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
9555 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
9556 
9557 /* Bits 7..0 : DPPI channel that event WRITE will publish to */
9558 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9559 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9560 
9561 /* Register: TWIS_PUBLISH_READ */
9562 /* Description: Publish configuration for event READ */
9563 
9564 /* Bit 31 :   */
9565 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
9566 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
9567 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
9568 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
9569 
9570 /* Bits 7..0 : DPPI channel that event READ will publish to */
9571 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9572 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9573 
9574 /* Register: TWIS_SHORTS */
9575 /* Description: Shortcuts between local events and tasks */
9576 
9577 /* Bit 14 : Shortcut between event READ and task SUSPEND */
9578 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
9579 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
9580 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9581 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9582 
9583 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
9584 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
9585 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
9586 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9587 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9588 
9589 /* Register: TWIS_INTEN */
9590 /* Description: Enable or disable interrupt */
9591 
9592 /* Bit 26 : Enable or disable interrupt for event READ */
9593 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9594 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9595 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9596 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9597 
9598 /* Bit 25 : Enable or disable interrupt for event WRITE */
9599 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9600 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
9601 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9602 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9603 
9604 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9605 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9606 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9607 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9608 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9609 
9610 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9611 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9612 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9613 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9614 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9615 
9616 /* Bit 9 : Enable or disable interrupt for event ERROR */
9617 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9618 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9619 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9620 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9621 
9622 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9623 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9624 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9625 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9626 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9627 
9628 /* Register: TWIS_INTENSET */
9629 /* Description: Enable interrupt */
9630 
9631 /* Bit 26 : Write '1' to enable interrupt for event READ */
9632 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9633 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9634 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9635 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9636 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9637 
9638 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9639 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9640 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
9641 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9642 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9643 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9644 
9645 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9646 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9647 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9648 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9649 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9650 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9651 
9652 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9653 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9654 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9655 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9656 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9657 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9658 
9659 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9660 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9661 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9662 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9663 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9664 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9665 
9666 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9667 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9668 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9669 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9670 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9671 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9672 
9673 /* Register: TWIS_INTENCLR */
9674 /* Description: Disable interrupt */
9675 
9676 /* Bit 26 : Write '1' to disable interrupt for event READ */
9677 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
9678 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
9679 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9680 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9681 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9682 
9683 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
9684 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9685 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
9686 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9687 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9688 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9689 
9690 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9691 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9692 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9693 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9694 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9695 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9696 
9697 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9698 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9699 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9700 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9701 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9702 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9703 
9704 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9705 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9706 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9707 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9708 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9709 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9710 
9711 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9712 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9713 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9714 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9715 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9716 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9717 
9718 /* Register: TWIS_ERRORSRC */
9719 /* Description: Error source */
9720 
9721 /* Bit 3 : TX buffer over-read detected, and prevented */
9722 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
9723 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
9724 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
9725 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
9726 
9727 /* Bit 2 : NACK sent after receiving a data byte */
9728 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9729 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9730 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9731 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9732 
9733 /* Bit 0 : RX buffer overflow detected, and prevented */
9734 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
9735 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
9736 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
9737 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
9738 
9739 /* Register: TWIS_MATCH */
9740 /* Description: Status register indicating which address had a match */
9741 
9742 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
9743 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
9744 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
9745 
9746 /* Register: TWIS_ENABLE */
9747 /* Description: Enable TWIS */
9748 
9749 /* Bits 3..0 : Enable or disable TWIS */
9750 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9751 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9752 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
9753 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
9754 
9755 /* Register: TWIS_PSEL_SCL */
9756 /* Description: Pin select for SCL signal */
9757 
9758 /* Bit 31 : Connection */
9759 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9760 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9761 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9762 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9763 
9764 /* Bits 4..0 : Pin number */
9765 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9766 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9767 
9768 /* Register: TWIS_PSEL_SDA */
9769 /* Description: Pin select for SDA signal */
9770 
9771 /* Bit 31 : Connection */
9772 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9773 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9774 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9775 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9776 
9777 /* Bits 4..0 : Pin number */
9778 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9779 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9780 
9781 /* Register: TWIS_RXD_PTR */
9782 /* Description: RXD Data pointer */
9783 
9784 /* Bits 31..0 : RXD Data pointer */
9785 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9786 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9787 
9788 /* Register: TWIS_RXD_MAXCNT */
9789 /* Description: Maximum number of bytes in RXD buffer */
9790 
9791 /* Bits 12..0 : Maximum number of bytes in RXD buffer */
9792 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9793 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9794 
9795 /* Register: TWIS_RXD_AMOUNT */
9796 /* Description: Number of bytes transferred in the last RXD transaction */
9797 
9798 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */
9799 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9800 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9801 
9802 /* Register: TWIS_RXD_LIST */
9803 /* Description: EasyDMA list type */
9804 
9805 /* Bits 1..0 : List type */
9806 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9807 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9808 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9809 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9810 
9811 /* Register: TWIS_TXD_PTR */
9812 /* Description: TXD Data pointer */
9813 
9814 /* Bits 31..0 : TXD Data pointer */
9815 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9816 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9817 
9818 /* Register: TWIS_TXD_MAXCNT */
9819 /* Description: Maximum number of bytes in TXD buffer */
9820 
9821 /* Bits 12..0 : Maximum number of bytes in TXD buffer */
9822 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9823 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9824 
9825 /* Register: TWIS_TXD_AMOUNT */
9826 /* Description: Number of bytes transferred in the last TXD transaction */
9827 
9828 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */
9829 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9830 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9831 
9832 /* Register: TWIS_TXD_LIST */
9833 /* Description: EasyDMA list type */
9834 
9835 /* Bits 1..0 : List type */
9836 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9837 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9838 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9839 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9840 
9841 /* Register: TWIS_ADDRESS */
9842 /* Description: Description collection: TWI slave address n */
9843 
9844 /* Bits 6..0 : TWI slave address */
9845 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9846 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9847 
9848 /* Register: TWIS_CONFIG */
9849 /* Description: Configuration register for the address match mechanism */
9850 
9851 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9852 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
9853 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
9854 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
9855 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9856 
9857 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9858 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
9859 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
9860 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
9861 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
9862 
9863 /* Register: TWIS_ORC */
9864 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9865 
9866 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9867 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
9868 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
9869 
9870 
9871 /* Peripheral: UARTE */
9872 /* Description: UART with EasyDMA 0 */
9873 
9874 /* Register: UARTE_TASKS_STARTRX */
9875 /* Description: Start UART receiver */
9876 
9877 /* Bit 0 : Start UART receiver */
9878 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9879 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9880 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9881 
9882 /* Register: UARTE_TASKS_STOPRX */
9883 /* Description: Stop UART receiver */
9884 
9885 /* Bit 0 : Stop UART receiver */
9886 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
9887 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
9888 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
9889 
9890 /* Register: UARTE_TASKS_STARTTX */
9891 /* Description: Start UART transmitter */
9892 
9893 /* Bit 0 : Start UART transmitter */
9894 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9895 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9896 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9897 
9898 /* Register: UARTE_TASKS_STOPTX */
9899 /* Description: Stop UART transmitter */
9900 
9901 /* Bit 0 : Stop UART transmitter */
9902 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
9903 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
9904 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
9905 
9906 /* Register: UARTE_TASKS_FLUSHRX */
9907 /* Description: Flush RX FIFO into RX buffer */
9908 
9909 /* Bit 0 : Flush RX FIFO into RX buffer */
9910 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
9911 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
9912 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
9913 
9914 /* Register: UARTE_SUBSCRIBE_STARTRX */
9915 /* Description: Subscribe configuration for task STARTRX */
9916 
9917 /* Bit 31 :   */
9918 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
9919 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
9920 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
9921 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
9922 
9923 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
9924 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9925 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9926 
9927 /* Register: UARTE_SUBSCRIBE_STOPRX */
9928 /* Description: Subscribe configuration for task STOPRX */
9929 
9930 /* Bit 31 :   */
9931 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
9932 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
9933 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
9934 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
9935 
9936 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
9937 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9938 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9939 
9940 /* Register: UARTE_SUBSCRIBE_STARTTX */
9941 /* Description: Subscribe configuration for task STARTTX */
9942 
9943 /* Bit 31 :   */
9944 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
9945 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
9946 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
9947 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
9948 
9949 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
9950 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9951 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9952 
9953 /* Register: UARTE_SUBSCRIBE_STOPTX */
9954 /* Description: Subscribe configuration for task STOPTX */
9955 
9956 /* Bit 31 :   */
9957 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
9958 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
9959 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
9960 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
9961 
9962 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
9963 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9964 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9965 
9966 /* Register: UARTE_SUBSCRIBE_FLUSHRX */
9967 /* Description: Subscribe configuration for task FLUSHRX */
9968 
9969 /* Bit 31 :   */
9970 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
9971 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
9972 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
9973 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
9974 
9975 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
9976 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9977 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9978 
9979 /* Register: UARTE_EVENTS_CTS */
9980 /* Description: CTS is activated (set low). Clear To Send. */
9981 
9982 /* Bit 0 : CTS is activated (set low). Clear To Send. */
9983 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
9984 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
9985 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
9986 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
9987 
9988 /* Register: UARTE_EVENTS_NCTS */
9989 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9990 
9991 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
9992 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
9993 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
9994 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
9995 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
9996 
9997 /* Register: UARTE_EVENTS_RXDRDY */
9998 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
9999 
10000 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
10001 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
10002 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
10003 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
10004 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
10005 
10006 /* Register: UARTE_EVENTS_ENDRX */
10007 /* Description: Receive buffer is filled up */
10008 
10009 /* Bit 0 : Receive buffer is filled up */
10010 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
10011 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
10012 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
10013 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
10014 
10015 /* Register: UARTE_EVENTS_TXDRDY */
10016 /* Description: Data sent from TXD */
10017 
10018 /* Bit 0 : Data sent from TXD */
10019 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
10020 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
10021 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
10022 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
10023 
10024 /* Register: UARTE_EVENTS_ENDTX */
10025 /* Description: Last TX byte transmitted */
10026 
10027 /* Bit 0 : Last TX byte transmitted */
10028 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
10029 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
10030 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
10031 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
10032 
10033 /* Register: UARTE_EVENTS_ERROR */
10034 /* Description: Error detected */
10035 
10036 /* Bit 0 : Error detected */
10037 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
10038 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
10039 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
10040 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
10041 
10042 /* Register: UARTE_EVENTS_RXTO */
10043 /* Description: Receiver timeout */
10044 
10045 /* Bit 0 : Receiver timeout */
10046 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
10047 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
10048 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
10049 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
10050 
10051 /* Register: UARTE_EVENTS_RXSTARTED */
10052 /* Description: UART receiver has started */
10053 
10054 /* Bit 0 : UART receiver has started */
10055 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
10056 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
10057 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10058 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
10059 
10060 /* Register: UARTE_EVENTS_TXSTARTED */
10061 /* Description: UART transmitter has started */
10062 
10063 /* Bit 0 : UART transmitter has started */
10064 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
10065 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
10066 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10067 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
10068 
10069 /* Register: UARTE_EVENTS_TXSTOPPED */
10070 /* Description: Transmitter stopped */
10071 
10072 /* Bit 0 : Transmitter stopped */
10073 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
10074 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
10075 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
10076 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
10077 
10078 /* Register: UARTE_PUBLISH_CTS */
10079 /* Description: Publish configuration for event CTS */
10080 
10081 /* Bit 31 :   */
10082 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
10083 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
10084 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
10085 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
10086 
10087 /* Bits 7..0 : DPPI channel that event CTS will publish to */
10088 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10089 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10090 
10091 /* Register: UARTE_PUBLISH_NCTS */
10092 /* Description: Publish configuration for event NCTS */
10093 
10094 /* Bit 31 :   */
10095 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
10096 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
10097 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
10098 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
10099 
10100 /* Bits 7..0 : DPPI channel that event NCTS will publish to */
10101 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10102 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10103 
10104 /* Register: UARTE_PUBLISH_RXDRDY */
10105 /* Description: Publish configuration for event RXDRDY */
10106 
10107 /* Bit 31 :   */
10108 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
10109 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
10110 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
10111 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
10112 
10113 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to */
10114 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10115 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10116 
10117 /* Register: UARTE_PUBLISH_ENDRX */
10118 /* Description: Publish configuration for event ENDRX */
10119 
10120 /* Bit 31 :   */
10121 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
10122 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
10123 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
10124 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
10125 
10126 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
10127 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10128 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10129 
10130 /* Register: UARTE_PUBLISH_TXDRDY */
10131 /* Description: Publish configuration for event TXDRDY */
10132 
10133 /* Bit 31 :   */
10134 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
10135 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
10136 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
10137 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
10138 
10139 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to */
10140 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10141 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10142 
10143 /* Register: UARTE_PUBLISH_ENDTX */
10144 /* Description: Publish configuration for event ENDTX */
10145 
10146 /* Bit 31 :   */
10147 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
10148 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
10149 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
10150 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
10151 
10152 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */
10153 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10154 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10155 
10156 /* Register: UARTE_PUBLISH_ERROR */
10157 /* Description: Publish configuration for event ERROR */
10158 
10159 /* Bit 31 :   */
10160 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
10161 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
10162 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
10163 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
10164 
10165 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
10166 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10167 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10168 
10169 /* Register: UARTE_PUBLISH_RXTO */
10170 /* Description: Publish configuration for event RXTO */
10171 
10172 /* Bit 31 :   */
10173 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
10174 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
10175 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
10176 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
10177 
10178 /* Bits 7..0 : DPPI channel that event RXTO will publish to */
10179 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10180 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10181 
10182 /* Register: UARTE_PUBLISH_RXSTARTED */
10183 /* Description: Publish configuration for event RXSTARTED */
10184 
10185 /* Bit 31 :   */
10186 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10187 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10188 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10189 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10190 
10191 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
10192 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10193 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10194 
10195 /* Register: UARTE_PUBLISH_TXSTARTED */
10196 /* Description: Publish configuration for event TXSTARTED */
10197 
10198 /* Bit 31 :   */
10199 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10200 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10201 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10202 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10203 
10204 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
10205 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10206 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10207 
10208 /* Register: UARTE_PUBLISH_TXSTOPPED */
10209 /* Description: Publish configuration for event TXSTOPPED */
10210 
10211 /* Bit 31 :   */
10212 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
10213 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
10214 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
10215 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
10216 
10217 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */
10218 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10219 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10220 
10221 /* Register: UARTE_SHORTS */
10222 /* Description: Shortcuts between local events and tasks */
10223 
10224 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
10225 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
10226 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
10227 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10228 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10229 
10230 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
10231 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
10232 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
10233 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10234 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10235 
10236 /* Register: UARTE_INTEN */
10237 /* Description: Enable or disable interrupt */
10238 
10239 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10240 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10241 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10242 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
10243 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10244 
10245 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10246 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10247 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10248 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10249 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10250 
10251 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10252 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10253 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10254 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10255 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10256 
10257 /* Bit 17 : Enable or disable interrupt for event RXTO */
10258 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10259 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
10260 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
10261 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10262 
10263 /* Bit 9 : Enable or disable interrupt for event ERROR */
10264 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10265 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
10266 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10267 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10268 
10269 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10270 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10271 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10272 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
10273 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10274 
10275 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10276 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10277 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10278 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
10279 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10280 
10281 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10282 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10283 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10284 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
10285 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10286 
10287 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10288 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10289 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10290 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
10291 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10292 
10293 /* Bit 1 : Enable or disable interrupt for event NCTS */
10294 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10295 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
10296 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
10297 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10298 
10299 /* Bit 0 : Enable or disable interrupt for event CTS */
10300 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
10301 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
10302 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
10303 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10304 
10305 /* Register: UARTE_INTENSET */
10306 /* Description: Enable interrupt */
10307 
10308 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10309 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10310 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10311 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10312 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10313 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10314 
10315 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10316 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10317 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10318 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10319 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10320 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10321 
10322 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10323 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10324 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10325 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10326 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10327 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10328 
10329 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10330 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10331 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
10332 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10333 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10334 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10335 
10336 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10337 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10338 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10339 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10340 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10341 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10342 
10343 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10344 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10345 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10346 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10347 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10348 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10349 
10350 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10351 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10352 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10353 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10354 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10355 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10356 
10357 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10358 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10359 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10360 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10361 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10362 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10363 
10364 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10365 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10366 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10367 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10368 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10369 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10370 
10371 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10372 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10373 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
10374 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10375 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10376 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10377 
10378 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10379 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
10380 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
10381 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10382 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10383 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10384 
10385 /* Register: UARTE_INTENCLR */
10386 /* Description: Disable interrupt */
10387 
10388 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10389 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10390 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10391 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10392 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10393 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10394 
10395 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10396 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10397 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10398 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10399 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10400 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10401 
10402 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10403 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10404 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10405 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10406 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10407 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10408 
10409 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10410 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10411 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
10412 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10413 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10414 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10415 
10416 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10417 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10418 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10419 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10420 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10421 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10422 
10423 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10424 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10425 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10426 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10427 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10428 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10429 
10430 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10431 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10432 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10433 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10434 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10435 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10436 
10437 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10438 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10439 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10440 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10441 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10442 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10443 
10444 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10445 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10446 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10447 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10448 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10449 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10450 
10451 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10452 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10453 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
10454 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10455 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10456 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10457 
10458 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10459 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
10460 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
10461 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10462 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10463 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10464 
10465 /* Register: UARTE_ERRORSRC */
10466 /* Description: Error source This register is read/write one to clear. */
10467 
10468 /* Bit 3 : Break condition */
10469 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
10470 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
10471 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10472 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10473 
10474 /* Bit 2 : Framing error occurred */
10475 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10476 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
10477 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10478 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10479 
10480 /* Bit 1 : Parity error */
10481 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10482 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
10483 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10484 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10485 
10486 /* Bit 0 : Overrun error */
10487 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10488 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10489 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10490 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10491 
10492 /* Register: UARTE_ENABLE */
10493 /* Description: Enable UART */
10494 
10495 /* Bits 3..0 : Enable or disable UARTE */
10496 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10497 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10498 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10499 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10500 
10501 /* Register: UARTE_PSEL_RTS */
10502 /* Description: Pin select for RTS signal */
10503 
10504 /* Bit 31 : Connection */
10505 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10506 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10507 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
10508 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10509 
10510 /* Bits 4..0 : Pin number */
10511 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10512 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
10513 
10514 /* Register: UARTE_PSEL_TXD */
10515 /* Description: Pin select for TXD signal */
10516 
10517 /* Bit 31 : Connection */
10518 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10519 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10520 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
10521 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10522 
10523 /* Bits 4..0 : Pin number */
10524 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10525 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
10526 
10527 /* Register: UARTE_PSEL_CTS */
10528 /* Description: Pin select for CTS signal */
10529 
10530 /* Bit 31 : Connection */
10531 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10532 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10533 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
10534 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10535 
10536 /* Bits 4..0 : Pin number */
10537 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10538 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
10539 
10540 /* Register: UARTE_PSEL_RXD */
10541 /* Description: Pin select for RXD signal */
10542 
10543 /* Bit 31 : Connection */
10544 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10545 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10546 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
10547 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10548 
10549 /* Bits 4..0 : Pin number */
10550 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10551 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
10552 
10553 /* Register: UARTE_BAUDRATE */
10554 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
10555 
10556 /* Bits 31..0 : Baud rate */
10557 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
10558 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
10559 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
10560 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
10561 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
10562 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
10563 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
10564 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
10565 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
10566 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
10567 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
10568 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
10569 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
10570 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
10571 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
10572 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
10573 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
10574 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
10575 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
10576 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
10577 
10578 /* Register: UARTE_RXD_PTR */
10579 /* Description: Data pointer */
10580 
10581 /* Bits 31..0 : Data pointer */
10582 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10583 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10584 
10585 /* Register: UARTE_RXD_MAXCNT */
10586 /* Description: Maximum number of bytes in receive buffer */
10587 
10588 /* Bits 12..0 : Maximum number of bytes in receive buffer */
10589 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10590 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10591 
10592 /* Register: UARTE_RXD_AMOUNT */
10593 /* Description: Number of bytes transferred in the last transaction */
10594 
10595 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10596 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10597 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10598 
10599 /* Register: UARTE_TXD_PTR */
10600 /* Description: Data pointer */
10601 
10602 /* Bits 31..0 : Data pointer */
10603 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10604 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10605 
10606 /* Register: UARTE_TXD_MAXCNT */
10607 /* Description: Maximum number of bytes in transmit buffer */
10608 
10609 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
10610 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10611 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10612 
10613 /* Register: UARTE_TXD_AMOUNT */
10614 /* Description: Number of bytes transferred in the last transaction */
10615 
10616 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10617 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10618 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10619 
10620 /* Register: UARTE_CONFIG */
10621 /* Description: Configuration of parity and hardware flow control */
10622 
10623 /* Bit 4 : Stop bits */
10624 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
10625 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
10626 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
10627 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10628 
10629 /* Bits 3..1 : Parity */
10630 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10631 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
10632 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
10633 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
10634 
10635 /* Bit 0 : Hardware flow control */
10636 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
10637 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
10638 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10639 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10640 
10641 
10642 /* Peripheral: UICR */
10643 /* Description: User information configuration registers User information configuration registers */
10644 
10645 /* Register: UICR_APPROTECT */
10646 /* Description: Access port protection */
10647 
10648 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
10649           memory mapped addresses */
10650 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10651 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10652 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10653 #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10654 
10655 /* Register: UICR_XOSC32M */
10656 /* Description: Oscillator control */
10657 
10658 /* Bits 5..0 : Pierce current DAC control signals */
10659 #define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */
10660 #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */
10661 
10662 /* Register: UICR_HFXOSRC */
10663 /* Description: HFXO clock source selection */
10664 
10665 /* Bit 0 : HFXO clock source selection */
10666 #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */
10667 #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */
10668 #define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */
10669 #define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */
10670 
10671 /* Register: UICR_HFXOCNT */
10672 /* Description: HFXO startup counter */
10673 
10674 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
10675 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
10676 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
10677 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
10678 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */
10679 
10680 /* Register: UICR_APPNVMCPOFGUARD */
10681 /* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */
10682 
10683 /* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */
10684 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */
10685 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */
10686 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */
10687 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */
10688 
10689 /* Register: UICR_SECUREAPPROTECT */
10690 /* Description: Secure access port protection */
10691 
10692 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
10693           memory mapped addresses */
10694 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10695 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10696 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10697 #define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10698 
10699 /* Register: UICR_ERASEPROTECT */
10700 /* Description: Erase protection */
10701 
10702 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */
10703 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10704 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10705 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10706 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10707 
10708 /* Register: UICR_OTP */
10709 /* Description: Description collection: One time programmable memory */
10710 
10711 /* Bits 31..16 : Upper half word */
10712 #define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
10713 #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */
10714 
10715 /* Bits 15..0 : Lower half word */
10716 #define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
10717 #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */
10718 
10719 /* Register: UICR_KEYSLOT_CONFIG_DEST */
10720 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
10721           will be pushed by KMU. Note that this address must match that of a peripherals
10722           APB mapped write-only key registers, else the KMU can push this key value into
10723           an address range which the CPU can potentially read. */
10724 
10725 /* Bits 31..0 : Secure APB destination address */
10726 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
10727 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
10728 
10729 /* Register: UICR_KEYSLOT_CONFIG_PERM */
10730 /* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */
10731 
10732 /* Bit 16 : Revocation state for the key slot */
10733 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
10734 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
10735 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */
10736 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
10737 
10738 /* Bit 2 : Push permission for key slot */
10739 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
10740 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
10741 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
10742 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */
10743 
10744 /* Bit 1 : Read permission for key slot */
10745 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
10746 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
10747 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
10748 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
10749 
10750 /* Bit 0 : Write permission for key slot */
10751 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
10752 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
10753 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */
10754 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
10755 
10756 /* Register: UICR_KEYSLOT_KEY_VALUE */
10757 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
10758 
10759 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
10760 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
10761 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
10762 
10763 
10764 /* Peripheral: VMC */
10765 /* Description: Volatile Memory controller 0 */
10766 
10767 /* Register: VMC_RAM_POWER */
10768 /* Description: Description cluster: RAMn power control register */
10769 
10770 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10771 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10772 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10773 #define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
10774 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
10775 
10776 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10777 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10778 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10779 #define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
10780 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
10781 
10782 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10783 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10784 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10785 #define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
10786 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
10787 
10788 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10789 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10790 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10791 #define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
10792 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
10793 
10794 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10795 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10796 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10797 #define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
10798 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
10799 
10800 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10801 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10802 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10803 #define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
10804 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
10805 
10806 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10807 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10808 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10809 #define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
10810 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
10811 
10812 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10813 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10814 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10815 #define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
10816 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
10817 
10818 /* Register: VMC_RAM_POWERSET */
10819 /* Description: Description cluster: RAMn power control set register */
10820 
10821 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10822 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10823 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10824 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
10825 
10826 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10827 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10828 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10829 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
10830 
10831 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10832 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10833 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10834 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
10835 
10836 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10837 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10838 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10839 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
10840 
10841 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10842 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10843 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10844 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
10845 
10846 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10847 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10848 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10849 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
10850 
10851 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10852 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10853 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10854 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
10855 
10856 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10857 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10858 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10859 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
10860 
10861 /* Register: VMC_RAM_POWERCLR */
10862 /* Description: Description cluster: RAMn power control clear register */
10863 
10864 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10865 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10866 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10867 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
10868 
10869 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10870 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10871 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10872 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
10873 
10874 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10875 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10876 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10877 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
10878 
10879 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10880 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10881 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10882 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
10883 
10884 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10885 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10886 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10887 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
10888 
10889 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10890 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10891 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10892 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
10893 
10894 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10895 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10896 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10897 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
10898 
10899 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10900 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10901 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10902 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
10903 
10904 
10905 /* Peripheral: WDT */
10906 /* Description: Watchdog Timer 0 */
10907 
10908 /* Register: WDT_TASKS_START */
10909 /* Description: Start the watchdog */
10910 
10911 /* Bit 0 : Start the watchdog */
10912 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10913 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10914 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10915 
10916 /* Register: WDT_SUBSCRIBE_START */
10917 /* Description: Subscribe configuration for task START */
10918 
10919 /* Bit 31 :   */
10920 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
10921 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
10922 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
10923 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
10924 
10925 /* Bits 7..0 : DPPI channel that task START will subscribe to */
10926 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10927 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10928 
10929 /* Register: WDT_EVENTS_TIMEOUT */
10930 /* Description: Watchdog timeout */
10931 
10932 /* Bit 0 : Watchdog timeout */
10933 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
10934 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
10935 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
10936 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
10937 
10938 /* Register: WDT_PUBLISH_TIMEOUT */
10939 /* Description: Publish configuration for event TIMEOUT */
10940 
10941 /* Bit 31 :   */
10942 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
10943 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
10944 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
10945 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
10946 
10947 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */
10948 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10949 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10950 
10951 /* Register: WDT_INTENSET */
10952 /* Description: Enable interrupt */
10953 
10954 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
10955 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
10956 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
10957 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10958 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10959 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
10960 
10961 /* Register: WDT_INTENCLR */
10962 /* Description: Disable interrupt */
10963 
10964 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
10965 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
10966 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
10967 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10968 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10969 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
10970 
10971 /* Register: WDT_RUNSTATUS */
10972 /* Description: Run status */
10973 
10974 /* Bit 0 : Indicates whether or not the watchdog is running */
10975 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
10976 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
10977 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */
10978 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
10979 
10980 /* Register: WDT_REQSTATUS */
10981 /* Description: Request status */
10982 
10983 /* Bit 7 : Request status for RR[7] register */
10984 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
10985 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
10986 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
10987 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
10988 
10989 /* Bit 6 : Request status for RR[6] register */
10990 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
10991 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
10992 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
10993 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
10994 
10995 /* Bit 5 : Request status for RR[5] register */
10996 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
10997 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
10998 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
10999 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
11000 
11001 /* Bit 4 : Request status for RR[4] register */
11002 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
11003 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
11004 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
11005 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
11006 
11007 /* Bit 3 : Request status for RR[3] register */
11008 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
11009 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
11010 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
11011 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
11012 
11013 /* Bit 2 : Request status for RR[2] register */
11014 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
11015 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
11016 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
11017 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
11018 
11019 /* Bit 1 : Request status for RR[1] register */
11020 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
11021 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
11022 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
11023 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
11024 
11025 /* Bit 0 : Request status for RR[0] register */
11026 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
11027 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
11028 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
11029 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
11030 
11031 /* Register: WDT_CRV */
11032 /* Description: Counter reload value */
11033 
11034 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
11035 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
11036 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
11037 
11038 /* Register: WDT_RREN */
11039 /* Description: Enable register for reload request registers */
11040 
11041 /* Bit 7 : Enable or disable RR[7] register */
11042 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
11043 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
11044 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
11045 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
11046 
11047 /* Bit 6 : Enable or disable RR[6] register */
11048 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
11049 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
11050 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
11051 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
11052 
11053 /* Bit 5 : Enable or disable RR[5] register */
11054 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
11055 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
11056 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
11057 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
11058 
11059 /* Bit 4 : Enable or disable RR[4] register */
11060 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
11061 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
11062 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
11063 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
11064 
11065 /* Bit 3 : Enable or disable RR[3] register */
11066 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
11067 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
11068 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
11069 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
11070 
11071 /* Bit 2 : Enable or disable RR[2] register */
11072 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
11073 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
11074 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
11075 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
11076 
11077 /* Bit 1 : Enable or disable RR[1] register */
11078 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
11079 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
11080 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
11081 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
11082 
11083 /* Bit 0 : Enable or disable RR[0] register */
11084 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
11085 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
11086 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
11087 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
11088 
11089 /* Register: WDT_CONFIG */
11090 /* Description: Configuration register */
11091 
11092 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
11093 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
11094 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
11095 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
11096 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
11097 
11098 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
11099 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
11100 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
11101 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
11102 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
11103 
11104 /* Register: WDT_RR */
11105 /* Description: Description collection: Reload request n */
11106 
11107 /* Bits 31..0 : Reload request register */
11108 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
11109 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
11110 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
11111 
11112 
11113 /*lint --flb "Leave library region" */
11114 #endif
11115