1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf9160.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:21 37 * from File 'nrf9160.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf9160 49 * @{ 50 */ 51 52 53 #ifndef NRF9160_H 54 #define NRF9160_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ 87 SPU_IRQn = 3, /*!< 3 SPU */ 88 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 89 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ 91 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ 92 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ 93 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 94 SAADC_IRQn = 14, /*!< 14 SAADC */ 95 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 96 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 97 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 98 RTC0_IRQn = 20, /*!< 20 RTC0 */ 99 RTC1_IRQn = 21, /*!< 21 RTC1 */ 100 WDT_IRQn = 24, /*!< 24 WDT */ 101 EGU0_IRQn = 27, /*!< 27 EGU0 */ 102 EGU1_IRQn = 28, /*!< 28 EGU1 */ 103 EGU2_IRQn = 29, /*!< 29 EGU2 */ 104 EGU3_IRQn = 30, /*!< 30 EGU3 */ 105 EGU4_IRQn = 31, /*!< 31 EGU4 */ 106 EGU5_IRQn = 32, /*!< 32 EGU5 */ 107 PWM0_IRQn = 33, /*!< 33 PWM0 */ 108 PWM1_IRQn = 34, /*!< 34 PWM1 */ 109 PWM2_IRQn = 35, /*!< 35 PWM2 */ 110 PWM3_IRQn = 36, /*!< 36 PWM3 */ 111 PDM_IRQn = 38, /*!< 38 PDM */ 112 I2S_IRQn = 40, /*!< 40 I2S */ 113 IPC_IRQn = 42, /*!< 42 IPC */ 114 FPU_IRQn = 44, /*!< 44 FPU */ 115 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 116 KMU_IRQn = 57, /*!< 57 KMU */ 117 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 118 } IRQn_Type; 119 120 121 122 /* =========================================================================================================================== */ 123 /* ================ Processor and Core Peripheral Section ================ */ 124 /* =========================================================================================================================== */ 125 126 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 127 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 128 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 129 #define __DSP_PRESENT 1 /*!< DSP present or not */ 130 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 131 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 132 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133 #define __MPU_PRESENT 1 /*!< MPU present */ 134 #define __FPU_PRESENT 1 /*!< FPU present */ 135 #define __FPU_DP 0 /*!< Double Precision FPU */ 136 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 137 138 139 /** @} */ /* End of group Configuration_of_CMSIS */ 140 141 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 142 #include "system_nrf9160.h" /*!< nrf9160 System */ 143 144 #ifndef __IM /*!< Fallback for older CMSIS versions */ 145 #define __IM __I 146 #endif 147 #ifndef __OM /*!< Fallback for older CMSIS versions */ 148 #define __OM __O 149 #endif 150 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151 #define __IOM __IO 152 #endif 153 154 155 /* =========================================================================================================================== */ 156 /* ================ Device Specific Cluster Section ================ */ 157 /* =========================================================================================================================== */ 158 159 160 /** @addtogroup Device_Peripheral_clusters 161 * @{ 162 */ 163 164 165 /** 166 * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info) 167 */ 168 typedef struct { 169 __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ 170 __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision, 171 encoded in ASCII, ex B0A or B1A */ 172 __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded 173 in ASCII, ex SIAA, SIBA or SICA */ 174 } FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */ 175 176 177 /** 178 * @brief FICR_INFO [INFO] (Device info) 179 */ 180 typedef struct { 181 __IM uint32_t RESERVED; 182 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 183 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 184 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 185 configuration */ 186 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 187 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 188 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 189 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 190 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 191 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 192 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 193 194 195 /** 196 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 197 */ 198 typedef struct { 199 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 200 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 201 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 202 203 204 /** 205 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 206 */ 207 typedef struct { 208 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 209 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 210 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 211 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 212 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 213 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 214 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 215 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 216 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 217 218 219 /** 220 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 221 */ 222 typedef struct { 223 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 224 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 225 ) will be pushed by KMU. Note that this 226 address must match that of a peripherals 227 APB mapped write-only key registers, else 228 the KMU can push this key value into an 229 address range which the CPU can potentially 230 read. */ 231 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 232 key slot. Bits 0-15 and 16-31 can only be 233 written when equal to 0xFFFF. */ 234 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 235 236 237 /** 238 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 239 */ 240 typedef struct { 241 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 242 of value assigned to KMU key slot. */ 243 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 244 245 246 /** 247 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 248 */ 249 typedef struct { 250 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 251 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 252 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 253 254 255 /** 256 * @brief TAD_PSEL [PSEL] (Unspecified) 257 */ 258 typedef struct { 259 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 260 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 261 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 262 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 263 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 264 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 265 266 267 /** 268 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 269 */ 270 typedef struct { 271 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 272 from the external domain n List capabilities 273 of the external domain n */ 274 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 275 276 277 /** 278 * @brief SPU_DPPI [DPPI] (Unspecified) 279 */ 280 typedef struct { 281 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 282 non-secure attribute for the DPPI channels. */ 283 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 284 of the corresponding PERM register */ 285 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 286 287 288 /** 289 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 290 */ 291 typedef struct { 292 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 293 non-secure attribute for pins 0 to 31 of 294 port n. */ 295 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 296 of the corresponding PERM register */ 297 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 298 299 300 /** 301 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 302 */ 303 typedef struct { 304 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 305 can contain the non-secure callable (NSC) 306 region n */ 307 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 308 callable (NSC) region n */ 309 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 310 311 312 /** 313 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 314 */ 315 typedef struct { 316 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 317 can contain the non-secure callable (NSC) 318 region n */ 319 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 320 callable (NSC) region n */ 321 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 322 323 324 /** 325 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 326 */ 327 typedef struct { 328 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 329 region n */ 330 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 331 332 333 /** 334 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 335 */ 336 typedef struct { 337 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 338 region n */ 339 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 340 341 342 /** 343 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 344 */ 345 typedef struct { 346 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 347 permissions for the peripheral with ID n */ 348 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 349 350 351 /** 352 * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) 353 */ 354 typedef struct { 355 __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ 356 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ 357 } POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ 358 359 360 /** 361 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 362 */ 363 typedef struct { 364 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 365 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 366 data sent from the debugger to the CPU has 367 been read. */ 368 __IM uint32_t RESERVED[30]; 369 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 370 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 371 the data sent from the CPU to the debugger 372 has been read. */ 373 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 374 375 376 /** 377 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 378 */ 379 typedef struct { 380 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 381 register from being written until next reset. */ 382 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 383 and performs an ERASEALL operation. */ 384 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 385 386 387 /** 388 * @brief SPIM_PSEL [PSEL] (Unspecified) 389 */ 390 typedef struct { 391 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 392 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 393 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 394 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 395 396 397 /** 398 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 399 */ 400 typedef struct { 401 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 402 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 403 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 404 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 405 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 406 407 408 /** 409 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 410 */ 411 typedef struct { 412 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 413 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 414 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 415 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 416 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 417 418 419 /** 420 * @brief SPIS_PSEL [PSEL] (Unspecified) 421 */ 422 typedef struct { 423 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 424 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 425 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 426 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 427 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 428 429 430 /** 431 * @brief SPIS_RXD [RXD] (Unspecified) 432 */ 433 typedef struct { 434 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 435 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 436 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 437 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 438 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 439 440 441 /** 442 * @brief SPIS_TXD [TXD] (Unspecified) 443 */ 444 typedef struct { 445 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 446 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 447 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 448 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 449 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 450 451 452 /** 453 * @brief TWIM_PSEL [PSEL] (Unspecified) 454 */ 455 typedef struct { 456 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 457 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 458 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 459 460 461 /** 462 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 463 */ 464 typedef struct { 465 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 466 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 467 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 468 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 469 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 470 471 472 /** 473 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 474 */ 475 typedef struct { 476 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 477 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 478 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 479 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 480 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 481 482 483 /** 484 * @brief TWIS_PSEL [PSEL] (Unspecified) 485 */ 486 typedef struct { 487 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 488 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 489 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 490 491 492 /** 493 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 494 */ 495 typedef struct { 496 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 497 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 498 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 499 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 500 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 501 502 503 /** 504 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 505 */ 506 typedef struct { 507 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 508 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 509 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 510 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 511 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 512 513 514 /** 515 * @brief UARTE_PSEL [PSEL] (Unspecified) 516 */ 517 typedef struct { 518 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 519 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 520 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 521 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 522 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 523 524 525 /** 526 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 527 */ 528 typedef struct { 529 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 530 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 531 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 532 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 533 534 535 /** 536 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 537 */ 538 typedef struct { 539 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 540 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 541 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 542 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 543 544 545 /** 546 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 547 */ 548 typedef struct { 549 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 550 above CH[n].LIMIT.HIGH */ 551 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 552 below CH[n].LIMIT.LOW */ 553 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 554 555 556 /** 557 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 558 */ 559 typedef struct { 560 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 561 event CH[n].LIMITH */ 562 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 563 event CH[n].LIMITL */ 564 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 565 566 567 /** 568 * @brief SAADC_CH [CH] (Unspecified) 569 */ 570 typedef struct { 571 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 572 for CH[n] */ 573 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 574 for CH[n] */ 575 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 576 CH[n] */ 577 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 578 monitoring a channel */ 579 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 580 581 582 /** 583 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 584 */ 585 typedef struct { 586 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 587 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 588 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 589 START */ 590 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 591 592 593 /** 594 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 595 */ 596 typedef struct { 597 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 598 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 599 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 600 601 602 /** 603 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 604 */ 605 typedef struct { 606 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 607 for task CHG[n].EN */ 608 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 609 for task CHG[n].DIS */ 610 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 611 612 613 /** 614 * @brief PWM_SEQ [SEQ] (Unspecified) 615 */ 616 typedef struct { 617 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 618 of this sequence */ 619 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 620 in this sequence */ 621 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 622 periods between samples loaded into compare 623 register */ 624 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 625 __IM uint32_t RESERVED[4]; 626 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 627 628 629 /** 630 * @brief PWM_PSEL [PSEL] (Unspecified) 631 */ 632 typedef struct { 633 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 634 PWM channel n */ 635 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 636 637 638 /** 639 * @brief PDM_PSEL [PSEL] (Unspecified) 640 */ 641 typedef struct { 642 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 643 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 644 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 645 646 647 /** 648 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 649 */ 650 typedef struct { 651 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 652 EasyDMA */ 653 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 654 mode */ 655 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 656 657 658 /** 659 * @brief I2S_CONFIG [CONFIG] (Unspecified) 660 */ 661 typedef struct { 662 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 663 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 664 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 665 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 666 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 667 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 668 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 669 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 670 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 671 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 672 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 673 674 675 /** 676 * @brief I2S_RXD [RXD] (Unspecified) 677 */ 678 typedef struct { 679 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 680 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 681 682 683 /** 684 * @brief I2S_TXD [TXD] (Unspecified) 685 */ 686 typedef struct { 687 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 688 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 689 690 691 /** 692 * @brief I2S_RXTXD [RXTXD] (Unspecified) 693 */ 694 typedef struct { 695 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 696 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 697 698 699 /** 700 * @brief I2S_PSEL [PSEL] (Unspecified) 701 */ 702 typedef struct { 703 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 704 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 705 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 706 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 707 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 708 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 709 710 711 /** 712 * @brief VMC_RAM [RAM] (Unspecified) 713 */ 714 typedef struct { 715 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 716 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 717 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 718 register */ 719 __IM uint32_t RESERVED; 720 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 721 722 723 /** @} */ /* End of group Device_Peripheral_clusters */ 724 725 726 /* =========================================================================================================================== */ 727 /* ================ Device Specific Peripheral Section ================ */ 728 /* =========================================================================================================================== */ 729 730 731 /** @addtogroup Device_Peripheral_peripherals 732 * @{ 733 */ 734 735 736 737 /* =========================================================================================================================== */ 738 /* ================ FICR_S ================ */ 739 /* =========================================================================================================================== */ 740 741 742 /** 743 * @brief Factory Information Configuration Registers (FICR_S) 744 */ 745 746 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 747 __IM uint32_t RESERVED[80]; 748 __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */ 749 __IM uint32_t RESERVED1[45]; 750 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 751 __IM uint32_t RESERVED2[53]; 752 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 753 __IM uint32_t RESERVED3[64]; 754 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 755 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 756 757 758 759 /* =========================================================================================================================== */ 760 /* ================ UICR_S ================ */ 761 /* =========================================================================================================================== */ 762 763 764 /** 765 * @brief User information configuration registers User information configuration registers (UICR_S) 766 */ 767 768 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 769 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 770 __IM uint32_t RESERVED[4]; 771 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 772 __IM uint32_t RESERVED1; 773 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 774 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 775 __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE 776 for Application NVM in POFWARN condition 777 . */ 778 __IM uint32_t RESERVED2; 779 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 780 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 781 __IM uint32_t RESERVED3[53]; 782 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable 783 memory */ 784 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 785 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 786 787 788 789 /* =========================================================================================================================== */ 790 /* ================ TAD_S ================ */ 791 /* =========================================================================================================================== */ 792 793 794 /** 795 * @brief Trace and debug control (TAD_S) 796 */ 797 798 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 799 __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ 800 __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ 801 __IM uint32_t RESERVED[318]; 802 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 803 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 804 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 805 Reset behavior is the same as debug components */ 806 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 807 808 809 810 /* =========================================================================================================================== */ 811 /* ================ SPU_S ================ */ 812 /* =========================================================================================================================== */ 813 814 815 /** 816 * @brief System protection unit (SPU_S) 817 */ 818 819 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 820 __IM uint32_t RESERVED[64]; 821 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 822 RAM memory space */ 823 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 824 flash memory space */ 825 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 826 or several peripherals */ 827 __IM uint32_t RESERVED1[29]; 828 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 829 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 830 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 831 __IM uint32_t RESERVED2[93]; 832 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 833 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 834 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 835 __IM uint32_t RESERVED3[61]; 836 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 837 __IM uint32_t RESERVED4[15]; 838 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 839 __IM uint32_t RESERVED5[15]; 840 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 841 __IM uint32_t RESERVED6[14]; 842 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 843 __IM uint32_t RESERVED7[14]; 844 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 845 __IM uint32_t RESERVED8[12]; 846 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 847 __IM uint32_t RESERVED9[44]; 848 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 849 __IM uint32_t RESERVED10[32]; 850 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 851 __IM uint32_t RESERVED11[32]; 852 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 853 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 854 855 856 857 /* =========================================================================================================================== */ 858 /* ================ REGULATORS_NS ================ */ 859 /* =========================================================================================================================== */ 860 861 862 /** 863 * @brief Voltage regulators control 0 (REGULATORS_NS) 864 */ 865 866 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 867 __IM uint32_t RESERVED[320]; 868 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 869 __IM uint32_t RESERVED1[4]; 870 __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ 871 __IM uint32_t RESERVED2[24]; 872 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */ 873 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 874 875 876 877 /* =========================================================================================================================== */ 878 /* ================ CLOCK_NS ================ */ 879 /* =========================================================================================================================== */ 880 881 882 /** 883 * @brief Clock management 0 (CLOCK_NS) 884 */ 885 886 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 887 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ 888 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ 889 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 890 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 891 __IM uint32_t RESERVED[28]; 892 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 893 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 894 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 895 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 896 __IM uint32_t RESERVED1[28]; 897 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 898 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 899 __IM uint32_t RESERVED2[30]; 900 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 901 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 902 __IM uint32_t RESERVED3[94]; 903 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 904 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 905 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 906 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 907 __IM uint32_t RESERVED4[62]; 908 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 909 triggered */ 910 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 911 by triggering HFCLKSTART task and if it 912 has been started (STATE) */ 913 __IM uint32_t RESERVED5; 914 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 915 triggered */ 916 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 917 requested (SRC) when triggering LFCLKSTART 918 task and if the source has been started 919 (STATE) */ 920 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 921 task has been triggered */ 922 __IM uint32_t RESERVED6[62]; 923 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 924 starts a clock source selected with this 925 register. */ 926 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 927 928 929 930 /* =========================================================================================================================== */ 931 /* ================ POWER_NS ================ */ 932 /* =========================================================================================================================== */ 933 934 935 /** 936 * @brief Power control 0 (POWER_NS) 937 */ 938 939 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 940 __IM uint32_t RESERVED[30]; 941 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 942 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 943 __IM uint32_t RESERVED1[30]; 944 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 945 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 946 __IM uint32_t RESERVED2[2]; 947 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 948 __IM uint32_t RESERVED3[2]; 949 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 950 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 951 __IM uint32_t RESERVED4[27]; 952 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 953 __IM uint32_t RESERVED5[2]; 954 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 955 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 956 __IM uint32_t RESERVED6[89]; 957 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 958 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 959 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 960 __IM uint32_t RESERVED7[61]; 961 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 962 __IM uint32_t RESERVED8[15]; 963 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 964 __IM uint32_t RESERVED9[54]; 965 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 966 register */ 967 __IM uint32_t RESERVED10[59]; 968 __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ 969 } NRF_POWER_Type; /*!< Size = 1560 (0x618) */ 970 971 972 973 /* =========================================================================================================================== */ 974 /* ================ CTRL_AP_PERI_S ================ */ 975 /* =========================================================================================================================== */ 976 977 978 /** 979 * @brief Control access port (CTRL_AP_PERI_S) 980 */ 981 982 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 983 __IM uint32_t RESERVED[256]; 984 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 985 __IM uint32_t RESERVED1[30]; 986 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 987 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 988 989 990 991 /* =========================================================================================================================== */ 992 /* ================ SPIM0_NS ================ */ 993 /* =========================================================================================================================== */ 994 995 996 /** 997 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 998 */ 999 1000 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1001 __IM uint32_t RESERVED[4]; 1002 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1003 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1004 __IM uint32_t RESERVED1; 1005 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1006 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1007 __IM uint32_t RESERVED2[27]; 1008 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1009 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1010 __IM uint32_t RESERVED3; 1011 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1012 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1013 __IM uint32_t RESERVED4[24]; 1014 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1015 __IM uint32_t RESERVED5[2]; 1016 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1017 __IM uint32_t RESERVED6; 1018 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1019 __IM uint32_t RESERVED7; 1020 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1021 __IM uint32_t RESERVED8[10]; 1022 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1023 __IM uint32_t RESERVED9[13]; 1024 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1025 __IM uint32_t RESERVED10[2]; 1026 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1027 __IM uint32_t RESERVED11; 1028 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1029 __IM uint32_t RESERVED12; 1030 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1031 __IM uint32_t RESERVED13[10]; 1032 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1033 __IM uint32_t RESERVED14[12]; 1034 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1035 __IM uint32_t RESERVED15[64]; 1036 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1037 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1038 __IM uint32_t RESERVED16[125]; 1039 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1040 __IM uint32_t RESERVED17; 1041 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1042 __IM uint32_t RESERVED18[4]; 1043 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1044 source selected. */ 1045 __IM uint32_t RESERVED19[3]; 1046 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1047 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1048 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1049 __IM uint32_t RESERVED20[26]; 1050 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1051 case an over-read of the TXD buffer. */ 1052 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1053 1054 1055 1056 /* =========================================================================================================================== */ 1057 /* ================ SPIS0_NS ================ */ 1058 /* =========================================================================================================================== */ 1059 1060 1061 /** 1062 * @brief SPI Slave 0 (SPIS0_NS) 1063 */ 1064 1065 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1066 __IM uint32_t RESERVED[9]; 1067 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1068 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1069 to acquire it */ 1070 __IM uint32_t RESERVED1[30]; 1071 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1072 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1073 __IM uint32_t RESERVED2[22]; 1074 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1075 __IM uint32_t RESERVED3[2]; 1076 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1077 __IM uint32_t RESERVED4[5]; 1078 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1079 __IM uint32_t RESERVED5[22]; 1080 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1081 __IM uint32_t RESERVED6[2]; 1082 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1083 __IM uint32_t RESERVED7[5]; 1084 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1085 __IM uint32_t RESERVED8[21]; 1086 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1087 __IM uint32_t RESERVED9[64]; 1088 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1089 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1090 __IM uint32_t RESERVED10[61]; 1091 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1092 __IM uint32_t RESERVED11[15]; 1093 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1094 __IM uint32_t RESERVED12[47]; 1095 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1096 __IM uint32_t RESERVED13; 1097 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1098 __IM uint32_t RESERVED14[7]; 1099 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1100 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1101 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1102 __IM uint32_t RESERVED15; 1103 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1104 of an ignored transaction. */ 1105 __IM uint32_t RESERVED16[24]; 1106 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1107 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1108 1109 1110 1111 /* =========================================================================================================================== */ 1112 /* ================ TWIM0_NS ================ */ 1113 /* =========================================================================================================================== */ 1114 1115 1116 /** 1117 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1118 */ 1119 1120 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1121 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1122 __IM uint32_t RESERVED; 1123 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1124 __IM uint32_t RESERVED1[2]; 1125 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1126 TWI master is not suspended. */ 1127 __IM uint32_t RESERVED2; 1128 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1129 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1130 __IM uint32_t RESERVED3[23]; 1131 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1132 __IM uint32_t RESERVED4; 1133 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1134 __IM uint32_t RESERVED5[2]; 1135 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1136 __IM uint32_t RESERVED6; 1137 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1138 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1139 __IM uint32_t RESERVED7[24]; 1140 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1141 __IM uint32_t RESERVED8[7]; 1142 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1143 __IM uint32_t RESERVED9[8]; 1144 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1145 now suspended. */ 1146 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1147 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1148 __IM uint32_t RESERVED10[2]; 1149 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1150 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1151 byte */ 1152 __IM uint32_t RESERVED11[8]; 1153 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1154 __IM uint32_t RESERVED12[7]; 1155 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1156 __IM uint32_t RESERVED13[8]; 1157 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1158 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1159 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1160 __IM uint32_t RESERVED14[2]; 1161 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1162 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1163 __IM uint32_t RESERVED15[7]; 1164 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1165 __IM uint32_t RESERVED16[63]; 1166 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1167 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1168 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1169 __IM uint32_t RESERVED17[110]; 1170 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1171 __IM uint32_t RESERVED18[14]; 1172 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1173 __IM uint32_t RESERVED19; 1174 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1175 __IM uint32_t RESERVED20[5]; 1176 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1177 source selected. */ 1178 __IM uint32_t RESERVED21[3]; 1179 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1180 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1181 __IM uint32_t RESERVED22[13]; 1182 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1183 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1184 1185 1186 1187 /* =========================================================================================================================== */ 1188 /* ================ TWIS0_NS ================ */ 1189 /* =========================================================================================================================== */ 1190 1191 1192 /** 1193 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1194 */ 1195 1196 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1197 __IM uint32_t RESERVED[5]; 1198 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1199 __IM uint32_t RESERVED1; 1200 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1201 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1202 __IM uint32_t RESERVED2[3]; 1203 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1204 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1205 __IM uint32_t RESERVED3[23]; 1206 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1207 __IM uint32_t RESERVED4; 1208 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1209 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1210 __IM uint32_t RESERVED5[3]; 1211 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1212 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1213 __IM uint32_t RESERVED6[19]; 1214 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1215 __IM uint32_t RESERVED7[7]; 1216 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1217 __IM uint32_t RESERVED8[9]; 1218 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1219 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1220 __IM uint32_t RESERVED9[4]; 1221 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1222 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1223 __IM uint32_t RESERVED10[6]; 1224 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1225 __IM uint32_t RESERVED11[7]; 1226 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1227 __IM uint32_t RESERVED12[9]; 1228 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1229 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1230 __IM uint32_t RESERVED13[4]; 1231 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1232 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1233 __IM uint32_t RESERVED14[5]; 1234 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1235 __IM uint32_t RESERVED15[63]; 1236 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1237 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1238 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1239 __IM uint32_t RESERVED16[113]; 1240 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1241 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1242 a match */ 1243 __IM uint32_t RESERVED17[10]; 1244 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1245 __IM uint32_t RESERVED18; 1246 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1247 __IM uint32_t RESERVED19[9]; 1248 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1249 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1250 __IM uint32_t RESERVED20[13]; 1251 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1252 __IM uint32_t RESERVED21; 1253 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1254 mechanism */ 1255 __IM uint32_t RESERVED22[10]; 1256 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1257 of an over-read of the transmit buffer. */ 1258 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1259 1260 1261 1262 /* =========================================================================================================================== */ 1263 /* ================ UARTE0_NS ================ */ 1264 /* =========================================================================================================================== */ 1265 1266 1267 /** 1268 * @brief UART with EasyDMA 0 (UARTE0_NS) 1269 */ 1270 1271 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1272 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1273 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1274 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1275 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1276 __IM uint32_t RESERVED[7]; 1277 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1278 __IM uint32_t RESERVED1[20]; 1279 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1280 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1281 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1282 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1283 __IM uint32_t RESERVED2[7]; 1284 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1285 __IM uint32_t RESERVED3[20]; 1286 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1287 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1288 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1289 transferred to Data RAM) */ 1290 __IM uint32_t RESERVED4; 1291 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1292 __IM uint32_t RESERVED5[2]; 1293 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1294 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1295 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1296 __IM uint32_t RESERVED6[7]; 1297 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1298 __IM uint32_t RESERVED7; 1299 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1300 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1301 __IM uint32_t RESERVED8; 1302 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1303 __IM uint32_t RESERVED9[9]; 1304 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1305 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1306 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1307 __IM uint32_t RESERVED10; 1308 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1309 __IM uint32_t RESERVED11[2]; 1310 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1311 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1312 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1313 __IM uint32_t RESERVED12[7]; 1314 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1315 __IM uint32_t RESERVED13; 1316 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1317 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1318 __IM uint32_t RESERVED14; 1319 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1320 __IM uint32_t RESERVED15[9]; 1321 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1322 __IM uint32_t RESERVED16[63]; 1323 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1324 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1325 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1326 __IM uint32_t RESERVED17[93]; 1327 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1328 to clear. */ 1329 __IM uint32_t RESERVED18[31]; 1330 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1331 __IM uint32_t RESERVED19; 1332 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1333 __IM uint32_t RESERVED20[3]; 1334 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1335 selected. */ 1336 __IM uint32_t RESERVED21[3]; 1337 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1338 __IM uint32_t RESERVED22; 1339 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1340 __IM uint32_t RESERVED23[7]; 1341 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1342 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1343 1344 1345 1346 /* =========================================================================================================================== */ 1347 /* ================ GPIOTE0_S ================ */ 1348 /* =========================================================================================================================== */ 1349 1350 1351 /** 1352 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1353 */ 1354 1355 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1356 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1357 specified in CONFIG[n].PSEL. Action on pin 1358 is configured in CONFIG[n].POLARITY. */ 1359 __IM uint32_t RESERVED[4]; 1360 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1361 specified in CONFIG[n].PSEL. Action on pin 1362 is to set it high. */ 1363 __IM uint32_t RESERVED1[4]; 1364 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1365 specified in CONFIG[n].PSEL. Action on pin 1366 is to set it low. */ 1367 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1368 for task OUT[n] */ 1369 __IM uint32_t RESERVED2[4]; 1370 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1371 for task SET[n] */ 1372 __IM uint32_t RESERVED3[4]; 1373 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1374 for task CLR[n] */ 1375 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1376 pin specified in CONFIG[n].PSEL */ 1377 __IM uint32_t RESERVED4[23]; 1378 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1379 with SENSE mechanism enabled */ 1380 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1381 for event IN[n] */ 1382 __IM uint32_t RESERVED5[23]; 1383 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1384 __IM uint32_t RESERVED6[65]; 1385 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1386 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1387 __IM uint32_t RESERVED7[129]; 1388 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1389 SET[n], and CLR[n] tasks and IN[n] event */ 1390 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1391 1392 1393 1394 /* =========================================================================================================================== */ 1395 /* ================ SAADC_NS ================ */ 1396 /* =========================================================================================================================== */ 1397 1398 1399 /** 1400 * @brief Analog to Digital Converter 0 (SAADC_NS) 1401 */ 1402 1403 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1404 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1405 RAM */ 1406 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1407 are sampled */ 1408 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1409 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1410 __IM uint32_t RESERVED[28]; 1411 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1412 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1413 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1414 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1415 __IM uint32_t RESERVED1[28]; 1416 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1417 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1418 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1419 on the mode, multiple conversions might 1420 be needed for a result to be transferred 1421 to RAM. */ 1422 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1423 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1424 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1425 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1426 __IM uint32_t RESERVED2[10]; 1427 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1428 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1429 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 1430 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 1431 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 1432 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 1433 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 1434 __IM uint32_t RESERVED3[74]; 1435 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1436 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1437 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1438 __IM uint32_t RESERVED4[61]; 1439 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1440 __IM uint32_t RESERVED5[63]; 1441 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1442 __IM uint32_t RESERVED6[3]; 1443 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1444 __IM uint32_t RESERVED7[24]; 1445 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1446 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1447 not be combined with SCAN. The RESOLUTION 1448 is applied before averaging, thus for high 1449 OVERSAMPLE a higher RESOLUTION should be 1450 used. */ 1451 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1452 __IM uint32_t RESERVED8[12]; 1453 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1454 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1455 1456 1457 1458 /* =========================================================================================================================== */ 1459 /* ================ TIMER0_NS ================ */ 1460 /* =========================================================================================================================== */ 1461 1462 1463 /** 1464 * @brief Timer/Counter 0 (TIMER0_NS) 1465 */ 1466 1467 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 1468 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1469 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1470 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1471 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1472 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1473 __IM uint32_t RESERVED[11]; 1474 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1475 CC[n] register */ 1476 __IM uint32_t RESERVED1[10]; 1477 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1478 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1479 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1480 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1481 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1482 for task SHUTDOWN */ 1483 __IM uint32_t RESERVED2[11]; 1484 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1485 for task CAPTURE[n] */ 1486 __IM uint32_t RESERVED3[26]; 1487 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1488 match */ 1489 __IM uint32_t RESERVED4[26]; 1490 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1491 for event COMPARE[n] */ 1492 __IM uint32_t RESERVED5[10]; 1493 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1494 __IM uint32_t RESERVED6[64]; 1495 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1496 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1497 __IM uint32_t RESERVED7[126]; 1498 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1499 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1500 __IM uint32_t RESERVED8; 1501 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1502 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation 1503 for Capture/Compare channel n */ 1504 __IM uint32_t RESERVED9[5]; 1505 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1506 n */ 1507 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1508 1509 1510 1511 /* =========================================================================================================================== */ 1512 /* ================ RTC0_NS ================ */ 1513 /* =========================================================================================================================== */ 1514 1515 1516 /** 1517 * @brief Real-time counter 0 (RTC0_NS) 1518 */ 1519 1520 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 1521 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1522 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1523 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1524 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1525 __IM uint32_t RESERVED[28]; 1526 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1527 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1528 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1529 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1530 __IM uint32_t RESERVED1[28]; 1531 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1532 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1533 __IM uint32_t RESERVED2[14]; 1534 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1535 match */ 1536 __IM uint32_t RESERVED3[12]; 1537 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1538 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1539 __IM uint32_t RESERVED4[14]; 1540 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1541 for event COMPARE[n] */ 1542 __IM uint32_t RESERVED5[77]; 1543 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1544 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1545 __IM uint32_t RESERVED6[13]; 1546 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1547 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1548 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1549 __IM uint32_t RESERVED7[110]; 1550 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1551 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1552 Must be written when RTC is stopped. */ 1553 __IM uint32_t RESERVED8[13]; 1554 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1555 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1556 1557 1558 1559 /* =========================================================================================================================== */ 1560 /* ================ DPPIC_NS ================ */ 1561 /* =========================================================================================================================== */ 1562 1563 1564 /** 1565 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 1566 */ 1567 1568 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 1569 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1570 __IM uint32_t RESERVED[20]; 1571 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1572 __IM uint32_t RESERVED1[276]; 1573 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1574 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1575 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1576 __IM uint32_t RESERVED2[189]; 1577 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1578 Writes to this register are ignored if either 1579 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1580 is enabled */ 1581 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1582 1583 1584 1585 /* =========================================================================================================================== */ 1586 /* ================ WDT_NS ================ */ 1587 /* =========================================================================================================================== */ 1588 1589 1590 /** 1591 * @brief Watchdog Timer 0 (WDT_NS) 1592 */ 1593 1594 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 1595 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1596 __IM uint32_t RESERVED[31]; 1597 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1598 __IM uint32_t RESERVED1[31]; 1599 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1600 __IM uint32_t RESERVED2[31]; 1601 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1602 __IM uint32_t RESERVED3[96]; 1603 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1604 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1605 __IM uint32_t RESERVED4[61]; 1606 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1607 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1608 __IM uint32_t RESERVED5[63]; 1609 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1610 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1611 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1612 __IM uint32_t RESERVED6[60]; 1613 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1614 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1615 1616 1617 1618 /* =========================================================================================================================== */ 1619 /* ================ EGU0_NS ================ */ 1620 /* =========================================================================================================================== */ 1621 1622 1623 /** 1624 * @brief Event generator unit 0 (EGU0_NS) 1625 */ 1626 1627 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1628 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1629 the corresponding TRIGGERED[n] event */ 1630 __IM uint32_t RESERVED[16]; 1631 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1632 for task TRIGGER[n] */ 1633 __IM uint32_t RESERVED1[16]; 1634 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1635 by triggering the corresponding TRIGGER[n] 1636 task */ 1637 __IM uint32_t RESERVED2[16]; 1638 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1639 for event TRIGGERED[n] */ 1640 __IM uint32_t RESERVED3[80]; 1641 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1642 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1643 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1644 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1645 1646 1647 1648 /* =========================================================================================================================== */ 1649 /* ================ PWM0_NS ================ */ 1650 /* =========================================================================================================================== */ 1651 1652 1653 /** 1654 * @brief Pulse width modulation unit 0 (PWM0_NS) 1655 */ 1656 1657 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 1658 __IM uint32_t RESERVED; 1659 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1660 the end of current PWM period, and stops 1661 sequence playback */ 1662 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1663 on all enabled channels from sequence n, 1664 and starts playing that sequence at the 1665 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1666 Causes PWM generation to start if not running. */ 1667 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1668 all enabled channels if DECODER.MODE=NextStep. 1669 Does not cause PWM generation to start if 1670 not running. */ 1671 __IM uint32_t RESERVED1[28]; 1672 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1673 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 1674 for task SEQSTART[n] */ 1675 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 1676 __IM uint32_t RESERVED2[28]; 1677 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1678 are no longer generated */ 1679 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1680 on sequence n */ 1681 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1682 sequence n, when last value from RAM has 1683 been applied to wave counter */ 1684 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1685 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1686 of times defined in LOOP.CNT */ 1687 __IM uint32_t RESERVED3[25]; 1688 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1689 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 1690 for event SEQSTARTED[n] */ 1691 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 1692 for event SEQEND[n] */ 1693 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 1694 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 1695 __IM uint32_t RESERVED4[24]; 1696 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1697 __IM uint32_t RESERVED5[63]; 1698 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1699 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1700 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1701 __IM uint32_t RESERVED6[125]; 1702 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1703 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1704 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1705 counts */ 1706 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1707 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1708 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1709 __IM uint32_t RESERVED7[2]; 1710 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1711 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1712 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1713 1714 1715 1716 /* =========================================================================================================================== */ 1717 /* ================ PDM_NS ================ */ 1718 /* =========================================================================================================================== */ 1719 1720 1721 /** 1722 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 1723 */ 1724 1725 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 1726 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1727 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1728 __IM uint32_t RESERVED[30]; 1729 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1730 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1731 __IM uint32_t RESERVED1[30]; 1732 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1733 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1734 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1735 by SAMPLE.MAXCNT (or the last sample after 1736 a STOP task has been received) to Data RAM */ 1737 __IM uint32_t RESERVED2[29]; 1738 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1739 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1740 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 1741 __IM uint32_t RESERVED3[93]; 1742 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1743 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1744 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1745 __IM uint32_t RESERVED4[125]; 1746 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1747 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1748 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1749 signals */ 1750 __IM uint32_t RESERVED5[3]; 1751 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1752 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1753 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 1754 sample rate. Change PDMCLKCTRL accordingly. */ 1755 __IM uint32_t RESERVED6[7]; 1756 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1757 __IM uint32_t RESERVED7[6]; 1758 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1759 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1760 1761 1762 1763 /* =========================================================================================================================== */ 1764 /* ================ I2S_NS ================ */ 1765 /* =========================================================================================================================== */ 1766 1767 1768 /** 1769 * @brief Inter-IC Sound 0 (I2S_NS) 1770 */ 1771 1772 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 1773 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 1774 generator when this is enabled. */ 1775 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 1776 Triggering this task will cause the STOPPED 1777 event to be generated. */ 1778 __IM uint32_t RESERVED[30]; 1779 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1780 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1781 __IM uint32_t RESERVED1[31]; 1782 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 1783 double-buffers. When the I2S module is started 1784 and RX is enabled, this event will be generated 1785 for every RXTXD.MAXCNT words that are received 1786 on the SDIN pin. */ 1787 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 1788 __IM uint32_t RESERVED2[2]; 1789 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 1790 double-buffers. When the I2S module is started 1791 and TX is enabled, this event will be generated 1792 for every RXTXD.MAXCNT words that are sent 1793 on the SDOUT pin. */ 1794 __IM uint32_t RESERVED3[27]; 1795 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 1796 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 1797 __IM uint32_t RESERVED4[2]; 1798 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 1799 __IM uint32_t RESERVED5[90]; 1800 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1801 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1802 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1803 __IM uint32_t RESERVED6[125]; 1804 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 1805 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 1806 __IM uint32_t RESERVED7[3]; 1807 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 1808 __IM uint32_t RESERVED8; 1809 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 1810 __IM uint32_t RESERVED9[3]; 1811 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 1812 __IM uint32_t RESERVED10[3]; 1813 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1814 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 1815 1816 1817 1818 /* =========================================================================================================================== */ 1819 /* ================ IPC_NS ================ */ 1820 /* =========================================================================================================================== */ 1821 1822 1823 /** 1824 * @brief Interprocessor communication 0 (IPC_NS) 1825 */ 1826 1827 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 1828 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 1829 channel enabled in SEND_CNF[n] */ 1830 __IM uint32_t RESERVED[24]; 1831 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1832 for task SEND[n] */ 1833 __IM uint32_t RESERVED1[24]; 1834 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 1835 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 1836 __IM uint32_t RESERVED2[24]; 1837 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1838 for event RECEIVE[n] */ 1839 __IM uint32_t RESERVED3[88]; 1840 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1841 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1842 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1843 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1844 __IM uint32_t RESERVED4[128]; 1845 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 1846 for TASKS_SEND[n] */ 1847 __IM uint32_t RESERVED5[24]; 1848 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1849 for EVENTS_RECEIVE[n] */ 1850 __IM uint32_t RESERVED6[24]; 1851 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 1852 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 1853 1854 1855 1856 /* =========================================================================================================================== */ 1857 /* ================ FPU_NS ================ */ 1858 /* =========================================================================================================================== */ 1859 1860 1861 /** 1862 * @brief FPU 0 (FPU_NS) 1863 */ 1864 1865 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 1866 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1867 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 1868 1869 1870 1871 /* =========================================================================================================================== */ 1872 /* ================ KMU_NS ================ */ 1873 /* =========================================================================================================================== */ 1874 1875 1876 /** 1877 * @brief Key management unit 0 (KMU_NS) 1878 */ 1879 1880 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 1881 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 1882 __IM uint32_t RESERVED[63]; 1883 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 1884 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 1885 for selection */ 1886 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 1887 defined, or error during push operation */ 1888 __IM uint32_t RESERVED1[125]; 1889 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1890 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1891 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1892 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1893 __IM uint32_t RESERVED2[63]; 1894 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 1895 __IM uint32_t RESERVED3[60]; 1896 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 1897 over secure APB when TASKS_PUSH_KEYSLOT 1898 is started */ 1899 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 1900 1901 1902 1903 /* =========================================================================================================================== */ 1904 /* ================ NVMC_NS ================ */ 1905 /* =========================================================================================================================== */ 1906 1907 1908 /** 1909 * @brief Non-volatile memory controller 0 (NVMC_NS) 1910 */ 1911 1912 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1913 __IM uint32_t RESERVED[256]; 1914 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1915 __IM uint32_t RESERVED1; 1916 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1917 __IM uint32_t RESERVED2[62]; 1918 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1919 __IM uint32_t RESERVED3; 1920 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1921 __IM uint32_t RESERVED4[3]; 1922 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1923 __IM uint32_t RESERVED5[8]; 1924 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1925 __IM uint32_t RESERVED6; 1926 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1927 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1928 __IM uint32_t RESERVED7[13]; 1929 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 1930 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 1931 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 1932 1933 1934 1935 /* =========================================================================================================================== */ 1936 /* ================ VMC_NS ================ */ 1937 /* =========================================================================================================================== */ 1938 1939 1940 /** 1941 * @brief Volatile Memory controller 0 (VMC_NS) 1942 */ 1943 1944 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 1945 __IM uint32_t RESERVED[384]; 1946 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 1947 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 1948 1949 1950 1951 /* =========================================================================================================================== */ 1952 /* ================ CC_HOST_RGF_S ================ */ 1953 /* =========================================================================================================================== */ 1954 1955 1956 /** 1957 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S) 1958 */ 1959 1960 typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */ 1961 __IM uint32_t RESERVED[1678]; 1962 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 1963 __IM uint32_t RESERVED1[4]; 1964 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 1965 When this register is set, K_PRTL cannot 1966 be used and a zeroed key will be used instead. 1967 The value of this register is saved in the 1968 CRYPTOCELL AO power domain. */ 1969 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 1970 of this register is saved in the CRYPTOCELL 1971 AO power domain. Reading from this address 1972 returns the K_DR valid status indicating 1973 if K_DR is successfully retained. */ 1974 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 1975 of this register is saved in the CRYPTOCELL 1976 AO power domain. */ 1977 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 1978 of this register is saved in the CRYPTOCELL 1979 AO power domain. */ 1980 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 1981 value of this register is saved in the CRYPTOCELL 1982 AO power domain. */ 1983 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 1984 subsystem */ 1985 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 1986 1987 1988 1989 /* =========================================================================================================================== */ 1990 /* ================ CRYPTOCELL_S ================ */ 1991 /* =========================================================================================================================== */ 1992 1993 1994 /** 1995 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 1996 */ 1997 1998 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 1999 __IM uint32_t RESERVED[320]; 2000 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2001 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2002 2003 2004 2005 /* =========================================================================================================================== */ 2006 /* ================ P0_NS ================ */ 2007 /* =========================================================================================================================== */ 2008 2009 2010 /** 2011 * @brief GPIO Port 0 (P0_NS) 2012 */ 2013 2014 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 2015 __IM uint32_t RESERVED; 2016 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 2017 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 2018 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 2019 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 2020 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 2021 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 2022 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 2023 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 2024 have met the criteria set in the PIN_CNF[n].SENSE 2025 registers */ 2026 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 2027 and LDETECT mode (For non-secure pin only) */ 2028 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 2029 and LDETECT mode (For secure pin only) */ 2030 __IM uint32_t RESERVED1[117]; 2031 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 2032 pins */ 2033 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 2034 2035 2036 /** @} */ /* End of group Device_Peripheral_peripherals */ 2037 2038 2039 /* =========================================================================================================================== */ 2040 /* ================ Device Specific Peripheral Address Map ================ */ 2041 /* =========================================================================================================================== */ 2042 2043 2044 /** @addtogroup Device_Peripheral_peripheralAddr 2045 * @{ 2046 */ 2047 2048 #define NRF_FICR_S_BASE 0x00FF0000UL 2049 #define NRF_UICR_S_BASE 0x00FF8000UL 2050 #define NRF_TAD_S_BASE 0xE0080000UL 2051 #define NRF_SPU_S_BASE 0x50003000UL 2052 #define NRF_REGULATORS_NS_BASE 0x40004000UL 2053 #define NRF_REGULATORS_S_BASE 0x50004000UL 2054 #define NRF_CLOCK_NS_BASE 0x40005000UL 2055 #define NRF_POWER_NS_BASE 0x40005000UL 2056 #define NRF_CLOCK_S_BASE 0x50005000UL 2057 #define NRF_POWER_S_BASE 0x50005000UL 2058 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 2059 #define NRF_SPIM0_NS_BASE 0x40008000UL 2060 #define NRF_SPIS0_NS_BASE 0x40008000UL 2061 #define NRF_TWIM0_NS_BASE 0x40008000UL 2062 #define NRF_TWIS0_NS_BASE 0x40008000UL 2063 #define NRF_UARTE0_NS_BASE 0x40008000UL 2064 #define NRF_SPIM0_S_BASE 0x50008000UL 2065 #define NRF_SPIS0_S_BASE 0x50008000UL 2066 #define NRF_TWIM0_S_BASE 0x50008000UL 2067 #define NRF_TWIS0_S_BASE 0x50008000UL 2068 #define NRF_UARTE0_S_BASE 0x50008000UL 2069 #define NRF_SPIM1_NS_BASE 0x40009000UL 2070 #define NRF_SPIS1_NS_BASE 0x40009000UL 2071 #define NRF_TWIM1_NS_BASE 0x40009000UL 2072 #define NRF_TWIS1_NS_BASE 0x40009000UL 2073 #define NRF_UARTE1_NS_BASE 0x40009000UL 2074 #define NRF_SPIM1_S_BASE 0x50009000UL 2075 #define NRF_SPIS1_S_BASE 0x50009000UL 2076 #define NRF_TWIM1_S_BASE 0x50009000UL 2077 #define NRF_TWIS1_S_BASE 0x50009000UL 2078 #define NRF_UARTE1_S_BASE 0x50009000UL 2079 #define NRF_SPIM2_NS_BASE 0x4000A000UL 2080 #define NRF_SPIS2_NS_BASE 0x4000A000UL 2081 #define NRF_TWIM2_NS_BASE 0x4000A000UL 2082 #define NRF_TWIS2_NS_BASE 0x4000A000UL 2083 #define NRF_UARTE2_NS_BASE 0x4000A000UL 2084 #define NRF_SPIM2_S_BASE 0x5000A000UL 2085 #define NRF_SPIS2_S_BASE 0x5000A000UL 2086 #define NRF_TWIM2_S_BASE 0x5000A000UL 2087 #define NRF_TWIS2_S_BASE 0x5000A000UL 2088 #define NRF_UARTE2_S_BASE 0x5000A000UL 2089 #define NRF_SPIM3_NS_BASE 0x4000B000UL 2090 #define NRF_SPIS3_NS_BASE 0x4000B000UL 2091 #define NRF_TWIM3_NS_BASE 0x4000B000UL 2092 #define NRF_TWIS3_NS_BASE 0x4000B000UL 2093 #define NRF_UARTE3_NS_BASE 0x4000B000UL 2094 #define NRF_SPIM3_S_BASE 0x5000B000UL 2095 #define NRF_SPIS3_S_BASE 0x5000B000UL 2096 #define NRF_TWIM3_S_BASE 0x5000B000UL 2097 #define NRF_TWIS3_S_BASE 0x5000B000UL 2098 #define NRF_UARTE3_S_BASE 0x5000B000UL 2099 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 2100 #define NRF_SAADC_NS_BASE 0x4000E000UL 2101 #define NRF_SAADC_S_BASE 0x5000E000UL 2102 #define NRF_TIMER0_NS_BASE 0x4000F000UL 2103 #define NRF_TIMER0_S_BASE 0x5000F000UL 2104 #define NRF_TIMER1_NS_BASE 0x40010000UL 2105 #define NRF_TIMER1_S_BASE 0x50010000UL 2106 #define NRF_TIMER2_NS_BASE 0x40011000UL 2107 #define NRF_TIMER2_S_BASE 0x50011000UL 2108 #define NRF_RTC0_NS_BASE 0x40014000UL 2109 #define NRF_RTC0_S_BASE 0x50014000UL 2110 #define NRF_RTC1_NS_BASE 0x40015000UL 2111 #define NRF_RTC1_S_BASE 0x50015000UL 2112 #define NRF_DPPIC_NS_BASE 0x40017000UL 2113 #define NRF_DPPIC_S_BASE 0x50017000UL 2114 #define NRF_WDT_NS_BASE 0x40018000UL 2115 #define NRF_WDT_S_BASE 0x50018000UL 2116 #define NRF_EGU0_NS_BASE 0x4001B000UL 2117 #define NRF_EGU0_S_BASE 0x5001B000UL 2118 #define NRF_EGU1_NS_BASE 0x4001C000UL 2119 #define NRF_EGU1_S_BASE 0x5001C000UL 2120 #define NRF_EGU2_NS_BASE 0x4001D000UL 2121 #define NRF_EGU2_S_BASE 0x5001D000UL 2122 #define NRF_EGU3_NS_BASE 0x4001E000UL 2123 #define NRF_EGU3_S_BASE 0x5001E000UL 2124 #define NRF_EGU4_NS_BASE 0x4001F000UL 2125 #define NRF_EGU4_S_BASE 0x5001F000UL 2126 #define NRF_EGU5_NS_BASE 0x40020000UL 2127 #define NRF_EGU5_S_BASE 0x50020000UL 2128 #define NRF_PWM0_NS_BASE 0x40021000UL 2129 #define NRF_PWM0_S_BASE 0x50021000UL 2130 #define NRF_PWM1_NS_BASE 0x40022000UL 2131 #define NRF_PWM1_S_BASE 0x50022000UL 2132 #define NRF_PWM2_NS_BASE 0x40023000UL 2133 #define NRF_PWM2_S_BASE 0x50023000UL 2134 #define NRF_PWM3_NS_BASE 0x40024000UL 2135 #define NRF_PWM3_S_BASE 0x50024000UL 2136 #define NRF_PDM_NS_BASE 0x40026000UL 2137 #define NRF_PDM_S_BASE 0x50026000UL 2138 #define NRF_I2S_NS_BASE 0x40028000UL 2139 #define NRF_I2S_S_BASE 0x50028000UL 2140 #define NRF_IPC_NS_BASE 0x4002A000UL 2141 #define NRF_IPC_S_BASE 0x5002A000UL 2142 #define NRF_FPU_NS_BASE 0x4002C000UL 2143 #define NRF_FPU_S_BASE 0x5002C000UL 2144 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 2145 #define NRF_KMU_NS_BASE 0x40039000UL 2146 #define NRF_NVMC_NS_BASE 0x40039000UL 2147 #define NRF_KMU_S_BASE 0x50039000UL 2148 #define NRF_NVMC_S_BASE 0x50039000UL 2149 #define NRF_VMC_NS_BASE 0x4003A000UL 2150 #define NRF_VMC_S_BASE 0x5003A000UL 2151 #define NRF_CC_HOST_RGF_S_BASE 0x50840000UL 2152 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 2153 #define NRF_P0_NS_BASE 0x40842500UL 2154 #define NRF_P0_S_BASE 0x50842500UL 2155 2156 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2157 2158 2159 /* =========================================================================================================================== */ 2160 /* ================ Peripheral declaration ================ */ 2161 /* =========================================================================================================================== */ 2162 2163 2164 /** @addtogroup Device_Peripheral_declaration 2165 * @{ 2166 */ 2167 2168 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 2169 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 2170 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 2171 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 2172 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 2173 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 2174 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 2175 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 2176 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 2177 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 2178 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 2179 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2180 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2181 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2182 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2183 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2184 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 2185 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 2186 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 2187 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 2188 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 2189 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 2190 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 2191 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 2192 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 2193 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 2194 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 2195 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 2196 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 2197 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 2198 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 2199 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 2200 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 2201 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 2202 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 2203 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 2204 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 2205 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 2206 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 2207 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 2208 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 2209 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 2210 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 2211 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 2212 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 2213 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 2214 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 2215 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 2216 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 2217 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 2218 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 2219 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 2220 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 2221 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 2222 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2223 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 2224 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2225 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 2226 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2227 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 2228 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2229 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 2230 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2231 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 2232 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2233 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 2234 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2235 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 2236 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2237 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 2238 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 2239 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 2240 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 2241 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 2242 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 2243 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 2244 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 2245 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 2246 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 2247 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 2248 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 2249 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 2250 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 2251 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 2252 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 2253 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 2254 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 2255 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 2256 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 2257 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 2258 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 2259 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 2260 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2261 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 2262 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 2263 #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 2264 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 2265 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 2266 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2267 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 2268 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 2269 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2270 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 2271 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 2272 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 2273 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2274 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 2275 2276 /** @} */ /* End of group Device_Peripheral_declaration */ 2277 2278 2279 #ifdef __cplusplus 2280 } 2281 #endif 2282 2283 #endif /* NRF9160_H */ 2284 2285 2286 /** @} */ /* End of group nrf9160 */ 2287 2288 /** @} */ /* End of group Nordic Semiconductor */ 2289
