1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf9120.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:17 37 * from File 'nrf9120.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf9120 49 * @{ 50 */ 51 52 53 #ifndef NRF9120_H 54 #define NRF9120_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ========================================== nrf9120 Specific Interrupt Numbers =========================================== */ 87 SPU_IRQn = 3, /*!< 3 SPU */ 88 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 89 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ 91 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ 92 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ 93 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 94 SAADC_IRQn = 14, /*!< 14 SAADC */ 95 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 96 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 97 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 98 RTC0_IRQn = 20, /*!< 20 RTC0 */ 99 RTC1_IRQn = 21, /*!< 21 RTC1 */ 100 WDT_IRQn = 24, /*!< 24 WDT */ 101 EGU0_IRQn = 27, /*!< 27 EGU0 */ 102 EGU1_IRQn = 28, /*!< 28 EGU1 */ 103 EGU2_IRQn = 29, /*!< 29 EGU2 */ 104 EGU3_IRQn = 30, /*!< 30 EGU3 */ 105 EGU4_IRQn = 31, /*!< 31 EGU4 */ 106 EGU5_IRQn = 32, /*!< 32 EGU5 */ 107 PWM0_IRQn = 33, /*!< 33 PWM0 */ 108 PWM1_IRQn = 34, /*!< 34 PWM1 */ 109 PWM2_IRQn = 35, /*!< 35 PWM2 */ 110 PWM3_IRQn = 36, /*!< 36 PWM3 */ 111 PDM_IRQn = 38, /*!< 38 PDM */ 112 I2S_IRQn = 40, /*!< 40 I2S */ 113 IPC_IRQn = 42, /*!< 42 IPC */ 114 FPU_IRQn = 44, /*!< 44 FPU */ 115 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 116 KMU_IRQn = 57, /*!< 57 KMU */ 117 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 118 } IRQn_Type; 119 120 121 122 /* =========================================================================================================================== */ 123 /* ================ Processor and Core Peripheral Section ================ */ 124 /* =========================================================================================================================== */ 125 126 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 127 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 128 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 129 #define __DSP_PRESENT 1 /*!< DSP present or not */ 130 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 131 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 132 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133 #define __MPU_PRESENT 1 /*!< MPU present */ 134 #define __FPU_PRESENT 1 /*!< FPU present */ 135 #define __FPU_DP 0 /*!< Double Precision FPU */ 136 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 137 138 139 /** @} */ /* End of group Configuration_of_CMSIS */ 140 141 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 142 #include "system_nrf9120.h" /*!< nrf9120 System */ 143 144 #ifndef __IM /*!< Fallback for older CMSIS versions */ 145 #define __IM __I 146 #endif 147 #ifndef __OM /*!< Fallback for older CMSIS versions */ 148 #define __OM __O 149 #endif 150 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151 #define __IOM __IO 152 #endif 153 154 155 /* ======================================== Start of section using anonymous unions ======================================== */ 156 #if defined (__CC_ARM) 157 #pragma push 158 #pragma anon_unions 159 #elif defined (__ICCARM__) 160 #pragma language=extended 161 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 162 #pragma clang diagnostic push 163 #pragma clang diagnostic ignored "-Wc11-extensions" 164 #pragma clang diagnostic ignored "-Wreserved-id-macro" 165 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 166 #pragma clang diagnostic ignored "-Wnested-anon-types" 167 #elif defined (__GNUC__) 168 /* anonymous unions are enabled by default */ 169 #elif defined (__TMS470__) 170 /* anonymous unions are enabled by default */ 171 #elif defined (__TASKING__) 172 #pragma warning 586 173 #elif defined (__CSMC__) 174 /* anonymous unions are enabled by default */ 175 #else 176 #warning Not supported compiler type 177 #endif 178 179 180 /* =========================================================================================================================== */ 181 /* ================ Device Specific Cluster Section ================ */ 182 /* =========================================================================================================================== */ 183 184 185 /** @addtogroup Device_Peripheral_clusters 186 * @{ 187 */ 188 189 190 /** 191 * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info) 192 */ 193 typedef struct { 194 __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ 195 __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision, 196 encoded in ASCII, ex B0A or B1A */ 197 __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded 198 in ASCII, ex SIAA, SIBA or SICA */ 199 } FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */ 200 201 202 /** 203 * @brief FICR_INFO [INFO] (Device info) 204 */ 205 typedef struct { 206 __IM uint32_t RESERVED; 207 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 208 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 209 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 210 configuration */ 211 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 212 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 213 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 214 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 215 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 216 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 217 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 218 219 220 /** 221 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 222 */ 223 typedef struct { 224 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 225 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 226 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 227 228 229 /** 230 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 231 */ 232 typedef struct { 233 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 234 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 235 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 236 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 237 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 238 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 239 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 240 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 241 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 242 243 244 /** 245 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 246 */ 247 typedef struct { 248 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 249 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 250 ) will be pushed by KMU. Note that this 251 address must match that of a peripherals 252 APB mapped write-only key registers, else 253 the KMU can push this key value into an 254 address range which the CPU can potentially 255 read. */ 256 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 257 key slot. Bits 0-15 and 16-31 can only be 258 written when equal to 0xFFFF. */ 259 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 260 261 262 /** 263 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 264 */ 265 typedef struct { 266 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 267 of value assigned to KMU key slot. */ 268 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 269 270 271 /** 272 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 273 */ 274 typedef struct { 275 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 276 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 277 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 278 279 280 /** 281 * @brief TAD_PSEL [PSEL] (Unspecified) 282 */ 283 typedef struct { 284 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 285 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 286 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 287 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 288 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 289 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 290 291 292 /** 293 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 294 */ 295 typedef struct { 296 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 297 from the external domain n List capabilities 298 of the external domain n */ 299 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 300 301 302 /** 303 * @brief SPU_DPPI [DPPI] (Unspecified) 304 */ 305 typedef struct { 306 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 307 non-secure attribute for the DPPI channels. */ 308 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 309 of the corresponding PERM register */ 310 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 311 312 313 /** 314 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 315 */ 316 typedef struct { 317 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 318 non-secure attribute for pins 0 to 31 of 319 port n. */ 320 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 321 of the corresponding PERM register */ 322 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 323 324 325 /** 326 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 327 */ 328 typedef struct { 329 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 330 can contain the non-secure callable (NSC) 331 region n */ 332 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 333 callable (NSC) region n */ 334 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 335 336 337 /** 338 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 339 */ 340 typedef struct { 341 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 342 can contain the non-secure callable (NSC) 343 region n */ 344 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 345 callable (NSC) region n */ 346 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 347 348 349 /** 350 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 351 */ 352 typedef struct { 353 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 354 region n */ 355 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 356 357 358 /** 359 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 360 */ 361 typedef struct { 362 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 363 region n */ 364 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 365 366 367 /** 368 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 369 */ 370 typedef struct { 371 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 372 permissions for the peripheral with ID n */ 373 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 374 375 376 /** 377 * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) 378 */ 379 typedef struct { 380 __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ 381 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ 382 } POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ 383 384 385 /** 386 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 387 */ 388 typedef struct { 389 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 390 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 391 data sent from the debugger to the CPU has 392 been read. */ 393 __IM uint32_t RESERVED[30]; 394 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 395 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 396 the data sent from the CPU to the debugger 397 has been read. */ 398 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 399 400 401 /** 402 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 403 */ 404 typedef struct { 405 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 406 register from being written until next reset. */ 407 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 408 and performs an ERASEALL operation. */ 409 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 410 411 412 /** 413 * @brief SPIM_PSEL [PSEL] (Unspecified) 414 */ 415 typedef struct { 416 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 417 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 418 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 419 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 420 421 422 /** 423 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 424 */ 425 typedef struct { 426 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 427 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 428 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 429 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 430 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 431 432 433 /** 434 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 435 */ 436 typedef struct { 437 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 438 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 439 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 440 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 441 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 442 443 444 /** 445 * @brief SPIS_PSEL [PSEL] (Unspecified) 446 */ 447 typedef struct { 448 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 449 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 450 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 451 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 452 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 453 454 455 /** 456 * @brief SPIS_RXD [RXD] (Unspecified) 457 */ 458 typedef struct { 459 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 460 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 461 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 462 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 463 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 464 465 466 /** 467 * @brief SPIS_TXD [TXD] (Unspecified) 468 */ 469 typedef struct { 470 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 471 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 472 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 473 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 474 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 475 476 477 /** 478 * @brief TWIM_PSEL [PSEL] (Unspecified) 479 */ 480 typedef struct { 481 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 482 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 483 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 484 485 486 /** 487 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 488 */ 489 typedef struct { 490 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 491 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 492 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 493 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 494 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 495 496 497 /** 498 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 499 */ 500 typedef struct { 501 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 502 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 503 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 504 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 505 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 506 507 508 /** 509 * @brief TWIS_PSEL [PSEL] (Unspecified) 510 */ 511 typedef struct { 512 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 513 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 514 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 515 516 517 /** 518 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 519 */ 520 typedef struct { 521 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 522 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 523 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 524 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 525 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 526 527 528 /** 529 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 530 */ 531 typedef struct { 532 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 533 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 534 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 535 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 536 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 537 538 539 /** 540 * @brief UARTE_PSEL [PSEL] (Unspecified) 541 */ 542 typedef struct { 543 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 544 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 545 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 546 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 547 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 548 549 550 /** 551 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 552 */ 553 typedef struct { 554 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 555 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 556 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 557 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 558 559 560 /** 561 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 562 */ 563 typedef struct { 564 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 565 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 566 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 567 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 568 569 570 /** 571 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 572 */ 573 typedef struct { 574 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 575 above CH[n].LIMIT.HIGH */ 576 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 577 below CH[n].LIMIT.LOW */ 578 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 579 580 581 /** 582 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 583 */ 584 typedef struct { 585 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 586 event CH[n].LIMITH */ 587 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 588 event CH[n].LIMITL */ 589 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 590 591 592 /** 593 * @brief SAADC_CH [CH] (Unspecified) 594 */ 595 typedef struct { 596 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 597 for CH[n] */ 598 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 599 for CH[n] */ 600 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 601 CH[n] */ 602 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 603 monitoring a channel */ 604 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 605 606 607 /** 608 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 609 */ 610 typedef struct { 611 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 612 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 613 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 614 START */ 615 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 616 617 618 /** 619 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 620 */ 621 typedef struct { 622 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 623 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 624 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 625 626 627 /** 628 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 629 */ 630 typedef struct { 631 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 632 for task CHG[n].EN */ 633 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 634 for task CHG[n].DIS */ 635 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 636 637 638 /** 639 * @brief PWM_SEQ [SEQ] (Unspecified) 640 */ 641 typedef struct { 642 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 643 of this sequence */ 644 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 645 in this sequence */ 646 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 647 periods between samples loaded into compare 648 register */ 649 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 650 __IM uint32_t RESERVED[4]; 651 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 652 653 654 /** 655 * @brief PWM_PSEL [PSEL] (Unspecified) 656 */ 657 typedef struct { 658 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 659 PWM channel n */ 660 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 661 662 663 /** 664 * @brief PDM_PSEL [PSEL] (Unspecified) 665 */ 666 typedef struct { 667 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 668 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 669 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 670 671 672 /** 673 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 674 */ 675 typedef struct { 676 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 677 EasyDMA */ 678 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 679 mode */ 680 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 681 682 683 /** 684 * @brief I2S_CONFIG [CONFIG] (Unspecified) 685 */ 686 typedef struct { 687 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 688 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 689 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 690 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 691 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 692 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 693 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 694 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 695 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 696 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 697 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 698 699 700 /** 701 * @brief I2S_RXD [RXD] (Unspecified) 702 */ 703 typedef struct { 704 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 705 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 706 707 708 /** 709 * @brief I2S_TXD [TXD] (Unspecified) 710 */ 711 typedef struct { 712 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 713 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 714 715 716 /** 717 * @brief I2S_RXTXD [RXTXD] (Unspecified) 718 */ 719 typedef struct { 720 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 721 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 722 723 724 /** 725 * @brief I2S_PSEL [PSEL] (Unspecified) 726 */ 727 typedef struct { 728 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 729 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 730 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 731 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 732 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 733 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 734 735 736 /** 737 * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) 738 */ 739 typedef struct { 740 union { 741 __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */ 742 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force SECUREAPPROTECT mechanism */ 743 }; 744 } APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 4 (0x4) */ 745 746 747 /** 748 * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified) 749 */ 750 typedef struct { 751 union { 752 __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */ 753 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force APPROTECT mechanism */ 754 }; 755 } APPROTECT_APPROTECT_Type; /*!< Size = 4 (0x4) */ 756 757 758 /** 759 * @brief VMC_RAM [RAM] (Unspecified) 760 */ 761 typedef struct { 762 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 763 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 764 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 765 register */ 766 __IM uint32_t RESERVED; 767 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 768 769 770 /** @} */ /* End of group Device_Peripheral_clusters */ 771 772 773 /* =========================================================================================================================== */ 774 /* ================ Device Specific Peripheral Section ================ */ 775 /* =========================================================================================================================== */ 776 777 778 /** @addtogroup Device_Peripheral_peripherals 779 * @{ 780 */ 781 782 783 784 /* =========================================================================================================================== */ 785 /* ================ FICR_S ================ */ 786 /* =========================================================================================================================== */ 787 788 789 /** 790 * @brief Factory Information Configuration Registers (FICR_S) 791 */ 792 793 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 794 __IM uint32_t RESERVED[80]; 795 __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device info */ 796 __IM uint32_t RESERVED1[45]; 797 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 798 __IM uint32_t RESERVED2[53]; 799 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 800 __IM uint32_t RESERVED3[64]; 801 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 802 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 803 804 805 806 /* =========================================================================================================================== */ 807 /* ================ UICR_S ================ */ 808 /* =========================================================================================================================== */ 809 810 811 /** 812 * @brief User information configuration registers User information configuration registers (UICR_S) 813 */ 814 815 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 816 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 817 __IM uint32_t RESERVED[4]; 818 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 819 __IM uint32_t RESERVED1; 820 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 821 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 822 __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE 823 for Application NVM in POFWARN condition 824 . */ 825 __IOM uint32_t PMICCONF; /*!< (@ 0x00000028) Polarity of PMIC polarity configuration signals. */ 826 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 827 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 828 __IM uint32_t RESERVED2[53]; 829 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable 830 memory */ 831 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 832 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 833 834 835 836 /* =========================================================================================================================== */ 837 /* ================ TAD_S ================ */ 838 /* =========================================================================================================================== */ 839 840 841 /** 842 * @brief Trace and debug control (TAD_S) 843 */ 844 845 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 846 __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ 847 __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ 848 __IM uint32_t RESERVED[318]; 849 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 850 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 851 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 852 Reset behavior is the same as debug components */ 853 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 854 855 856 857 /* =========================================================================================================================== */ 858 /* ================ SPU_S ================ */ 859 /* =========================================================================================================================== */ 860 861 862 /** 863 * @brief System protection unit (SPU_S) 864 */ 865 866 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 867 __IM uint32_t RESERVED[64]; 868 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 869 RAM memory space */ 870 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 871 flash memory space */ 872 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 873 or several peripherals */ 874 __IM uint32_t RESERVED1[29]; 875 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 876 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 877 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 878 __IM uint32_t RESERVED2[93]; 879 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 880 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 881 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 882 __IM uint32_t RESERVED3[61]; 883 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 884 __IM uint32_t RESERVED4[15]; 885 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 886 __IM uint32_t RESERVED5[15]; 887 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 888 __IM uint32_t RESERVED6[14]; 889 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 890 __IM uint32_t RESERVED7[14]; 891 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 892 __IM uint32_t RESERVED8[12]; 893 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 894 __IM uint32_t RESERVED9[44]; 895 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 896 __IM uint32_t RESERVED10[32]; 897 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 898 __IM uint32_t RESERVED11[32]; 899 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 900 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 901 902 903 904 /* =========================================================================================================================== */ 905 /* ================ REGULATORS_NS ================ */ 906 /* =========================================================================================================================== */ 907 908 909 /** 910 * @brief Voltage regulators control 0 (REGULATORS_NS) 911 */ 912 913 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 914 __IM uint32_t RESERVED[320]; 915 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 916 __IM uint32_t RESERVED1[4]; 917 __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ 918 __IM uint32_t RESERVED2[24]; 919 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator. */ 920 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 921 922 923 924 /* =========================================================================================================================== */ 925 /* ================ CLOCK_NS ================ */ 926 /* =========================================================================================================================== */ 927 928 929 /** 930 * @brief Clock management 0 (CLOCK_NS) 931 */ 932 933 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 934 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ 935 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ 936 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 937 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 938 __IM uint32_t RESERVED[28]; 939 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 940 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 941 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 942 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 943 __IM uint32_t RESERVED1[28]; 944 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 945 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 946 __IM uint32_t RESERVED2[30]; 947 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 948 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 949 __IM uint32_t RESERVED3[94]; 950 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 951 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 952 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 953 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 954 __IM uint32_t RESERVED4[62]; 955 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 956 triggered */ 957 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 958 by triggering HFCLKSTART task and if it 959 has been started (STATE) */ 960 __IM uint32_t RESERVED5; 961 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 962 triggered */ 963 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 964 requested (SRC) when triggering LFCLKSTART 965 task and if the source has been started 966 (STATE) */ 967 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 968 task has been triggered */ 969 __IM uint32_t RESERVED6[62]; 970 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 971 starts a clock source selected with this 972 register. */ 973 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 974 975 976 977 /* =========================================================================================================================== */ 978 /* ================ POWER_NS ================ */ 979 /* =========================================================================================================================== */ 980 981 982 /** 983 * @brief Power control 0 (POWER_NS) 984 */ 985 986 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 987 __IM uint32_t RESERVED[28]; 988 __OM uint32_t TASKS_PWMREQSTART; /*!< (@ 0x00000070) Request forcing PWM mode in external DC/DC voltage 989 regulator. (Drives FPWM_DCDC pin high or 990 low depending on a setting in UICR). */ 991 __OM uint32_t TASKS_PWMREQSTOP; /*!< (@ 0x00000074) Stop requesting forcing PWM mode in external 992 DC/DC voltage regulator */ 993 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 994 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 995 __IM uint32_t RESERVED1[28]; 996 __IOM uint32_t SUBSCRIBE_PWMREQSTART; /*!< (@ 0x000000F0) Subscribe configuration for task PWMREQSTART */ 997 __IOM uint32_t SUBSCRIBE_PWMREQSTOP; /*!< (@ 0x000000F4) Subscribe configuration for task PWMREQSTOP */ 998 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 999 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 1000 __IM uint32_t RESERVED2[2]; 1001 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1002 __IM uint32_t RESERVED3[2]; 1003 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1004 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1005 __IM uint32_t RESERVED4[27]; 1006 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 1007 __IM uint32_t RESERVED5[2]; 1008 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 1009 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 1010 __IM uint32_t RESERVED6[89]; 1011 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1012 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1013 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1014 __IM uint32_t RESERVED7[61]; 1015 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1016 __IM uint32_t RESERVED8[15]; 1017 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 1018 __IM uint32_t RESERVED9[54]; 1019 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 1020 register */ 1021 __IM uint32_t RESERVED10[59]; 1022 __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ 1023 } NRF_POWER_Type; /*!< Size = 1560 (0x618) */ 1024 1025 1026 1027 /* =========================================================================================================================== */ 1028 /* ================ CTRL_AP_PERI_S ================ */ 1029 /* =========================================================================================================================== */ 1030 1031 1032 /** 1033 * @brief Control access port (CTRL_AP_PERI_S) 1034 */ 1035 1036 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 1037 __IM uint32_t RESERVED[256]; 1038 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 1039 __IM uint32_t RESERVED1[30]; 1040 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 1041 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 1042 1043 1044 1045 /* =========================================================================================================================== */ 1046 /* ================ SPIM0_NS ================ */ 1047 /* =========================================================================================================================== */ 1048 1049 1050 /** 1051 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 1052 */ 1053 1054 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1055 __IM uint32_t RESERVED[4]; 1056 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1057 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1058 __IM uint32_t RESERVED1; 1059 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1060 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1061 __IM uint32_t RESERVED2[27]; 1062 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1063 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1064 __IM uint32_t RESERVED3; 1065 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1066 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1067 __IM uint32_t RESERVED4[24]; 1068 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1069 __IM uint32_t RESERVED5[2]; 1070 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1071 __IM uint32_t RESERVED6; 1072 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1073 __IM uint32_t RESERVED7; 1074 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1075 __IM uint32_t RESERVED8[10]; 1076 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1077 __IM uint32_t RESERVED9[13]; 1078 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1079 __IM uint32_t RESERVED10[2]; 1080 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1081 __IM uint32_t RESERVED11; 1082 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1083 __IM uint32_t RESERVED12; 1084 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1085 __IM uint32_t RESERVED13[10]; 1086 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1087 __IM uint32_t RESERVED14[12]; 1088 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1089 __IM uint32_t RESERVED15[64]; 1090 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1091 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1092 __IM uint32_t RESERVED16[125]; 1093 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1094 __IM uint32_t RESERVED17; 1095 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1096 __IM uint32_t RESERVED18[4]; 1097 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1098 source selected. */ 1099 __IM uint32_t RESERVED19[3]; 1100 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1101 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1102 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1103 __IM uint32_t RESERVED20[26]; 1104 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1105 case an over-read of the TXD buffer. */ 1106 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1107 1108 1109 1110 /* =========================================================================================================================== */ 1111 /* ================ SPIS0_NS ================ */ 1112 /* =========================================================================================================================== */ 1113 1114 1115 /** 1116 * @brief SPI Slave 0 (SPIS0_NS) 1117 */ 1118 1119 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1120 __IM uint32_t RESERVED[9]; 1121 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1122 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1123 to acquire it */ 1124 __IM uint32_t RESERVED1[30]; 1125 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1126 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1127 __IM uint32_t RESERVED2[22]; 1128 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1129 __IM uint32_t RESERVED3[2]; 1130 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1131 __IM uint32_t RESERVED4[5]; 1132 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1133 __IM uint32_t RESERVED5[22]; 1134 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1135 __IM uint32_t RESERVED6[2]; 1136 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1137 __IM uint32_t RESERVED7[5]; 1138 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1139 __IM uint32_t RESERVED8[21]; 1140 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1141 __IM uint32_t RESERVED9[64]; 1142 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1143 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1144 __IM uint32_t RESERVED10[61]; 1145 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1146 __IM uint32_t RESERVED11[15]; 1147 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1148 __IM uint32_t RESERVED12[47]; 1149 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1150 __IM uint32_t RESERVED13; 1151 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1152 __IM uint32_t RESERVED14[7]; 1153 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1154 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1155 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1156 __IM uint32_t RESERVED15; 1157 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1158 of an ignored transaction. */ 1159 __IM uint32_t RESERVED16[24]; 1160 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1161 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1162 1163 1164 1165 /* =========================================================================================================================== */ 1166 /* ================ TWIM0_NS ================ */ 1167 /* =========================================================================================================================== */ 1168 1169 1170 /** 1171 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1172 */ 1173 1174 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1175 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1176 __IM uint32_t RESERVED; 1177 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1178 __IM uint32_t RESERVED1[2]; 1179 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1180 TWI master is not suspended. */ 1181 __IM uint32_t RESERVED2; 1182 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1183 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1184 __IM uint32_t RESERVED3[23]; 1185 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1186 __IM uint32_t RESERVED4; 1187 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1188 __IM uint32_t RESERVED5[2]; 1189 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1190 __IM uint32_t RESERVED6; 1191 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1192 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1193 __IM uint32_t RESERVED7[24]; 1194 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1195 __IM uint32_t RESERVED8[7]; 1196 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1197 __IM uint32_t RESERVED9[8]; 1198 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1199 now suspended. */ 1200 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1201 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1202 __IM uint32_t RESERVED10[2]; 1203 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1204 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1205 byte */ 1206 __IM uint32_t RESERVED11[8]; 1207 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1208 __IM uint32_t RESERVED12[7]; 1209 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1210 __IM uint32_t RESERVED13[8]; 1211 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1212 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1213 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1214 __IM uint32_t RESERVED14[2]; 1215 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1216 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1217 __IM uint32_t RESERVED15[7]; 1218 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1219 __IM uint32_t RESERVED16[63]; 1220 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1221 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1222 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1223 __IM uint32_t RESERVED17[110]; 1224 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1225 __IM uint32_t RESERVED18[14]; 1226 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1227 __IM uint32_t RESERVED19; 1228 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1229 __IM uint32_t RESERVED20[5]; 1230 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1231 source selected. */ 1232 __IM uint32_t RESERVED21[3]; 1233 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1234 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1235 __IM uint32_t RESERVED22[13]; 1236 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1237 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1238 1239 1240 1241 /* =========================================================================================================================== */ 1242 /* ================ TWIS0_NS ================ */ 1243 /* =========================================================================================================================== */ 1244 1245 1246 /** 1247 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1248 */ 1249 1250 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1251 __IM uint32_t RESERVED[5]; 1252 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1253 __IM uint32_t RESERVED1; 1254 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1255 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1256 __IM uint32_t RESERVED2[3]; 1257 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1258 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1259 __IM uint32_t RESERVED3[23]; 1260 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1261 __IM uint32_t RESERVED4; 1262 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1263 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1264 __IM uint32_t RESERVED5[3]; 1265 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1266 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1267 __IM uint32_t RESERVED6[19]; 1268 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1269 __IM uint32_t RESERVED7[7]; 1270 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1271 __IM uint32_t RESERVED8[9]; 1272 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1273 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1274 __IM uint32_t RESERVED9[4]; 1275 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1276 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1277 __IM uint32_t RESERVED10[6]; 1278 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1279 __IM uint32_t RESERVED11[7]; 1280 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1281 __IM uint32_t RESERVED12[9]; 1282 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1283 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1284 __IM uint32_t RESERVED13[4]; 1285 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1286 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1287 __IM uint32_t RESERVED14[5]; 1288 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1289 __IM uint32_t RESERVED15[63]; 1290 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1291 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1292 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1293 __IM uint32_t RESERVED16[113]; 1294 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1295 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1296 a match */ 1297 __IM uint32_t RESERVED17[10]; 1298 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1299 __IM uint32_t RESERVED18; 1300 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1301 __IM uint32_t RESERVED19[9]; 1302 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1303 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1304 __IM uint32_t RESERVED20[13]; 1305 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1306 __IM uint32_t RESERVED21; 1307 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1308 mechanism */ 1309 __IM uint32_t RESERVED22[10]; 1310 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1311 of an over-read of the transmit buffer. */ 1312 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1313 1314 1315 1316 /* =========================================================================================================================== */ 1317 /* ================ UARTE0_NS ================ */ 1318 /* =========================================================================================================================== */ 1319 1320 1321 /** 1322 * @brief UART with EasyDMA 0 (UARTE0_NS) 1323 */ 1324 1325 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1326 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1327 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1328 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1329 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1330 __IM uint32_t RESERVED[7]; 1331 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1332 __IM uint32_t RESERVED1[20]; 1333 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1334 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1335 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1336 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1337 __IM uint32_t RESERVED2[7]; 1338 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1339 __IM uint32_t RESERVED3[20]; 1340 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1341 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1342 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1343 transferred to Data RAM) */ 1344 __IM uint32_t RESERVED4; 1345 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1346 __IM uint32_t RESERVED5[2]; 1347 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1348 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1349 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1350 __IM uint32_t RESERVED6[7]; 1351 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1352 __IM uint32_t RESERVED7; 1353 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1354 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1355 __IM uint32_t RESERVED8; 1356 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1357 __IM uint32_t RESERVED9[9]; 1358 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1359 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1360 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1361 __IM uint32_t RESERVED10; 1362 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1363 __IM uint32_t RESERVED11[2]; 1364 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1365 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1366 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1367 __IM uint32_t RESERVED12[7]; 1368 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1369 __IM uint32_t RESERVED13; 1370 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1371 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1372 __IM uint32_t RESERVED14; 1373 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1374 __IM uint32_t RESERVED15[9]; 1375 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1376 __IM uint32_t RESERVED16[63]; 1377 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1378 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1379 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1380 __IM uint32_t RESERVED17[93]; 1381 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1382 to clear. */ 1383 __IM uint32_t RESERVED18[31]; 1384 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1385 __IM uint32_t RESERVED19; 1386 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1387 __IM uint32_t RESERVED20[3]; 1388 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1389 selected. */ 1390 __IM uint32_t RESERVED21[3]; 1391 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1392 __IM uint32_t RESERVED22; 1393 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1394 __IM uint32_t RESERVED23[7]; 1395 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1396 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1397 1398 1399 1400 /* =========================================================================================================================== */ 1401 /* ================ GPIOTE0_S ================ */ 1402 /* =========================================================================================================================== */ 1403 1404 1405 /** 1406 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1407 */ 1408 1409 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1410 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1411 specified in CONFIG[n].PSEL. Action on pin 1412 is configured in CONFIG[n].POLARITY. */ 1413 __IM uint32_t RESERVED[4]; 1414 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1415 specified in CONFIG[n].PSEL. Action on pin 1416 is to set it high. */ 1417 __IM uint32_t RESERVED1[4]; 1418 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1419 specified in CONFIG[n].PSEL. Action on pin 1420 is to set it low. */ 1421 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1422 for task OUT[n] */ 1423 __IM uint32_t RESERVED2[4]; 1424 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1425 for task SET[n] */ 1426 __IM uint32_t RESERVED3[4]; 1427 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1428 for task CLR[n] */ 1429 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1430 pin specified in CONFIG[n].PSEL */ 1431 __IM uint32_t RESERVED4[23]; 1432 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1433 with SENSE mechanism enabled */ 1434 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1435 for event IN[n] */ 1436 __IM uint32_t RESERVED5[23]; 1437 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1438 __IM uint32_t RESERVED6[65]; 1439 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1440 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1441 __IM uint32_t RESERVED7[129]; 1442 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1443 SET[n], and CLR[n] tasks and IN[n] event */ 1444 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1445 1446 1447 1448 /* =========================================================================================================================== */ 1449 /* ================ SAADC_NS ================ */ 1450 /* =========================================================================================================================== */ 1451 1452 1453 /** 1454 * @brief Analog to Digital Converter 0 (SAADC_NS) 1455 */ 1456 1457 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1458 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1459 RAM */ 1460 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1461 are sampled */ 1462 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1463 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1464 __IM uint32_t RESERVED[28]; 1465 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1466 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1467 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1468 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1469 __IM uint32_t RESERVED1[28]; 1470 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1471 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1472 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1473 on the mode, multiple conversions might 1474 be needed for a result to be transferred 1475 to RAM. */ 1476 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1477 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1478 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1479 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1480 __IM uint32_t RESERVED2[10]; 1481 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1482 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1483 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 1484 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 1485 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 1486 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 1487 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 1488 __IM uint32_t RESERVED3[74]; 1489 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1490 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1491 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1492 __IM uint32_t RESERVED4[61]; 1493 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1494 __IM uint32_t RESERVED5[63]; 1495 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1496 __IM uint32_t RESERVED6[3]; 1497 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1498 __IM uint32_t RESERVED7[24]; 1499 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1500 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1501 not be combined with SCAN. The RESOLUTION 1502 is applied before averaging, thus for high 1503 OVERSAMPLE a higher RESOLUTION should be 1504 used. */ 1505 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1506 __IM uint32_t RESERVED8[12]; 1507 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1508 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1509 1510 1511 1512 /* =========================================================================================================================== */ 1513 /* ================ TIMER0_NS ================ */ 1514 /* =========================================================================================================================== */ 1515 1516 1517 /** 1518 * @brief Timer/Counter 0 (TIMER0_NS) 1519 */ 1520 1521 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 1522 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1523 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1524 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1525 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1526 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1527 __IM uint32_t RESERVED[11]; 1528 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1529 CC[n] register */ 1530 __IM uint32_t RESERVED1[10]; 1531 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1532 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1533 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1534 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1535 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1536 for task SHUTDOWN */ 1537 __IM uint32_t RESERVED2[11]; 1538 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1539 for task CAPTURE[n] */ 1540 __IM uint32_t RESERVED3[26]; 1541 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1542 match */ 1543 __IM uint32_t RESERVED4[26]; 1544 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1545 for event COMPARE[n] */ 1546 __IM uint32_t RESERVED5[10]; 1547 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1548 __IM uint32_t RESERVED6[64]; 1549 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1550 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1551 __IM uint32_t RESERVED7[126]; 1552 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1553 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1554 __IM uint32_t RESERVED8; 1555 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1556 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation 1557 for Capture/Compare channel n */ 1558 __IM uint32_t RESERVED9[5]; 1559 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1560 n */ 1561 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1562 1563 1564 1565 /* =========================================================================================================================== */ 1566 /* ================ RTC0_NS ================ */ 1567 /* =========================================================================================================================== */ 1568 1569 1570 /** 1571 * @brief Real-time counter 0 (RTC0_NS) 1572 */ 1573 1574 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 1575 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1576 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1577 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1578 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1579 __IM uint32_t RESERVED[28]; 1580 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1581 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1582 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1583 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1584 __IM uint32_t RESERVED1[28]; 1585 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1586 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1587 __IM uint32_t RESERVED2[14]; 1588 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1589 match */ 1590 __IM uint32_t RESERVED3[12]; 1591 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1592 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1593 __IM uint32_t RESERVED4[14]; 1594 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1595 for event COMPARE[n] */ 1596 __IM uint32_t RESERVED5[77]; 1597 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1598 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1599 __IM uint32_t RESERVED6[13]; 1600 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1601 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1602 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1603 __IM uint32_t RESERVED7[110]; 1604 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1605 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1606 Must be written when RTC is stopped. */ 1607 __IM uint32_t RESERVED8[13]; 1608 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1609 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1610 1611 1612 1613 /* =========================================================================================================================== */ 1614 /* ================ DPPIC_NS ================ */ 1615 /* =========================================================================================================================== */ 1616 1617 1618 /** 1619 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 1620 */ 1621 1622 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 1623 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1624 __IM uint32_t RESERVED[20]; 1625 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1626 __IM uint32_t RESERVED1[276]; 1627 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1628 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1629 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1630 __IM uint32_t RESERVED2[189]; 1631 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1632 Writes to this register are ignored if either 1633 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1634 is enabled */ 1635 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1636 1637 1638 1639 /* =========================================================================================================================== */ 1640 /* ================ WDT_NS ================ */ 1641 /* =========================================================================================================================== */ 1642 1643 1644 /** 1645 * @brief Watchdog Timer 0 (WDT_NS) 1646 */ 1647 1648 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 1649 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1650 __IM uint32_t RESERVED[31]; 1651 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1652 __IM uint32_t RESERVED1[31]; 1653 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1654 __IM uint32_t RESERVED2[31]; 1655 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1656 __IM uint32_t RESERVED3[96]; 1657 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1658 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1659 __IM uint32_t RESERVED4[61]; 1660 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1661 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1662 __IM uint32_t RESERVED5[63]; 1663 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1664 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1665 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1666 __IM uint32_t RESERVED6[60]; 1667 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1668 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1669 1670 1671 1672 /* =========================================================================================================================== */ 1673 /* ================ EGU0_NS ================ */ 1674 /* =========================================================================================================================== */ 1675 1676 1677 /** 1678 * @brief Event generator unit 0 (EGU0_NS) 1679 */ 1680 1681 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1682 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1683 the corresponding TRIGGERED[n] event */ 1684 __IM uint32_t RESERVED[16]; 1685 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1686 for task TRIGGER[n] */ 1687 __IM uint32_t RESERVED1[16]; 1688 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1689 by triggering the corresponding TRIGGER[n] 1690 task */ 1691 __IM uint32_t RESERVED2[16]; 1692 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1693 for event TRIGGERED[n] */ 1694 __IM uint32_t RESERVED3[80]; 1695 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1696 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1697 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1698 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1699 1700 1701 1702 /* =========================================================================================================================== */ 1703 /* ================ PWM0_NS ================ */ 1704 /* =========================================================================================================================== */ 1705 1706 1707 /** 1708 * @brief Pulse width modulation unit 0 (PWM0_NS) 1709 */ 1710 1711 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 1712 __IM uint32_t RESERVED; 1713 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1714 the end of current PWM period, and stops 1715 sequence playback */ 1716 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1717 on all enabled channels from sequence n, 1718 and starts playing that sequence at the 1719 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1720 Causes PWM generation to start if not running. */ 1721 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1722 all enabled channels if DECODER.MODE=NextStep. 1723 Does not cause PWM generation to start if 1724 not running. */ 1725 __IM uint32_t RESERVED1[28]; 1726 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1727 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 1728 for task SEQSTART[n] */ 1729 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 1730 __IM uint32_t RESERVED2[28]; 1731 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1732 are no longer generated */ 1733 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1734 on sequence n */ 1735 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1736 sequence n, when last value from RAM has 1737 been applied to wave counter */ 1738 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1739 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1740 of times defined in LOOP.CNT */ 1741 __IM uint32_t RESERVED3[25]; 1742 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1743 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 1744 for event SEQSTARTED[n] */ 1745 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 1746 for event SEQEND[n] */ 1747 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 1748 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 1749 __IM uint32_t RESERVED4[24]; 1750 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1751 __IM uint32_t RESERVED5[63]; 1752 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1753 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1754 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1755 __IM uint32_t RESERVED6[125]; 1756 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1757 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1758 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1759 counts */ 1760 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1761 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1762 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1763 __IM uint32_t RESERVED7[2]; 1764 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1765 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1766 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1767 1768 1769 1770 /* =========================================================================================================================== */ 1771 /* ================ PDM_NS ================ */ 1772 /* =========================================================================================================================== */ 1773 1774 1775 /** 1776 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 1777 */ 1778 1779 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 1780 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1781 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1782 __IM uint32_t RESERVED[30]; 1783 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1784 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1785 __IM uint32_t RESERVED1[30]; 1786 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1787 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1788 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1789 by SAMPLE.MAXCNT (or the last sample after 1790 a STOP task has been received) to Data RAM */ 1791 __IM uint32_t RESERVED2[29]; 1792 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1793 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1794 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 1795 __IM uint32_t RESERVED3[93]; 1796 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1797 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1798 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1799 __IM uint32_t RESERVED4[125]; 1800 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1801 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1802 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1803 signals */ 1804 __IM uint32_t RESERVED5[3]; 1805 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1806 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1807 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 1808 sample rate. Change PDMCLKCTRL accordingly. */ 1809 __IM uint32_t RESERVED6[7]; 1810 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1811 __IM uint32_t RESERVED7[6]; 1812 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1813 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1814 1815 1816 1817 /* =========================================================================================================================== */ 1818 /* ================ I2S_NS ================ */ 1819 /* =========================================================================================================================== */ 1820 1821 1822 /** 1823 * @brief Inter-IC Sound 0 (I2S_NS) 1824 */ 1825 1826 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 1827 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 1828 generator when this is enabled. */ 1829 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 1830 Triggering this task will cause the STOPPED 1831 event to be generated. */ 1832 __IM uint32_t RESERVED[30]; 1833 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1834 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1835 __IM uint32_t RESERVED1[31]; 1836 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 1837 double-buffers. When the I2S module is started 1838 and RX is enabled, this event will be generated 1839 for every RXTXD.MAXCNT words that are received 1840 on the SDIN pin. */ 1841 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 1842 __IM uint32_t RESERVED2[2]; 1843 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 1844 double-buffers. When the I2S module is started 1845 and TX is enabled, this event will be generated 1846 for every RXTXD.MAXCNT words that are sent 1847 on the SDOUT pin. */ 1848 __IM uint32_t RESERVED3[27]; 1849 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 1850 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 1851 __IM uint32_t RESERVED4[2]; 1852 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 1853 __IM uint32_t RESERVED5[90]; 1854 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1855 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1856 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1857 __IM uint32_t RESERVED6[125]; 1858 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 1859 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 1860 __IM uint32_t RESERVED7[3]; 1861 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 1862 __IM uint32_t RESERVED8; 1863 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 1864 __IM uint32_t RESERVED9[3]; 1865 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 1866 __IM uint32_t RESERVED10[3]; 1867 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1868 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 1869 1870 1871 1872 /* =========================================================================================================================== */ 1873 /* ================ IPC_NS ================ */ 1874 /* =========================================================================================================================== */ 1875 1876 1877 /** 1878 * @brief Interprocessor communication 0 (IPC_NS) 1879 */ 1880 1881 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 1882 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 1883 channel enabled in SEND_CNF[n] */ 1884 __IM uint32_t RESERVED[24]; 1885 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1886 for task SEND[n] */ 1887 __IM uint32_t RESERVED1[24]; 1888 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 1889 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 1890 __IM uint32_t RESERVED2[24]; 1891 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1892 for event RECEIVE[n] */ 1893 __IM uint32_t RESERVED3[88]; 1894 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1895 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1896 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1897 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1898 __IM uint32_t RESERVED4[128]; 1899 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 1900 for TASKS_SEND[n] */ 1901 __IM uint32_t RESERVED5[24]; 1902 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1903 for EVENTS_RECEIVE[n] */ 1904 __IM uint32_t RESERVED6[24]; 1905 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 1906 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 1907 1908 1909 1910 /* =========================================================================================================================== */ 1911 /* ================ FPU_NS ================ */ 1912 /* =========================================================================================================================== */ 1913 1914 1915 /** 1916 * @brief FPU (FPU_NS) 1917 */ 1918 1919 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 1920 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1921 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 1922 1923 1924 1925 /* =========================================================================================================================== */ 1926 /* ================ APPROTECT_NS ================ */ 1927 /* =========================================================================================================================== */ 1928 1929 1930 /** 1931 * @brief Access Port Protection 0 (APPROTECT_NS) 1932 */ 1933 1934 typedef struct { /*!< (@ 0x40039000) APPROTECT_NS Structure */ 1935 __IM uint32_t RESERVED[896]; 1936 __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified */ 1937 __IM uint32_t RESERVED1[3]; 1938 __IOM APPROTECT_APPROTECT_Type APPROTECT; /*!< (@ 0x00000E10) Unspecified */ 1939 } NRF_APPROTECT_Type; /*!< Size = 3604 (0xe14) */ 1940 1941 1942 1943 /* =========================================================================================================================== */ 1944 /* ================ KMU_NS ================ */ 1945 /* =========================================================================================================================== */ 1946 1947 1948 /** 1949 * @brief Key management unit 0 (KMU_NS) 1950 */ 1951 1952 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 1953 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 1954 __IM uint32_t RESERVED[63]; 1955 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 1956 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 1957 for selection */ 1958 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 1959 defined, or error during push operation */ 1960 __IM uint32_t RESERVED1[125]; 1961 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1962 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1963 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1964 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1965 __IM uint32_t RESERVED2[63]; 1966 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 1967 __IM uint32_t RESERVED3[60]; 1968 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 1969 over secure APB when TASKS_PUSH_KEYSLOT 1970 is started */ 1971 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 1972 1973 1974 1975 /* =========================================================================================================================== */ 1976 /* ================ NVMC_NS ================ */ 1977 /* =========================================================================================================================== */ 1978 1979 1980 /** 1981 * @brief Non-volatile memory controller 0 (NVMC_NS) 1982 */ 1983 1984 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1985 __IM uint32_t RESERVED[256]; 1986 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1987 __IM uint32_t RESERVED1; 1988 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1989 __IM uint32_t RESERVED2[62]; 1990 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1991 __IM uint32_t RESERVED3; 1992 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1993 __IM uint32_t RESERVED4[3]; 1994 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1995 __IM uint32_t RESERVED5[8]; 1996 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1997 __IM uint32_t RESERVED6; 1998 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1999 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2000 __IM uint32_t RESERVED7[13]; 2001 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 2002 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 2003 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 2004 2005 2006 2007 /* =========================================================================================================================== */ 2008 /* ================ VMC_NS ================ */ 2009 /* =========================================================================================================================== */ 2010 2011 2012 /** 2013 * @brief Volatile Memory controller 0 (VMC_NS) 2014 */ 2015 2016 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 2017 __IM uint32_t RESERVED[384]; 2018 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 2019 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 2020 2021 2022 2023 /* =========================================================================================================================== */ 2024 /* ================ CC_HOST_RGF_S ================ */ 2025 /* =========================================================================================================================== */ 2026 2027 2028 /** 2029 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S) 2030 */ 2031 2032 typedef struct { /*!< (@ 0x50840000) CC_HOST_RGF_S Structure */ 2033 __IM uint32_t RESERVED[1678]; 2034 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 2035 __IM uint32_t RESERVED1[4]; 2036 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 2037 When this register is set, K_PRTL cannot 2038 be used and a zeroed key will be used instead. 2039 The value of this register is saved in the 2040 CRYPTOCELL AO power domain. */ 2041 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 2042 of this register is saved in the CRYPTOCELL 2043 AO power domain. Reading from this address 2044 returns the K_DR valid status indicating 2045 if K_DR is successfully retained. */ 2046 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 2047 of this register is saved in the CRYPTOCELL 2048 AO power domain. */ 2049 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 2050 of this register is saved in the CRYPTOCELL 2051 AO power domain. */ 2052 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 2053 value of this register is saved in the CRYPTOCELL 2054 AO power domain. */ 2055 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 2056 subsystem */ 2057 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 2058 2059 2060 2061 /* =========================================================================================================================== */ 2062 /* ================ CRYPTOCELL_S ================ */ 2063 /* =========================================================================================================================== */ 2064 2065 2066 /** 2067 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 2068 */ 2069 2070 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 2071 __IM uint32_t RESERVED[320]; 2072 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2073 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2074 2075 2076 2077 /* =========================================================================================================================== */ 2078 /* ================ P0_NS ================ */ 2079 /* =========================================================================================================================== */ 2080 2081 2082 /** 2083 * @brief GPIO Port 0 (P0_NS) 2084 */ 2085 2086 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 2087 __IM uint32_t RESERVED; 2088 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 2089 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 2090 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 2091 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 2092 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 2093 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 2094 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 2095 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 2096 have met the criteria set in the PIN_CNF[n].SENSE 2097 registers */ 2098 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 2099 and LDETECT mode (For non-secure pin only) */ 2100 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 2101 and LDETECT mode (For secure pin only) */ 2102 __IM uint32_t RESERVED1[117]; 2103 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 2104 pins */ 2105 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 2106 2107 2108 /** @} */ /* End of group Device_Peripheral_peripherals */ 2109 2110 2111 /* =========================================================================================================================== */ 2112 /* ================ Device Specific Peripheral Address Map ================ */ 2113 /* =========================================================================================================================== */ 2114 2115 2116 /** @addtogroup Device_Peripheral_peripheralAddr 2117 * @{ 2118 */ 2119 2120 #define NRF_FICR_S_BASE 0x00FF0000UL 2121 #define NRF_UICR_S_BASE 0x00FF8000UL 2122 #define NRF_TAD_S_BASE 0xE0080000UL 2123 #define NRF_SPU_S_BASE 0x50003000UL 2124 #define NRF_REGULATORS_NS_BASE 0x40004000UL 2125 #define NRF_REGULATORS_S_BASE 0x50004000UL 2126 #define NRF_CLOCK_NS_BASE 0x40005000UL 2127 #define NRF_POWER_NS_BASE 0x40005000UL 2128 #define NRF_CLOCK_S_BASE 0x50005000UL 2129 #define NRF_POWER_S_BASE 0x50005000UL 2130 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 2131 #define NRF_SPIM0_NS_BASE 0x40008000UL 2132 #define NRF_SPIS0_NS_BASE 0x40008000UL 2133 #define NRF_TWIM0_NS_BASE 0x40008000UL 2134 #define NRF_TWIS0_NS_BASE 0x40008000UL 2135 #define NRF_UARTE0_NS_BASE 0x40008000UL 2136 #define NRF_SPIM0_S_BASE 0x50008000UL 2137 #define NRF_SPIS0_S_BASE 0x50008000UL 2138 #define NRF_TWIM0_S_BASE 0x50008000UL 2139 #define NRF_TWIS0_S_BASE 0x50008000UL 2140 #define NRF_UARTE0_S_BASE 0x50008000UL 2141 #define NRF_SPIM1_NS_BASE 0x40009000UL 2142 #define NRF_SPIS1_NS_BASE 0x40009000UL 2143 #define NRF_TWIM1_NS_BASE 0x40009000UL 2144 #define NRF_TWIS1_NS_BASE 0x40009000UL 2145 #define NRF_UARTE1_NS_BASE 0x40009000UL 2146 #define NRF_SPIM1_S_BASE 0x50009000UL 2147 #define NRF_SPIS1_S_BASE 0x50009000UL 2148 #define NRF_TWIM1_S_BASE 0x50009000UL 2149 #define NRF_TWIS1_S_BASE 0x50009000UL 2150 #define NRF_UARTE1_S_BASE 0x50009000UL 2151 #define NRF_SPIM2_NS_BASE 0x4000A000UL 2152 #define NRF_SPIS2_NS_BASE 0x4000A000UL 2153 #define NRF_TWIM2_NS_BASE 0x4000A000UL 2154 #define NRF_TWIS2_NS_BASE 0x4000A000UL 2155 #define NRF_UARTE2_NS_BASE 0x4000A000UL 2156 #define NRF_SPIM2_S_BASE 0x5000A000UL 2157 #define NRF_SPIS2_S_BASE 0x5000A000UL 2158 #define NRF_TWIM2_S_BASE 0x5000A000UL 2159 #define NRF_TWIS2_S_BASE 0x5000A000UL 2160 #define NRF_UARTE2_S_BASE 0x5000A000UL 2161 #define NRF_SPIM3_NS_BASE 0x4000B000UL 2162 #define NRF_SPIS3_NS_BASE 0x4000B000UL 2163 #define NRF_TWIM3_NS_BASE 0x4000B000UL 2164 #define NRF_TWIS3_NS_BASE 0x4000B000UL 2165 #define NRF_UARTE3_NS_BASE 0x4000B000UL 2166 #define NRF_SPIM3_S_BASE 0x5000B000UL 2167 #define NRF_SPIS3_S_BASE 0x5000B000UL 2168 #define NRF_TWIM3_S_BASE 0x5000B000UL 2169 #define NRF_TWIS3_S_BASE 0x5000B000UL 2170 #define NRF_UARTE3_S_BASE 0x5000B000UL 2171 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 2172 #define NRF_SAADC_NS_BASE 0x4000E000UL 2173 #define NRF_SAADC_S_BASE 0x5000E000UL 2174 #define NRF_TIMER0_NS_BASE 0x4000F000UL 2175 #define NRF_TIMER0_S_BASE 0x5000F000UL 2176 #define NRF_TIMER1_NS_BASE 0x40010000UL 2177 #define NRF_TIMER1_S_BASE 0x50010000UL 2178 #define NRF_TIMER2_NS_BASE 0x40011000UL 2179 #define NRF_TIMER2_S_BASE 0x50011000UL 2180 #define NRF_RTC0_NS_BASE 0x40014000UL 2181 #define NRF_RTC0_S_BASE 0x50014000UL 2182 #define NRF_RTC1_NS_BASE 0x40015000UL 2183 #define NRF_RTC1_S_BASE 0x50015000UL 2184 #define NRF_DPPIC_NS_BASE 0x40017000UL 2185 #define NRF_DPPIC_S_BASE 0x50017000UL 2186 #define NRF_WDT_NS_BASE 0x40018000UL 2187 #define NRF_WDT_S_BASE 0x50018000UL 2188 #define NRF_EGU0_NS_BASE 0x4001B000UL 2189 #define NRF_EGU0_S_BASE 0x5001B000UL 2190 #define NRF_EGU1_NS_BASE 0x4001C000UL 2191 #define NRF_EGU1_S_BASE 0x5001C000UL 2192 #define NRF_EGU2_NS_BASE 0x4001D000UL 2193 #define NRF_EGU2_S_BASE 0x5001D000UL 2194 #define NRF_EGU3_NS_BASE 0x4001E000UL 2195 #define NRF_EGU3_S_BASE 0x5001E000UL 2196 #define NRF_EGU4_NS_BASE 0x4001F000UL 2197 #define NRF_EGU4_S_BASE 0x5001F000UL 2198 #define NRF_EGU5_NS_BASE 0x40020000UL 2199 #define NRF_EGU5_S_BASE 0x50020000UL 2200 #define NRF_PWM0_NS_BASE 0x40021000UL 2201 #define NRF_PWM0_S_BASE 0x50021000UL 2202 #define NRF_PWM1_NS_BASE 0x40022000UL 2203 #define NRF_PWM1_S_BASE 0x50022000UL 2204 #define NRF_PWM2_NS_BASE 0x40023000UL 2205 #define NRF_PWM2_S_BASE 0x50023000UL 2206 #define NRF_PWM3_NS_BASE 0x40024000UL 2207 #define NRF_PWM3_S_BASE 0x50024000UL 2208 #define NRF_PDM_NS_BASE 0x40026000UL 2209 #define NRF_PDM_S_BASE 0x50026000UL 2210 #define NRF_I2S_NS_BASE 0x40028000UL 2211 #define NRF_I2S_S_BASE 0x50028000UL 2212 #define NRF_IPC_NS_BASE 0x4002A000UL 2213 #define NRF_IPC_S_BASE 0x5002A000UL 2214 #define NRF_FPU_NS_BASE 0x4002C000UL 2215 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 2216 #define NRF_APPROTECT_NS_BASE 0x40039000UL 2217 #define NRF_KMU_NS_BASE 0x40039000UL 2218 #define NRF_NVMC_NS_BASE 0x40039000UL 2219 #define NRF_APPROTECT_S_BASE 0x50039000UL 2220 #define NRF_KMU_S_BASE 0x50039000UL 2221 #define NRF_NVMC_S_BASE 0x50039000UL 2222 #define NRF_VMC_NS_BASE 0x4003A000UL 2223 #define NRF_VMC_S_BASE 0x5003A000UL 2224 #define NRF_CC_HOST_RGF_S_BASE 0x50840000UL 2225 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 2226 #define NRF_P0_NS_BASE 0x40842500UL 2227 #define NRF_P0_S_BASE 0x50842500UL 2228 2229 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2230 2231 2232 /* =========================================================================================================================== */ 2233 /* ================ Peripheral declaration ================ */ 2234 /* =========================================================================================================================== */ 2235 2236 2237 /** @addtogroup Device_Peripheral_declaration 2238 * @{ 2239 */ 2240 2241 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 2242 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 2243 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 2244 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 2245 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 2246 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 2247 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 2248 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 2249 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 2250 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 2251 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 2252 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2253 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2254 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2255 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2256 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2257 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 2258 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 2259 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 2260 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 2261 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 2262 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 2263 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 2264 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 2265 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 2266 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 2267 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 2268 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 2269 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 2270 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 2271 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 2272 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 2273 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 2274 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 2275 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 2276 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 2277 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 2278 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 2279 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 2280 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 2281 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 2282 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 2283 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 2284 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 2285 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 2286 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 2287 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 2288 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 2289 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 2290 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 2291 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 2292 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 2293 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 2294 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 2295 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2296 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 2297 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2298 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 2299 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2300 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 2301 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2302 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 2303 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2304 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 2305 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2306 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 2307 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2308 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 2309 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2310 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 2311 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 2312 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 2313 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 2314 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 2315 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 2316 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 2317 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 2318 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 2319 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 2320 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 2321 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 2322 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 2323 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 2324 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 2325 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 2326 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 2327 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 2328 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 2329 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 2330 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 2331 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 2332 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 2333 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2334 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 2335 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 2336 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 2337 #define NRF_APPROTECT_NS ((NRF_APPROTECT_Type*) NRF_APPROTECT_NS_BASE) 2338 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 2339 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2340 #define NRF_APPROTECT_S ((NRF_APPROTECT_Type*) NRF_APPROTECT_S_BASE) 2341 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 2342 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 2343 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2344 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 2345 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 2346 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 2347 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2348 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 2349 2350 /** @} */ /* End of group Device_Peripheral_declaration */ 2351 2352 2353 /* ========================================= End of section using anonymous unions ========================================= */ 2354 #if defined (__CC_ARM) 2355 #pragma pop 2356 #elif defined (__ICCARM__) 2357 /* leave anonymous unions enabled */ 2358 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2359 #pragma clang diagnostic pop 2360 #elif defined (__GNUC__) 2361 /* anonymous unions are enabled by default */ 2362 #elif defined (__TMS470__) 2363 /* anonymous unions are enabled by default */ 2364 #elif defined (__TASKING__) 2365 #pragma warning restore 2366 #elif defined (__CSMC__) 2367 /* anonymous unions are enabled by default */ 2368 #endif 2369 2370 2371 #ifdef __cplusplus 2372 } 2373 #endif 2374 2375 #endif /* NRF9120_H */ 2376 2377 2378 /** @} */ /* End of group nrf9120 */ 2379 2380 /** @} */ /* End of group Nordic Semiconductor */ 2381
