1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54L15_FLPR_H 36 #define NRF54L15_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 SPU00_IRQn = 64, /*!< 64 SPU00 */ 86 MPC00_IRQn = 65, /*!< 65 MPC00 */ 87 AAR00_CCM00_IRQn = 70, /*!< 70 AAR00_CCM00 */ 88 ECB00_IRQn = 71, /*!< 71 ECB00 */ 89 CRACEN_IRQn = 72, /*!< 72 CRACEN */ 90 SERIAL00_IRQn = 74, /*!< 74 SERIAL00 */ 91 RRAMC_IRQn = 75, /*!< 75 RRAMC */ 92 VPR00_IRQn = 76, /*!< 76 VPR00 */ 93 CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ 94 TIMER00_IRQn = 85, /*!< 85 TIMER00 */ 95 SPU10_IRQn = 128, /*!< 128 SPU10 */ 96 TIMER10_IRQn = 133, /*!< 133 TIMER10 */ 97 RTC10_IRQn = 134, /*!< 134 RTC10 */ 98 EGU10_IRQn = 135, /*!< 135 EGU10 */ 99 RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ 100 RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ 101 SPU20_IRQn = 192, /*!< 192 SPU20 */ 102 SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ 103 SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ 104 SERIAL22_IRQn = 200, /*!< 200 SERIAL22 */ 105 EGU20_IRQn = 201, /*!< 201 EGU20 */ 106 TIMER20_IRQn = 202, /*!< 202 TIMER20 */ 107 TIMER21_IRQn = 203, /*!< 203 TIMER21 */ 108 TIMER22_IRQn = 204, /*!< 204 TIMER22 */ 109 TIMER23_IRQn = 205, /*!< 205 TIMER23 */ 110 TIMER24_IRQn = 206, /*!< 206 TIMER24 */ 111 PDM20_IRQn = 208, /*!< 208 PDM20 */ 112 PDM21_IRQn = 209, /*!< 209 PDM21 */ 113 PWM20_IRQn = 210, /*!< 210 PWM20 */ 114 PWM21_IRQn = 211, /*!< 211 PWM21 */ 115 PWM22_IRQn = 212, /*!< 212 PWM22 */ 116 SAADC_IRQn = 213, /*!< 213 SAADC */ 117 NFCT_IRQn = 214, /*!< 214 NFCT */ 118 TEMP_IRQn = 215, /*!< 215 TEMP */ 119 GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ 120 GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ 121 TAMPC_IRQn = 220, /*!< 220 TAMPC */ 122 I2S20_IRQn = 221, /*!< 221 I2S20 */ 123 QDEC20_IRQn = 224, /*!< 224 QDEC20 */ 124 QDEC21_IRQn = 225, /*!< 225 QDEC21 */ 125 GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ 126 GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ 127 GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ 128 GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ 129 SPU30_IRQn = 256, /*!< 256 SPU30 */ 130 SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ 131 RTC30_IRQn = 261, /*!< 261 RTC30 */ 132 COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ 133 WDT30_IRQn = 264, /*!< 264 WDT30 */ 134 WDT31_IRQn = 265, /*!< 265 WDT31 */ 135 GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ 136 GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ 137 CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ 138 } IRQn_Type; 139 140 /* ==================================================== Interrupt Aliases ==================================================== */ 141 #define AAR00_IRQn AAR00_CCM00_IRQn 142 #define AAR00_IRQHandler AAR00_CCM00_IRQHandler 143 #define CCM00_IRQn AAR00_CCM00_IRQn 144 #define CCM00_IRQHandler AAR00_CCM00_IRQHandler 145 #define SPIM00_IRQn SERIAL00_IRQn 146 #define SPIM00_IRQHandler SERIAL00_IRQHandler 147 #define SPIS00_IRQn SERIAL00_IRQn 148 #define SPIS00_IRQHandler SERIAL00_IRQHandler 149 #define UARTE00_IRQn SERIAL00_IRQn 150 #define UARTE00_IRQHandler SERIAL00_IRQHandler 151 #define SPIM20_IRQn SERIAL20_IRQn 152 #define SPIM20_IRQHandler SERIAL20_IRQHandler 153 #define SPIS20_IRQn SERIAL20_IRQn 154 #define SPIS20_IRQHandler SERIAL20_IRQHandler 155 #define TWIM20_IRQn SERIAL20_IRQn 156 #define TWIM20_IRQHandler SERIAL20_IRQHandler 157 #define TWIS20_IRQn SERIAL20_IRQn 158 #define TWIS20_IRQHandler SERIAL20_IRQHandler 159 #define UARTE20_IRQn SERIAL20_IRQn 160 #define UARTE20_IRQHandler SERIAL20_IRQHandler 161 #define SPIM21_IRQn SERIAL21_IRQn 162 #define SPIM21_IRQHandler SERIAL21_IRQHandler 163 #define SPIS21_IRQn SERIAL21_IRQn 164 #define SPIS21_IRQHandler SERIAL21_IRQHandler 165 #define TWIM21_IRQn SERIAL21_IRQn 166 #define TWIM21_IRQHandler SERIAL21_IRQHandler 167 #define TWIS21_IRQn SERIAL21_IRQn 168 #define TWIS21_IRQHandler SERIAL21_IRQHandler 169 #define UARTE21_IRQn SERIAL21_IRQn 170 #define UARTE21_IRQHandler SERIAL21_IRQHandler 171 #define SPIM22_IRQn SERIAL22_IRQn 172 #define SPIM22_IRQHandler SERIAL22_IRQHandler 173 #define SPIS22_IRQn SERIAL22_IRQn 174 #define SPIS22_IRQHandler SERIAL22_IRQHandler 175 #define TWIM22_IRQn SERIAL22_IRQn 176 #define TWIM22_IRQHandler SERIAL22_IRQHandler 177 #define TWIS22_IRQn SERIAL22_IRQn 178 #define TWIS22_IRQHandler SERIAL22_IRQHandler 179 #define UARTE22_IRQn SERIAL22_IRQn 180 #define UARTE22_IRQHandler SERIAL22_IRQHandler 181 #define SPIM30_IRQn SERIAL30_IRQn 182 #define SPIM30_IRQHandler SERIAL30_IRQHandler 183 #define SPIS30_IRQn SERIAL30_IRQn 184 #define SPIS30_IRQHandler SERIAL30_IRQHandler 185 #define TWIM30_IRQn SERIAL30_IRQn 186 #define TWIM30_IRQHandler SERIAL30_IRQHandler 187 #define TWIS30_IRQn SERIAL30_IRQn 188 #define TWIS30_IRQHandler SERIAL30_IRQHandler 189 #define UARTE30_IRQn SERIAL30_IRQn 190 #define UARTE30_IRQHandler SERIAL30_IRQHandler 191 #define COMP_IRQn COMP_LPCOMP_IRQn 192 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 193 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 194 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 195 #define CLOCK_IRQn CLOCK_POWER_IRQn 196 #define CLOCK_IRQHandler CLOCK_POWER_IRQHandler 197 #define POWER_IRQn CLOCK_POWER_IRQn 198 #define POWER_IRQHandler CLOCK_POWER_IRQHandler 199 200 /* =========================================================================================================================== */ 201 /* ================ Processor and Core Peripheral Section ================ */ 202 /* =========================================================================================================================== */ 203 204 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 205 #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ 206 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 207 #define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ 208 #define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ 209 #define __DSP_PRESENT 0 /*!< DSP present or not */ 210 #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 211 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 212 #define __MPU_PRESENT 1 /*!< MPU present */ 213 #define __FPU_PRESENT 0 /*!< FPU present */ 214 #define __FPU_DP 0 /*!< Double Precision FPU */ 215 #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ 216 217 #define NRF_VPR NRF_VPR00 /*!< VPR instance name */ 218 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 219 #include "system_nrf.h" /*!< nrf54l15_flpr System Library */ 220 221 #endif /*!< NRF_FLPR */ 222 223 224 #ifdef NRF_FLPR 225 226 #define NRF_DOMAIN NRF_DOMAIN_NONE 227 #define NRF_PROCESSOR NRF_PROCESSOR_VPR 228 229 #endif /*!< NRF_FLPR */ 230 231 232 /* ========================================= Start of section using anonymous unions ========================================= */ 233 234 #include "compiler_abstraction.h" 235 236 #if defined (__CC_ARM) 237 #pragma push 238 #pragma anon_unions 239 #elif defined (__ICCARM__) 240 #pragma language=extended 241 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 242 #pragma clang diagnostic push 243 #pragma clang diagnostic ignored "-Wc11-extensions" 244 #pragma clang diagnostic ignored "-Wreserved-id-macro" 245 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 246 #pragma clang diagnostic ignored "-Wnested-anon-types" 247 #elif defined (__GNUC__) 248 /* anonymous unions are enabled by default */ 249 #elif defined (__TMS470__) 250 /* anonymous unions are enabled by default */ 251 #elif defined (__TASKING__) 252 #pragma warning 586 253 #elif defined (__CSMC__) 254 /* anonymous unions are enabled by default */ 255 #else 256 #warning Unsupported compiler type 257 #endif 258 259 /* =========================================================================================================================== */ 260 /* ================ Peripheral Address Map ================ */ 261 /* =========================================================================================================================== */ 262 263 #define NRF_FLPR_VPRCLIC_NS_BASE 0xF0000000UL 264 265 /* =========================================================================================================================== */ 266 /* ================ Peripheral Declaration ================ */ 267 /* =========================================================================================================================== */ 268 269 #define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) 270 271 /* =========================================================================================================================== */ 272 /* ================ TrustZone Remapping ================ */ 273 /* =========================================================================================================================== */ 274 275 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 276 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 277 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 278 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 279 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 280 281 /* =========================================================================================================================== */ 282 /* ================ Local Domain Remapping ================ */ 283 /* =========================================================================================================================== */ 284 285 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 286 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 287 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 288 #else /*!< Remap all instances. */ 289 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 290 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 291 #endif /*!< NRF_FLPR */ 292 293 /* ========================================== End of section using anonymous unions ========================================== */ 294 295 #if defined (__CC_ARM) 296 #pragma pop 297 #elif defined (__ICCARM__) 298 /* leave anonymous unions enabled */ 299 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 300 #pragma clang diagnostic pop 301 #elif defined (__GNUC__) 302 /* anonymous unions are enabled by default */ 303 #elif defined (__TMS470__) 304 /* anonymous unions are enabled by default */ 305 #elif defined (__TASKING__) 306 #pragma warning restore 307 #elif defined (__CSMC__) 308 /* anonymous unions are enabled by default */ 309 #endif 310 311 312 #ifdef __cplusplus 313 } 314 #endif 315 #endif /* NRF54L15_FLPR_H */ 316 317
