1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54L15_ENGA_FLPR_PERIPHERALS_H 36 #define NRF54L15_ENGA_FLPR_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*VPR CSR registers*/ 44 #define VPRCSR_PRESENT 1 45 #define VPRCSR_COUNT 1 46 47 #define VPRCSR_HARTNUM 14 /*!< HARTNUM: 14 */ 48 #define VPRCSR_MCLICBASERESET 0xF0000000 /*!< MCLICBASE: 0xF0000000 */ 49 #define VPRCSR_MULDIV 2 /*!< MULDIV: 2 */ 50 #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ 51 #define VPRCSR_DBG 1 /*!< DBG: 1 */ 52 #define VPRCSR_REMAP 1 /*!< Code patching (REMAP): 1 */ 53 #define VPRCSR_BUSWIDTH 64 /*!< BUSWIDTH: 64 */ 54 #define VPRCSR_BKPT 1 /*!< BKPT: 1 */ 55 #define VPRCSR_RETAINED 1 /*!< (unspecified) */ 56 #define VPRCSR_VIOPINS 0x0000FFFF /*!< CSR VIOPINS value: 0x0000FFFF */ 57 #define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 58 #define VPRCSR_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 59 #define VPRCSR_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 60 #define VPRCSR_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ 61 #define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ 62 #define VPRCSR_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ 63 #define VPRCSR_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ 64 #define VPRCSR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ 65 #define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ 66 #define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ 67 #define VPRCSR_BEXT 1 /*!< Bit-Manipulation extension: 1 */ 68 #define VPRCSR_CACHE_EN 1 /*!< (unspecified) */ 69 #define VPRCSR_CACHEEXTRATAGBUF 0 /*!< CACHEEXTRATAGBUF: 0 */ 70 #define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ 71 #define VPRCSR_VPR_BUS_PRIO 1 /*!< (unspecified) */ 72 #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ 73 74 /*VPR CLIC registers*/ 75 #define CLIC_PRESENT 1 76 #define CLIC_COUNT 1 77 78 #define VPRCLIC_IRQ_COUNT 32 79 #define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..270 */ 80 #define VPRCLIC_IRQNUM_MAX 270 /*!< Supported interrupts (IRQNUM): 0..270 */ 81 #define VPRCLIC_IRQNUM_SIZE 271 /*!< Supported interrupts (IRQNUM): 0..270 */ 82 #define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 83 #define VPRCLIC_CLIC_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 84 #define VPRCLIC_CLIC_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 85 #define VPRCLIC_CLIC_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ 86 #define VPRCLIC_COUNTER_IRQ_NUM 32 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 32 */ 87 #define VPRCLIC_CLIC_VPR_1_2 1 /*!< (unspecified) */ 88 89 /*Factory Information Configuration Registers*/ 90 #define FICR_PRESENT 1 91 #define FICR_COUNT 1 92 93 /*User Information Configuration Registers*/ 94 #define UICR_PRESENT 1 95 #define UICR_COUNT 1 96 97 /*Factory Information Configuration Registers*/ 98 #define SICR_PRESENT 1 99 #define SICR_COUNT 1 100 101 /*CRACENCORE*/ 102 #define CRACENCORE_PRESENT 1 103 #define CRACENCORE_COUNT 1 104 105 #define CRACENCORE_CRYPTMSTRDMAREGS 1 /*!< (unspecified) */ 106 #define CRACENCORE_CRYPTMSTRHWREGS 1 /*!< (unspecified) */ 107 #define CRACENCORE_RNGCONTROLREGS 1 /*!< (unspecified) */ 108 #define CRACENCORE_PKREGS 1 /*!< (unspecified) */ 109 #define CRACENCORE_IKGREGS 1 /*!< (unspecified) */ 110 #define CRACENCORE_RNGDATAREGS 1 /*!< (unspecified) */ 111 #define CRACENCORE_PKDATAMEMORYREGS 1 /*!< (unspecified) */ 112 #define CRACENCORE_PKUCODEREGS 1 /*!< (unspecified) */ 113 #define CRACENCORE_CRACENRESETVALUES 1 /*!< (unspecified) */ 114 #define CRACENCORE_SHA3RESETVALUES 0 /*!< (unspecified) */ 115 #define CRACENCORE_PKE_DATA_MEMORY 0x51808000 /*!< (unspecified) */ 116 #define CRACENCORE_PKE_DATA_MEMORY_SIZE 17408 /*!< (unspecified) */ 117 #define CRACENCORE_PKE_CODE_MEMORY 0x5180C000 /*!< (unspecified) */ 118 #define CRACENCORE_PKE_CODE_MEMORY_SIZE 5120 /*!< (unspecified) */ 119 120 /*System protection unit*/ 121 #define SPU_PRESENT 1 122 #define SPU_COUNT 4 123 124 #define SPU00_BELLS 0 /*!< (unspecified) */ 125 #define SPU00_IPCT 0 /*!< (unspecified) */ 126 #define SPU00_DPPI 1 /*!< (unspecified) */ 127 #define SPU00_GPIOTE 0 /*!< (unspecified) */ 128 #define SPU00_GRTC 0 /*!< (unspecified) */ 129 #define SPU00_GPIO 1 /*!< (unspecified) */ 130 #define SPU00_CRACEN 1 /*!< (unspecified) */ 131 #define SPU00_MRAMC 0 /*!< (unspecified) */ 132 #define SPU00_COEXC 0 /*!< (unspecified) */ 133 #define SPU00_ANTSWC 0 /*!< (unspecified) */ 134 #define SPU00_TDD 0 /*!< (unspecified) */ 135 #define SPU00_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 136 peripheral slave index)*/ 137 138 #define SPU10_BELLS 0 /*!< (unspecified) */ 139 #define SPU10_IPCT 0 /*!< (unspecified) */ 140 #define SPU10_DPPI 1 /*!< (unspecified) */ 141 #define SPU10_GPIOTE 0 /*!< (unspecified) */ 142 #define SPU10_GRTC 0 /*!< (unspecified) */ 143 #define SPU10_GPIO 0 /*!< (unspecified) */ 144 #define SPU10_CRACEN 0 /*!< (unspecified) */ 145 #define SPU10_MRAMC 0 /*!< (unspecified) */ 146 #define SPU10_COEXC 0 /*!< (unspecified) */ 147 #define SPU10_ANTSWC 0 /*!< (unspecified) */ 148 #define SPU10_TDD 0 /*!< (unspecified) */ 149 #define SPU10_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 150 peripheral slave index)*/ 151 152 #define SPU20_BELLS 0 /*!< (unspecified) */ 153 #define SPU20_IPCT 0 /*!< (unspecified) */ 154 #define SPU20_DPPI 1 /*!< (unspecified) */ 155 #define SPU20_GPIOTE 1 /*!< (unspecified) */ 156 #define SPU20_GRTC 1 /*!< (unspecified) */ 157 #define SPU20_GPIO 1 /*!< (unspecified) */ 158 #define SPU20_CRACEN 0 /*!< (unspecified) */ 159 #define SPU20_MRAMC 0 /*!< (unspecified) */ 160 #define SPU20_COEXC 0 /*!< (unspecified) */ 161 #define SPU20_ANTSWC 0 /*!< (unspecified) */ 162 #define SPU20_TDD 0 /*!< (unspecified) */ 163 #define SPU20_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 164 peripheral slave index)*/ 165 166 #define SPU30_BELLS 0 /*!< (unspecified) */ 167 #define SPU30_IPCT 0 /*!< (unspecified) */ 168 #define SPU30_DPPI 1 /*!< (unspecified) */ 169 #define SPU30_GPIOTE 1 /*!< (unspecified) */ 170 #define SPU30_GRTC 0 /*!< (unspecified) */ 171 #define SPU30_GPIO 1 /*!< (unspecified) */ 172 #define SPU30_CRACEN 0 /*!< (unspecified) */ 173 #define SPU30_MRAMC 0 /*!< (unspecified) */ 174 #define SPU30_COEXC 0 /*!< (unspecified) */ 175 #define SPU30_ANTSWC 0 /*!< (unspecified) */ 176 #define SPU30_TDD 0 /*!< (unspecified) */ 177 #define SPU30_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 178 peripheral slave index)*/ 179 180 /*Memory Privilege Controller*/ 181 #define MPC_PRESENT 1 182 #define MPC_COUNT 1 183 184 #define MPC00_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 185 #define MPC00_RTCHOKE 0 /*!< (unspecified) */ 186 #define MPC00_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 187 188 /*Distributed programmable peripheral interconnect controller*/ 189 #define DPPIC_PRESENT 1 190 #define DPPIC_COUNT 4 191 192 #define DPPIC00_HASCHANNELGROUPS 1 /*!< (unspecified) */ 193 #define DPPIC00_CH_NUM_MIN 0 /*!< (unspecified) */ 194 #define DPPIC00_CH_NUM_MAX 7 /*!< (unspecified) */ 195 #define DPPIC00_CH_NUM_SIZE 8 /*!< (unspecified) */ 196 #define DPPIC00_GROUP_NUM_MIN 0 /*!< (unspecified) */ 197 #define DPPIC00_GROUP_NUM_MAX 1 /*!< (unspecified) */ 198 #define DPPIC00_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 199 200 #define DPPIC10_HASCHANNELGROUPS 1 /*!< (unspecified) */ 201 #define DPPIC10_CH_NUM_MIN 0 /*!< (unspecified) */ 202 #define DPPIC10_CH_NUM_MAX 23 /*!< (unspecified) */ 203 #define DPPIC10_CH_NUM_SIZE 24 /*!< (unspecified) */ 204 #define DPPIC10_GROUP_NUM_MIN 0 /*!< (unspecified) */ 205 #define DPPIC10_GROUP_NUM_MAX 5 /*!< (unspecified) */ 206 #define DPPIC10_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 207 208 #define DPPIC20_HASCHANNELGROUPS 1 /*!< (unspecified) */ 209 #define DPPIC20_CH_NUM_MIN 0 /*!< (unspecified) */ 210 #define DPPIC20_CH_NUM_MAX 15 /*!< (unspecified) */ 211 #define DPPIC20_CH_NUM_SIZE 16 /*!< (unspecified) */ 212 #define DPPIC20_GROUP_NUM_MIN 0 /*!< (unspecified) */ 213 #define DPPIC20_GROUP_NUM_MAX 5 /*!< (unspecified) */ 214 #define DPPIC20_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 215 216 #define DPPIC30_HASCHANNELGROUPS 1 /*!< (unspecified) */ 217 #define DPPIC30_CH_NUM_MIN 0 /*!< (unspecified) */ 218 #define DPPIC30_CH_NUM_MAX 3 /*!< (unspecified) */ 219 #define DPPIC30_CH_NUM_SIZE 4 /*!< (unspecified) */ 220 #define DPPIC30_GROUP_NUM_MIN 0 /*!< (unspecified) */ 221 #define DPPIC30_GROUP_NUM_MAX 1 /*!< (unspecified) */ 222 #define DPPIC30_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 223 224 /*PPIB APB registers*/ 225 #define PPIB_PRESENT 1 226 #define PPIB_COUNT 8 227 228 #define PPIB00_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 229 #define PPIB00_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 230 #define PPIB00_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 231 232 #define PPIB01_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 233 #define PPIB01_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 234 #define PPIB01_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 235 236 #define PPIB10_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 237 #define PPIB10_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 238 #define PPIB10_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 239 240 #define PPIB11_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 241 #define PPIB11_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 242 #define PPIB11_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 243 244 #define PPIB20_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 245 #define PPIB20_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 246 #define PPIB20_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 247 248 #define PPIB21_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 249 #define PPIB21_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 250 #define PPIB21_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 251 252 #define PPIB22_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 253 #define PPIB22_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 254 #define PPIB22_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 255 256 #define PPIB30_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 257 #define PPIB30_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 258 #define PPIB30_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 259 260 /*Key management unit*/ 261 #define KMU_PRESENT 1 262 #define KMU_COUNT 1 263 264 #define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ 265 #define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ 266 267 /*Accelerated Address Resolver*/ 268 #define AAR_PRESENT 1 269 #define AAR_COUNT 1 270 271 #define AAR00_DMAERROR 1 /*!< (unspecified) */ 272 273 /*AES CCM Mode Encryption*/ 274 #define CCM_PRESENT 1 275 #define CCM_COUNT 1 276 277 #define CCM00_AMOUNTREG 0 /*!< (unspecified) */ 278 #define CCM00_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 279 #define CCM00_DMAERROR 1 /*!< (unspecified) */ 280 281 /*AES ECB Mode Encryption*/ 282 #define ECB_PRESENT 1 283 #define ECB_COUNT 1 284 285 #define ECB00_AMOUNTREG 0 /*!< (unspecified) */ 286 #define ECB00_DMAERROR 1 /*!< (unspecified) */ 287 288 /*CRACEN*/ 289 #define CRACEN_PRESENT 1 290 #define CRACEN_COUNT 1 291 292 #define CRACEN_CRYPTOACCELERATOR 1 /*!< (unspecified) */ 293 #define CRACEN_SEEDRAMLOCK 1 /*!< (unspecified) */ 294 #define CRACEN_SPLITKEYRAMLOCK 0 /*!< (unspecified) */ 295 #define CRACEN_SEEDALIGNED 0 /*!< (unspecified) */ 296 #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ 297 #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ 298 #define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ 299 #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ 300 #define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ 301 #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ 302 #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ 303 #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ 304 #define CRACEN_PROTECTED_RAM_SM4_KEY1 0x51810090 /*!< (unspecified) */ 305 #define CRACEN_PROTECTED_RAM_SM4_KEY1_SIZE 16 /*!< (unspecified) */ 306 #define CRACEN_PROTECTED_RAM_SM4_KEY2 0x518100A0 /*!< (unspecified) */ 307 #define CRACEN_PROTECTED_RAM_SM4_KEY2_SIZE 16 /*!< (unspecified) */ 308 #define CRACEN_PROTECTED_RAM_SM4_KEY3 0x518100B0 /*!< (unspecified) */ 309 #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ 310 #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ 311 #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ 312 #define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned 313 access, i.e. using an operation where a word-aligned address is used 314 for a word, or a halfword-aligned address is used for a halfword 315 access.*/ 316 #define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned 317 access, i.e. using an operation where a word-aligned address is used 318 for a word, or a halfword-aligned address is used for a halfword 319 access.*/ 320 321 /*Serial Peripheral Interface Master with EasyDMA*/ 322 #define SPIM_PRESENT 1 323 #define SPIM_COUNT 5 324 325 #define SPIM00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 326 #define SPIM00_MAX_DATARATE 32 /*!< (unspecified) */ 327 #define SPIM00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 328 #define SPIM00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 329 #define SPIM00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 330 #define SPIM00_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 331 #define SPIM00_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 332 #define SPIM00_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 333 #define SPIM00_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 334 #define SPIM00_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 335 #define SPIM00_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 336 #define SPIM00_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 337 #define SPIM00_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 338 #define SPIM00_CORE_FREQUENCY 128 /*!< Peripheral core frequency is 128 MHz. */ 339 #define SPIM00_PRESCALER_PRESENT 1 /*!< (unspecified) */ 340 #define SPIM00_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 341 #define SPIM00_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 342 #define SPIM00_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 343 #define SPIM00_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 344 #define SPIM00_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 345 #define SPIM00_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 346 #define SPIM00_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 347 #define SPIM00_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 348 #define SPIM00_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 349 #define SPIM00_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 350 351 #define SPIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 352 #define SPIM20_MAX_DATARATE 8 /*!< (unspecified) */ 353 #define SPIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 354 #define SPIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 355 #define SPIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 356 #define SPIM20_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 357 #define SPIM20_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 358 #define SPIM20_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 359 #define SPIM20_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 360 #define SPIM20_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 361 #define SPIM20_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 362 #define SPIM20_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 363 #define SPIM20_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 364 #define SPIM20_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 365 #define SPIM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 366 #define SPIM20_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 367 #define SPIM20_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 368 #define SPIM20_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 369 #define SPIM20_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 370 #define SPIM20_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 371 #define SPIM20_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 372 #define SPIM20_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 373 #define SPIM20_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 374 #define SPIM20_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 375 #define SPIM20_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 376 377 #define SPIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 378 #define SPIM21_MAX_DATARATE 8 /*!< (unspecified) */ 379 #define SPIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 380 #define SPIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 381 #define SPIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 382 #define SPIM21_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 383 #define SPIM21_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 384 #define SPIM21_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 385 #define SPIM21_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 386 #define SPIM21_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 387 #define SPIM21_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 388 #define SPIM21_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 389 #define SPIM21_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 390 #define SPIM21_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 391 #define SPIM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 392 #define SPIM21_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 393 #define SPIM21_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 394 #define SPIM21_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 395 #define SPIM21_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 396 #define SPIM21_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 397 #define SPIM21_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 398 #define SPIM21_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 399 #define SPIM21_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 400 #define SPIM21_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 401 #define SPIM21_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 402 403 #define SPIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 404 #define SPIM22_MAX_DATARATE 8 /*!< (unspecified) */ 405 #define SPIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 406 #define SPIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 407 #define SPIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 408 #define SPIM22_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 409 #define SPIM22_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 410 #define SPIM22_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 411 #define SPIM22_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 412 #define SPIM22_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 413 #define SPIM22_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 414 #define SPIM22_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 415 #define SPIM22_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 416 #define SPIM22_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 417 #define SPIM22_PRESCALER_PRESENT 1 /*!< (unspecified) */ 418 #define SPIM22_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 419 #define SPIM22_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 420 #define SPIM22_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 421 #define SPIM22_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 422 #define SPIM22_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 423 #define SPIM22_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 424 #define SPIM22_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 425 #define SPIM22_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 426 #define SPIM22_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 427 #define SPIM22_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 428 429 #define SPIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 430 #define SPIM30_MAX_DATARATE 8 /*!< (unspecified) */ 431 #define SPIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 432 #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 433 #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 434 #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 435 #define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 436 #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 437 #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 438 #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 439 #define SPIM30_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 440 #define SPIM30_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 441 #define SPIM30_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 442 #define SPIM30_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 443 #define SPIM30_PRESCALER_PRESENT 1 /*!< (unspecified) */ 444 #define SPIM30_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 445 #define SPIM30_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 446 #define SPIM30_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 447 #define SPIM30_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 448 #define SPIM30_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 449 #define SPIM30_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 450 #define SPIM30_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 451 #define SPIM30_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 452 #define SPIM30_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 453 #define SPIM30_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 454 455 /*SPI Slave*/ 456 #define SPIS_PRESENT 1 457 #define SPIS_COUNT 5 458 459 #define SPIS00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 460 #define SPIS00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 461 #define SPIS00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 462 #define SPIS00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 463 464 #define SPIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 465 #define SPIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 466 #define SPIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 467 #define SPIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 468 469 #define SPIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 470 #define SPIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 471 #define SPIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 472 #define SPIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 473 474 #define SPIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 475 #define SPIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 476 #define SPIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 477 #define SPIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 478 479 #define SPIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 480 #define SPIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 481 #define SPIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 482 #define SPIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 483 484 /*UART with EasyDMA*/ 485 #define UARTE_PRESENT 1 486 #define UARTE_COUNT 5 487 488 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 489 #define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 490 #define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 491 #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 492 #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 493 #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ 494 #define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ 495 #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 496 #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 497 498 #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 499 #define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 500 #define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 501 #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 502 #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 503 #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 504 #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ 505 #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 506 #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 507 508 #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 509 #define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 510 #define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 511 #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 512 #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 513 #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 514 #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ 515 #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 516 #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 517 518 #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 519 #define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 520 #define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 521 #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 522 #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 523 #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 524 #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ 525 #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 526 #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 527 528 #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 529 #define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 530 #define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 531 #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 532 #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 533 #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 534 #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ 535 #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 536 #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 537 538 /*Voltage glitch detectors*/ 539 #define GLITCHDET_PRESENT 1 540 #define GLITCHDET_COUNT 1 541 542 /*RRAM controller GLITCH detector*/ 543 #define RRAMC_PRESENT 1 544 #define RRAMC_COUNT 1 545 546 #define RRAMC_NRRAMWORDSIZE 128 /*!< RRAM word size : 128 bits per wordline */ 547 #define RRAMC_NWRITEBUFSIZE 32 /*!< Maximum write buffer size : 32 */ 548 #define RRAMC_REGION0ADDR_WRITABLE 0 /*!< (unspecified) */ 549 #define RRAMC_REGION0SIZE 4 /*!< (unspecified) */ 550 #define RRAMC_REGION0SIZE_WRITABLE 0 /*!< (unspecified) */ 551 #define RRAMC_REGION0READ 1 /*!< (unspecified) */ 552 #define RRAMC_REGION0READ_WRITABLE 1 /*!< (unspecified) */ 553 #define RRAMC_REGION0WRITE 1 /*!< (unspecified) */ 554 #define RRAMC_REGION0WRITE_WRITABLE 1 /*!< (unspecified) */ 555 #define RRAMC_REGION0EXECUTE 0 /*!< (unspecified) */ 556 #define RRAMC_REGION0EXECUTE_WRITABLE 0 /*!< (unspecified) */ 557 #define RRAMC_REGION0SECURE 0 /*!< (unspecified) */ 558 #define RRAMC_REGION0SECURE_WRITABLE 0 /*!< (unspecified) */ 559 #define RRAMC_REGION0OWNER 0 /*!< (unspecified) */ 560 #define RRAMC_REGION0OWNER_WRITABLE 1 /*!< (unspecified) */ 561 #define RRAMC_REGION0WRITEONCE 1 /*!< (unspecified) */ 562 #define RRAMC_REGION0WRITEONCE_WRITABLE 0 /*!< (unspecified) */ 563 #define RRAMC_REGION0LOCK 0 /*!< (unspecified) */ 564 #define RRAMC_REGION0LOCK_WRITABLE 1 /*!< (unspecified) */ 565 #define RRAMC_REGION1ADDR_WRITABLE 0 /*!< (unspecified) */ 566 #define RRAMC_REGION1SIZE 4 /*!< (unspecified) */ 567 #define RRAMC_REGION1SIZE_WRITABLE 0 /*!< (unspecified) */ 568 #define RRAMC_REGION1READ 1 /*!< (unspecified) */ 569 #define RRAMC_REGION1READ_WRITABLE 1 /*!< (unspecified) */ 570 #define RRAMC_REGION1WRITE 1 /*!< (unspecified) */ 571 #define RRAMC_REGION1WRITE_WRITABLE 1 /*!< (unspecified) */ 572 #define RRAMC_REGION1EXECUTE 0 /*!< (unspecified) */ 573 #define RRAMC_REGION1EXECUTE_WRITABLE 0 /*!< (unspecified) */ 574 #define RRAMC_REGION1SECURE 1 /*!< (unspecified) */ 575 #define RRAMC_REGION1SECURE_WRITABLE 1 /*!< (unspecified) */ 576 #define RRAMC_REGION1OWNER 0 /*!< (unspecified) */ 577 #define RRAMC_REGION1OWNER_WRITABLE 1 /*!< (unspecified) */ 578 #define RRAMC_REGION1WRITEONCE 1 /*!< (unspecified) */ 579 #define RRAMC_REGION1WRITEONCE_WRITABLE 0 /*!< (unspecified) */ 580 #define RRAMC_REGION1LOCK 0 /*!< (unspecified) */ 581 #define RRAMC_REGION1LOCK_WRITABLE 1 /*!< (unspecified) */ 582 #define RRAMC_REGION2ADDR_WRITABLE 0 /*!< (unspecified) */ 583 #define RRAMC_REGION2SIZE 8 /*!< (unspecified) */ 584 #define RRAMC_REGION2SIZE_WRITABLE 0 /*!< (unspecified) */ 585 #define RRAMC_REGION2READ 1 /*!< (unspecified) */ 586 #define RRAMC_REGION2READ_WRITABLE 1 /*!< (unspecified) */ 587 #define RRAMC_REGION2WRITE 1 /*!< (unspecified) */ 588 #define RRAMC_REGION2WRITE_WRITABLE 1 /*!< (unspecified) */ 589 #define RRAMC_REGION2EXECUTE 0 /*!< (unspecified) */ 590 #define RRAMC_REGION2EXECUTE_WRITABLE 0 /*!< (unspecified) */ 591 #define RRAMC_REGION2SECURE 1 /*!< (unspecified) */ 592 #define RRAMC_REGION2SECURE_WRITABLE 0 /*!< (unspecified) */ 593 #define RRAMC_REGION2OWNER 2 /*!< (unspecified) */ 594 #define RRAMC_REGION2OWNER_WRITABLE 0 /*!< (unspecified) */ 595 #define RRAMC_REGION2WRITEONCE 0 /*!< (unspecified) */ 596 #define RRAMC_REGION2WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 597 #define RRAMC_REGION2LOCK 0 /*!< (unspecified) */ 598 #define RRAMC_REGION2LOCK_WRITABLE 1 /*!< (unspecified) */ 599 #define RRAMC_REGION3ADDR_WRITABLE 0 /*!< (unspecified) */ 600 #define RRAMC_REGION3SIZE 0 /*!< (unspecified) */ 601 #define RRAMC_REGION3SIZE_WRITABLE 1 /*!< (unspecified) */ 602 #define RRAMC_REGION3READ 1 /*!< (unspecified) */ 603 #define RRAMC_REGION3READ_WRITABLE 1 /*!< (unspecified) */ 604 #define RRAMC_REGION3WRITE 1 /*!< (unspecified) */ 605 #define RRAMC_REGION3WRITE_WRITABLE 1 /*!< (unspecified) */ 606 #define RRAMC_REGION3EXECUTE 1 /*!< (unspecified) */ 607 #define RRAMC_REGION3EXECUTE_WRITABLE 1 /*!< (unspecified) */ 608 #define RRAMC_REGION3SECURE 1 /*!< (unspecified) */ 609 #define RRAMC_REGION3SECURE_WRITABLE 1 /*!< (unspecified) */ 610 #define RRAMC_REGION3OWNER 0 /*!< (unspecified) */ 611 #define RRAMC_REGION3OWNER_WRITABLE 1 /*!< (unspecified) */ 612 #define RRAMC_REGION3WRITEONCE 0 /*!< (unspecified) */ 613 #define RRAMC_REGION3WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 614 #define RRAMC_REGION3LOCK 0 /*!< (unspecified) */ 615 #define RRAMC_REGION3LOCK_WRITABLE 1 /*!< (unspecified) */ 616 #define RRAMC_REGION4ADDR_WRITABLE 1 /*!< (unspecified) */ 617 #define RRAMC_REGION4SIZE 0 /*!< (unspecified) */ 618 #define RRAMC_REGION4SIZE_WRITABLE 1 /*!< (unspecified) */ 619 #define RRAMC_REGION4READ 1 /*!< (unspecified) */ 620 #define RRAMC_REGION4READ_WRITABLE 1 /*!< (unspecified) */ 621 #define RRAMC_REGION4WRITE 1 /*!< (unspecified) */ 622 #define RRAMC_REGION4WRITE_WRITABLE 1 /*!< (unspecified) */ 623 #define RRAMC_REGION4EXECUTE 1 /*!< (unspecified) */ 624 #define RRAMC_REGION4EXECUTE_WRITABLE 1 /*!< (unspecified) */ 625 #define RRAMC_REGION4SECURE 1 /*!< (unspecified) */ 626 #define RRAMC_REGION4SECURE_WRITABLE 1 /*!< (unspecified) */ 627 #define RRAMC_REGION4OWNER 0 /*!< (unspecified) */ 628 #define RRAMC_REGION4OWNER_WRITABLE 1 /*!< (unspecified) */ 629 #define RRAMC_REGION4WRITEONCE 0 /*!< (unspecified) */ 630 #define RRAMC_REGION4WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 631 #define RRAMC_REGION4LOCK 0 /*!< (unspecified) */ 632 #define RRAMC_REGION4LOCK_WRITABLE 1 /*!< (unspecified) */ 633 #define RRAMC_GLITCHDETECTORS 0 /*!< (unspecified) */ 634 635 /*VPR peripheral registers*/ 636 #define VPR_PRESENT 1 637 #define VPR_COUNT 1 638 639 #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 640 #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 641 #define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ 642 #define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM 643 size))*/ 644 #define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ 645 #define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ 646 #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 647 #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ 648 #define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ 649 #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 650 #define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ 651 #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ 652 #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ 653 #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ 654 #define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ 655 #define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ 656 #define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ 657 #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ 658 #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ 659 #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ 660 #define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ 661 #define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ 662 #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ 663 664 /*GPIO Port*/ 665 #define GPIO_PRESENT 1 666 #define GPIO_COUNT 3 667 668 #define P2_CTRLSEL_MAP1 0 /*!< (unspecified) */ 669 #define P2_CTRLSEL_MAP2 1 /*!< (unspecified) */ 670 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 671 #define P2_PIN_NUM_MAX 10 /*!< (unspecified) */ 672 #define P2_PIN_NUM_SIZE 11 /*!< (unspecified) */ 673 #define P2_PINS_PRESENT 2047 /*!< (unspecified) */ 674 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 675 #define P2_RETAIN 0 /*!< (unspecified) */ 676 #define P2_PWRCTRL 0 /*!< (unspecified) */ 677 #define P2_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 678 #define P2_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 679 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 680 #define P2_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 681 #define P2_RETAIN_PER_PIN 0 /*!< (unspecified) */ 682 #define P2_CLOCKPIN 0 /*!< (unspecified) */ 683 684 #define P1_CTRLSEL_MAP1 0 /*!< (unspecified) */ 685 #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ 686 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 687 #define P1_PIN_NUM_MAX 15 /*!< (unspecified) */ 688 #define P1_PIN_NUM_SIZE 16 /*!< (unspecified) */ 689 #define P1_PINS_PRESENT 65535 /*!< (unspecified) */ 690 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 691 #define P1_RETAIN 0 /*!< (unspecified) */ 692 #define P1_PWRCTRL 0 /*!< (unspecified) */ 693 #define P1_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 694 #define P1_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 695 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 696 #define P1_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 697 #define P1_RETAIN_PER_PIN 0 /*!< (unspecified) */ 698 #define P1_CLOCKPIN 0 /*!< (unspecified) */ 699 700 #define P0_CTRLSEL_MAP1 0 /*!< (unspecified) */ 701 #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ 702 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 703 #define P0_PIN_NUM_MAX 4 /*!< (unspecified) */ 704 #define P0_PIN_NUM_SIZE 5 /*!< (unspecified) */ 705 #define P0_PINS_PRESENT 31 /*!< (unspecified) */ 706 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 707 #define P0_RETAIN 0 /*!< (unspecified) */ 708 #define P0_PWRCTRL 0 /*!< (unspecified) */ 709 #define P0_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 710 #define P0_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 711 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 712 #define P0_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 713 #define P0_RETAIN_PER_PIN 0 /*!< (unspecified) */ 714 #define P0_CLOCKPIN 0 /*!< (unspecified) */ 715 716 /*Control access port*/ 717 #define CTRLAPPERI_PRESENT 1 718 #define CTRLAPPERI_COUNT 1 719 720 /*Trace and debug control*/ 721 #define TAD_PRESENT 1 722 #define TAD_COUNT 1 723 724 #define TAD_TADFORCEON 0 /*!< (unspecified) */ 725 #define TAD_TAD_HAS_TASKS 0 /*!< (unspecified) */ 726 #define TAD_PDREQCLR 1 /*!< (unspecified) */ 727 728 /*Timer/Counter*/ 729 #define TIMER_PRESENT 1 730 #define TIMER_COUNT 7 731 732 #define TIMER00_CC_NUM_MIN 0 /*!< (unspecified) */ 733 #define TIMER00_CC_NUM_MAX 5 /*!< (unspecified) */ 734 #define TIMER00_CC_NUM_SIZE 6 /*!< (unspecified) */ 735 #define TIMER00_MAX_SIZE_MIN 0 /*!< (unspecified) */ 736 #define TIMER00_MAX_SIZE_MAX 31 /*!< (unspecified) */ 737 #define TIMER00_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 738 #define TIMER00_PCLK_MHZ 128 /*!< Peripheral clock frequency (PCLK) is 128 MHz */ 739 #define TIMER00_PCLK_VARIABLE 1 /*!< (unspecified) */ 740 741 #define TIMER10_CC_NUM_MIN 0 /*!< (unspecified) */ 742 #define TIMER10_CC_NUM_MAX 7 /*!< (unspecified) */ 743 #define TIMER10_CC_NUM_SIZE 8 /*!< (unspecified) */ 744 #define TIMER10_MAX_SIZE_MIN 0 /*!< (unspecified) */ 745 #define TIMER10_MAX_SIZE_MAX 31 /*!< (unspecified) */ 746 #define TIMER10_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 747 #define TIMER10_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 748 #define TIMER10_PCLK_VARIABLE 0 /*!< (unspecified) */ 749 750 #define TIMER20_CC_NUM_MIN 0 /*!< (unspecified) */ 751 #define TIMER20_CC_NUM_MAX 5 /*!< (unspecified) */ 752 #define TIMER20_CC_NUM_SIZE 6 /*!< (unspecified) */ 753 #define TIMER20_MAX_SIZE_MIN 0 /*!< (unspecified) */ 754 #define TIMER20_MAX_SIZE_MAX 31 /*!< (unspecified) */ 755 #define TIMER20_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 756 #define TIMER20_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 757 #define TIMER20_PCLK_VARIABLE 0 /*!< (unspecified) */ 758 759 #define TIMER21_CC_NUM_MIN 0 /*!< (unspecified) */ 760 #define TIMER21_CC_NUM_MAX 5 /*!< (unspecified) */ 761 #define TIMER21_CC_NUM_SIZE 6 /*!< (unspecified) */ 762 #define TIMER21_MAX_SIZE_MIN 0 /*!< (unspecified) */ 763 #define TIMER21_MAX_SIZE_MAX 31 /*!< (unspecified) */ 764 #define TIMER21_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 765 #define TIMER21_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 766 #define TIMER21_PCLK_VARIABLE 0 /*!< (unspecified) */ 767 768 #define TIMER22_CC_NUM_MIN 0 /*!< (unspecified) */ 769 #define TIMER22_CC_NUM_MAX 5 /*!< (unspecified) */ 770 #define TIMER22_CC_NUM_SIZE 6 /*!< (unspecified) */ 771 #define TIMER22_MAX_SIZE_MIN 0 /*!< (unspecified) */ 772 #define TIMER22_MAX_SIZE_MAX 31 /*!< (unspecified) */ 773 #define TIMER22_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 774 #define TIMER22_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 775 #define TIMER22_PCLK_VARIABLE 0 /*!< (unspecified) */ 776 777 #define TIMER23_CC_NUM_MIN 0 /*!< (unspecified) */ 778 #define TIMER23_CC_NUM_MAX 5 /*!< (unspecified) */ 779 #define TIMER23_CC_NUM_SIZE 6 /*!< (unspecified) */ 780 #define TIMER23_MAX_SIZE_MIN 0 /*!< (unspecified) */ 781 #define TIMER23_MAX_SIZE_MAX 31 /*!< (unspecified) */ 782 #define TIMER23_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 783 #define TIMER23_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 784 #define TIMER23_PCLK_VARIABLE 0 /*!< (unspecified) */ 785 786 #define TIMER24_CC_NUM_MIN 0 /*!< (unspecified) */ 787 #define TIMER24_CC_NUM_MAX 5 /*!< (unspecified) */ 788 #define TIMER24_CC_NUM_SIZE 6 /*!< (unspecified) */ 789 #define TIMER24_MAX_SIZE_MIN 0 /*!< (unspecified) */ 790 #define TIMER24_MAX_SIZE_MAX 31 /*!< (unspecified) */ 791 #define TIMER24_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 792 #define TIMER24_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 793 #define TIMER24_PCLK_VARIABLE 0 /*!< (unspecified) */ 794 795 /*Real-time counter*/ 796 #define RTC_PRESENT 1 797 #define RTC_COUNT 2 798 799 #define RTC10_CC_NUM_MIN 0 /*!< (unspecified) */ 800 #define RTC10_CC_NUM_MAX 3 /*!< (unspecified) */ 801 #define RTC10_CC_NUM_SIZE 4 /*!< (unspecified) */ 802 803 #define RTC30_CC_NUM_MIN 0 /*!< (unspecified) */ 804 #define RTC30_CC_NUM_MAX 3 /*!< (unspecified) */ 805 #define RTC30_CC_NUM_SIZE 4 /*!< (unspecified) */ 806 807 /*Event generator unit*/ 808 #define EGU_PRESENT 1 809 #define EGU_COUNT 2 810 811 #define EGU10_PEND 0 /*!< (unspecified) */ 812 #define EGU10_CH_NUM_MIN 0 /*!< (unspecified) */ 813 #define EGU10_CH_NUM_MAX 15 /*!< (unspecified) */ 814 #define EGU10_CH_NUM_SIZE 16 /*!< (unspecified) */ 815 816 #define EGU20_PEND 0 /*!< (unspecified) */ 817 #define EGU20_CH_NUM_MIN 0 /*!< (unspecified) */ 818 #define EGU20_CH_NUM_MAX 5 /*!< (unspecified) */ 819 #define EGU20_CH_NUM_SIZE 6 /*!< (unspecified) */ 820 821 /*2.4 GHz radio*/ 822 #define RADIO_PRESENT 1 823 #define RADIO_COUNT 1 824 825 #define RADIO_IRQ_COUNT 2 826 #define RADIO_WHITENINGPOLY 0 /*!< (unspecified) */ 827 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 828 829 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 830 #define TWIM_PRESENT 1 831 #define TWIM_COUNT 4 832 833 #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 834 #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 835 #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 836 #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 837 838 #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 839 #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 840 #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 841 #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 842 843 #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 844 #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 845 #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 846 #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 847 848 #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 849 #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 850 #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 851 #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 852 853 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 854 #define TWIS_PRESENT 1 855 #define TWIS_COUNT 4 856 857 #define TWIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 858 #define TWIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 859 #define TWIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 860 #define TWIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 861 862 #define TWIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 863 #define TWIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 864 #define TWIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 865 #define TWIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 866 867 #define TWIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 868 #define TWIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 869 #define TWIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 870 #define TWIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 871 872 #define TWIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 873 #define TWIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 874 #define TWIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 875 #define TWIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 876 877 /*Memory configuration*/ 878 #define MEMCONF_PRESENT 1 879 #define MEMCONF_COUNT 1 880 881 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 882 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 883 #define MEMCONF_POWER 1 /*!< (unspecified) */ 884 885 /*Pulse width modulation unit*/ 886 #define PWM_PRESENT 1 887 #define PWM_COUNT 3 888 889 #define PWM20_IDLE_OUT 1 /*!< (unspecified) */ 890 #define PWM20_COMPARE_MATCH 1 /*!< (unspecified) */ 891 #define PWM20_FEATURES_V2 0 /*!< (unspecified) */ 892 #define PWM20_NO_FEATURES_V2 1 /*!< (unspecified) */ 893 #define PWM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 894 895 #define PWM21_IDLE_OUT 1 /*!< (unspecified) */ 896 #define PWM21_COMPARE_MATCH 1 /*!< (unspecified) */ 897 #define PWM21_FEATURES_V2 0 /*!< (unspecified) */ 898 #define PWM21_NO_FEATURES_V2 1 /*!< (unspecified) */ 899 #define PWM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 900 901 #define PWM22_IDLE_OUT 1 /*!< (unspecified) */ 902 #define PWM22_COMPARE_MATCH 1 /*!< (unspecified) */ 903 #define PWM22_FEATURES_V2 0 /*!< (unspecified) */ 904 #define PWM22_NO_FEATURES_V2 1 /*!< (unspecified) */ 905 #define PWM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 906 907 /*Analog to Digital Converter*/ 908 #define SAADC_PRESENT 1 909 #define SAADC_COUNT 1 910 911 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 912 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 913 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ 914 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 915 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 916 #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 917 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 918 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 919 #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 920 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 921 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 922 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 923 924 /*NFC-A compatible radio NFC-A compatible radio*/ 925 #define NFCT_PRESENT 1 926 #define NFCT_COUNT 1 927 928 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 929 930 /*Temperature Sensor*/ 931 #define TEMP_PRESENT 1 932 #define TEMP_COUNT 1 933 934 /*GPIO Tasks and Events*/ 935 #define GPIOTE_PRESENT 1 936 #define GPIOTE_COUNT 2 937 938 #define GPIOTE20_IRQ_COUNT 2 939 #define GPIOTE20_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 940 #define GPIOTE20_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 941 #define GPIOTE20_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 942 #define GPIOTE20_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 943 #define GPIOTE20_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 944 #define GPIOTE20_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 945 #define GPIOTE20_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 946 #define GPIOTE20_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 947 #define GPIOTE20_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 948 #define GPIOTE20_HAS_PORT_EVENT 1 /*!< (unspecified) */ 949 950 #define GPIOTE30_IRQ_COUNT 2 951 #define GPIOTE30_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..3 */ 952 #define GPIOTE30_GPIOTE_NCHANNELS_MAX 3 /*!< Number of GPIOTE channels: 0..3 */ 953 #define GPIOTE30_GPIOTE_NCHANNELS_SIZE 4 /*!< Number of GPIOTE channels: 0..3 */ 954 #define GPIOTE30_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 955 #define GPIOTE30_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 956 #define GPIOTE30_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 957 #define GPIOTE30_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 958 #define GPIOTE30_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 959 #define GPIOTE30_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 960 #define GPIOTE30_HAS_PORT_EVENT 1 /*!< (unspecified) */ 961 962 /*Tamper controller*/ 963 #define TAMPC_PRESENT 1 964 #define TAMPC_COUNT 1 965 966 #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ 967 #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ 968 #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ 969 970 /*Inter-IC Sound*/ 971 #define I2S_PRESENT 1 972 #define I2S_COUNT 1 973 974 #define I2S20_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 975 #define I2S20_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 976 #define I2S20_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 977 #define I2S20_CLKCONFIG 0 /*!< (unspecified) */ 978 979 /*Quadrature Decoder*/ 980 #define QDEC_PRESENT 1 981 #define QDEC_COUNT 2 982 983 /*Global Real-time counter*/ 984 #define GRTC_PRESENT 1 985 #define GRTC_COUNT 1 986 987 #define GRTC_IRQ_COUNT 4 988 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 989 0..14*/ 990 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 991 0..14*/ 992 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 993 0..14*/ 994 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..11 */ 995 #define GRTC_NCC_MAX 11 /*!< Number of compare/capture registers : 0..11 */ 996 #define GRTC_NCC_SIZE 12 /*!< Number of compare/capture registers : 0..11 */ 997 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 998 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 999 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 1000 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1001 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1002 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1003 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..3 */ 1004 #define GRTC_GRTC_NINTERRUPTS_MAX 3 /*!< Number of GRTC interrupts : 0..3 */ 1005 #define GRTC_GRTC_NINTERRUPTS_SIZE 4 /*!< Number of GRTC interrupts : 0..3 */ 1006 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 1007 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 1008 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 1009 #define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ 1010 #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ 1011 1012 /*Comparator*/ 1013 #define COMP_PRESENT 1 1014 #define COMP_COUNT 1 1015 1016 /*Low-power comparator*/ 1017 #define LPCOMP_PRESENT 1 1018 #define LPCOMP_COUNT 1 1019 1020 /*Watchdog Timer*/ 1021 #define WDT_PRESENT 1 1022 #define WDT_COUNT 2 1023 1024 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ 1025 #define WDT30_HAS_INTEN 0 /*!< (unspecified) */ 1026 1027 #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ 1028 #define WDT31_HAS_INTEN 0 /*!< (unspecified) */ 1029 1030 /*Clock management*/ 1031 #define CLOCK_PRESENT 1 1032 #define CLOCK_COUNT 1 1033 1034 #define CLOCK_XOTUNE 0 /*!< (unspecified) */ 1035 1036 /*Power control*/ 1037 #define POWER_PRESENT 1 1038 #define POWER_COUNT 1 1039 1040 #define POWER_CONSTLATSTAT 0 /*!< (unspecified) */ 1041 1042 /*Reset control*/ 1043 #define RESET_PRESENT 1 1044 #define RESET_COUNT 1 1045 1046 /*Oscillator control*/ 1047 #define OSCILLATORS_PRESENT 1 1048 #define OSCILLATORS_COUNT 1 1049 1050 /*Voltage regulators*/ 1051 #define REGULATORS_PRESENT 1 1052 #define REGULATORS_COUNT 1 1053 1054 /* ==================================================== Baudrate settings ==================================================== */ 1055 /** 1056 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1057 */ 1058 typedef enum { 1059 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core 1060 frequency*/ 1061 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core 1062 frequency*/ 1063 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core 1064 frequency*/ 1065 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core 1066 frequency*/ 1067 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core 1068 frequency*/ 1069 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz 1070 core frequency*/ 1071 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz 1072 core frequency*/ 1073 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core 1074 frequency*/ 1075 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core 1076 frequency*/ 1077 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core 1078 frequency*/ 1079 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core 1080 frequency*/ 1081 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core 1082 frequency*/ 1083 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz 1084 core frequency*/ 1085 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz 1086 core frequency*/ 1087 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz 1088 core frequency*/ 1089 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz 1090 core frequency*/ 1091 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz 1092 core frequency*/ 1093 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 1094 MHz core frequency*/ 1095 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core 1096 frequency*/ 1097 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core 1098 frequency*/ 1099 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core 1100 frequency*/ 1101 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core 1102 frequency*/ 1103 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz 1104 core frequency*/ 1105 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz 1106 core frequency*/ 1107 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz 1108 core frequency*/ 1109 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz 1110 core frequency*/ 1111 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz 1112 core frequency*/ 1113 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz 1114 core frequency*/ 1115 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz 1116 core frequency*/ 1117 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz 1118 core frequency*/ 1119 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz 1120 core frequency*/ 1121 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz 1122 core frequency*/ 1123 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz 1124 core frequency*/ 1125 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 1126 MHz core frequency*/ 1127 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 1128 MHz core frequency*/ 1129 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 1130 MHz core frequency*/ 1131 } NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; 1132 1133 /* ==================================================== Baudrate settings ==================================================== */ 1134 /** 1135 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1136 */ 1137 typedef enum { 1138 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1139 frequency*/ 1140 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1141 frequency*/ 1142 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1143 frequency*/ 1144 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1145 frequency*/ 1146 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1147 frequency*/ 1148 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1149 frequency*/ 1150 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1151 frequency*/ 1152 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1153 frequency*/ 1154 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1155 core frequency*/ 1156 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1157 core frequency*/ 1158 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1159 core frequency*/ 1160 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1161 core frequency*/ 1162 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1163 core frequency*/ 1164 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1165 core frequency*/ 1166 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1167 core frequency*/ 1168 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1169 MHz core frequency*/ 1170 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1171 core frequency*/ 1172 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1173 MHz core frequency*/ 1174 } NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; 1175 1176 /* ==================================================== Baudrate settings ==================================================== */ 1177 /** 1178 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1179 */ 1180 typedef enum { 1181 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1182 frequency*/ 1183 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1184 frequency*/ 1185 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1186 frequency*/ 1187 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1188 frequency*/ 1189 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1190 frequency*/ 1191 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1192 frequency*/ 1193 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1194 frequency*/ 1195 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1196 frequency*/ 1197 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1198 core frequency*/ 1199 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1200 core frequency*/ 1201 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1202 core frequency*/ 1203 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1204 core frequency*/ 1205 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1206 core frequency*/ 1207 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1208 core frequency*/ 1209 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1210 core frequency*/ 1211 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1212 MHz core frequency*/ 1213 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1214 core frequency*/ 1215 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1216 MHz core frequency*/ 1217 } NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; 1218 1219 /* ==================================================== Baudrate settings ==================================================== */ 1220 /** 1221 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1222 */ 1223 typedef enum { 1224 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1225 frequency*/ 1226 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1227 frequency*/ 1228 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1229 frequency*/ 1230 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1231 frequency*/ 1232 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1233 frequency*/ 1234 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1235 frequency*/ 1236 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1237 frequency*/ 1238 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1239 frequency*/ 1240 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1241 core frequency*/ 1242 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1243 core frequency*/ 1244 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1245 core frequency*/ 1246 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1247 core frequency*/ 1248 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1249 core frequency*/ 1250 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1251 core frequency*/ 1252 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1253 core frequency*/ 1254 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1255 MHz core frequency*/ 1256 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1257 core frequency*/ 1258 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1259 MHz core frequency*/ 1260 } NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; 1261 1262 /* ==================================================== Baudrate settings ==================================================== */ 1263 /** 1264 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1265 */ 1266 typedef enum { 1267 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1268 frequency*/ 1269 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1270 frequency*/ 1271 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1272 frequency*/ 1273 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1274 frequency*/ 1275 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1276 frequency*/ 1277 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1278 frequency*/ 1279 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1280 frequency*/ 1281 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1282 frequency*/ 1283 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1284 core frequency*/ 1285 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1286 core frequency*/ 1287 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1288 core frequency*/ 1289 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1290 core frequency*/ 1291 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1292 core frequency*/ 1293 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1294 core frequency*/ 1295 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1296 core frequency*/ 1297 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1298 MHz core frequency*/ 1299 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1300 core frequency*/ 1301 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1302 MHz core frequency*/ 1303 } NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; 1304 1305 1306 #ifdef __cplusplus 1307 } 1308 #endif 1309 #endif /* NRF54L15_ENGA_FLPR_PERIPHERALS_H */ 1310 1311
