1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54L15_ENGA_APPLICATION_PERIPHERALS_H 36 #define NRF54L15_ENGA_APPLICATION_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*CACHEDATA*/ 44 #define CACHEDATA_PRESENT 1 45 #define CACHEDATA_COUNT 1 46 47 #define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ 48 #define ICACHEDATA_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ 49 #define ICACHEDATA_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ 50 #define ICACHEDATA_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ 51 #define ICACHEDATA_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ 52 #define ICACHEDATA_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ 53 #define ICACHEDATA_NUMDATAUNIT_MIN 0 /*!< Number of data units : 0..3 */ 54 #define ICACHEDATA_NUMDATAUNIT_MAX 3 /*!< Number of data units : 0..3 */ 55 #define ICACHEDATA_NUMDATAUNIT_SIZE 4 /*!< Number of data units : 0..3 */ 56 #define ICACHEDATA_DATAWIDTH_MIN 0 /*!< Data width of a data unit : 0..1 words */ 57 #define ICACHEDATA_DATAWIDTH_MAX 1 /*!< Data width of a data unit : 0..1 words */ 58 #define ICACHEDATA_DATAWIDTH_SIZE 2 /*!< Data width of a data unit : 0..1 words */ 59 60 /*CACHEINFO*/ 61 #define CACHEINFO_PRESENT 1 62 #define CACHEINFO_COUNT 1 63 64 #define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ 65 #define ICACHEINFO_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ 66 #define ICACHEINFO_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ 67 #define ICACHEINFO_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ 68 #define ICACHEINFO_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ 69 #define ICACHEINFO_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ 70 #define ICACHEINFO_NUMDATAUNIT_MIN 0 /*!< Number of data units : 0..7 */ 71 #define ICACHEINFO_NUMDATAUNIT_MAX 7 /*!< Number of data units : 0..7 */ 72 #define ICACHEINFO_NUMDATAUNIT_SIZE 8 /*!< Number of data units : 0..7 */ 73 #define ICACHEINFO_DATAWIDTH_MIN 0 /*!< Data width of a data unit : 0..3 words */ 74 #define ICACHEINFO_DATAWIDTH_MAX 3 /*!< Data width of a data unit : 0..3 words */ 75 #define ICACHEINFO_DATAWIDTH_SIZE 4 /*!< Data width of a data unit : 0..3 words */ 76 #define ICACHEINFO_TAGWIDTH_MIN 0 /*!< TAG width : 0..23 */ 77 #define ICACHEINFO_TAGWIDTH_MAX 23 /*!< TAG width : 0..23 */ 78 #define ICACHEINFO_TAGWIDTH_SIZE 24 /*!< TAG width : 0..23 */ 79 #define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ 80 81 /*Trace Port Interface Unit*/ 82 #define TPIU_PRESENT 1 83 #define TPIU_COUNT 1 84 85 /*Embedded Trace Macrocell*/ 86 #define ETM_PRESENT 1 87 #define ETM_COUNT 1 88 89 /*CPU control*/ 90 #define CPUC_PRESENT 1 91 #define CPUC_COUNT 1 92 93 /*Cache*/ 94 #define CACHE_PRESENT 1 95 #define CACHE_COUNT 1 96 97 #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 98 #define ICACHE_FLUSH 0 /*!< (unspecified) */ 99 #define ICACHE_CLEAN 0 /*!< (unspecified) */ 100 #define ICACHE_NONCACHEABLEMISS 0 /*!< (unspecified) */ 101 #define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ 102 #define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ 103 #define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ 104 105 /*Software interrupt*/ 106 #define SWI_PRESENT 1 107 #define SWI_COUNT 4 108 109 /*Factory Information Configuration Registers*/ 110 #define FICR_PRESENT 1 111 #define FICR_COUNT 1 112 113 /*User Information Configuration Registers*/ 114 #define UICR_PRESENT 1 115 #define UICR_COUNT 1 116 117 /*Factory Information Configuration Registers*/ 118 #define SICR_PRESENT 1 119 #define SICR_COUNT 1 120 121 /*CRACENCORE*/ 122 #define CRACENCORE_PRESENT 1 123 #define CRACENCORE_COUNT 1 124 125 #define CRACENCORE_CRYPTMSTRDMAREGS 1 /*!< (unspecified) */ 126 #define CRACENCORE_CRYPTMSTRHWREGS 1 /*!< (unspecified) */ 127 #define CRACENCORE_RNGCONTROLREGS 1 /*!< (unspecified) */ 128 #define CRACENCORE_PKREGS 1 /*!< (unspecified) */ 129 #define CRACENCORE_IKGREGS 1 /*!< (unspecified) */ 130 #define CRACENCORE_RNGDATAREGS 1 /*!< (unspecified) */ 131 #define CRACENCORE_PKDATAMEMORYREGS 1 /*!< (unspecified) */ 132 #define CRACENCORE_PKUCODEREGS 1 /*!< (unspecified) */ 133 #define CRACENCORE_CRACENRESETVALUES 1 /*!< (unspecified) */ 134 #define CRACENCORE_SHA3RESETVALUES 0 /*!< (unspecified) */ 135 #define CRACENCORE_PKE_DATA_MEMORY 0x51808000 /*!< (unspecified) */ 136 #define CRACENCORE_PKE_DATA_MEMORY_SIZE 17408 /*!< (unspecified) */ 137 #define CRACENCORE_PKE_CODE_MEMORY 0x5180C000 /*!< (unspecified) */ 138 #define CRACENCORE_PKE_CODE_MEMORY_SIZE 5120 /*!< (unspecified) */ 139 140 /*System protection unit*/ 141 #define SPU_PRESENT 1 142 #define SPU_COUNT 4 143 144 #define SPU00_BELLS 0 /*!< (unspecified) */ 145 #define SPU00_IPCT 0 /*!< (unspecified) */ 146 #define SPU00_DPPI 1 /*!< (unspecified) */ 147 #define SPU00_GPIOTE 0 /*!< (unspecified) */ 148 #define SPU00_GRTC 0 /*!< (unspecified) */ 149 #define SPU00_GPIO 1 /*!< (unspecified) */ 150 #define SPU00_CRACEN 1 /*!< (unspecified) */ 151 #define SPU00_MRAMC 0 /*!< (unspecified) */ 152 #define SPU00_COEXC 0 /*!< (unspecified) */ 153 #define SPU00_ANTSWC 0 /*!< (unspecified) */ 154 #define SPU00_TDD 0 /*!< (unspecified) */ 155 #define SPU00_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 156 peripheral slave index)*/ 157 158 #define SPU10_BELLS 0 /*!< (unspecified) */ 159 #define SPU10_IPCT 0 /*!< (unspecified) */ 160 #define SPU10_DPPI 1 /*!< (unspecified) */ 161 #define SPU10_GPIOTE 0 /*!< (unspecified) */ 162 #define SPU10_GRTC 0 /*!< (unspecified) */ 163 #define SPU10_GPIO 0 /*!< (unspecified) */ 164 #define SPU10_CRACEN 0 /*!< (unspecified) */ 165 #define SPU10_MRAMC 0 /*!< (unspecified) */ 166 #define SPU10_COEXC 0 /*!< (unspecified) */ 167 #define SPU10_ANTSWC 0 /*!< (unspecified) */ 168 #define SPU10_TDD 0 /*!< (unspecified) */ 169 #define SPU10_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 170 peripheral slave index)*/ 171 172 #define SPU20_BELLS 0 /*!< (unspecified) */ 173 #define SPU20_IPCT 0 /*!< (unspecified) */ 174 #define SPU20_DPPI 1 /*!< (unspecified) */ 175 #define SPU20_GPIOTE 1 /*!< (unspecified) */ 176 #define SPU20_GRTC 1 /*!< (unspecified) */ 177 #define SPU20_GPIO 1 /*!< (unspecified) */ 178 #define SPU20_CRACEN 0 /*!< (unspecified) */ 179 #define SPU20_MRAMC 0 /*!< (unspecified) */ 180 #define SPU20_COEXC 0 /*!< (unspecified) */ 181 #define SPU20_ANTSWC 0 /*!< (unspecified) */ 182 #define SPU20_TDD 0 /*!< (unspecified) */ 183 #define SPU20_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 184 peripheral slave index)*/ 185 186 #define SPU30_BELLS 0 /*!< (unspecified) */ 187 #define SPU30_IPCT 0 /*!< (unspecified) */ 188 #define SPU30_DPPI 1 /*!< (unspecified) */ 189 #define SPU30_GPIOTE 1 /*!< (unspecified) */ 190 #define SPU30_GRTC 0 /*!< (unspecified) */ 191 #define SPU30_GPIO 1 /*!< (unspecified) */ 192 #define SPU30_CRACEN 0 /*!< (unspecified) */ 193 #define SPU30_MRAMC 0 /*!< (unspecified) */ 194 #define SPU30_COEXC 0 /*!< (unspecified) */ 195 #define SPU30_ANTSWC 0 /*!< (unspecified) */ 196 #define SPU30_TDD 0 /*!< (unspecified) */ 197 #define SPU30_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 198 peripheral slave index)*/ 199 200 /*Memory Privilege Controller*/ 201 #define MPC_PRESENT 1 202 #define MPC_COUNT 1 203 204 #define MPC00_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 205 #define MPC00_RTCHOKE 0 /*!< (unspecified) */ 206 #define MPC00_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 207 208 /*Distributed programmable peripheral interconnect controller*/ 209 #define DPPIC_PRESENT 1 210 #define DPPIC_COUNT 4 211 212 #define DPPIC00_HASCHANNELGROUPS 1 /*!< (unspecified) */ 213 #define DPPIC00_CH_NUM_MIN 0 /*!< (unspecified) */ 214 #define DPPIC00_CH_NUM_MAX 7 /*!< (unspecified) */ 215 #define DPPIC00_CH_NUM_SIZE 8 /*!< (unspecified) */ 216 #define DPPIC00_GROUP_NUM_MIN 0 /*!< (unspecified) */ 217 #define DPPIC00_GROUP_NUM_MAX 1 /*!< (unspecified) */ 218 #define DPPIC00_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 219 220 #define DPPIC10_HASCHANNELGROUPS 1 /*!< (unspecified) */ 221 #define DPPIC10_CH_NUM_MIN 0 /*!< (unspecified) */ 222 #define DPPIC10_CH_NUM_MAX 23 /*!< (unspecified) */ 223 #define DPPIC10_CH_NUM_SIZE 24 /*!< (unspecified) */ 224 #define DPPIC10_GROUP_NUM_MIN 0 /*!< (unspecified) */ 225 #define DPPIC10_GROUP_NUM_MAX 5 /*!< (unspecified) */ 226 #define DPPIC10_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 227 228 #define DPPIC20_HASCHANNELGROUPS 1 /*!< (unspecified) */ 229 #define DPPIC20_CH_NUM_MIN 0 /*!< (unspecified) */ 230 #define DPPIC20_CH_NUM_MAX 15 /*!< (unspecified) */ 231 #define DPPIC20_CH_NUM_SIZE 16 /*!< (unspecified) */ 232 #define DPPIC20_GROUP_NUM_MIN 0 /*!< (unspecified) */ 233 #define DPPIC20_GROUP_NUM_MAX 5 /*!< (unspecified) */ 234 #define DPPIC20_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 235 236 #define DPPIC30_HASCHANNELGROUPS 1 /*!< (unspecified) */ 237 #define DPPIC30_CH_NUM_MIN 0 /*!< (unspecified) */ 238 #define DPPIC30_CH_NUM_MAX 3 /*!< (unspecified) */ 239 #define DPPIC30_CH_NUM_SIZE 4 /*!< (unspecified) */ 240 #define DPPIC30_GROUP_NUM_MIN 0 /*!< (unspecified) */ 241 #define DPPIC30_GROUP_NUM_MAX 1 /*!< (unspecified) */ 242 #define DPPIC30_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 243 244 /*PPIB APB registers*/ 245 #define PPIB_PRESENT 1 246 #define PPIB_COUNT 8 247 248 #define PPIB00_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 249 #define PPIB00_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 250 #define PPIB00_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 251 252 #define PPIB01_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 253 #define PPIB01_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 254 #define PPIB01_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 255 256 #define PPIB10_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 257 #define PPIB10_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 258 #define PPIB10_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 259 260 #define PPIB11_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 261 #define PPIB11_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 262 #define PPIB11_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 263 264 #define PPIB20_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 265 #define PPIB20_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 266 #define PPIB20_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 267 268 #define PPIB21_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 269 #define PPIB21_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 270 #define PPIB21_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 271 272 #define PPIB22_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 273 #define PPIB22_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 274 #define PPIB22_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 275 276 #define PPIB30_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 277 #define PPIB30_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 278 #define PPIB30_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 279 280 /*Key management unit*/ 281 #define KMU_PRESENT 1 282 #define KMU_COUNT 1 283 284 #define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ 285 #define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ 286 287 /*Accelerated Address Resolver*/ 288 #define AAR_PRESENT 1 289 #define AAR_COUNT 1 290 291 #define AAR00_DMAERROR 1 /*!< (unspecified) */ 292 293 /*AES CCM Mode Encryption*/ 294 #define CCM_PRESENT 1 295 #define CCM_COUNT 1 296 297 #define CCM00_AMOUNTREG 0 /*!< (unspecified) */ 298 #define CCM00_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 299 #define CCM00_DMAERROR 1 /*!< (unspecified) */ 300 301 /*AES ECB Mode Encryption*/ 302 #define ECB_PRESENT 1 303 #define ECB_COUNT 1 304 305 #define ECB00_AMOUNTREG 0 /*!< (unspecified) */ 306 #define ECB00_DMAERROR 1 /*!< (unspecified) */ 307 308 /*CRACEN*/ 309 #define CRACEN_PRESENT 1 310 #define CRACEN_COUNT 1 311 312 #define CRACEN_CRYPTOACCELERATOR 1 /*!< (unspecified) */ 313 #define CRACEN_SEEDRAMLOCK 1 /*!< (unspecified) */ 314 #define CRACEN_SPLITKEYRAMLOCK 0 /*!< (unspecified) */ 315 #define CRACEN_SEEDALIGNED 0 /*!< (unspecified) */ 316 #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ 317 #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ 318 #define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ 319 #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ 320 #define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ 321 #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ 322 #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ 323 #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ 324 #define CRACEN_PROTECTED_RAM_SM4_KEY1 0x51810090 /*!< (unspecified) */ 325 #define CRACEN_PROTECTED_RAM_SM4_KEY1_SIZE 16 /*!< (unspecified) */ 326 #define CRACEN_PROTECTED_RAM_SM4_KEY2 0x518100A0 /*!< (unspecified) */ 327 #define CRACEN_PROTECTED_RAM_SM4_KEY2_SIZE 16 /*!< (unspecified) */ 328 #define CRACEN_PROTECTED_RAM_SM4_KEY3 0x518100B0 /*!< (unspecified) */ 329 #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ 330 #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ 331 #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ 332 #define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned 333 access, i.e. using an operation where a word-aligned address is used 334 for a word, or a halfword-aligned address is used for a halfword 335 access.*/ 336 #define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned 337 access, i.e. using an operation where a word-aligned address is used 338 for a word, or a halfword-aligned address is used for a halfword 339 access.*/ 340 341 /*Serial Peripheral Interface Master with EasyDMA*/ 342 #define SPIM_PRESENT 1 343 #define SPIM_COUNT 5 344 345 #define SPIM00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 346 #define SPIM00_MAX_DATARATE 32 /*!< (unspecified) */ 347 #define SPIM00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 348 #define SPIM00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 349 #define SPIM00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 350 #define SPIM00_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 351 #define SPIM00_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 352 #define SPIM00_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 353 #define SPIM00_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 354 #define SPIM00_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 355 #define SPIM00_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 356 #define SPIM00_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 357 #define SPIM00_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 358 #define SPIM00_CORE_FREQUENCY 128 /*!< Peripheral core frequency is 128 MHz. */ 359 #define SPIM00_PRESCALER_PRESENT 1 /*!< (unspecified) */ 360 #define SPIM00_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 361 #define SPIM00_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 362 #define SPIM00_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 363 #define SPIM00_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 364 #define SPIM00_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 365 #define SPIM00_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 366 #define SPIM00_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 367 #define SPIM00_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 368 #define SPIM00_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 369 #define SPIM00_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 370 371 #define SPIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 372 #define SPIM20_MAX_DATARATE 8 /*!< (unspecified) */ 373 #define SPIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 374 #define SPIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 375 #define SPIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 376 #define SPIM20_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 377 #define SPIM20_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 378 #define SPIM20_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 379 #define SPIM20_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 380 #define SPIM20_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 381 #define SPIM20_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 382 #define SPIM20_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 383 #define SPIM20_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 384 #define SPIM20_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 385 #define SPIM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 386 #define SPIM20_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 387 #define SPIM20_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 388 #define SPIM20_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 389 #define SPIM20_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 390 #define SPIM20_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 391 #define SPIM20_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 392 #define SPIM20_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 393 #define SPIM20_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 394 #define SPIM20_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 395 #define SPIM20_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 396 397 #define SPIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 398 #define SPIM21_MAX_DATARATE 8 /*!< (unspecified) */ 399 #define SPIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 400 #define SPIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 401 #define SPIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 402 #define SPIM21_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 403 #define SPIM21_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 404 #define SPIM21_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 405 #define SPIM21_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 406 #define SPIM21_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 407 #define SPIM21_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 408 #define SPIM21_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 409 #define SPIM21_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 410 #define SPIM21_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 411 #define SPIM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 412 #define SPIM21_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 413 #define SPIM21_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 414 #define SPIM21_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 415 #define SPIM21_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 416 #define SPIM21_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 417 #define SPIM21_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 418 #define SPIM21_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 419 #define SPIM21_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 420 #define SPIM21_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 421 #define SPIM21_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 422 423 #define SPIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 424 #define SPIM22_MAX_DATARATE 8 /*!< (unspecified) */ 425 #define SPIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 426 #define SPIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 427 #define SPIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 428 #define SPIM22_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 429 #define SPIM22_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 430 #define SPIM22_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 431 #define SPIM22_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 432 #define SPIM22_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 433 #define SPIM22_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 434 #define SPIM22_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 435 #define SPIM22_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 436 #define SPIM22_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 437 #define SPIM22_PRESCALER_PRESENT 1 /*!< (unspecified) */ 438 #define SPIM22_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 439 #define SPIM22_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 440 #define SPIM22_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 441 #define SPIM22_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 442 #define SPIM22_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 443 #define SPIM22_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 444 #define SPIM22_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 445 #define SPIM22_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 446 #define SPIM22_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 447 #define SPIM22_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 448 449 #define SPIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 450 #define SPIM30_MAX_DATARATE 8 /*!< (unspecified) */ 451 #define SPIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 452 #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 453 #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 454 #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 455 #define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 456 #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 457 #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 458 #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 459 #define SPIM30_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 460 #define SPIM30_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 461 #define SPIM30_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 462 #define SPIM30_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 463 #define SPIM30_PRESCALER_PRESENT 1 /*!< (unspecified) */ 464 #define SPIM30_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 465 #define SPIM30_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 466 #define SPIM30_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 467 #define SPIM30_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 468 #define SPIM30_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 469 #define SPIM30_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 470 #define SPIM30_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 471 #define SPIM30_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 472 #define SPIM30_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 473 #define SPIM30_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 474 475 /*SPI Slave*/ 476 #define SPIS_PRESENT 1 477 #define SPIS_COUNT 5 478 479 #define SPIS00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 480 #define SPIS00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 481 #define SPIS00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 482 #define SPIS00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 483 484 #define SPIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 485 #define SPIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 486 #define SPIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 487 #define SPIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 488 489 #define SPIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 490 #define SPIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 491 #define SPIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 492 #define SPIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 493 494 #define SPIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 495 #define SPIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 496 #define SPIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 497 #define SPIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 498 499 #define SPIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 500 #define SPIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 501 #define SPIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 502 #define SPIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 503 504 /*UART with EasyDMA*/ 505 #define UARTE_PRESENT 1 506 #define UARTE_COUNT 5 507 508 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 509 #define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 510 #define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 511 #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 512 #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 513 #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ 514 #define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ 515 #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 516 #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 517 518 #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 519 #define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 520 #define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 521 #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 522 #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 523 #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 524 #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ 525 #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 526 #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 527 528 #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 529 #define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 530 #define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 531 #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 532 #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 533 #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 534 #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ 535 #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 536 #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 537 538 #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 539 #define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 540 #define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 541 #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 542 #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 543 #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 544 #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ 545 #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 546 #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 547 548 #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 549 #define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 550 #define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 551 #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 552 #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 553 #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 554 #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ 555 #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 556 #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 557 558 /*Voltage glitch detectors*/ 559 #define GLITCHDET_PRESENT 1 560 #define GLITCHDET_COUNT 1 561 562 /*RRAM controller GLITCH detector*/ 563 #define RRAMC_PRESENT 1 564 #define RRAMC_COUNT 1 565 566 #define RRAMC_NRRAMWORDSIZE 128 /*!< RRAM word size : 128 bits per wordline */ 567 #define RRAMC_NWRITEBUFSIZE 32 /*!< Maximum write buffer size : 32 */ 568 #define RRAMC_REGION0ADDR_WRITABLE 0 /*!< (unspecified) */ 569 #define RRAMC_REGION0SIZE 4 /*!< (unspecified) */ 570 #define RRAMC_REGION0SIZE_WRITABLE 0 /*!< (unspecified) */ 571 #define RRAMC_REGION0READ 1 /*!< (unspecified) */ 572 #define RRAMC_REGION0READ_WRITABLE 1 /*!< (unspecified) */ 573 #define RRAMC_REGION0WRITE 1 /*!< (unspecified) */ 574 #define RRAMC_REGION0WRITE_WRITABLE 1 /*!< (unspecified) */ 575 #define RRAMC_REGION0EXECUTE 0 /*!< (unspecified) */ 576 #define RRAMC_REGION0EXECUTE_WRITABLE 0 /*!< (unspecified) */ 577 #define RRAMC_REGION0SECURE 0 /*!< (unspecified) */ 578 #define RRAMC_REGION0SECURE_WRITABLE 0 /*!< (unspecified) */ 579 #define RRAMC_REGION0OWNER 0 /*!< (unspecified) */ 580 #define RRAMC_REGION0OWNER_WRITABLE 1 /*!< (unspecified) */ 581 #define RRAMC_REGION0WRITEONCE 1 /*!< (unspecified) */ 582 #define RRAMC_REGION0WRITEONCE_WRITABLE 0 /*!< (unspecified) */ 583 #define RRAMC_REGION0LOCK 0 /*!< (unspecified) */ 584 #define RRAMC_REGION0LOCK_WRITABLE 1 /*!< (unspecified) */ 585 #define RRAMC_REGION1ADDR_WRITABLE 0 /*!< (unspecified) */ 586 #define RRAMC_REGION1SIZE 4 /*!< (unspecified) */ 587 #define RRAMC_REGION1SIZE_WRITABLE 0 /*!< (unspecified) */ 588 #define RRAMC_REGION1READ 1 /*!< (unspecified) */ 589 #define RRAMC_REGION1READ_WRITABLE 1 /*!< (unspecified) */ 590 #define RRAMC_REGION1WRITE 1 /*!< (unspecified) */ 591 #define RRAMC_REGION1WRITE_WRITABLE 1 /*!< (unspecified) */ 592 #define RRAMC_REGION1EXECUTE 0 /*!< (unspecified) */ 593 #define RRAMC_REGION1EXECUTE_WRITABLE 0 /*!< (unspecified) */ 594 #define RRAMC_REGION1SECURE 1 /*!< (unspecified) */ 595 #define RRAMC_REGION1SECURE_WRITABLE 1 /*!< (unspecified) */ 596 #define RRAMC_REGION1OWNER 0 /*!< (unspecified) */ 597 #define RRAMC_REGION1OWNER_WRITABLE 1 /*!< (unspecified) */ 598 #define RRAMC_REGION1WRITEONCE 1 /*!< (unspecified) */ 599 #define RRAMC_REGION1WRITEONCE_WRITABLE 0 /*!< (unspecified) */ 600 #define RRAMC_REGION1LOCK 0 /*!< (unspecified) */ 601 #define RRAMC_REGION1LOCK_WRITABLE 1 /*!< (unspecified) */ 602 #define RRAMC_REGION2ADDR_WRITABLE 0 /*!< (unspecified) */ 603 #define RRAMC_REGION2SIZE 8 /*!< (unspecified) */ 604 #define RRAMC_REGION2SIZE_WRITABLE 0 /*!< (unspecified) */ 605 #define RRAMC_REGION2READ 1 /*!< (unspecified) */ 606 #define RRAMC_REGION2READ_WRITABLE 1 /*!< (unspecified) */ 607 #define RRAMC_REGION2WRITE 1 /*!< (unspecified) */ 608 #define RRAMC_REGION2WRITE_WRITABLE 1 /*!< (unspecified) */ 609 #define RRAMC_REGION2EXECUTE 0 /*!< (unspecified) */ 610 #define RRAMC_REGION2EXECUTE_WRITABLE 0 /*!< (unspecified) */ 611 #define RRAMC_REGION2SECURE 1 /*!< (unspecified) */ 612 #define RRAMC_REGION2SECURE_WRITABLE 0 /*!< (unspecified) */ 613 #define RRAMC_REGION2OWNER 2 /*!< (unspecified) */ 614 #define RRAMC_REGION2OWNER_WRITABLE 0 /*!< (unspecified) */ 615 #define RRAMC_REGION2WRITEONCE 0 /*!< (unspecified) */ 616 #define RRAMC_REGION2WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 617 #define RRAMC_REGION2LOCK 0 /*!< (unspecified) */ 618 #define RRAMC_REGION2LOCK_WRITABLE 1 /*!< (unspecified) */ 619 #define RRAMC_REGION3ADDR_WRITABLE 0 /*!< (unspecified) */ 620 #define RRAMC_REGION3SIZE 0 /*!< (unspecified) */ 621 #define RRAMC_REGION3SIZE_WRITABLE 1 /*!< (unspecified) */ 622 #define RRAMC_REGION3READ 1 /*!< (unspecified) */ 623 #define RRAMC_REGION3READ_WRITABLE 1 /*!< (unspecified) */ 624 #define RRAMC_REGION3WRITE 1 /*!< (unspecified) */ 625 #define RRAMC_REGION3WRITE_WRITABLE 1 /*!< (unspecified) */ 626 #define RRAMC_REGION3EXECUTE 1 /*!< (unspecified) */ 627 #define RRAMC_REGION3EXECUTE_WRITABLE 1 /*!< (unspecified) */ 628 #define RRAMC_REGION3SECURE 1 /*!< (unspecified) */ 629 #define RRAMC_REGION3SECURE_WRITABLE 1 /*!< (unspecified) */ 630 #define RRAMC_REGION3OWNER 0 /*!< (unspecified) */ 631 #define RRAMC_REGION3OWNER_WRITABLE 1 /*!< (unspecified) */ 632 #define RRAMC_REGION3WRITEONCE 0 /*!< (unspecified) */ 633 #define RRAMC_REGION3WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 634 #define RRAMC_REGION3LOCK 0 /*!< (unspecified) */ 635 #define RRAMC_REGION3LOCK_WRITABLE 1 /*!< (unspecified) */ 636 #define RRAMC_REGION4ADDR_WRITABLE 1 /*!< (unspecified) */ 637 #define RRAMC_REGION4SIZE 0 /*!< (unspecified) */ 638 #define RRAMC_REGION4SIZE_WRITABLE 1 /*!< (unspecified) */ 639 #define RRAMC_REGION4READ 1 /*!< (unspecified) */ 640 #define RRAMC_REGION4READ_WRITABLE 1 /*!< (unspecified) */ 641 #define RRAMC_REGION4WRITE 1 /*!< (unspecified) */ 642 #define RRAMC_REGION4WRITE_WRITABLE 1 /*!< (unspecified) */ 643 #define RRAMC_REGION4EXECUTE 1 /*!< (unspecified) */ 644 #define RRAMC_REGION4EXECUTE_WRITABLE 1 /*!< (unspecified) */ 645 #define RRAMC_REGION4SECURE 1 /*!< (unspecified) */ 646 #define RRAMC_REGION4SECURE_WRITABLE 1 /*!< (unspecified) */ 647 #define RRAMC_REGION4OWNER 0 /*!< (unspecified) */ 648 #define RRAMC_REGION4OWNER_WRITABLE 1 /*!< (unspecified) */ 649 #define RRAMC_REGION4WRITEONCE 0 /*!< (unspecified) */ 650 #define RRAMC_REGION4WRITEONCE_WRITABLE 1 /*!< (unspecified) */ 651 #define RRAMC_REGION4LOCK 0 /*!< (unspecified) */ 652 #define RRAMC_REGION4LOCK_WRITABLE 1 /*!< (unspecified) */ 653 #define RRAMC_GLITCHDETECTORS 0 /*!< (unspecified) */ 654 655 /*VPR peripheral registers*/ 656 #define VPR_PRESENT 1 657 #define VPR_COUNT 1 658 659 #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 660 #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 661 #define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ 662 #define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM 663 size))*/ 664 #define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ 665 #define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ 666 #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 667 #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ 668 #define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ 669 #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 670 #define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ 671 #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ 672 #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ 673 #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ 674 #define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ 675 #define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ 676 #define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ 677 #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ 678 #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ 679 #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ 680 #define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ 681 #define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ 682 #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ 683 684 /*GPIO Port*/ 685 #define GPIO_PRESENT 1 686 #define GPIO_COUNT 3 687 688 #define P2_CTRLSEL_MAP1 0 /*!< (unspecified) */ 689 #define P2_CTRLSEL_MAP2 1 /*!< (unspecified) */ 690 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 691 #define P2_PIN_NUM_MAX 10 /*!< (unspecified) */ 692 #define P2_PIN_NUM_SIZE 11 /*!< (unspecified) */ 693 #define P2_PINS_PRESENT 2047 /*!< (unspecified) */ 694 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 695 #define P2_RETAIN 0 /*!< (unspecified) */ 696 #define P2_PWRCTRL 0 /*!< (unspecified) */ 697 #define P2_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 698 #define P2_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 699 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 700 #define P2_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 701 #define P2_RETAIN_PER_PIN 0 /*!< (unspecified) */ 702 #define P2_CLOCKPIN 0 /*!< (unspecified) */ 703 704 #define P1_CTRLSEL_MAP1 0 /*!< (unspecified) */ 705 #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ 706 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 707 #define P1_PIN_NUM_MAX 15 /*!< (unspecified) */ 708 #define P1_PIN_NUM_SIZE 16 /*!< (unspecified) */ 709 #define P1_PINS_PRESENT 65535 /*!< (unspecified) */ 710 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 711 #define P1_RETAIN 0 /*!< (unspecified) */ 712 #define P1_PWRCTRL 0 /*!< (unspecified) */ 713 #define P1_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 714 #define P1_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 715 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 716 #define P1_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 717 #define P1_RETAIN_PER_PIN 0 /*!< (unspecified) */ 718 #define P1_CLOCKPIN 0 /*!< (unspecified) */ 719 720 #define P0_CTRLSEL_MAP1 0 /*!< (unspecified) */ 721 #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ 722 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 723 #define P0_PIN_NUM_MAX 4 /*!< (unspecified) */ 724 #define P0_PIN_NUM_SIZE 5 /*!< (unspecified) */ 725 #define P0_PINS_PRESENT 31 /*!< (unspecified) */ 726 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 727 #define P0_RETAIN 0 /*!< (unspecified) */ 728 #define P0_PWRCTRL 0 /*!< (unspecified) */ 729 #define P0_PWRCTRL_SEPARATE_REG 0 /*!< (unspecified) */ 730 #define P0_VSS_FLOAT_DFT 0 /*!< (unspecified) */ 731 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 732 #define P0_WIFI_CORE_PRESENT 0 /*!< (unspecified) */ 733 #define P0_RETAIN_PER_PIN 0 /*!< (unspecified) */ 734 #define P0_CLOCKPIN 0 /*!< (unspecified) */ 735 736 /*Control access port*/ 737 #define CTRLAPPERI_PRESENT 1 738 #define CTRLAPPERI_COUNT 1 739 740 /*Trace and debug control*/ 741 #define TAD_PRESENT 1 742 #define TAD_COUNT 1 743 744 #define TAD_TADFORCEON 0 /*!< (unspecified) */ 745 #define TAD_TAD_HAS_TASKS 0 /*!< (unspecified) */ 746 #define TAD_PDREQCLR 1 /*!< (unspecified) */ 747 748 /*Timer/Counter*/ 749 #define TIMER_PRESENT 1 750 #define TIMER_COUNT 7 751 752 #define TIMER00_CC_NUM_MIN 0 /*!< (unspecified) */ 753 #define TIMER00_CC_NUM_MAX 5 /*!< (unspecified) */ 754 #define TIMER00_CC_NUM_SIZE 6 /*!< (unspecified) */ 755 #define TIMER00_MAX_SIZE_MIN 0 /*!< (unspecified) */ 756 #define TIMER00_MAX_SIZE_MAX 31 /*!< (unspecified) */ 757 #define TIMER00_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 758 #define TIMER00_PCLK_MHZ 128 /*!< Peripheral clock frequency (PCLK) is 128 MHz */ 759 #define TIMER00_PCLK_VARIABLE 1 /*!< (unspecified) */ 760 761 #define TIMER10_CC_NUM_MIN 0 /*!< (unspecified) */ 762 #define TIMER10_CC_NUM_MAX 7 /*!< (unspecified) */ 763 #define TIMER10_CC_NUM_SIZE 8 /*!< (unspecified) */ 764 #define TIMER10_MAX_SIZE_MIN 0 /*!< (unspecified) */ 765 #define TIMER10_MAX_SIZE_MAX 31 /*!< (unspecified) */ 766 #define TIMER10_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 767 #define TIMER10_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 768 #define TIMER10_PCLK_VARIABLE 0 /*!< (unspecified) */ 769 770 #define TIMER20_CC_NUM_MIN 0 /*!< (unspecified) */ 771 #define TIMER20_CC_NUM_MAX 5 /*!< (unspecified) */ 772 #define TIMER20_CC_NUM_SIZE 6 /*!< (unspecified) */ 773 #define TIMER20_MAX_SIZE_MIN 0 /*!< (unspecified) */ 774 #define TIMER20_MAX_SIZE_MAX 31 /*!< (unspecified) */ 775 #define TIMER20_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 776 #define TIMER20_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 777 #define TIMER20_PCLK_VARIABLE 0 /*!< (unspecified) */ 778 779 #define TIMER21_CC_NUM_MIN 0 /*!< (unspecified) */ 780 #define TIMER21_CC_NUM_MAX 5 /*!< (unspecified) */ 781 #define TIMER21_CC_NUM_SIZE 6 /*!< (unspecified) */ 782 #define TIMER21_MAX_SIZE_MIN 0 /*!< (unspecified) */ 783 #define TIMER21_MAX_SIZE_MAX 31 /*!< (unspecified) */ 784 #define TIMER21_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 785 #define TIMER21_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 786 #define TIMER21_PCLK_VARIABLE 0 /*!< (unspecified) */ 787 788 #define TIMER22_CC_NUM_MIN 0 /*!< (unspecified) */ 789 #define TIMER22_CC_NUM_MAX 5 /*!< (unspecified) */ 790 #define TIMER22_CC_NUM_SIZE 6 /*!< (unspecified) */ 791 #define TIMER22_MAX_SIZE_MIN 0 /*!< (unspecified) */ 792 #define TIMER22_MAX_SIZE_MAX 31 /*!< (unspecified) */ 793 #define TIMER22_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 794 #define TIMER22_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 795 #define TIMER22_PCLK_VARIABLE 0 /*!< (unspecified) */ 796 797 #define TIMER23_CC_NUM_MIN 0 /*!< (unspecified) */ 798 #define TIMER23_CC_NUM_MAX 5 /*!< (unspecified) */ 799 #define TIMER23_CC_NUM_SIZE 6 /*!< (unspecified) */ 800 #define TIMER23_MAX_SIZE_MIN 0 /*!< (unspecified) */ 801 #define TIMER23_MAX_SIZE_MAX 31 /*!< (unspecified) */ 802 #define TIMER23_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 803 #define TIMER23_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 804 #define TIMER23_PCLK_VARIABLE 0 /*!< (unspecified) */ 805 806 #define TIMER24_CC_NUM_MIN 0 /*!< (unspecified) */ 807 #define TIMER24_CC_NUM_MAX 5 /*!< (unspecified) */ 808 #define TIMER24_CC_NUM_SIZE 6 /*!< (unspecified) */ 809 #define TIMER24_MAX_SIZE_MIN 0 /*!< (unspecified) */ 810 #define TIMER24_MAX_SIZE_MAX 31 /*!< (unspecified) */ 811 #define TIMER24_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 812 #define TIMER24_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 813 #define TIMER24_PCLK_VARIABLE 0 /*!< (unspecified) */ 814 815 /*Real-time counter*/ 816 #define RTC_PRESENT 1 817 #define RTC_COUNT 2 818 819 #define RTC10_CC_NUM_MIN 0 /*!< (unspecified) */ 820 #define RTC10_CC_NUM_MAX 3 /*!< (unspecified) */ 821 #define RTC10_CC_NUM_SIZE 4 /*!< (unspecified) */ 822 823 #define RTC30_CC_NUM_MIN 0 /*!< (unspecified) */ 824 #define RTC30_CC_NUM_MAX 3 /*!< (unspecified) */ 825 #define RTC30_CC_NUM_SIZE 4 /*!< (unspecified) */ 826 827 /*Event generator unit*/ 828 #define EGU_PRESENT 1 829 #define EGU_COUNT 2 830 831 #define EGU10_PEND 0 /*!< (unspecified) */ 832 #define EGU10_CH_NUM_MIN 0 /*!< (unspecified) */ 833 #define EGU10_CH_NUM_MAX 15 /*!< (unspecified) */ 834 #define EGU10_CH_NUM_SIZE 16 /*!< (unspecified) */ 835 836 #define EGU20_PEND 0 /*!< (unspecified) */ 837 #define EGU20_CH_NUM_MIN 0 /*!< (unspecified) */ 838 #define EGU20_CH_NUM_MAX 5 /*!< (unspecified) */ 839 #define EGU20_CH_NUM_SIZE 6 /*!< (unspecified) */ 840 841 /*2.4 GHz radio*/ 842 #define RADIO_PRESENT 1 843 #define RADIO_COUNT 1 844 845 #define RADIO_IRQ_COUNT 2 846 #define RADIO_WHITENINGPOLY 0 /*!< (unspecified) */ 847 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 848 849 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 850 #define TWIM_PRESENT 1 851 #define TWIM_COUNT 4 852 853 #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 854 #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 855 #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 856 #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 857 858 #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 859 #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 860 #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 861 #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 862 863 #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 864 #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 865 #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 866 #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 867 868 #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 869 #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 870 #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 871 #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 872 873 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 874 #define TWIS_PRESENT 1 875 #define TWIS_COUNT 4 876 877 #define TWIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 878 #define TWIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 879 #define TWIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 880 #define TWIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 881 882 #define TWIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 883 #define TWIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 884 #define TWIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 885 #define TWIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 886 887 #define TWIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 888 #define TWIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 889 #define TWIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 890 #define TWIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 891 892 #define TWIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 893 #define TWIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 894 #define TWIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 895 #define TWIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 896 897 /*Memory configuration*/ 898 #define MEMCONF_PRESENT 1 899 #define MEMCONF_COUNT 1 900 901 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 902 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 903 #define MEMCONF_POWER 1 /*!< (unspecified) */ 904 905 /*Pulse width modulation unit*/ 906 #define PWM_PRESENT 1 907 #define PWM_COUNT 3 908 909 #define PWM20_IDLE_OUT 1 /*!< (unspecified) */ 910 #define PWM20_COMPARE_MATCH 1 /*!< (unspecified) */ 911 #define PWM20_FEATURES_V2 0 /*!< (unspecified) */ 912 #define PWM20_NO_FEATURES_V2 1 /*!< (unspecified) */ 913 #define PWM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 914 915 #define PWM21_IDLE_OUT 1 /*!< (unspecified) */ 916 #define PWM21_COMPARE_MATCH 1 /*!< (unspecified) */ 917 #define PWM21_FEATURES_V2 0 /*!< (unspecified) */ 918 #define PWM21_NO_FEATURES_V2 1 /*!< (unspecified) */ 919 #define PWM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 920 921 #define PWM22_IDLE_OUT 1 /*!< (unspecified) */ 922 #define PWM22_COMPARE_MATCH 1 /*!< (unspecified) */ 923 #define PWM22_FEATURES_V2 0 /*!< (unspecified) */ 924 #define PWM22_NO_FEATURES_V2 1 /*!< (unspecified) */ 925 #define PWM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 926 927 /*Analog to Digital Converter*/ 928 #define SAADC_PRESENT 1 929 #define SAADC_COUNT 1 930 931 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 932 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 933 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ 934 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 935 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 936 #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 937 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 938 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 939 #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 940 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 941 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 942 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 943 944 /*NFC-A compatible radio NFC-A compatible radio*/ 945 #define NFCT_PRESENT 1 946 #define NFCT_COUNT 1 947 948 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 949 950 /*Temperature Sensor*/ 951 #define TEMP_PRESENT 1 952 #define TEMP_COUNT 1 953 954 /*GPIO Tasks and Events*/ 955 #define GPIOTE_PRESENT 1 956 #define GPIOTE_COUNT 2 957 958 #define GPIOTE20_IRQ_COUNT 2 959 #define GPIOTE20_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 960 #define GPIOTE20_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 961 #define GPIOTE20_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 962 #define GPIOTE20_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 963 #define GPIOTE20_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 964 #define GPIOTE20_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 965 #define GPIOTE20_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 966 #define GPIOTE20_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 967 #define GPIOTE20_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 968 #define GPIOTE20_HAS_PORT_EVENT 1 /*!< (unspecified) */ 969 970 #define GPIOTE30_IRQ_COUNT 2 971 #define GPIOTE30_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..3 */ 972 #define GPIOTE30_GPIOTE_NCHANNELS_MAX 3 /*!< Number of GPIOTE channels: 0..3 */ 973 #define GPIOTE30_GPIOTE_NCHANNELS_SIZE 4 /*!< Number of GPIOTE channels: 0..3 */ 974 #define GPIOTE30_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 975 #define GPIOTE30_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 976 #define GPIOTE30_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 977 #define GPIOTE30_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 978 #define GPIOTE30_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 979 #define GPIOTE30_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 980 #define GPIOTE30_HAS_PORT_EVENT 1 /*!< (unspecified) */ 981 982 /*Tamper controller*/ 983 #define TAMPC_PRESENT 1 984 #define TAMPC_COUNT 1 985 986 #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ 987 #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ 988 #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ 989 990 /*Inter-IC Sound*/ 991 #define I2S_PRESENT 1 992 #define I2S_COUNT 1 993 994 #define I2S20_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 995 #define I2S20_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 996 #define I2S20_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 997 #define I2S20_CLKCONFIG 0 /*!< (unspecified) */ 998 999 /*Quadrature Decoder*/ 1000 #define QDEC_PRESENT 1 1001 #define QDEC_COUNT 2 1002 1003 /*Global Real-time counter*/ 1004 #define GRTC_PRESENT 1 1005 #define GRTC_COUNT 1 1006 1007 #define GRTC_IRQ_COUNT 4 1008 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1009 0..14*/ 1010 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1011 0..14*/ 1012 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1013 0..14*/ 1014 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..11 */ 1015 #define GRTC_NCC_MAX 11 /*!< Number of compare/capture registers : 0..11 */ 1016 #define GRTC_NCC_SIZE 12 /*!< Number of compare/capture registers : 0..11 */ 1017 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 1018 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 1019 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 1020 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1021 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1022 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 1023 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..3 */ 1024 #define GRTC_GRTC_NINTERRUPTS_MAX 3 /*!< Number of GRTC interrupts : 0..3 */ 1025 #define GRTC_GRTC_NINTERRUPTS_SIZE 4 /*!< Number of GRTC interrupts : 0..3 */ 1026 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 1027 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 1028 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 1029 #define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ 1030 #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ 1031 1032 /*Comparator*/ 1033 #define COMP_PRESENT 1 1034 #define COMP_COUNT 1 1035 1036 /*Low-power comparator*/ 1037 #define LPCOMP_PRESENT 1 1038 #define LPCOMP_COUNT 1 1039 1040 /*Watchdog Timer*/ 1041 #define WDT_PRESENT 1 1042 #define WDT_COUNT 2 1043 1044 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ 1045 #define WDT30_HAS_INTEN 0 /*!< (unspecified) */ 1046 1047 #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ 1048 #define WDT31_HAS_INTEN 0 /*!< (unspecified) */ 1049 1050 /*Clock management*/ 1051 #define CLOCK_PRESENT 1 1052 #define CLOCK_COUNT 1 1053 1054 #define CLOCK_XOTUNE 0 /*!< (unspecified) */ 1055 1056 /*Power control*/ 1057 #define POWER_PRESENT 1 1058 #define POWER_COUNT 1 1059 1060 #define POWER_CONSTLATSTAT 0 /*!< (unspecified) */ 1061 1062 /*Reset control*/ 1063 #define RESET_PRESENT 1 1064 #define RESET_COUNT 1 1065 1066 /*Oscillator control*/ 1067 #define OSCILLATORS_PRESENT 1 1068 #define OSCILLATORS_COUNT 1 1069 1070 /*Voltage regulators*/ 1071 #define REGULATORS_PRESENT 1 1072 #define REGULATORS_COUNT 1 1073 1074 /* ==================================================== Baudrate settings ==================================================== */ 1075 /** 1076 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1077 */ 1078 typedef enum { 1079 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core 1080 frequency*/ 1081 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core 1082 frequency*/ 1083 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core 1084 frequency*/ 1085 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core 1086 frequency*/ 1087 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core 1088 frequency*/ 1089 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz 1090 core frequency*/ 1091 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz 1092 core frequency*/ 1093 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core 1094 frequency*/ 1095 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core 1096 frequency*/ 1097 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core 1098 frequency*/ 1099 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core 1100 frequency*/ 1101 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core 1102 frequency*/ 1103 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz 1104 core frequency*/ 1105 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz 1106 core frequency*/ 1107 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz 1108 core frequency*/ 1109 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz 1110 core frequency*/ 1111 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz 1112 core frequency*/ 1113 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 1114 MHz core frequency*/ 1115 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core 1116 frequency*/ 1117 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core 1118 frequency*/ 1119 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core 1120 frequency*/ 1121 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core 1122 frequency*/ 1123 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz 1124 core frequency*/ 1125 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz 1126 core frequency*/ 1127 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz 1128 core frequency*/ 1129 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz 1130 core frequency*/ 1131 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz 1132 core frequency*/ 1133 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz 1134 core frequency*/ 1135 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz 1136 core frequency*/ 1137 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz 1138 core frequency*/ 1139 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz 1140 core frequency*/ 1141 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz 1142 core frequency*/ 1143 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz 1144 core frequency*/ 1145 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 1146 MHz core frequency*/ 1147 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 1148 MHz core frequency*/ 1149 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 1150 MHz core frequency*/ 1151 } NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; 1152 1153 /* ==================================================== Baudrate settings ==================================================== */ 1154 /** 1155 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1156 */ 1157 typedef enum { 1158 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1159 frequency*/ 1160 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1161 frequency*/ 1162 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1163 frequency*/ 1164 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1165 frequency*/ 1166 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1167 frequency*/ 1168 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1169 frequency*/ 1170 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1171 frequency*/ 1172 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1173 frequency*/ 1174 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1175 core frequency*/ 1176 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1177 core frequency*/ 1178 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1179 core frequency*/ 1180 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1181 core frequency*/ 1182 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1183 core frequency*/ 1184 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1185 core frequency*/ 1186 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1187 core frequency*/ 1188 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1189 MHz core frequency*/ 1190 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1191 core frequency*/ 1192 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1193 MHz core frequency*/ 1194 } NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; 1195 1196 /* ==================================================== Baudrate settings ==================================================== */ 1197 /** 1198 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1199 */ 1200 typedef enum { 1201 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1202 frequency*/ 1203 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1204 frequency*/ 1205 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1206 frequency*/ 1207 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1208 frequency*/ 1209 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1210 frequency*/ 1211 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1212 frequency*/ 1213 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1214 frequency*/ 1215 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1216 frequency*/ 1217 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1218 core frequency*/ 1219 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1220 core frequency*/ 1221 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1222 core frequency*/ 1223 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1224 core frequency*/ 1225 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1226 core frequency*/ 1227 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1228 core frequency*/ 1229 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1230 core frequency*/ 1231 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1232 MHz core frequency*/ 1233 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1234 core frequency*/ 1235 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1236 MHz core frequency*/ 1237 } NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; 1238 1239 /* ==================================================== Baudrate settings ==================================================== */ 1240 /** 1241 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1242 */ 1243 typedef enum { 1244 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1245 frequency*/ 1246 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1247 frequency*/ 1248 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1249 frequency*/ 1250 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1251 frequency*/ 1252 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1253 frequency*/ 1254 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1255 frequency*/ 1256 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1257 frequency*/ 1258 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1259 frequency*/ 1260 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1261 core frequency*/ 1262 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1263 core frequency*/ 1264 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1265 core frequency*/ 1266 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1267 core frequency*/ 1268 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1269 core frequency*/ 1270 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1271 core frequency*/ 1272 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1273 core frequency*/ 1274 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1275 MHz core frequency*/ 1276 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1277 core frequency*/ 1278 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1279 MHz core frequency*/ 1280 } NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; 1281 1282 /* ==================================================== Baudrate settings ==================================================== */ 1283 /** 1284 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1285 */ 1286 typedef enum { 1287 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1288 frequency*/ 1289 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1290 frequency*/ 1291 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1292 frequency*/ 1293 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1294 frequency*/ 1295 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1296 frequency*/ 1297 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1298 frequency*/ 1299 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1300 frequency*/ 1301 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1302 frequency*/ 1303 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1304 core frequency*/ 1305 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1306 core frequency*/ 1307 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1308 core frequency*/ 1309 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1310 core frequency*/ 1311 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1312 core frequency*/ 1313 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1314 core frequency*/ 1315 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1316 core frequency*/ 1317 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1318 MHz core frequency*/ 1319 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1320 core frequency*/ 1321 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1322 MHz core frequency*/ 1323 } NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; 1324 1325 1326 #ifdef __cplusplus 1327 } 1328 #endif 1329 #endif /* NRF54L15_ENGA_APPLICATION_PERIPHERALS_H */ 1330 1331
