1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_RADIOCORE_PERIPHERALS_H 36 #define NRF54H20_RADIOCORE_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*CACHEDATA*/ 44 #define ICACHEDATA_PRESENT 1 45 #define ICACHEDATA_COUNT 1 46 47 #define ICACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ 48 #define ICACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ 49 #define ICACHEDATA_NUMDATAUNIT 4 /*!< Number of data units : 4 */ 50 #define ICACHEDATA_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ 51 52 /*CACHEINFO*/ 53 #define ICACHEINFO_PRESENT 1 54 #define ICACHEINFO_COUNT 1 55 56 #define ICACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ 57 #define ICACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ 58 #define ICACHEINFO_NUMDATAUNIT 4 /*!< Number of data units : 4 */ 59 #define ICACHEINFO_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ 60 #define ICACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ 61 #define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ 62 63 /*User information configuration registers*/ 64 #define UICR_PRESENT 1 65 #define UICR_COUNT 1 66 67 /*CACHEDATA*/ 68 #define DCACHEDATA_PRESENT 1 69 #define DCACHEDATA_COUNT 1 70 71 #define DCACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ 72 #define DCACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ 73 #define DCACHEDATA_NUMDATAUNIT 8 /*!< Number of data units : 8 */ 74 #define DCACHEDATA_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ 75 76 /*CACHEINFO*/ 77 #define DCACHEINFO_PRESENT 1 78 #define DCACHEINFO_COUNT 1 79 80 #define DCACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ 81 #define DCACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ 82 #define DCACHEINFO_NUMDATAUNIT 8 /*!< Number of data units : 8 */ 83 #define DCACHEINFO_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ 84 #define DCACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ 85 #define DCACHEINFO_DU_EXTENSION 1 /*!< (unspecified) */ 86 87 /*Embedded Trace Macrocell*/ 88 #define ETM_PRESENT 1 89 #define ETM_COUNT 1 90 91 /*Cross-Trigger Interface control*/ 92 #define CTI_PRESENT 1 93 #define CTI_COUNT 3 94 95 /*Cache*/ 96 #define CACHE_PRESENT 1 97 #define CACHE_COUNT 2 98 99 #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 100 #define ICACHE_FLUSH 0 /*!< (unspecified) */ 101 #define ICACHE_CLEAN 0 /*!< (unspecified) */ 102 #define ICACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ 103 #define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ 104 #define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ 105 #define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ 106 #define ICACHE_SECUREINVALIDATE 1 /*!< (unspecified) */ 107 108 #define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 109 #define DCACHE_FLUSH 1 /*!< (unspecified) */ 110 #define DCACHE_CLEAN 1 /*!< (unspecified) */ 111 #define DCACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ 112 #define DCACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ 113 #define DCACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ 114 #define DCACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ 115 #define DCACHE_SECUREINVALIDATE 1 /*!< (unspecified) */ 116 117 /*System protection unit*/ 118 #define SPU_PRESENT 1 119 #define SPU_COUNT 4 120 121 #define SPU000_BELLS 0 /*!< (unspecified) */ 122 #define SPU000_IPCT 0 /*!< (unspecified) */ 123 #define SPU000_DPPI 0 /*!< (unspecified) */ 124 #define SPU000_GPIOTE 0 /*!< (unspecified) */ 125 #define SPU000_GRTC 0 /*!< (unspecified) */ 126 #define SPU000_GPIO 0 /*!< (unspecified) */ 127 #define SPU000_CRACEN 0 /*!< (unspecified) */ 128 #define SPU000_MRAMC 0 /*!< (unspecified) */ 129 #define SPU000_COEXC 0 /*!< (unspecified) */ 130 #define SPU000_ANTSWC 0 /*!< (unspecified) */ 131 #define SPU000_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 132 peripheral slave index)*/ 133 134 #define SPU010_BELLS 0 /*!< (unspecified) */ 135 #define SPU010_IPCT 0 /*!< (unspecified) */ 136 #define SPU010_DPPI 0 /*!< (unspecified) */ 137 #define SPU010_GPIOTE 0 /*!< (unspecified) */ 138 #define SPU010_GRTC 0 /*!< (unspecified) */ 139 #define SPU010_GPIO 0 /*!< (unspecified) */ 140 #define SPU010_CRACEN 0 /*!< (unspecified) */ 141 #define SPU010_MRAMC 0 /*!< (unspecified) */ 142 #define SPU010_COEXC 0 /*!< (unspecified) */ 143 #define SPU010_ANTSWC 0 /*!< (unspecified) */ 144 #define SPU010_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 145 peripheral slave index)*/ 146 147 #define SPU020_BELLS 0 /*!< (unspecified) */ 148 #define SPU020_IPCT 1 /*!< (unspecified) */ 149 #define SPU020_DPPI 1 /*!< (unspecified) */ 150 #define SPU020_GPIOTE 0 /*!< (unspecified) */ 151 #define SPU020_GRTC 0 /*!< (unspecified) */ 152 #define SPU020_GPIO 0 /*!< (unspecified) */ 153 #define SPU020_CRACEN 0 /*!< (unspecified) */ 154 #define SPU020_MRAMC 0 /*!< (unspecified) */ 155 #define SPU020_COEXC 0 /*!< (unspecified) */ 156 #define SPU020_ANTSWC 0 /*!< (unspecified) */ 157 #define SPU020_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 158 peripheral slave index)*/ 159 160 #define SPU030_BELLS 0 /*!< (unspecified) */ 161 #define SPU030_IPCT 0 /*!< (unspecified) */ 162 #define SPU030_DPPI 1 /*!< (unspecified) */ 163 #define SPU030_GPIOTE 0 /*!< (unspecified) */ 164 #define SPU030_GRTC 0 /*!< (unspecified) */ 165 #define SPU030_GPIO 0 /*!< (unspecified) */ 166 #define SPU030_CRACEN 0 /*!< (unspecified) */ 167 #define SPU030_MRAMC 0 /*!< (unspecified) */ 168 #define SPU030_COEXC 0 /*!< (unspecified) */ 169 #define SPU030_ANTSWC 0 /*!< (unspecified) */ 170 #define SPU030_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 171 peripheral slave index)*/ 172 173 /*Memory Privilege Controller*/ 174 #define MPC_PRESENT 1 175 #define MPC_COUNT 1 176 177 #define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 178 #define MPC_RTCHOKE 1 /*!< (unspecified) */ 179 #define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 180 181 /*CM33 SubSystem*/ 182 #define CM33SS_PRESENT 1 183 #define CM33SS_COUNT 1 184 185 #define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ 186 187 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 188 189 #define MVDMA_PRESENT 1 190 #define MVDMA_COUNT 2 191 192 #define MVDMA_COMPLETED_EVENT 1 /*!< (unspecified) */ 193 #define MVDMA_DPPI_DISCONNECTED 0 /*!< (unspecified) */ 194 #define MVDMA_INSTANCE_IN_WRAPPER 0 /*!< (unspecified) */ 195 196 #define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ 197 #define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ 198 #define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ 199 200 /*RAM Controller*/ 201 #define RAMC_PRESENT 1 202 #define RAMC_COUNT 3 203 204 #define RAMC000_ECC 0 /*!< (unspecified) */ 205 #define RAMC000_SEC 1 /*!< (unspecified) */ 206 207 #define RAMC001_ECC 0 /*!< (unspecified) */ 208 #define RAMC001_SEC 0 /*!< (unspecified) */ 209 210 #define RAMC122_ECC 0 /*!< (unspecified) */ 211 #define RAMC122_SEC 0 /*!< (unspecified) */ 212 213 /*HSFLL*/ 214 #define HSFLL_PRESENT 1 215 #define HSFLL_COUNT 1 216 217 #define HSFLL_DITHER_32B 1 /*!< (unspecified) */ 218 #define HSFLL_CLOCKCTRL_MULT_RESET 4 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ 219 #define HSFLL_CLOCKCTRL_INTEGER_DIVISION 0 /*!< (unspecified) */ 220 221 /*LRCCONF*/ 222 #define LRCCONF_PRESENT 1 223 #define LRCCONF_COUNT 3 224 225 #define LRCCONF000_POWERON 0 /*!< (unspecified) */ 226 #define LRCCONF000_RETAIN 0 /*!< (unspecified) */ 227 #define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ 228 #define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ 229 #define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ 230 #define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ 231 #define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ 232 #define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ 233 #define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ 234 #define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ 235 #define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ 236 #define LRCCONF000_PDACT 0 /*!< (unspecified) */ 237 #define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ 238 #define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ 239 #define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ 240 #define LRCCONF000_OTHERON 0 /*!< (unspecified) */ 241 #define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ 242 #define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ 243 #define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ 244 #define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ 245 #define LRCCONF000_POWERON_MAIN_RESET 0 /*!< (unspecified) */ 246 #define LRCCONF000_POWERON_ACT_RESET 0 /*!< (unspecified) */ 247 #define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ 248 #define LRCCONF000_RETAIN_ACT_RESET 1 /*!< (unspecified) */ 249 250 #define LRCCONF010_POWERON 1 /*!< (unspecified) */ 251 #define LRCCONF010_RETAIN 1 /*!< (unspecified) */ 252 #define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ 253 #define LRCCONF010_LRCREQHFXO 1 /*!< (unspecified) */ 254 #define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ 255 #define LRCCONF010_NCLK_MAX 0 /*!< (unspecified) */ 256 #define LRCCONF010_NCLK_SIZE 1 /*!< (unspecified) */ 257 #define LRCCONF010_CLKCTRL 1 /*!< (unspecified) */ 258 #define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ 259 #define LRCCONF010_NACTPD_MAX 1 /*!< (unspecified) */ 260 #define LRCCONF010_NACTPD_SIZE 2 /*!< (unspecified) */ 261 #define LRCCONF010_PDACT 1 /*!< (unspecified) */ 262 #define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ 263 #define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ 264 #define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ 265 #define LRCCONF010_OTHERON 0 /*!< (unspecified) */ 266 #define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ 267 #define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ 268 #define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ 269 #define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ 270 #define LRCCONF010_POWERON_MAIN_RESET 1 /*!< Reset value of register POWERON.MAIN: 1 */ 271 #define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 272 #define LRCCONF010_RETAIN_MAIN_RESET 0 /*!< Reset value of register RETAIN.MAIN: 0 */ 273 #define LRCCONF010_RETAIN_ACT_RESET 0 /*!< Reset value of register RETAIN.ACT: 0 */ 274 275 #define LRCCONF020_POWERON 0 /*!< (unspecified) */ 276 #define LRCCONF020_RETAIN 0 /*!< (unspecified) */ 277 #define LRCCONF020_SYSTEMOFF 0 /*!< (unspecified) */ 278 #define LRCCONF020_LRCREQHFXO 0 /*!< (unspecified) */ 279 #define LRCCONF020_NCLK_MIN 0 /*!< (unspecified) */ 280 #define LRCCONF020_NCLK_MAX 7 /*!< (unspecified) */ 281 #define LRCCONF020_NCLK_SIZE 8 /*!< (unspecified) */ 282 #define LRCCONF020_CLKCTRL 0 /*!< (unspecified) */ 283 #define LRCCONF020_NACTPD_MIN 0 /*!< (unspecified) */ 284 #define LRCCONF020_NACTPD_MAX 7 /*!< (unspecified) */ 285 #define LRCCONF020_NACTPD_SIZE 8 /*!< (unspecified) */ 286 #define LRCCONF020_PDACT 0 /*!< (unspecified) */ 287 #define LRCCONF020_NPD_MIN 0 /*!< (unspecified) */ 288 #define LRCCONF020_NPD_MAX 7 /*!< (unspecified) */ 289 #define LRCCONF020_NPD_SIZE 8 /*!< (unspecified) */ 290 #define LRCCONF020_OTHERON 0 /*!< (unspecified) */ 291 #define LRCCONF020_NDOMAINS_MIN 0 /*!< (unspecified) */ 292 #define LRCCONF020_NDOMAINS_MAX 15 /*!< (unspecified) */ 293 #define LRCCONF020_NDOMAINS_SIZE 16 /*!< (unspecified) */ 294 #define LRCCONF020_AX2XWAITSTATES 0 /*!< (unspecified) */ 295 #define LRCCONF020_POWERON_MAIN_RESET 0 /*!< (unspecified) */ 296 #define LRCCONF020_POWERON_ACT_RESET 0 /*!< (unspecified) */ 297 #define LRCCONF020_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ 298 #define LRCCONF020_RETAIN_ACT_RESET 1 /*!< (unspecified) */ 299 300 /*Memory configuration*/ 301 #define MEMCONF_PRESENT 1 302 #define MEMCONF_COUNT 1 303 304 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 305 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 306 #define MEMCONF_POWER 1 /*!< (unspecified) */ 307 308 /*Watchdog Timer*/ 309 #define WDT_PRESENT 1 310 #define WDT_COUNT 4 311 312 #define WDT010_ALLOW_STOP 0 /*!< (unspecified) */ 313 #define WDT010_HAS_INTEN 1 /*!< (unspecified) */ 314 315 #define WDT011_ALLOW_STOP 0 /*!< (unspecified) */ 316 #define WDT011_HAS_INTEN 1 /*!< (unspecified) */ 317 318 #define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ 319 #define WDT131_HAS_INTEN 1 /*!< (unspecified) */ 320 321 #define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ 322 #define WDT132_HAS_INTEN 1 /*!< (unspecified) */ 323 324 /*RESETINFO*/ 325 #define RESETINFO_PRESENT 1 326 #define RESETINFO_COUNT 1 327 328 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ 329 #define RESETINFO_CROSSDOMAINRESET 0 /*!< (unspecified) */ 330 331 /*Distributed programmable peripheral interconnect controller*/ 332 #define DPPIC_PRESENT 1 333 #define DPPIC_COUNT 9 334 335 #define DPPIC020_HASCHANNELGROUPS 1 /*!< (unspecified) */ 336 #define DPPIC020_CH_NUM_MIN 0 /*!< (unspecified) */ 337 #define DPPIC020_CH_NUM_MAX 31 /*!< (unspecified) */ 338 #define DPPIC020_CH_NUM_SIZE 32 /*!< (unspecified) */ 339 #define DPPIC020_GROUP_NUM_MIN 0 /*!< (unspecified) */ 340 #define DPPIC020_GROUP_NUM_MAX 3 /*!< (unspecified) */ 341 #define DPPIC020_GROUP_NUM_SIZE 4 /*!< (unspecified) */ 342 343 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 344 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 345 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 346 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 347 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 348 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 349 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 350 351 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 352 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 353 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 354 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 355 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 356 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 357 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 358 359 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 360 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 361 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 362 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 363 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 364 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 365 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 366 367 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 368 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 369 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 370 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 371 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 372 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 373 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 374 375 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 376 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 377 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 378 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 379 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 380 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 381 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 382 383 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 384 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 385 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 386 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 387 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 388 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 389 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 390 391 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 392 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 393 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 394 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 395 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 396 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 397 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 398 399 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 400 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 401 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 402 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 403 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 404 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 405 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 406 407 /*PPIB APB registers*/ 408 #define PPIB_PRESENT 1 409 #define PPIB_COUNT 2 410 411 #define PPIB020_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 412 #define PPIB020_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 413 #define PPIB020_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 414 415 #define PPIB030_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 416 #define PPIB030_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ 417 #define PPIB030_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ 418 419 /*Event generator unit*/ 420 #define EGU_PRESENT 1 421 #define EGU_COUNT 2 422 423 #define EGU020_PEND 0 /*!< (unspecified) */ 424 #define EGU020_CH_NUM_MIN 0 /*!< (unspecified) */ 425 #define EGU020_CH_NUM_MAX 15 /*!< (unspecified) */ 426 #define EGU020_CH_NUM_SIZE 16 /*!< (unspecified) */ 427 428 #define EGU130_PEND 0 /*!< (unspecified) */ 429 #define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ 430 #define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ 431 #define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ 432 433 /*GPIO Tasks and Events*/ 434 #define GPIOTE_PRESENT 1 435 #define GPIOTE_COUNT 2 436 437 #define GPIOTE_IRQ_COUNT 1 438 #define GPIOTE_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 439 #define GPIOTE_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 440 #define GPIOTE_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 441 #define GPIOTE_GPIOTE_NPORTEVENTS 0 /*!< Number of GPIOTE port events: 0 */ 442 #define GPIOTE_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..0 */ 443 #define GPIOTE_GPIOTE_NINTERRUPTS_MAX 0 /*!< Number of GPIOTE interrupts: 0..0 */ 444 #define GPIOTE_GPIOTE_NINTERRUPTS_SIZE 1 /*!< Number of GPIOTE interrupts: 0..0 */ 445 #define GPIOTE_HAS_PORT_EVENT 0 /*!< (unspecified) */ 446 447 #define GPIOTE130_IRQ_COUNT 2 448 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 449 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 450 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 451 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 452 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 453 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 454 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 455 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 456 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 457 #define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ 458 459 /*Timer/Counter*/ 460 #define TIMER_PRESENT 1 461 #define TIMER_COUNT 13 462 463 #define TIMER020_CC_NUM_MIN 0 /*!< (unspecified) */ 464 #define TIMER020_CC_NUM_MAX 7 /*!< (unspecified) */ 465 #define TIMER020_CC_NUM_SIZE 8 /*!< (unspecified) */ 466 #define TIMER020_MAX_SIZE_MIN 0 /*!< (unspecified) */ 467 #define TIMER020_MAX_SIZE_MAX 31 /*!< (unspecified) */ 468 #define TIMER020_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 469 #define TIMER020_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 470 #define TIMER020_PCLK_VARIABLE 0 /*!< (unspecified) */ 471 472 #define TIMER021_CC_NUM_MIN 0 /*!< (unspecified) */ 473 #define TIMER021_CC_NUM_MAX 7 /*!< (unspecified) */ 474 #define TIMER021_CC_NUM_SIZE 8 /*!< (unspecified) */ 475 #define TIMER021_MAX_SIZE_MIN 0 /*!< (unspecified) */ 476 #define TIMER021_MAX_SIZE_MAX 31 /*!< (unspecified) */ 477 #define TIMER021_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 478 #define TIMER021_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 479 #define TIMER021_PCLK_VARIABLE 0 /*!< (unspecified) */ 480 481 #define TIMER022_CC_NUM_MIN 0 /*!< (unspecified) */ 482 #define TIMER022_CC_NUM_MAX 7 /*!< (unspecified) */ 483 #define TIMER022_CC_NUM_SIZE 8 /*!< (unspecified) */ 484 #define TIMER022_MAX_SIZE_MIN 0 /*!< (unspecified) */ 485 #define TIMER022_MAX_SIZE_MAX 31 /*!< (unspecified) */ 486 #define TIMER022_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 487 #define TIMER022_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 488 #define TIMER022_PCLK_VARIABLE 0 /*!< (unspecified) */ 489 490 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 491 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 492 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 493 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 494 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 495 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 496 #define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 497 #define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ 498 499 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 500 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 501 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 502 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 503 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 504 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 505 #define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 506 #define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ 507 508 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 509 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 510 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 511 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 512 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 513 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 514 #define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 515 #define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ 516 517 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 518 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 519 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 520 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 521 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 522 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 523 #define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 524 #define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ 525 526 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 527 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 528 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 529 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 530 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 531 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 532 #define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 533 #define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ 534 535 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 536 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 537 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 538 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 539 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 540 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 541 #define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 542 #define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ 543 544 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 545 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 546 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 547 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 548 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 549 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 550 #define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 551 #define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ 552 553 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 554 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 555 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 556 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 557 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 558 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 559 #define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 560 #define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ 561 562 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 563 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 564 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 565 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 566 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 567 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 568 #define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 569 #define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ 570 571 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 572 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 573 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 574 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 575 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 576 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 577 #define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 578 #define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ 579 580 /*Real-time counter*/ 581 #define RTC_PRESENT 1 582 #define RTC_COUNT 3 583 584 #define RTC_CC_NUM_MIN 0 /*!< (unspecified) */ 585 #define RTC_CC_NUM_MAX 7 /*!< (unspecified) */ 586 #define RTC_CC_NUM_SIZE 8 /*!< (unspecified) */ 587 #define RTC_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 588 #define RTC_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 589 #define RTC_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 590 #define RTC_LFCLK_ENABLE 0 /*!< (unspecified) */ 591 592 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 593 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 594 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 595 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 596 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 597 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 598 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 599 600 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 601 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 602 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 603 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 604 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 605 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 606 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 607 608 /*2.4 GHz radio*/ 609 #define RADIO_PRESENT 1 610 #define RADIO_COUNT 1 611 612 #define RADIO_IRQ_COUNT 2 613 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 614 615 /*VPR peripheral registers*/ 616 #define VPR_PRESENT 1 617 #define VPR_COUNT 3 618 619 #define VPR_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 620 #define VPR_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 621 #define VPR_RAM_BASE_ADDR 0x23040000 /*!< (unspecified) */ 622 #define VPR_RAM_SZ 15 /*!< (unspecified) */ 623 #define VPR_RETAINED 1 /*!< (unspecified) */ 624 #define VPR_VPRSAVEDCTX 0 /*!< (unspecified) */ 625 #define VPR_VPRSAVEADDR 0x00000000 /*!< (unspecified) */ 626 #define VPR_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 627 #define VPR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 628 #define VPR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 629 #define VPR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 630 #define VPR_VEVIF_TASKS_MASK 0x0000FF00 /*!< Mask of supported VEVIF tasks: 0x0000FF00 */ 631 #define VPR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..10 */ 632 #define VPR_VEVIF_NDPPI_MAX 10 /*!< VEVIF DPPI channels: 8..10 */ 633 #define VPR_VEVIF_NDPPI_SIZE 11 /*!< VEVIF DPPI channels: 8..10 */ 634 #define VPR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 635 #define VPR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 636 #define VPR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 637 #define VPR_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x53034400 */ 638 639 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 640 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 641 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 642 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 643 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 644 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 645 #define VPR121_RETAINED 0 /*!< (unspecified) */ 646 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 647 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 648 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 649 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 650 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 651 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 652 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 653 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 654 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 655 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 656 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 657 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 658 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 659 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 660 661 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 662 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 663 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 664 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 665 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 666 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 667 #define VPR130_RETAINED 1 /*!< (unspecified) */ 668 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 669 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 670 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 671 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 672 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 673 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 674 #define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ 675 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 676 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 677 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 678 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 679 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 680 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 681 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 682 683 /*Accelerated Address Resolver*/ 684 #define AAR_PRESENT 1 685 #define AAR_COUNT 2 686 687 /*AES CCM Mode Encryption*/ 688 #define CCM_PRESENT 1 689 #define CCM_COUNT 2 690 691 #define CCM030_AMOUNTREG 0 /*!< (unspecified) */ 692 #define CCM030_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 693 #define CCM030_DMAERROR 1 /*!< (unspecified) */ 694 695 #define CCM031_AMOUNTREG 0 /*!< (unspecified) */ 696 #define CCM031_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 697 #define CCM031_DMAERROR 1 /*!< (unspecified) */ 698 699 /*AES ECB Mode Encryption*/ 700 #define ECB_PRESENT 1 701 #define ECB_COUNT 2 702 703 #define ECB030_AMOUNTREG 1 /*!< (unspecified) */ 704 705 #define ECB031_AMOUNTREG 1 /*!< (unspecified) */ 706 707 /*IPCT APB registers*/ 708 #define IPCT_PRESENT 1 709 #define IPCT_COUNT 3 710 711 #define IPCT_IRQ_COUNT 2 712 713 #define IPCT120_IRQ_COUNT 1 714 715 #define IPCT130_IRQ_COUNT 1 716 717 /*Software interrupt*/ 718 #define SWI_PRESENT 1 719 #define SWI_COUNT 8 720 721 /*BELLBOARD APB registers*/ 722 #define BELLBOARD_PRESENT 1 723 #define BELLBOARD_COUNT 1 724 725 #define BELLBOARD_IRQ_COUNT 4 726 727 /*Factory Information Configuration Registers*/ 728 #define FICR_PRESENT 1 729 #define FICR_COUNT 1 730 731 /*USBHSCORE*/ 732 #define USBHSCORE_PRESENT 1 733 #define USBHSCORE_COUNT 1 734 735 /*I3CCORE*/ 736 #define I3CCORE_PRESENT 1 737 #define I3CCORE_COUNT 2 738 739 /*DMU*/ 740 #define DMU_PRESENT 1 741 #define DMU_COUNT 1 742 743 /*MCAN*/ 744 #define MCAN_PRESENT 1 745 #define MCAN_COUNT 1 746 747 /*System Trace Macrocell data buffer*/ 748 #define STMDATA_PRESENT 1 749 #define STMDATA_COUNT 1 750 751 /*TDDCONF*/ 752 #define TDDCONF_PRESENT 1 753 #define TDDCONF_COUNT 1 754 755 #define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 1 /*!< (unspecified) */ 756 #define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 0 /*!< (unspecified) */ 757 758 /*System Trace Macrocell*/ 759 #define STM_PRESENT 1 760 #define STM_COUNT 1 761 762 /*Trace Port Interface Unit*/ 763 #define TPIU_PRESENT 1 764 #define TPIU_COUNT 1 765 766 /*ATB Replicator module*/ 767 #define ATBREPLICATOR_PRESENT 1 768 #define ATBREPLICATOR_COUNT 4 769 770 /*ATB funnel module*/ 771 #define ATBFUNNEL_PRESENT 1 772 #define ATBFUNNEL_COUNT 4 773 774 /*Global Real-time counter*/ 775 #define GRTC_PRESENT 1 776 #define GRTC_COUNT 1 777 778 #define GRTC_IRQ_COUNT 3 779 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 780 0..14*/ 781 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 782 0..14*/ 783 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 784 0..14*/ 785 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 786 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 787 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 788 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 789 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 790 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 791 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 792 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 793 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 794 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ 795 #define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ 796 #define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ 797 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 798 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 799 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 800 #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ 801 #define GRTC_CCADD_WRITE_ONLY 1 /*!< (unspecified) */ 802 #define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ 803 804 /*Trace buffer monitor*/ 805 #define TBM_PRESENT 1 806 #define TBM_COUNT 1 807 808 /*USBHS*/ 809 #define USBHS_PRESENT 1 810 #define USBHS_COUNT 1 811 812 /*External Memory Interface*/ 813 #define EXMIF_PRESENT 1 814 #define EXMIF_COUNT 1 815 816 /*BELLBOARD public registers*/ 817 #define BELLBOARDPUBLIC_PRESENT 1 818 #define BELLBOARDPUBLIC_COUNT 1 819 820 /*VPR peripheral registers*/ 821 #define VPRPUBLIC_PRESENT 1 822 #define VPRPUBLIC_COUNT 1 823 824 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 825 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 826 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 827 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 828 829 /*MUTEX*/ 830 #define MUTEX_PRESENT 1 831 #define MUTEX_COUNT 2 832 833 /*I3C*/ 834 #define I3C_PRESENT 1 835 #define I3C_COUNT 2 836 837 /*Controller Area Network*/ 838 #define CAN_PRESENT 1 839 #define CAN_COUNT 1 840 841 /*Pulse width modulation unit*/ 842 #define PWM_PRESENT 1 843 #define PWM_COUNT 5 844 845 #define PWM120_IDLE_OUT 1 /*!< (unspecified) */ 846 #define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ 847 #define PWM120_FEATURES_V2 0 /*!< (unspecified) */ 848 #define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ 849 #define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 850 851 #define PWM130_IDLE_OUT 1 /*!< (unspecified) */ 852 #define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ 853 #define PWM130_FEATURES_V2 0 /*!< (unspecified) */ 854 #define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ 855 #define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 856 857 #define PWM131_IDLE_OUT 1 /*!< (unspecified) */ 858 #define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ 859 #define PWM131_FEATURES_V2 0 /*!< (unspecified) */ 860 #define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ 861 #define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 862 863 #define PWM132_IDLE_OUT 1 /*!< (unspecified) */ 864 #define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ 865 #define PWM132_FEATURES_V2 0 /*!< (unspecified) */ 866 #define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ 867 #define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 868 869 #define PWM133_IDLE_OUT 1 /*!< (unspecified) */ 870 #define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ 871 #define PWM133_FEATURES_V2 0 /*!< (unspecified) */ 872 #define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ 873 #define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 874 875 /*SPI Slave*/ 876 #define SPIS_PRESENT 1 877 #define SPIS_COUNT 9 878 879 #define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 880 #define SPIS120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 881 #define SPIS120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 882 #define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 883 884 #define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 885 #define SPIS130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 886 #define SPIS130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 887 #define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 888 889 #define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 890 #define SPIS131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 891 #define SPIS131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 892 #define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 893 894 #define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 895 #define SPIS132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 896 #define SPIS132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 897 #define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 898 899 #define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 900 #define SPIS133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 901 #define SPIS133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 902 #define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 903 904 #define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 905 #define SPIS134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 906 #define SPIS134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 907 #define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 908 909 #define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 910 #define SPIS135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 911 #define SPIS135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 912 #define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 913 914 #define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 915 #define SPIS136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 916 #define SPIS136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 917 #define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 918 919 #define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 920 #define SPIS137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 921 #define SPIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 922 #define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 923 924 /*Serial Peripheral Interface Master with EasyDMA*/ 925 #define SPIM_PRESENT 1 926 #define SPIM_COUNT 10 927 928 #define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 929 #define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ 930 #define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 931 #define SPIM120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 932 #define SPIM120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 933 #define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 934 #define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 935 #define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 936 #define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 937 #define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 938 #define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 939 #define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 940 #define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 941 #define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 942 #define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ 943 #define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 944 #define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 945 #define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 946 #define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 947 #define SPIM120_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 948 #define SPIM120_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 949 #define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 950 #define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 951 #define SPIM120_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 952 #define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 953 954 #define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 955 #define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ 956 #define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 957 #define SPIM121_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 958 #define SPIM121_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 959 #define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 960 #define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 961 #define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 962 #define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 963 #define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 964 #define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 965 #define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 966 #define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 967 #define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 968 #define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ 969 #define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 970 #define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 971 #define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 972 #define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 973 #define SPIM121_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 974 #define SPIM121_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 975 #define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 976 #define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 977 #define SPIM121_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 978 #define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 979 980 #define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 981 #define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ 982 #define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 983 #define SPIM130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 984 #define SPIM130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 985 #define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 986 #define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 987 #define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 988 #define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 989 #define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 990 #define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 991 #define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 992 #define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 993 #define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 994 #define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ 995 #define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 996 #define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 997 #define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 998 #define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 999 #define SPIM130_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1000 #define SPIM130_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1001 #define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1002 #define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1003 #define SPIM130_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1004 #define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1005 1006 #define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1007 #define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ 1008 #define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1009 #define SPIM131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1010 #define SPIM131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1011 #define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1012 #define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1013 #define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1014 #define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1015 #define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1016 #define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1017 #define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1018 #define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1019 #define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1020 #define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1021 #define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1022 #define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1023 #define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1024 #define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1025 #define SPIM131_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1026 #define SPIM131_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1027 #define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1028 #define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1029 #define SPIM131_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1030 #define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1031 1032 #define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1033 #define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ 1034 #define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1035 #define SPIM132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1036 #define SPIM132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1037 #define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1038 #define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1039 #define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1040 #define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1041 #define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1042 #define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1043 #define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1044 #define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1045 #define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1046 #define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1047 #define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1048 #define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1049 #define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1050 #define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1051 #define SPIM132_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1052 #define SPIM132_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1053 #define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1054 #define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1055 #define SPIM132_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1056 #define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1057 1058 #define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1059 #define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ 1060 #define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1061 #define SPIM133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1062 #define SPIM133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1063 #define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1064 #define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1065 #define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1066 #define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1067 #define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1068 #define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1069 #define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1070 #define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1071 #define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1072 #define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1073 #define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1074 #define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1075 #define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1076 #define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1077 #define SPIM133_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1078 #define SPIM133_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1079 #define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1080 #define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1081 #define SPIM133_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1082 #define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1083 1084 #define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1085 #define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ 1086 #define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1087 #define SPIM134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1088 #define SPIM134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1089 #define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1090 #define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1091 #define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1092 #define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1093 #define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1094 #define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1095 #define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1096 #define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1097 #define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1098 #define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1099 #define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1100 #define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1101 #define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1102 #define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1103 #define SPIM134_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1104 #define SPIM134_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1105 #define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1106 #define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1107 #define SPIM134_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1108 #define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1109 1110 #define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1111 #define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ 1112 #define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1113 #define SPIM135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1114 #define SPIM135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1115 #define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1116 #define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1117 #define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1118 #define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1119 #define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1120 #define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1121 #define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1122 #define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1123 #define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1124 #define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1125 #define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1126 #define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1127 #define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1128 #define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1129 #define SPIM135_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1130 #define SPIM135_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1131 #define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1132 #define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1133 #define SPIM135_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1134 #define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1135 1136 #define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1137 #define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ 1138 #define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1139 #define SPIM136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1140 #define SPIM136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1141 #define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1142 #define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1143 #define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1144 #define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1145 #define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1146 #define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1147 #define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1148 #define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1149 #define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1150 #define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1151 #define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1152 #define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1153 #define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1154 #define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1155 #define SPIM136_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1156 #define SPIM136_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1157 #define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1158 #define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1159 #define SPIM136_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1160 #define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1161 1162 #define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1163 #define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ 1164 #define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1165 #define SPIM137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1166 #define SPIM137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1167 #define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1168 #define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1169 #define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1170 #define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1171 #define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1172 #define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1173 #define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1174 #define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1175 #define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1176 #define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1177 #define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1178 #define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1179 #define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1180 #define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1181 #define SPIM137_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1182 #define SPIM137_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1183 #define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1184 #define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1185 #define SPIM137_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1186 #define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1187 1188 /*UART with EasyDMA*/ 1189 #define UARTE_PRESENT 1 1190 #define UARTE_COUNT 9 1191 1192 #define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1193 #define UARTE120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1194 #define UARTE120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1195 #define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1196 #define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1197 #define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ 1198 #define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ 1199 #define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1200 #define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1201 1202 #define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1203 #define UARTE130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1204 #define UARTE130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1205 #define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1206 #define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1207 #define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1208 #define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ 1209 #define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1210 #define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1211 1212 #define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1213 #define UARTE131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1214 #define UARTE131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1215 #define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1216 #define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1217 #define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1218 #define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ 1219 #define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1220 #define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1221 1222 #define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1223 #define UARTE132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1224 #define UARTE132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1225 #define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1226 #define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1227 #define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1228 #define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ 1229 #define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1230 #define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1231 1232 #define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1233 #define UARTE133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1234 #define UARTE133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1235 #define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1236 #define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1237 #define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1238 #define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ 1239 #define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1240 #define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1241 1242 #define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1243 #define UARTE134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1244 #define UARTE134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1245 #define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1246 #define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1247 #define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1248 #define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ 1249 #define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1250 #define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1251 1252 #define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1253 #define UARTE135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1254 #define UARTE135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1255 #define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1256 #define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1257 #define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1258 #define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ 1259 #define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1260 #define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1261 1262 #define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1263 #define UARTE136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1264 #define UARTE136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1265 #define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1266 #define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1267 #define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1268 #define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ 1269 #define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1270 #define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1271 1272 #define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1273 #define UARTE137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1274 #define UARTE137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1275 #define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1276 #define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1277 #define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1278 #define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ 1279 #define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1280 #define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1281 1282 /*GPIO Port*/ 1283 #define GPIO_PRESENT 1 1284 #define GPIO_COUNT 6 1285 1286 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1287 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1288 #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1289 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 1290 #define P0_PIN_NUM_MAX 11 /*!< (unspecified) */ 1291 #define P0_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1292 #define P0_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1293 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 1294 #define P0_RETAIN 1 /*!< (unspecified) */ 1295 #define P0_PWRCTRL 0 /*!< (unspecified) */ 1296 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1297 #define P0_BIASCTRL 0 /*!< (unspecified) */ 1298 1299 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1300 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1301 #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1302 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 1303 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 1304 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1305 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1306 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 1307 #define P1_RETAIN 1 /*!< (unspecified) */ 1308 #define P1_PWRCTRL 0 /*!< (unspecified) */ 1309 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1310 #define P1_BIASCTRL 0 /*!< (unspecified) */ 1311 1312 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1313 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1314 #define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1315 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 1316 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 1317 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1318 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1319 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 1320 #define P2_RETAIN 1 /*!< (unspecified) */ 1321 #define P2_PWRCTRL 0 /*!< (unspecified) */ 1322 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1323 #define P2_BIASCTRL 0 /*!< (unspecified) */ 1324 1325 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1326 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1327 #define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1328 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 1329 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 1330 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 1331 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 1332 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 1333 #define P6_RETAIN 1 /*!< (unspecified) */ 1334 #define P6_PWRCTRL 0 /*!< (unspecified) */ 1335 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1336 #define P6_BIASCTRL 0 /*!< (unspecified) */ 1337 1338 #define P7_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1339 #define P7_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1340 #define P7_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1341 #define P7_PIN_NUM_MIN 0 /*!< (unspecified) */ 1342 #define P7_PIN_NUM_MAX 7 /*!< (unspecified) */ 1343 #define P7_PIN_NUM_SIZE 8 /*!< (unspecified) */ 1344 #define P7_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 1345 #define P7_DRIVECTRL 1 /*!< (unspecified) */ 1346 #define P7_RETAIN 1 /*!< (unspecified) */ 1347 #define P7_PWRCTRL 0 /*!< (unspecified) */ 1348 #define P7_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1349 #define P7_BIASCTRL 0 /*!< (unspecified) */ 1350 1351 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1352 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1353 #define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1354 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 1355 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 1356 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 1357 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 1358 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 1359 #define P9_RETAIN 1 /*!< (unspecified) */ 1360 #define P9_PWRCTRL 1 /*!< (unspecified) */ 1361 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1362 #define P9_BIASCTRL 0 /*!< (unspecified) */ 1363 1364 /*Analog to Digital Converter*/ 1365 #define SAADC_PRESENT 1 1366 #define SAADC_COUNT 1 1367 1368 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 1369 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 1370 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 4 /*!< (unspecified) */ 1371 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 1372 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 1373 #define SAADC_TACQ_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1374 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 1375 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 1376 #define SAADC_TCONV_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1377 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 1378 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 1379 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1380 1381 /*Comparator*/ 1382 #define COMP_PRESENT 1 1383 #define COMP_COUNT 1 1384 1385 /*Low-power comparator*/ 1386 #define LPCOMP_PRESENT 1 1387 #define LPCOMP_COUNT 1 1388 1389 /*Temperature Sensor*/ 1390 #define TEMP_PRESENT 1 1391 #define TEMP_COUNT 1 1392 1393 /*NFC-A compatible radio NFC-A compatible radio*/ 1394 #define NFCT_PRESENT 1 1395 #define NFCT_COUNT 1 1396 1397 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 1398 1399 /*Time division multiplexed audio interface*/ 1400 #define TDM_PRESENT 1 1401 #define TDM_COUNT 2 1402 1403 #define TDM130_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1404 #define TDM130_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1405 #define TDM130_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1406 #define TDM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1407 1408 #define TDM131_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1409 #define TDM131_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1410 #define TDM131_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1411 #define TDM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1412 1413 /*Pulse Density Modulation (Digital Microphone) Interface*/ 1414 #define PDM_PRESENT 1 1415 #define PDM_COUNT 1 1416 1417 #define PDM_SAMPLE16 0 /*!< (unspecified) */ 1418 #define PDM_SAMPLE48 1 /*!< (unspecified) */ 1419 #define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1420 1421 /*Quadrature Decoder*/ 1422 #define QDEC_PRESENT 1 1423 #define QDEC_COUNT 2 1424 1425 /*SIM card interface*/ 1426 #define SIMIF_PRESENT 1 1427 #define SIMIF_COUNT 1 1428 1429 #define SIMIF130_SWOVERRIDE_REGS 0 /*!< (unspecified) */ 1430 1431 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 1432 #define TWIM_PRESENT 1 1433 #define TWIM_COUNT 8 1434 1435 #define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1436 #define TWIM130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1437 #define TWIM130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1438 #define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1439 1440 #define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1441 #define TWIM131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1442 #define TWIM131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1443 #define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1444 1445 #define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1446 #define TWIM132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1447 #define TWIM132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1448 #define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1449 1450 #define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1451 #define TWIM133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1452 #define TWIM133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1453 #define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1454 1455 #define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1456 #define TWIM134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1457 #define TWIM134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1458 #define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1459 1460 #define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1461 #define TWIM135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1462 #define TWIM135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1463 #define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1464 1465 #define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1466 #define TWIM136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1467 #define TWIM136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1468 #define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1469 1470 #define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1471 #define TWIM137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1472 #define TWIM137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1473 #define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1474 1475 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 1476 #define TWIS_PRESENT 1 1477 #define TWIS_COUNT 8 1478 1479 #define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1480 #define TWIS130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1481 #define TWIS130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1482 #define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1483 1484 #define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1485 #define TWIS131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1486 #define TWIS131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1487 #define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1488 1489 #define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1490 #define TWIS132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1491 #define TWIS132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1492 #define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1493 1494 #define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1495 #define TWIS133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1496 #define TWIS133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1497 #define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1498 1499 #define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1500 #define TWIS134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1501 #define TWIS134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1502 #define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1503 1504 #define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1505 #define TWIS135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1506 #define TWIS135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1507 #define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1508 1509 #define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1510 #define TWIS136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1511 #define TWIS136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1512 #define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1513 1514 #define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1515 #define TWIS137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1516 #define TWIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1517 #define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1518 1519 /* ============================================= SPU020 Split Security Features ============================================== */ 1520 /** 1521 * @brief Indexes in SPU020.FEATURES controlling access permissions of features with split security 1522 */ 1523 typedef enum { 1524 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_0 = 0, /*!< Index of access permissions for channel 0 of IPCT */ 1525 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_1 = 1, /*!< Index of access permissions for channel 1 of IPCT */ 1526 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_2 = 2, /*!< Index of access permissions for channel 2 of IPCT */ 1527 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_3 = 3, /*!< Index of access permissions for channel 3 of IPCT */ 1528 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_4 = 4, /*!< Index of access permissions for channel 4 of IPCT */ 1529 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_5 = 5, /*!< Index of access permissions for channel 5 of IPCT */ 1530 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_6 = 6, /*!< Index of access permissions for channel 6 of IPCT */ 1531 NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_7 = 7, /*!< Index of access permissions for channel 7 of IPCT */ 1532 NRF_RADIOCORE_SPU020_FEATURES_IPCT_INTERRUPT_0 = 24, /*!< Index of access permissions for interrupt 0 of IPCT */ 1533 NRF_RADIOCORE_SPU020_FEATURES_IPCT_INTERRUPT_1 = 25, /*!< Index of access permissions for interrupt 1 of IPCT */ 1534 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_0 = 32, /*!< Index of access permissions for channel 0 of DPPIC020 */ 1535 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_1 = 33, /*!< Index of access permissions for channel 1 of DPPIC020 */ 1536 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_2 = 34, /*!< Index of access permissions for channel 2 of DPPIC020 */ 1537 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_3 = 35, /*!< Index of access permissions for channel 3 of DPPIC020 */ 1538 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_4 = 36, /*!< Index of access permissions for channel 4 of DPPIC020 */ 1539 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_5 = 37, /*!< Index of access permissions for channel 5 of DPPIC020 */ 1540 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_6 = 38, /*!< Index of access permissions for channel 6 of DPPIC020 */ 1541 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_7 = 39, /*!< Index of access permissions for channel 7 of DPPIC020 */ 1542 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_8 = 40, /*!< Index of access permissions for channel 8 of DPPIC020 */ 1543 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_9 = 41, /*!< Index of access permissions for channel 9 of DPPIC020 */ 1544 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_10 = 42, /*!< Index of access permissions for channel 10 of DPPIC020 */ 1545 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_11 = 43, /*!< Index of access permissions for channel 11 of DPPIC020 */ 1546 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_12 = 44, /*!< Index of access permissions for channel 12 of DPPIC020 */ 1547 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_13 = 45, /*!< Index of access permissions for channel 13 of DPPIC020 */ 1548 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_14 = 46, /*!< Index of access permissions for channel 14 of DPPIC020 */ 1549 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_15 = 47, /*!< Index of access permissions for channel 15 of DPPIC020 */ 1550 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_16 = 48, /*!< Index of access permissions for channel 16 of DPPIC020 */ 1551 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_17 = 49, /*!< Index of access permissions for channel 17 of DPPIC020 */ 1552 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_18 = 50, /*!< Index of access permissions for channel 18 of DPPIC020 */ 1553 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_19 = 51, /*!< Index of access permissions for channel 19 of DPPIC020 */ 1554 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_20 = 52, /*!< Index of access permissions for channel 20 of DPPIC020 */ 1555 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_21 = 53, /*!< Index of access permissions for channel 21 of DPPIC020 */ 1556 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_22 = 54, /*!< Index of access permissions for channel 22 of DPPIC020 */ 1557 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_23 = 55, /*!< Index of access permissions for channel 23 of DPPIC020 */ 1558 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_24 = 56, /*!< Index of access permissions for channel 24 of DPPIC020 */ 1559 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_25 = 57, /*!< Index of access permissions for channel 25 of DPPIC020 */ 1560 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_26 = 58, /*!< Index of access permissions for channel 26 of DPPIC020 */ 1561 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_27 = 59, /*!< Index of access permissions for channel 27 of DPPIC020 */ 1562 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_28 = 60, /*!< Index of access permissions for channel 28 of DPPIC020 */ 1563 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_29 = 61, /*!< Index of access permissions for channel 29 of DPPIC020 */ 1564 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_30 = 62, /*!< Index of access permissions for channel 30 of DPPIC020 */ 1565 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_31 = 63, /*!< Index of access permissions for channel 31 of DPPIC020 */ 1566 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_0 = 64, /*!< Index of access permissions for channel group 0 of DPPIC020 */ 1567 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_1 = 65, /*!< Index of access permissions for channel group 1 of DPPIC020 */ 1568 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_2 = 66, /*!< Index of access permissions for channel group 2 of DPPIC020 */ 1569 NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_3 = 67, /*!< Index of access permissions for channel group 3 of DPPIC020 */ 1570 } NRF_RADIOCORE_SPU020_FEATURES_ENUM_t; 1571 1572 /* ============================================= SPU030 Split Security Features ============================================== */ 1573 /** 1574 * @brief Indexes in SPU030.FEATURES controlling access permissions of features with split security 1575 */ 1576 typedef enum { 1577 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_0 = 32, /*!< Index of access permissions for channel 0 of DPPIC030 */ 1578 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_1 = 33, /*!< Index of access permissions for channel 1 of DPPIC030 */ 1579 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_2 = 34, /*!< Index of access permissions for channel 2 of DPPIC030 */ 1580 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_3 = 35, /*!< Index of access permissions for channel 3 of DPPIC030 */ 1581 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_4 = 36, /*!< Index of access permissions for channel 4 of DPPIC030 */ 1582 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_5 = 37, /*!< Index of access permissions for channel 5 of DPPIC030 */ 1583 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_6 = 38, /*!< Index of access permissions for channel 6 of DPPIC030 */ 1584 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_7 = 39, /*!< Index of access permissions for channel 7 of DPPIC030 */ 1585 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_8 = 40, /*!< Index of access permissions for channel 8 of DPPIC030 */ 1586 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_9 = 41, /*!< Index of access permissions for channel 9 of DPPIC030 */ 1587 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_10 = 42, /*!< Index of access permissions for channel 10 of DPPIC030 */ 1588 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_11 = 43, /*!< Index of access permissions for channel 11 of DPPIC030 */ 1589 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_12 = 44, /*!< Index of access permissions for channel 12 of DPPIC030 */ 1590 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_13 = 45, /*!< Index of access permissions for channel 13 of DPPIC030 */ 1591 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_14 = 46, /*!< Index of access permissions for channel 14 of DPPIC030 */ 1592 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_15 = 47, /*!< Index of access permissions for channel 15 of DPPIC030 */ 1593 NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CHG_0 = 56, /*!< Index of access permissions for channel group 0 of DPPIC030 */ 1594 } NRF_RADIOCORE_SPU030_FEATURES_ENUM_t; 1595 1596 1597 #ifdef __cplusplus 1598 } 1599 #endif 1600 #endif /* NRF54H20_RADIOCORE_PERIPHERALS_H */ 1601 1602
