1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_PPR_H 36 #define NRF54H20_PPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_PPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRTIM_IRQn = 16, /*!< 16 VPRTIM */ 70 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 71 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 72 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 73 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 74 GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ 75 TBM_IRQn = 127, /*!< 127 TBM */ 76 USBHS_IRQn = 134, /*!< 134 USBHS */ 77 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 78 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 79 I3C120_IRQn = 211, /*!< 211 I3C120 */ 80 VPR121_IRQn = 212, /*!< 212 VPR121 */ 81 CAN120_IRQn = 216, /*!< 216 CAN120 */ 82 MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ 83 I3C121_IRQn = 222, /*!< 222 I3C121 */ 84 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 85 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 86 PWM120_IRQn = 228, /*!< 228 PWM120 */ 87 SPIS120_IRQn = 229, /*!< 229 SPIS120 */ 88 SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ 89 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 90 VPR130_IRQn = 264, /*!< 264 VPR130 */ 91 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 92 RTC130_IRQn = 296, /*!< 296 RTC130 */ 93 RTC131_IRQn = 297, /*!< 297 RTC131 */ 94 WDT131_IRQn = 299, /*!< 299 WDT131 */ 95 WDT132_IRQn = 300, /*!< 300 WDT132 */ 96 EGU130_IRQn = 301, /*!< 301 EGU130 */ 97 SAADC_IRQn = 386, /*!< 386 SAADC */ 98 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 99 TEMP_IRQn = 388, /*!< 388 TEMP */ 100 NFCT_IRQn = 389, /*!< 389 NFCT */ 101 TDM130_IRQn = 402, /*!< 402 TDM130 */ 102 PDM_IRQn = 403, /*!< 403 PDM */ 103 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 104 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 105 SIMIF130_IRQn = 406, /*!< 406 SIMIF130 */ 106 TDM131_IRQn = 407, /*!< 407 TDM131 */ 107 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 108 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 109 PWM130_IRQn = 420, /*!< 420 PWM130 */ 110 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 111 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 112 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 113 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 114 PWM131_IRQn = 436, /*!< 436 PWM131 */ 115 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 116 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 117 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 118 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 119 PWM132_IRQn = 452, /*!< 452 PWM132 */ 120 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 121 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 122 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 123 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 124 PWM133_IRQn = 468, /*!< 468 PWM133 */ 125 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 126 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 127 } IRQn_Type; 128 129 /* ==================================================== Interrupt Aliases ==================================================== */ 130 #define SPIM120_IRQn SPIM120_UARTE120_IRQn 131 #define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler 132 #define UARTE120_IRQn SPIM120_UARTE120_IRQn 133 #define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler 134 #define COMP_IRQn COMP_LPCOMP_IRQn 135 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 136 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 137 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 138 #define SPIM130_IRQn SERIAL0_IRQn 139 #define SPIM130_IRQHandler SERIAL0_IRQHandler 140 #define SPIS130_IRQn SERIAL0_IRQn 141 #define SPIS130_IRQHandler SERIAL0_IRQHandler 142 #define TWIM130_IRQn SERIAL0_IRQn 143 #define TWIM130_IRQHandler SERIAL0_IRQHandler 144 #define TWIS130_IRQn SERIAL0_IRQn 145 #define TWIS130_IRQHandler SERIAL0_IRQHandler 146 #define UARTE130_IRQn SERIAL0_IRQn 147 #define UARTE130_IRQHandler SERIAL0_IRQHandler 148 #define SPIM131_IRQn SERIAL1_IRQn 149 #define SPIM131_IRQHandler SERIAL1_IRQHandler 150 #define SPIS131_IRQn SERIAL1_IRQn 151 #define SPIS131_IRQHandler SERIAL1_IRQHandler 152 #define TWIM131_IRQn SERIAL1_IRQn 153 #define TWIM131_IRQHandler SERIAL1_IRQHandler 154 #define TWIS131_IRQn SERIAL1_IRQn 155 #define TWIS131_IRQHandler SERIAL1_IRQHandler 156 #define UARTE131_IRQn SERIAL1_IRQn 157 #define UARTE131_IRQHandler SERIAL1_IRQHandler 158 #define SPIM132_IRQn SERIAL2_IRQn 159 #define SPIM132_IRQHandler SERIAL2_IRQHandler 160 #define SPIS132_IRQn SERIAL2_IRQn 161 #define SPIS132_IRQHandler SERIAL2_IRQHandler 162 #define TWIM132_IRQn SERIAL2_IRQn 163 #define TWIM132_IRQHandler SERIAL2_IRQHandler 164 #define TWIS132_IRQn SERIAL2_IRQn 165 #define TWIS132_IRQHandler SERIAL2_IRQHandler 166 #define UARTE132_IRQn SERIAL2_IRQn 167 #define UARTE132_IRQHandler SERIAL2_IRQHandler 168 #define SPIM133_IRQn SERIAL3_IRQn 169 #define SPIM133_IRQHandler SERIAL3_IRQHandler 170 #define SPIS133_IRQn SERIAL3_IRQn 171 #define SPIS133_IRQHandler SERIAL3_IRQHandler 172 #define TWIM133_IRQn SERIAL3_IRQn 173 #define TWIM133_IRQHandler SERIAL3_IRQHandler 174 #define TWIS133_IRQn SERIAL3_IRQn 175 #define TWIS133_IRQHandler SERIAL3_IRQHandler 176 #define UARTE133_IRQn SERIAL3_IRQn 177 #define UARTE133_IRQHandler SERIAL3_IRQHandler 178 #define SPIM134_IRQn SERIAL4_IRQn 179 #define SPIM134_IRQHandler SERIAL4_IRQHandler 180 #define SPIS134_IRQn SERIAL4_IRQn 181 #define SPIS134_IRQHandler SERIAL4_IRQHandler 182 #define TWIM134_IRQn SERIAL4_IRQn 183 #define TWIM134_IRQHandler SERIAL4_IRQHandler 184 #define TWIS134_IRQn SERIAL4_IRQn 185 #define TWIS134_IRQHandler SERIAL4_IRQHandler 186 #define UARTE134_IRQn SERIAL4_IRQn 187 #define UARTE134_IRQHandler SERIAL4_IRQHandler 188 #define SPIM135_IRQn SERIAL5_IRQn 189 #define SPIM135_IRQHandler SERIAL5_IRQHandler 190 #define SPIS135_IRQn SERIAL5_IRQn 191 #define SPIS135_IRQHandler SERIAL5_IRQHandler 192 #define TWIM135_IRQn SERIAL5_IRQn 193 #define TWIM135_IRQHandler SERIAL5_IRQHandler 194 #define TWIS135_IRQn SERIAL5_IRQn 195 #define TWIS135_IRQHandler SERIAL5_IRQHandler 196 #define UARTE135_IRQn SERIAL5_IRQn 197 #define UARTE135_IRQHandler SERIAL5_IRQHandler 198 #define SPIM136_IRQn SERIAL6_IRQn 199 #define SPIM136_IRQHandler SERIAL6_IRQHandler 200 #define SPIS136_IRQn SERIAL6_IRQn 201 #define SPIS136_IRQHandler SERIAL6_IRQHandler 202 #define TWIM136_IRQn SERIAL6_IRQn 203 #define TWIM136_IRQHandler SERIAL6_IRQHandler 204 #define TWIS136_IRQn SERIAL6_IRQn 205 #define TWIS136_IRQHandler SERIAL6_IRQHandler 206 #define UARTE136_IRQn SERIAL6_IRQn 207 #define UARTE136_IRQHandler SERIAL6_IRQHandler 208 #define SPIM137_IRQn SERIAL7_IRQn 209 #define SPIM137_IRQHandler SERIAL7_IRQHandler 210 #define SPIS137_IRQn SERIAL7_IRQn 211 #define SPIS137_IRQHandler SERIAL7_IRQHandler 212 #define TWIM137_IRQn SERIAL7_IRQn 213 #define TWIM137_IRQHandler SERIAL7_IRQHandler 214 #define TWIS137_IRQn SERIAL7_IRQn 215 #define TWIS137_IRQHandler SERIAL7_IRQHandler 216 #define UARTE137_IRQn SERIAL7_IRQn 217 #define UARTE137_IRQHandler SERIAL7_IRQHandler 218 219 /* =========================================================================================================================== */ 220 /* ================ Processor and Core Peripheral Section ================ */ 221 /* =========================================================================================================================== */ 222 223 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 224 #define __VPR_REV 1.1 /*!< VPR Core Revision */ 225 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 226 #define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ 227 #define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ 228 #define __DSP_PRESENT 0 /*!< DSP present or not */ 229 #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 230 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 231 #define __MPU_PRESENT 1 /*!< MPU present */ 232 #define __FPU_PRESENT 0 /*!< FPU present */ 233 #define __FPU_DP 0 /*!< Double Precision FPU */ 234 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 235 236 #define NRF_VPR NRF_VPR130 /*!< VPR instance name */ 237 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 238 #include "system_nrf.h" /*!< nrf54h20_ppr System Library */ 239 240 #endif /*!< NRF_PPR */ 241 242 243 #ifdef NRF_PPR 244 245 #define NRF_DOMAIN NRF_DOMAIN_GLOBALSLOW 246 #define NRF_PROCESSOR NRF_PROCESSOR_PPR 247 #ifndef NRF_OWNER 248 #define NRF_OWNER NRF_OWNER_APPLICATION 249 #endif 250 251 #endif /*!< NRF_PPR */ 252 253 254 /* ========================================= Start of section using anonymous unions ========================================= */ 255 256 #include "compiler_abstraction.h" 257 258 #if defined (__CC_ARM) 259 #pragma push 260 #pragma anon_unions 261 #elif defined (__ICCARM__) 262 #pragma language=extended 263 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 264 #pragma clang diagnostic push 265 #pragma clang diagnostic ignored "-Wc11-extensions" 266 #pragma clang diagnostic ignored "-Wreserved-id-macro" 267 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 268 #pragma clang diagnostic ignored "-Wnested-anon-types" 269 #elif defined (__GNUC__) 270 /* anonymous unions are enabled by default */ 271 #elif defined (__TMS470__) 272 /* anonymous unions are enabled by default */ 273 #elif defined (__TASKING__) 274 #pragma warning 586 275 #elif defined (__CSMC__) 276 /* anonymous unions are enabled by default */ 277 #else 278 #warning Unsupported compiler type 279 #endif 280 281 /* =========================================================================================================================== */ 282 /* ================ Peripheral Address Map ================ */ 283 /* =========================================================================================================================== */ 284 285 #define NRF_PPR_VPRCLIC_BASE 0xF0000000UL 286 287 /* =========================================================================================================================== */ 288 /* ================ Peripheral Declaration ================ */ 289 /* =========================================================================================================================== */ 290 291 #define NRF_PPR_VPRCLIC ((NRF_CLIC_Type*) NRF_PPR_VPRCLIC_BASE) 292 293 /* =========================================================================================================================== */ 294 /* ================ Local Domain Remapping ================ */ 295 /* =========================================================================================================================== */ 296 297 #ifdef NRF_PPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 298 #define NRF_VPRCLIC NRF_PPR_VPRCLIC 299 #endif /*!< NRF_PPR */ 300 301 /* ========================================== End of section using anonymous unions ========================================== */ 302 303 #if defined (__CC_ARM) 304 #pragma pop 305 #elif defined (__ICCARM__) 306 /* leave anonymous unions enabled */ 307 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 308 #pragma clang diagnostic pop 309 #elif defined (__GNUC__) 310 /* anonymous unions are enabled by default */ 311 #elif defined (__TMS470__) 312 /* anonymous unions are enabled by default */ 313 #elif defined (__TASKING__) 314 #pragma warning restore 315 #elif defined (__CSMC__) 316 /* anonymous unions are enabled by default */ 317 #endif 318 319 320 #ifdef __cplusplus 321 } 322 #endif 323 #endif /* NRF54H20_PPR_H */ 324 325
