1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_RADIOCORE_PERIPHERALS_H 36 #define NRF54H20_ENGA_RADIOCORE_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*User information configuration registers*/ 44 #define UICR_PRESENT 1 45 #define UICR_COUNT 1 46 47 /*CACHEDATA*/ 48 #define CACHEDATA_PRESENT 1 49 #define CACHEDATA_COUNT 2 50 51 /*CACHEINFO*/ 52 #define CACHEINFO_PRESENT 1 53 #define CACHEINFO_COUNT 2 54 55 /*Embedded Trace Macrocell*/ 56 #define ETM_PRESENT 1 57 #define ETM_COUNT 1 58 59 /*Cross-Trigger Interface control*/ 60 #define CTI_PRESENT 1 61 #define CTI_COUNT 3 62 63 /*CM33 SubSystem*/ 64 #define CM33SS_PRESENT 1 65 #define CM33SS_COUNT 1 66 67 #define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ 68 69 /*Cache*/ 70 #define CACHE_PRESENT 1 71 #define CACHE_COUNT 2 72 73 #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 74 #define ICACHE_FLUSH 1 /*!< (unspecified) */ 75 #define ICACHE_CLEAN 0 /*!< (unspecified) */ 76 77 #define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 78 #define DCACHE_FLUSH 1 /*!< (unspecified) */ 79 #define DCACHE_CLEAN 1 /*!< (unspecified) */ 80 81 /*System protection unit*/ 82 #define SPU_PRESENT 1 83 #define SPU_COUNT 4 84 85 #define SPU000_BELLS 0 /*!< (unspecified) */ 86 #define SPU000_IPCT 0 /*!< (unspecified) */ 87 #define SPU000_DPPI 0 /*!< (unspecified) */ 88 #define SPU000_GPIOTE 0 /*!< (unspecified) */ 89 #define SPU000_GRTC 1 /*!< (unspecified) */ 90 #define SPU000_GPIO 0 /*!< (unspecified) */ 91 92 #define SPU010_BELLS 0 /*!< (unspecified) */ 93 #define SPU010_IPCT 0 /*!< (unspecified) */ 94 #define SPU010_DPPI 0 /*!< (unspecified) */ 95 #define SPU010_GPIOTE 0 /*!< (unspecified) */ 96 #define SPU010_GRTC 1 /*!< (unspecified) */ 97 #define SPU010_GPIO 0 /*!< (unspecified) */ 98 99 #define SPU020_BELLS 0 /*!< (unspecified) */ 100 #define SPU020_IPCT 1 /*!< (unspecified) */ 101 #define SPU020_DPPI 1 /*!< (unspecified) */ 102 #define SPU020_GPIOTE 0 /*!< (unspecified) */ 103 #define SPU020_GRTC 1 /*!< (unspecified) */ 104 #define SPU020_GPIO 0 /*!< (unspecified) */ 105 106 #define SPU030_BELLS 0 /*!< (unspecified) */ 107 #define SPU030_IPCT 0 /*!< (unspecified) */ 108 #define SPU030_DPPI 1 /*!< (unspecified) */ 109 #define SPU030_GPIOTE 0 /*!< (unspecified) */ 110 #define SPU030_GRTC 1 /*!< (unspecified) */ 111 #define SPU030_GPIO 0 /*!< (unspecified) */ 112 113 /*Memory Privilege Controller*/ 114 #define MPC_PRESENT 1 115 #define MPC_COUNT 1 116 117 #define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 118 #define MPC_RTCHOKE 1 /*!< (unspecified) */ 119 #define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 120 121 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 122 123 #define MVDMA_PRESENT 1 124 #define MVDMA_COUNT 1 125 126 /*RAM Controller*/ 127 #define RAMC_PRESENT 1 128 #define RAMC_COUNT 2 129 130 #define RAMC000_ECC 0 /*!< (unspecified) */ 131 #define RAMC000_SEC 1 /*!< (unspecified) */ 132 133 #define RAMC001_ECC 0 /*!< (unspecified) */ 134 #define RAMC001_SEC 0 /*!< (unspecified) */ 135 136 /*HSFLL*/ 137 #define HSFLL_PRESENT 1 138 #define HSFLL_COUNT 1 139 140 #define HSFLL_DITHER_32B 0 /*!< (unspecified) */ 141 #define HSFLL_CLOCKCTRL_MULT_RESET 6 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ 142 143 /*LRCCONF*/ 144 #define LRCCONF_PRESENT 1 145 #define LRCCONF_COUNT 3 146 147 #define LRCCONF000_POWERON 0 /*!< (unspecified) */ 148 #define LRCCONF000_RETAIN 0 /*!< (unspecified) */ 149 #define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ 150 #define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ 151 #define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ 152 #define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ 153 #define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ 154 #define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ 155 #define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ 156 #define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ 157 #define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ 158 #define LRCCONF000_PDACT 0 /*!< (unspecified) */ 159 #define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ 160 #define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ 161 #define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ 162 #define LRCCONF000_OTHERON 0 /*!< (unspecified) */ 163 #define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ 164 #define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ 165 #define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ 166 #define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ 167 #define LRCCONF000_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 168 #define LRCCONF000_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 169 #define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 170 #define LRCCONF000_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 171 172 #define LRCCONF010_POWERON 1 /*!< (unspecified) */ 173 #define LRCCONF010_RETAIN 1 /*!< (unspecified) */ 174 #define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ 175 #define LRCCONF010_LRCREQHFXO 0 /*!< (unspecified) */ 176 #define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ 177 #define LRCCONF010_NCLK_MAX 7 /*!< (unspecified) */ 178 #define LRCCONF010_NCLK_SIZE 8 /*!< (unspecified) */ 179 #define LRCCONF010_CLKCTRL 0 /*!< (unspecified) */ 180 #define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ 181 #define LRCCONF010_NACTPD_MAX 1 /*!< (unspecified) */ 182 #define LRCCONF010_NACTPD_SIZE 2 /*!< (unspecified) */ 183 #define LRCCONF010_PDACT 1 /*!< (unspecified) */ 184 #define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ 185 #define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ 186 #define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ 187 #define LRCCONF010_OTHERON 0 /*!< (unspecified) */ 188 #define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ 189 #define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ 190 #define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ 191 #define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ 192 #define LRCCONF010_POWERON_MAIN_RESET 1 /*!< Reset value of register POWERON.MAIN: 1 */ 193 #define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 194 #define LRCCONF010_RETAIN_MAIN_RESET 0 /*!< Reset value of register RETAIN.MAIN: 0 */ 195 #define LRCCONF010_RETAIN_ACT_RESET 0 /*!< Reset value of register RETAIN.ACT: 0 */ 196 197 #define LRCCONF020_POWERON 0 /*!< (unspecified) */ 198 #define LRCCONF020_RETAIN 0 /*!< (unspecified) */ 199 #define LRCCONF020_SYSTEMOFF 0 /*!< (unspecified) */ 200 #define LRCCONF020_LRCREQHFXO 0 /*!< (unspecified) */ 201 #define LRCCONF020_NCLK_MIN 0 /*!< (unspecified) */ 202 #define LRCCONF020_NCLK_MAX 7 /*!< (unspecified) */ 203 #define LRCCONF020_NCLK_SIZE 8 /*!< (unspecified) */ 204 #define LRCCONF020_CLKCTRL 0 /*!< (unspecified) */ 205 #define LRCCONF020_NACTPD_MIN 0 /*!< (unspecified) */ 206 #define LRCCONF020_NACTPD_MAX 7 /*!< (unspecified) */ 207 #define LRCCONF020_NACTPD_SIZE 8 /*!< (unspecified) */ 208 #define LRCCONF020_PDACT 0 /*!< (unspecified) */ 209 #define LRCCONF020_NPD_MIN 0 /*!< (unspecified) */ 210 #define LRCCONF020_NPD_MAX 7 /*!< (unspecified) */ 211 #define LRCCONF020_NPD_SIZE 8 /*!< (unspecified) */ 212 #define LRCCONF020_OTHERON 0 /*!< (unspecified) */ 213 #define LRCCONF020_NDOMAINS_MIN 0 /*!< (unspecified) */ 214 #define LRCCONF020_NDOMAINS_MAX 15 /*!< (unspecified) */ 215 #define LRCCONF020_NDOMAINS_SIZE 16 /*!< (unspecified) */ 216 #define LRCCONF020_AX2XWAITSTATES 0 /*!< (unspecified) */ 217 #define LRCCONF020_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 218 #define LRCCONF020_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 219 #define LRCCONF020_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 220 #define LRCCONF020_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 221 222 /*Memory configuration*/ 223 #define MEMCONF_PRESENT 1 224 #define MEMCONF_COUNT 1 225 226 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 227 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 228 #define MEMCONF_POWER 1 /*!< (unspecified) */ 229 230 /*Watchdog Timer*/ 231 #define WDT_PRESENT 1 232 #define WDT_COUNT 4 233 234 /*RESETINFO*/ 235 #define RESETINFO_PRESENT 1 236 #define RESETINFO_COUNT 1 237 238 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ 239 240 /*Distributed programmable peripheral interconnect controller*/ 241 #define DPPIC_PRESENT 1 242 #define DPPIC_COUNT 9 243 244 #define DPPIC020_HASCHANNELGROUPS 1 /*!< (unspecified) */ 245 #define DPPIC020_CH_NUM_MIN 0 /*!< (unspecified) */ 246 #define DPPIC020_CH_NUM_MAX 15 /*!< (unspecified) */ 247 #define DPPIC020_CH_NUM_SIZE 16 /*!< (unspecified) */ 248 #define DPPIC020_GROUP_NUM_MIN 0 /*!< (unspecified) */ 249 #define DPPIC020_GROUP_NUM_MAX 1 /*!< (unspecified) */ 250 #define DPPIC020_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 251 252 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 253 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 254 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 255 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 256 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 257 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 258 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 259 260 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 261 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 262 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 263 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 264 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 265 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 266 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 267 268 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 269 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 270 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 271 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 272 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 273 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 274 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 275 276 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 277 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 278 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 279 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 280 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 281 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 282 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 283 284 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 285 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 286 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 287 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 288 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 289 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 290 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 291 292 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 293 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 294 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 295 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 296 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 297 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 298 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 299 300 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 301 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 302 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 303 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 304 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 305 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 306 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 307 308 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 309 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 310 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 311 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 312 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 313 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 314 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 315 316 /*PPIB APB registers*/ 317 #define PPIB_PRESENT 1 318 #define PPIB_COUNT 2 319 320 /*Event generator unit*/ 321 #define EGU_PRESENT 1 322 #define EGU_COUNT 1 323 324 #define EGU020_PEND 0 /*!< (unspecified) */ 325 #define EGU020_CH_NUM_MIN 0 /*!< (unspecified) */ 326 #define EGU020_CH_NUM_MAX 15 /*!< (unspecified) */ 327 #define EGU020_CH_NUM_SIZE 16 /*!< (unspecified) */ 328 329 /*Accelerated Address Resolver*/ 330 #define AAR_PRESENT 1 331 #define AAR_COUNT 2 332 333 /*AES CCM Mode Encryption*/ 334 #define CCM_PRESENT 1 335 #define CCM_COUNT 2 336 337 /*AES ECB Mode Encryption*/ 338 #define ECB_PRESENT 1 339 #define ECB_COUNT 2 340 341 #define ECB020_AMOUNTREG 1 /*!< (unspecified) */ 342 343 #define ECB030_AMOUNTREG 1 /*!< (unspecified) */ 344 345 /*Timer/Counter*/ 346 #define TIMER_PRESENT 1 347 #define TIMER_COUNT 13 348 349 #define TIMER020_CC_NUM_MIN 0 /*!< (unspecified) */ 350 #define TIMER020_CC_NUM_MAX 7 /*!< (unspecified) */ 351 #define TIMER020_CC_NUM_SIZE 8 /*!< (unspecified) */ 352 #define TIMER020_MAX_SIZE_MIN 0 /*!< (unspecified) */ 353 #define TIMER020_MAX_SIZE_MAX 31 /*!< (unspecified) */ 354 #define TIMER020_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 355 356 #define TIMER021_CC_NUM_MIN 0 /*!< (unspecified) */ 357 #define TIMER021_CC_NUM_MAX 7 /*!< (unspecified) */ 358 #define TIMER021_CC_NUM_SIZE 8 /*!< (unspecified) */ 359 #define TIMER021_MAX_SIZE_MIN 0 /*!< (unspecified) */ 360 #define TIMER021_MAX_SIZE_MAX 31 /*!< (unspecified) */ 361 #define TIMER021_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 362 363 #define TIMER022_CC_NUM_MIN 0 /*!< (unspecified) */ 364 #define TIMER022_CC_NUM_MAX 7 /*!< (unspecified) */ 365 #define TIMER022_CC_NUM_SIZE 8 /*!< (unspecified) */ 366 #define TIMER022_MAX_SIZE_MIN 0 /*!< (unspecified) */ 367 #define TIMER022_MAX_SIZE_MAX 31 /*!< (unspecified) */ 368 #define TIMER022_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 369 370 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 371 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 372 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 373 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 374 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 375 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 376 377 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 378 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 379 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 380 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 381 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 382 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 383 384 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 385 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 386 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 387 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 388 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 389 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 390 391 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 392 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 393 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 394 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 395 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 396 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 397 398 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 399 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 400 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 401 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 402 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 403 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 404 405 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 406 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 407 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 408 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 409 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 410 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 411 412 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 413 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 414 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 415 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 416 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 417 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 418 419 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 420 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 421 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 422 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 423 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 424 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 425 426 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 427 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 428 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 429 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 430 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 431 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 432 433 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 434 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 435 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 436 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 437 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 438 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 439 440 /*Real-time counter*/ 441 #define RTC_PRESENT 1 442 #define RTC_COUNT 3 443 444 #define RTC_CC_NUM_MIN 0 /*!< (unspecified) */ 445 #define RTC_CC_NUM_MAX 7 /*!< (unspecified) */ 446 #define RTC_CC_NUM_SIZE 8 /*!< (unspecified) */ 447 #define RTC_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 448 #define RTC_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 449 #define RTC_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 450 #define RTC_LFCLK_ENABLE 0 /*!< (unspecified) */ 451 452 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 453 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 454 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 455 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 456 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 457 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 458 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 459 460 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 461 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 462 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 463 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 464 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 465 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 466 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 467 468 /*2.4 GHz radio*/ 469 #define RADIO_PRESENT 1 470 #define RADIO_COUNT 1 471 472 #define RADIO_IRQ_COUNT 2 473 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 474 #define RADIO_PERPOWER 0 /*!< (unspecified) */ 475 476 /*VPR peripheral registers*/ 477 #define VPR_PRESENT 1 478 #define VPR_COUNT 3 479 480 #define VPR_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 481 #define VPR_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 482 #define VPR_RAM_BASE_ADDR 0x23010000 /*!< (unspecified) */ 483 #define VPR_RAM_SZ 15 /*!< (unspecified) */ 484 #define VPR_RETAINED 1 /*!< (unspecified) */ 485 #define VPR_VPRSAVEDCTX 0 /*!< (unspecified) */ 486 #define VPR_VPRSAVEADDR 0x00000000 /*!< (unspecified) */ 487 #define VPR_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 488 #define VPR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 489 #define VPR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 490 #define VPR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 491 #define VPR_VEVIF_TASKS_MASK 0x0000FF00 /*!< Mask of supported VEVIF tasks: 0x0000FF00 */ 492 #define VPR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..10 */ 493 #define VPR_VEVIF_NDPPI_MAX 10 /*!< VEVIF DPPI channels: 8..10 */ 494 #define VPR_VEVIF_NDPPI_SIZE 11 /*!< VEVIF DPPI channels: 8..10 */ 495 #define VPR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 496 #define VPR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 497 #define VPR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 498 #define VPR_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x53034400 */ 499 500 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 501 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 502 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 503 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 504 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 505 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 506 #define VPR121_RETAINED 0 /*!< (unspecified) */ 507 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 508 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 509 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 510 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 511 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 512 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 513 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 514 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 515 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 516 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 517 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 518 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 519 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 520 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 521 522 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 523 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 524 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 525 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 526 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 527 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 528 #define VPR130_RETAINED 0 /*!< (unspecified) */ 529 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 530 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 531 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 532 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 533 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 534 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 535 #define VPR130_VEVIF_TASKS_MASK 0xFFFFFFF0 /*!< Mask of supported VEVIF tasks: 0xFFFFFFF0 */ 536 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 537 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 538 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 539 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 540 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 541 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 542 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 543 544 /*IPCT APB registers*/ 545 #define IPCT_PRESENT 1 546 #define IPCT_COUNT 3 547 548 #define IPCT_IRQ_COUNT 2 549 550 #define IPCT120_IRQ_COUNT 1 551 552 #define IPCT130_IRQ_COUNT 1 553 554 /*BELLBOARD APB registers*/ 555 #define BELLBOARD_PRESENT 1 556 #define BELLBOARD_COUNT 1 557 558 #define BELLBOARD_IRQ_COUNT 4 559 560 /*Factory Information Configuration Registers*/ 561 #define FICR_PRESENT 1 562 #define FICR_COUNT 1 563 564 /*USBHSCORE*/ 565 #define USBHSCORE_PRESENT 1 566 #define USBHSCORE_COUNT 1 567 568 /*I3CCORE*/ 569 #define I3CCORE_PRESENT 1 570 #define I3CCORE_COUNT 2 571 572 /*DMU*/ 573 #define DMU_PRESENT 1 574 #define DMU_COUNT 1 575 576 /*MCAN*/ 577 #define MCAN_PRESENT 1 578 #define MCAN_COUNT 1 579 580 /*System Trace Macrocell data buffer*/ 581 #define STMDATA_PRESENT 1 582 #define STMDATA_COUNT 1 583 584 /*TDDCONF*/ 585 #define TDDCONF_PRESENT 1 586 #define TDDCONF_COUNT 1 587 588 /*System Trace Macrocell*/ 589 #define STM_PRESENT 1 590 #define STM_COUNT 1 591 592 /*Trace Port Interface Unit*/ 593 #define TPIU_PRESENT 1 594 #define TPIU_COUNT 1 595 596 /*ATB Replicator module*/ 597 #define ATBREPLICATOR_PRESENT 1 598 #define ATBREPLICATOR_COUNT 4 599 600 /*ATB funnel module*/ 601 #define ATBFUNNEL_PRESENT 1 602 #define ATBFUNNEL_COUNT 4 603 604 /*GPIO Tasks and Events*/ 605 #define GPIOTE_PRESENT 1 606 #define GPIOTE_COUNT 1 607 608 #define GPIOTE130_IRQ_COUNT 2 609 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 610 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 611 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 612 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 613 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 614 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 615 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 616 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 617 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 618 619 /*Global Real-time counter*/ 620 #define GRTC_PRESENT 1 621 #define GRTC_COUNT 1 622 623 #define GRTC_IRQ_COUNT 2 624 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 625 0..14*/ 626 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 627 0..14*/ 628 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 629 0..14*/ 630 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 631 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 632 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 633 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 634 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 635 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 636 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 637 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 638 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 639 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..1 */ 640 #define GRTC_GRTC_NINTERRUPTS_MAX 1 /*!< Number of GRTC interrupts : 0..1 */ 641 #define GRTC_GRTC_NINTERRUPTS_SIZE 2 /*!< Number of GRTC interrupts : 0..1 */ 642 #define GRTC_PWMREGS 0 /*!< (unspecified) */ 643 #define GRTC_CLKOUTREG 0 /*!< (unspecified) */ 644 645 /*Trace buffer monitor*/ 646 #define TBM_PRESENT 1 647 #define TBM_COUNT 1 648 649 /*USBHS*/ 650 #define USBHS_PRESENT 1 651 #define USBHS_COUNT 1 652 653 /*External Memory Interface*/ 654 #define EXMIF_PRESENT 1 655 #define EXMIF_COUNT 1 656 657 /*BELLBOARD public registers*/ 658 #define BELLBOARDPUBLIC_PRESENT 1 659 #define BELLBOARDPUBLIC_COUNT 1 660 661 /*VPR peripheral registers*/ 662 #define VPRPUBLIC_PRESENT 1 663 #define VPRPUBLIC_COUNT 1 664 665 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 666 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 667 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 668 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 669 670 /*MUTEX*/ 671 #define MUTEX_PRESENT 1 672 #define MUTEX_COUNT 2 673 674 /*I3C*/ 675 #define I3C_PRESENT 1 676 #define I3C_COUNT 2 677 678 /*Controller Area Network*/ 679 #define CAN_PRESENT 1 680 #define CAN_COUNT 1 681 682 /*Pulse width modulation unit*/ 683 #define PWM_PRESENT 1 684 #define PWM_COUNT 5 685 686 /*SPI Slave*/ 687 #define SPIS_PRESENT 1 688 #define SPIS_COUNT 9 689 690 #define SPIS120_LEGACYPSEL 0 /*!< (unspecified) */ 691 #define SPIS120_LEGACYEDMA 0 /*!< (unspecified) */ 692 693 #define SPIS130_LEGACYPSEL 0 /*!< (unspecified) */ 694 #define SPIS130_LEGACYEDMA 0 /*!< (unspecified) */ 695 696 #define SPIS131_LEGACYPSEL 0 /*!< (unspecified) */ 697 #define SPIS131_LEGACYEDMA 0 /*!< (unspecified) */ 698 699 #define SPIS132_LEGACYPSEL 0 /*!< (unspecified) */ 700 #define SPIS132_LEGACYEDMA 0 /*!< (unspecified) */ 701 702 #define SPIS133_LEGACYPSEL 0 /*!< (unspecified) */ 703 #define SPIS133_LEGACYEDMA 0 /*!< (unspecified) */ 704 705 #define SPIS134_LEGACYPSEL 0 /*!< (unspecified) */ 706 #define SPIS134_LEGACYEDMA 0 /*!< (unspecified) */ 707 708 #define SPIS135_LEGACYPSEL 0 /*!< (unspecified) */ 709 #define SPIS135_LEGACYEDMA 0 /*!< (unspecified) */ 710 711 #define SPIS136_LEGACYPSEL 0 /*!< (unspecified) */ 712 #define SPIS136_LEGACYEDMA 0 /*!< (unspecified) */ 713 714 #define SPIS137_LEGACYPSEL 0 /*!< (unspecified) */ 715 #define SPIS137_LEGACYEDMA 0 /*!< (unspecified) */ 716 717 /*UART with EasyDMA*/ 718 #define UARTE_PRESENT 1 719 #define UARTE_COUNT 9 720 721 #define UARTE120_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 722 #define UARTE120_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 723 #define UARTE120_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 724 725 #define UARTE130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 726 #define UARTE130_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 727 #define UARTE130_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 728 729 #define UARTE131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 730 #define UARTE131_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 731 #define UARTE131_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 732 733 #define UARTE132_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 734 #define UARTE132_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 735 #define UARTE132_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 736 737 #define UARTE133_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 738 #define UARTE133_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 739 #define UARTE133_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 740 741 #define UARTE134_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 742 #define UARTE134_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 743 #define UARTE134_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 744 745 #define UARTE135_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 746 #define UARTE135_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 747 #define UARTE135_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 748 749 #define UARTE136_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 750 #define UARTE136_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 751 #define UARTE136_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 752 753 #define UARTE137_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 754 #define UARTE137_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 755 #define UARTE137_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 756 757 /*Serial Peripheral Interface Master with EasyDMA*/ 758 #define SPIM_PRESENT 1 759 #define SPIM_COUNT 10 760 761 #define SPIM120_HSSPI 1 /*!< (unspecified) */ 762 763 #define SPIM121_HSSPI 1 /*!< (unspecified) */ 764 765 #define SPIM130_HSSPI 1 /*!< (unspecified) */ 766 767 #define SPIM131_HSSPI 1 /*!< (unspecified) */ 768 769 #define SPIM132_HSSPI 1 /*!< (unspecified) */ 770 771 #define SPIM133_HSSPI 1 /*!< (unspecified) */ 772 773 #define SPIM134_HSSPI 1 /*!< (unspecified) */ 774 775 #define SPIM135_HSSPI 1 /*!< (unspecified) */ 776 777 #define SPIM136_HSSPI 1 /*!< (unspecified) */ 778 779 #define SPIM137_HSSPI 1 /*!< (unspecified) */ 780 781 /*GPIO Port*/ 782 #define GPIO_PRESENT 1 783 #define GPIO_COUNT 6 784 785 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 786 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 787 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 788 #define P0_PIN_NUM_MAX 11 /*!< (unspecified) */ 789 #define P0_PIN_NUM_SIZE 12 /*!< (unspecified) */ 790 #define P0_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 791 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 792 #define P0_RETAIN 1 /*!< (unspecified) */ 793 #define P0_PWRCTRL 0 /*!< (unspecified) */ 794 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 795 #define P0_BIASCTRL 0 /*!< (unspecified) */ 796 797 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 798 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 799 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 800 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 801 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 802 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 803 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 804 #define P1_RETAIN 1 /*!< (unspecified) */ 805 #define P1_PWRCTRL 0 /*!< (unspecified) */ 806 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 807 #define P1_BIASCTRL 0 /*!< (unspecified) */ 808 809 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 810 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 811 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 812 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 813 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 814 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 815 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 816 #define P2_RETAIN 1 /*!< (unspecified) */ 817 #define P2_PWRCTRL 0 /*!< (unspecified) */ 818 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 819 #define P2_BIASCTRL 0 /*!< (unspecified) */ 820 821 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 822 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 823 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 824 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 825 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 826 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 827 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 828 #define P6_RETAIN 1 /*!< (unspecified) */ 829 #define P6_PWRCTRL 0 /*!< (unspecified) */ 830 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 831 #define P6_BIASCTRL 0 /*!< (unspecified) */ 832 833 #define P7_CTRLSEL_MAP1 1 /*!< (unspecified) */ 834 #define P7_CTRLSEL_MAP2 0 /*!< (unspecified) */ 835 #define P7_PIN_NUM_MIN 0 /*!< (unspecified) */ 836 #define P7_PIN_NUM_MAX 7 /*!< (unspecified) */ 837 #define P7_PIN_NUM_SIZE 8 /*!< (unspecified) */ 838 #define P7_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 839 #define P7_DRIVECTRL 1 /*!< (unspecified) */ 840 #define P7_RETAIN 1 /*!< (unspecified) */ 841 #define P7_PWRCTRL 0 /*!< (unspecified) */ 842 #define P7_PIN_OWNER_SEC 0 /*!< (unspecified) */ 843 #define P7_BIASCTRL 0 /*!< (unspecified) */ 844 845 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 846 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 847 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 848 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 849 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 850 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 851 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 852 #define P9_RETAIN 1 /*!< (unspecified) */ 853 #define P9_PWRCTRL 1 /*!< (unspecified) */ 854 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 855 #define P9_BIASCTRL 0 /*!< (unspecified) */ 856 857 /*Analog to Digital Converter*/ 858 #define SAADC_PRESENT 1 859 #define SAADC_COUNT 1 860 861 /*Comparator*/ 862 #define COMP_PRESENT 1 863 #define COMP_COUNT 1 864 865 /*Low-power comparator*/ 866 #define LPCOMP_PRESENT 1 867 #define LPCOMP_COUNT 1 868 869 /*Temperature Sensor*/ 870 #define TEMP_PRESENT 1 871 #define TEMP_COUNT 1 872 873 /*NFC-A compatible radio NFC-A compatible radio*/ 874 #define NFCT_PRESENT 1 875 #define NFCT_COUNT 1 876 877 /*Inter-IC Sound*/ 878 #define I2S_PRESENT 1 879 #define I2S_COUNT 2 880 881 #define I2S130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 882 #define I2S130_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 883 #define I2S130_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 884 885 #define I2S131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 886 #define I2S131_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 887 #define I2S131_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 888 889 /*Pulse Density Modulation (Digital Microphone) Interface*/ 890 #define PDM_PRESENT 1 891 #define PDM_COUNT 1 892 893 /*Quadrature Decoder*/ 894 #define QDEC_PRESENT 1 895 #define QDEC_COUNT 2 896 897 #define QDEC130_LEGACYPSEL 0 /*!< (unspecified) */ 898 899 #define QDEC131_LEGACYPSEL 0 /*!< (unspecified) */ 900 901 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 902 #define TWIM_PRESENT 1 903 #define TWIM_COUNT 8 904 905 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 906 #define TWIS_PRESENT 1 907 #define TWIS_COUNT 8 908 909 910 #ifdef __cplusplus 911 } 912 #endif 913 #endif /* NRF54H20_ENGA_RADIOCORE_PERIPHERALS_H */ 914 915
