1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_RADIOCORE_H 36 #define NRF54H20_ENGA_RADIOCORE_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_RADIOCORE /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 53 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 54 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 55 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No 56 Match*/ 57 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 58 related Fault*/ 59 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 60 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 61 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 62 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 63 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 64 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 65 /* ============================================== Processor Specific Interrupts ============================================== */ 66 SPU000_IRQn = 0, /*!< 0 SPU000 */ 67 MPC_IRQn = 1, /*!< 1 MPC */ 68 MVDMA_IRQn = 3, /*!< 3 MVDMA */ 69 SPU010_IRQn = 16, /*!< 16 SPU010 */ 70 WDT010_IRQn = 19, /*!< 19 WDT010 */ 71 WDT011_IRQn = 20, /*!< 20 WDT011 */ 72 SPU020_IRQn = 32, /*!< 32 SPU020 */ 73 EGU020_IRQn = 37, /*!< 37 EGU020 */ 74 AAR020_CCM020_IRQn = 38, /*!< 38 AAR020_CCM020 */ 75 ECB020_IRQn = 39, /*!< 39 ECB020 */ 76 TIMER020_IRQn = 40, /*!< 40 TIMER020 */ 77 TIMER021_IRQn = 41, /*!< 41 TIMER021 */ 78 TIMER022_IRQn = 42, /*!< 42 TIMER022 */ 79 RTC_IRQn = 43, /*!< 43 RTC */ 80 RADIO_0_IRQn = 44, /*!< 44 RADIO_0 */ 81 RADIO_1_IRQn = 45, /*!< 45 RADIO_1 */ 82 SPU030_IRQn = 48, /*!< 48 SPU030 */ 83 VPR_IRQn = 52, /*!< 52 VPR */ 84 AAR030_CCM030_IRQn = 58, /*!< 58 AAR030_CCM030 */ 85 ECB030_IRQn = 59, /*!< 59 ECB030 */ 86 IPCT_0_IRQn = 64, /*!< 64 IPCT_0 */ 87 IPCT_1_IRQn = 65, /*!< 65 IPCT_1 */ 88 BELLBOARD_0_IRQn = 96, /*!< 96 BELLBOARD_0 */ 89 BELLBOARD_1_IRQn = 97, /*!< 97 BELLBOARD_1 */ 90 BELLBOARD_2_IRQn = 98, /*!< 98 BELLBOARD_2 */ 91 BELLBOARD_3_IRQn = 99, /*!< 99 BELLBOARD_3 */ 92 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 93 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 94 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 95 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 96 TBM_IRQn = 127, /*!< 127 TBM */ 97 USBHS_IRQn = 134, /*!< 134 USBHS */ 98 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 99 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 100 I3C120_IRQn = 211, /*!< 211 I3C120 */ 101 VPR121_IRQn = 212, /*!< 212 VPR121 */ 102 CAN_IRQn = 216, /*!< 216 CAN */ 103 I3C121_IRQn = 222, /*!< 222 I3C121 */ 104 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 105 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 106 PWM120_IRQn = 228, /*!< 228 PWM120 */ 107 SPIS120_UARTE120_IRQn = 229, /*!< 229 SPIS120_UARTE120 */ 108 SPIM120_IRQn = 230, /*!< 230 SPIM120 */ 109 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 110 VPR130_IRQn = 264, /*!< 264 VPR130 */ 111 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 112 RTC130_IRQn = 296, /*!< 296 RTC130 */ 113 RTC131_IRQn = 297, /*!< 297 RTC131 */ 114 WDT131_IRQn = 299, /*!< 299 WDT131 */ 115 WDT132_IRQn = 300, /*!< 300 WDT132 */ 116 SAADC_IRQn = 386, /*!< 386 SAADC */ 117 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 118 TEMP_IRQn = 388, /*!< 388 TEMP */ 119 NFCT_IRQn = 389, /*!< 389 NFCT */ 120 I2S130_IRQn = 402, /*!< 402 I2S130 */ 121 PDM_IRQn = 403, /*!< 403 PDM */ 122 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 123 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 124 I2S131_IRQn = 407, /*!< 407 I2S131 */ 125 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 126 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 127 PWM130_IRQn = 420, /*!< 420 PWM130 */ 128 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 129 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 130 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 131 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 132 PWM131_IRQn = 436, /*!< 436 PWM131 */ 133 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 134 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 135 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 136 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 137 PWM132_IRQn = 452, /*!< 452 PWM132 */ 138 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 139 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 140 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 141 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 142 PWM133_IRQn = 468, /*!< 468 PWM133 */ 143 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 144 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 145 } IRQn_Type; 146 147 /* ==================================================== Interrupt Aliases ==================================================== */ 148 #define AAR020_IRQn AAR020_CCM020_IRQn 149 #define AAR020_IRQHandler AAR020_CCM020_IRQHandler 150 #define CCM020_IRQn AAR020_CCM020_IRQn 151 #define CCM020_IRQHandler AAR020_CCM020_IRQHandler 152 #define AAR030_IRQn AAR030_CCM030_IRQn 153 #define AAR030_IRQHandler AAR030_CCM030_IRQHandler 154 #define CCM030_IRQn AAR030_CCM030_IRQn 155 #define CCM030_IRQHandler AAR030_CCM030_IRQHandler 156 #define SPIS120_IRQn SPIS120_UARTE120_IRQn 157 #define SPIS120_IRQHandler SPIS120_UARTE120_IRQHandler 158 #define UARTE120_IRQn SPIS120_UARTE120_IRQn 159 #define UARTE120_IRQHandler SPIS120_UARTE120_IRQHandler 160 #define COMP_IRQn COMP_LPCOMP_IRQn 161 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 162 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 163 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 164 #define SPIM130_IRQn SERIAL0_IRQn 165 #define SPIM130_IRQHandler SERIAL0_IRQHandler 166 #define SPIS130_IRQn SERIAL0_IRQn 167 #define SPIS130_IRQHandler SERIAL0_IRQHandler 168 #define TWIM130_IRQn SERIAL0_IRQn 169 #define TWIM130_IRQHandler SERIAL0_IRQHandler 170 #define TWIS130_IRQn SERIAL0_IRQn 171 #define TWIS130_IRQHandler SERIAL0_IRQHandler 172 #define UARTE130_IRQn SERIAL0_IRQn 173 #define UARTE130_IRQHandler SERIAL0_IRQHandler 174 #define SPIM131_IRQn SERIAL1_IRQn 175 #define SPIM131_IRQHandler SERIAL1_IRQHandler 176 #define SPIS131_IRQn SERIAL1_IRQn 177 #define SPIS131_IRQHandler SERIAL1_IRQHandler 178 #define TWIM131_IRQn SERIAL1_IRQn 179 #define TWIM131_IRQHandler SERIAL1_IRQHandler 180 #define TWIS131_IRQn SERIAL1_IRQn 181 #define TWIS131_IRQHandler SERIAL1_IRQHandler 182 #define UARTE131_IRQn SERIAL1_IRQn 183 #define UARTE131_IRQHandler SERIAL1_IRQHandler 184 #define SPIM132_IRQn SERIAL2_IRQn 185 #define SPIM132_IRQHandler SERIAL2_IRQHandler 186 #define SPIS132_IRQn SERIAL2_IRQn 187 #define SPIS132_IRQHandler SERIAL2_IRQHandler 188 #define TWIM132_IRQn SERIAL2_IRQn 189 #define TWIM132_IRQHandler SERIAL2_IRQHandler 190 #define TWIS132_IRQn SERIAL2_IRQn 191 #define TWIS132_IRQHandler SERIAL2_IRQHandler 192 #define UARTE132_IRQn SERIAL2_IRQn 193 #define UARTE132_IRQHandler SERIAL2_IRQHandler 194 #define SPIM133_IRQn SERIAL3_IRQn 195 #define SPIM133_IRQHandler SERIAL3_IRQHandler 196 #define SPIS133_IRQn SERIAL3_IRQn 197 #define SPIS133_IRQHandler SERIAL3_IRQHandler 198 #define TWIM133_IRQn SERIAL3_IRQn 199 #define TWIM133_IRQHandler SERIAL3_IRQHandler 200 #define TWIS133_IRQn SERIAL3_IRQn 201 #define TWIS133_IRQHandler SERIAL3_IRQHandler 202 #define UARTE133_IRQn SERIAL3_IRQn 203 #define UARTE133_IRQHandler SERIAL3_IRQHandler 204 #define SPIM134_IRQn SERIAL4_IRQn 205 #define SPIM134_IRQHandler SERIAL4_IRQHandler 206 #define SPIS134_IRQn SERIAL4_IRQn 207 #define SPIS134_IRQHandler SERIAL4_IRQHandler 208 #define TWIM134_IRQn SERIAL4_IRQn 209 #define TWIM134_IRQHandler SERIAL4_IRQHandler 210 #define TWIS134_IRQn SERIAL4_IRQn 211 #define TWIS134_IRQHandler SERIAL4_IRQHandler 212 #define UARTE134_IRQn SERIAL4_IRQn 213 #define UARTE134_IRQHandler SERIAL4_IRQHandler 214 #define SPIM135_IRQn SERIAL5_IRQn 215 #define SPIM135_IRQHandler SERIAL5_IRQHandler 216 #define SPIS135_IRQn SERIAL5_IRQn 217 #define SPIS135_IRQHandler SERIAL5_IRQHandler 218 #define TWIM135_IRQn SERIAL5_IRQn 219 #define TWIM135_IRQHandler SERIAL5_IRQHandler 220 #define TWIS135_IRQn SERIAL5_IRQn 221 #define TWIS135_IRQHandler SERIAL5_IRQHandler 222 #define UARTE135_IRQn SERIAL5_IRQn 223 #define UARTE135_IRQHandler SERIAL5_IRQHandler 224 #define SPIM136_IRQn SERIAL6_IRQn 225 #define SPIM136_IRQHandler SERIAL6_IRQHandler 226 #define SPIS136_IRQn SERIAL6_IRQn 227 #define SPIS136_IRQHandler SERIAL6_IRQHandler 228 #define TWIM136_IRQn SERIAL6_IRQn 229 #define TWIM136_IRQHandler SERIAL6_IRQHandler 230 #define TWIS136_IRQn SERIAL6_IRQn 231 #define TWIS136_IRQHandler SERIAL6_IRQHandler 232 #define UARTE136_IRQn SERIAL6_IRQn 233 #define UARTE136_IRQHandler SERIAL6_IRQHandler 234 #define SPIM137_IRQn SERIAL7_IRQn 235 #define SPIM137_IRQHandler SERIAL7_IRQHandler 236 #define SPIS137_IRQn SERIAL7_IRQn 237 #define SPIS137_IRQHandler SERIAL7_IRQHandler 238 #define TWIM137_IRQn SERIAL7_IRQn 239 #define TWIM137_IRQHandler SERIAL7_IRQHandler 240 #define TWIS137_IRQn SERIAL7_IRQn 241 #define TWIS137_IRQHandler SERIAL7_IRQHandler 242 #define UARTE137_IRQn SERIAL7_IRQn 243 #define UARTE137_IRQHandler SERIAL7_IRQHandler 244 245 /* =========================================================================================================================== */ 246 /* ================ Processor and Core Peripheral Section ================ */ 247 /* =========================================================================================================================== */ 248 249 /* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ 250 #define __CM33_REV r0p4 /*!< CM33 Core Revision */ 251 #define __DSP_PRESENT 1 /*!< DSP present or not */ 252 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 253 #define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 254 #define __MPU_PRESENT 1 /*!< MPU present */ 255 #define __FPU_PRESENT 1 /*!< FPU present */ 256 #define __FPU_DP 0 /*!< Double Precision FPU */ 257 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 258 #define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ 259 #define __SAUREGION_PRESENT 1 /*!< SAU present */ 260 #define __NUM_SAUREGIONS 4 /*!< Number of regions */ 261 262 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 263 #include "system_nrf.h" /*!< nrf54h20_enga_radiocore System Library */ 264 265 #endif /*!< NRF_RADIOCORE */ 266 267 268 #ifdef NRF_RADIOCORE 269 270 #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE 271 #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE 272 #define NRF_OWNER NRF_OWNER_RADIOCORE 273 274 #endif /*!< NRF_RADIOCORE */ 275 276 277 /* ========================================= Start of section using anonymous unions ========================================= */ 278 279 #include "compiler_abstraction.h" 280 281 #if defined (__CC_ARM) 282 #pragma push 283 #pragma anon_unions 284 #elif defined (__ICCARM__) 285 #pragma language=extended 286 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 287 #pragma clang diagnostic push 288 #pragma clang diagnostic ignored "-Wc11-extensions" 289 #pragma clang diagnostic ignored "-Wreserved-id-macro" 290 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 291 #pragma clang diagnostic ignored "-Wnested-anon-types" 292 #elif defined (__GNUC__) 293 /* anonymous unions are enabled by default */ 294 #elif defined (__TMS470__) 295 /* anonymous unions are enabled by default */ 296 #elif defined (__TASKING__) 297 #pragma warning 586 298 #elif defined (__CSMC__) 299 /* anonymous unions are enabled by default */ 300 #else 301 #warning Unsupported compiler type 302 #endif 303 304 /* =========================================================================================================================== */ 305 /* ================ Peripheral Address Map ================ */ 306 /* =========================================================================================================================== */ 307 308 #define NRF_RADIOCORE_UICR_NS_BASE 0x0FFFA000UL 309 #define NRF_RADIOCORE_ICACHEDATA_S_BASE 0x13F00000UL 310 #define NRF_RADIOCORE_ICACHEINFO_S_BASE 0x13F10000UL 311 #define NRF_RADIOCORE_DCACHEDATA_S_BASE 0x33F00000UL 312 #define NRF_RADIOCORE_DCACHEINFO_S_BASE 0x33F10000UL 313 #define NRF_RADIOCORE_ETM_NS_BASE 0xE0041000UL 314 #define NRF_RADIOCORE_CTI_S_BASE 0xE0042000UL 315 #define NRF_RADIOCORE_CPUC_S_BASE 0xE0080000UL 316 #define NRF_RADIOCORE_ICACHE_S_BASE 0xE0082000UL 317 #define NRF_RADIOCORE_DCACHE_S_BASE 0xE0083000UL 318 #define NRF_RADIOCORE_SPU000_S_BASE 0x53000000UL 319 #define NRF_RADIOCORE_MPC_S_BASE 0x53001000UL 320 #define NRF_RADIOCORE_MVDMA_NS_BASE 0x43003000UL 321 #define NRF_RADIOCORE_MVDMA_S_BASE 0x53003000UL 322 #define NRF_RADIOCORE_RAMC000_NS_BASE 0x43004000UL 323 #define NRF_RADIOCORE_RAMC000_S_BASE 0x53004000UL 324 #define NRF_RADIOCORE_HSFLL_S_BASE 0x5300D000UL 325 #define NRF_RADIOCORE_LRCCONF000_S_BASE 0x5300E000UL 326 #define NRF_RADIOCORE_SPU010_S_BASE 0x53010000UL 327 #define NRF_RADIOCORE_MEMCONF_NS_BASE 0x43012000UL 328 #define NRF_RADIOCORE_MEMCONF_S_BASE 0x53012000UL 329 #define NRF_RADIOCORE_WDT010_NS_BASE 0x43013000UL 330 #define NRF_RADIOCORE_WDT010_S_BASE 0x53013000UL 331 #define NRF_RADIOCORE_WDT011_NS_BASE 0x43014000UL 332 #define NRF_RADIOCORE_WDT011_S_BASE 0x53014000UL 333 #define NRF_RADIOCORE_LRCCONF010_S_BASE 0x5301E000UL 334 #define NRF_RADIOCORE_RESETINFO_S_BASE 0x5301E000UL 335 #define NRF_RADIOCORE_SPU020_S_BASE 0x53020000UL 336 #define NRF_RADIOCORE_DPPIC020_NS_BASE 0x43022000UL 337 #define NRF_RADIOCORE_DPPIC020_S_BASE 0x53022000UL 338 #define NRF_RADIOCORE_PPIB020_S_BASE 0x53023000UL 339 #define NRF_RADIOCORE_EGU020_NS_BASE 0x43025000UL 340 #define NRF_RADIOCORE_EGU020_S_BASE 0x53025000UL 341 #define NRF_RADIOCORE_AAR020_NS_BASE 0x43026000UL 342 #define NRF_RADIOCORE_CCM020_NS_BASE 0x43026000UL 343 #define NRF_RADIOCORE_AAR020_S_BASE 0x53026000UL 344 #define NRF_RADIOCORE_CCM020_S_BASE 0x53026000UL 345 #define NRF_RADIOCORE_ECB020_NS_BASE 0x43027000UL 346 #define NRF_RADIOCORE_ECB020_S_BASE 0x53027000UL 347 #define NRF_RADIOCORE_TIMER020_NS_BASE 0x43028000UL 348 #define NRF_RADIOCORE_TIMER020_S_BASE 0x53028000UL 349 #define NRF_RADIOCORE_TIMER021_NS_BASE 0x43029000UL 350 #define NRF_RADIOCORE_TIMER021_S_BASE 0x53029000UL 351 #define NRF_RADIOCORE_TIMER022_NS_BASE 0x4302A000UL 352 #define NRF_RADIOCORE_TIMER022_S_BASE 0x5302A000UL 353 #define NRF_RADIOCORE_RTC_NS_BASE 0x4302B000UL 354 #define NRF_RADIOCORE_RTC_S_BASE 0x5302B000UL 355 #define NRF_RADIOCORE_RADIO_NS_BASE 0x4302C000UL 356 #define NRF_RADIOCORE_RADIO_S_BASE 0x5302C000UL 357 #define NRF_RADIOCORE_LRCCONF020_S_BASE 0x5302E000UL 358 #define NRF_RADIOCORE_SPU030_S_BASE 0x53030000UL 359 #define NRF_RADIOCORE_PPIB030_S_BASE 0x53031000UL 360 #define NRF_RADIOCORE_VPR_NS_BASE 0x43034000UL 361 #define NRF_RADIOCORE_VPR_S_BASE 0x53034000UL 362 #define NRF_RADIOCORE_RAMC001_NS_BASE 0x43038000UL 363 #define NRF_RADIOCORE_RAMC001_S_BASE 0x53038000UL 364 #define NRF_RADIOCORE_AAR030_NS_BASE 0x4303A000UL 365 #define NRF_RADIOCORE_CCM030_NS_BASE 0x4303A000UL 366 #define NRF_RADIOCORE_AAR030_S_BASE 0x5303A000UL 367 #define NRF_RADIOCORE_CCM030_S_BASE 0x5303A000UL 368 #define NRF_RADIOCORE_ECB030_NS_BASE 0x4303B000UL 369 #define NRF_RADIOCORE_ECB030_S_BASE 0x5303B000UL 370 #define NRF_RADIOCORE_IPCT_NS_BASE 0x43024000UL 371 #define NRF_RADIOCORE_IPCT_S_BASE 0x53024000UL 372 #define NRF_RADIOCORE_BELLBOARD_NS_BASE 0x4F09B000UL 373 #define NRF_RADIOCORE_BELLBOARD_S_BASE 0x5F09B000UL 374 375 /* =========================================================================================================================== */ 376 /* ================ Peripheral Declaration ================ */ 377 /* =========================================================================================================================== */ 378 379 #define NRF_RADIOCORE_UICR_NS ((NRF_UICR_Type*) NRF_RADIOCORE_UICR_NS_BASE) 380 #define NRF_RADIOCORE_ICACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_RADIOCORE_ICACHEDATA_S_BASE) 381 #define NRF_RADIOCORE_ICACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_RADIOCORE_ICACHEINFO_S_BASE) 382 #define NRF_RADIOCORE_DCACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_RADIOCORE_DCACHEDATA_S_BASE) 383 #define NRF_RADIOCORE_DCACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_RADIOCORE_DCACHEINFO_S_BASE) 384 #define NRF_RADIOCORE_ETM_NS ((NRF_ETM_Type*) NRF_RADIOCORE_ETM_NS_BASE) 385 #define NRF_RADIOCORE_CTI_S ((NRF_CTI_Type*) NRF_RADIOCORE_CTI_S_BASE) 386 #define NRF_RADIOCORE_CPUC_S ((NRF_CM33SS_Type*) NRF_RADIOCORE_CPUC_S_BASE) 387 #define NRF_RADIOCORE_ICACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_ICACHE_S_BASE) 388 #define NRF_RADIOCORE_DCACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_DCACHE_S_BASE) 389 #define NRF_RADIOCORE_SPU000_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU000_S_BASE) 390 #define NRF_RADIOCORE_MPC_S ((NRF_MPC_Type*) NRF_RADIOCORE_MPC_S_BASE) 391 #define NRF_RADIOCORE_MVDMA_NS ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_NS_BASE) 392 #define NRF_RADIOCORE_MVDMA_S ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_S_BASE) 393 #define NRF_RADIOCORE_RAMC000_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_NS_BASE) 394 #define NRF_RADIOCORE_RAMC000_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_S_BASE) 395 #define NRF_RADIOCORE_HSFLL_S ((NRF_HSFLL_Type*) NRF_RADIOCORE_HSFLL_S_BASE) 396 #define NRF_RADIOCORE_LRCCONF000_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF000_S_BASE) 397 #define NRF_RADIOCORE_SPU010_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU010_S_BASE) 398 #define NRF_RADIOCORE_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_NS_BASE) 399 #define NRF_RADIOCORE_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_S_BASE) 400 #define NRF_RADIOCORE_WDT010_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_NS_BASE) 401 #define NRF_RADIOCORE_WDT010_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_S_BASE) 402 #define NRF_RADIOCORE_WDT011_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_NS_BASE) 403 #define NRF_RADIOCORE_WDT011_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_S_BASE) 404 #define NRF_RADIOCORE_LRCCONF010_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF010_S_BASE) 405 #define NRF_RADIOCORE_RESETINFO_S ((NRF_RESETINFO_Type*) NRF_RADIOCORE_RESETINFO_S_BASE) 406 #define NRF_RADIOCORE_SPU020_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU020_S_BASE) 407 #define NRF_RADIOCORE_DPPIC020_NS ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_NS_BASE) 408 #define NRF_RADIOCORE_DPPIC020_S ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_S_BASE) 409 #define NRF_RADIOCORE_PPIB020_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB020_S_BASE) 410 #define NRF_RADIOCORE_EGU020_NS ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_NS_BASE) 411 #define NRF_RADIOCORE_EGU020_S ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_S_BASE) 412 #define NRF_RADIOCORE_AAR020_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR020_NS_BASE) 413 #define NRF_RADIOCORE_CCM020_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM020_NS_BASE) 414 #define NRF_RADIOCORE_AAR020_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR020_S_BASE) 415 #define NRF_RADIOCORE_CCM020_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM020_S_BASE) 416 #define NRF_RADIOCORE_ECB020_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB020_NS_BASE) 417 #define NRF_RADIOCORE_ECB020_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB020_S_BASE) 418 #define NRF_RADIOCORE_TIMER020_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_NS_BASE) 419 #define NRF_RADIOCORE_TIMER020_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_S_BASE) 420 #define NRF_RADIOCORE_TIMER021_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_NS_BASE) 421 #define NRF_RADIOCORE_TIMER021_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_S_BASE) 422 #define NRF_RADIOCORE_TIMER022_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_NS_BASE) 423 #define NRF_RADIOCORE_TIMER022_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_S_BASE) 424 #define NRF_RADIOCORE_RTC_NS ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_NS_BASE) 425 #define NRF_RADIOCORE_RTC_S ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_S_BASE) 426 #define NRF_RADIOCORE_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_NS_BASE) 427 #define NRF_RADIOCORE_RADIO_S ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_S_BASE) 428 #define NRF_RADIOCORE_LRCCONF020_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF020_S_BASE) 429 #define NRF_RADIOCORE_SPU030_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU030_S_BASE) 430 #define NRF_RADIOCORE_PPIB030_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB030_S_BASE) 431 #define NRF_RADIOCORE_VPR_NS ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_NS_BASE) 432 #define NRF_RADIOCORE_VPR_S ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_S_BASE) 433 #define NRF_RADIOCORE_RAMC001_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_NS_BASE) 434 #define NRF_RADIOCORE_RAMC001_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_S_BASE) 435 #define NRF_RADIOCORE_AAR030_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_NS_BASE) 436 #define NRF_RADIOCORE_CCM030_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_NS_BASE) 437 #define NRF_RADIOCORE_AAR030_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_S_BASE) 438 #define NRF_RADIOCORE_CCM030_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_S_BASE) 439 #define NRF_RADIOCORE_ECB030_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_NS_BASE) 440 #define NRF_RADIOCORE_ECB030_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_S_BASE) 441 #define NRF_RADIOCORE_IPCT_NS ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_NS_BASE) 442 #define NRF_RADIOCORE_IPCT_S ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_S_BASE) 443 #define NRF_RADIOCORE_BELLBOARD_NS ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_NS_BASE) 444 #define NRF_RADIOCORE_BELLBOARD_S ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_S_BASE) 445 446 /* =========================================================================================================================== */ 447 /* ================ TrustZone Remapping ================ */ 448 /* =========================================================================================================================== */ 449 450 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 451 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 452 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 453 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_NS 454 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_NS 455 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_NS 456 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_NS 457 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_NS 458 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_NS 459 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_NS 460 #define NRF_RADIOCORE_AAR020 NRF_RADIOCORE_AAR020_NS 461 #define NRF_RADIOCORE_CCM020 NRF_RADIOCORE_CCM020_NS 462 #define NRF_RADIOCORE_ECB020 NRF_RADIOCORE_ECB020_NS 463 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_NS 464 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_NS 465 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_NS 466 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_NS 467 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_NS 468 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_NS 469 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_NS 470 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_NS 471 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_NS 472 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_NS 473 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_NS 474 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_NS 475 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 476 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 477 #define NRF_RADIOCORE_ICACHEDATA NRF_RADIOCORE_ICACHEDATA_S 478 #define NRF_RADIOCORE_ICACHEINFO NRF_RADIOCORE_ICACHEINFO_S 479 #define NRF_RADIOCORE_DCACHEDATA NRF_RADIOCORE_DCACHEDATA_S 480 #define NRF_RADIOCORE_DCACHEINFO NRF_RADIOCORE_DCACHEINFO_S 481 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 482 #define NRF_RADIOCORE_CTI NRF_RADIOCORE_CTI_S 483 #define NRF_RADIOCORE_CPUC NRF_RADIOCORE_CPUC_S 484 #define NRF_RADIOCORE_ICACHE NRF_RADIOCORE_ICACHE_S 485 #define NRF_RADIOCORE_DCACHE NRF_RADIOCORE_DCACHE_S 486 #define NRF_RADIOCORE_SPU000 NRF_RADIOCORE_SPU000_S 487 #define NRF_RADIOCORE_MPC NRF_RADIOCORE_MPC_S 488 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_S 489 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_S 490 #define NRF_RADIOCORE_HSFLL NRF_RADIOCORE_HSFLL_S 491 #define NRF_RADIOCORE_LRCCONF000 NRF_RADIOCORE_LRCCONF000_S 492 #define NRF_RADIOCORE_SPU010 NRF_RADIOCORE_SPU010_S 493 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_S 494 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_S 495 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_S 496 #define NRF_RADIOCORE_LRCCONF010 NRF_RADIOCORE_LRCCONF010_S 497 #define NRF_RADIOCORE_RESETINFO NRF_RADIOCORE_RESETINFO_S 498 #define NRF_RADIOCORE_SPU020 NRF_RADIOCORE_SPU020_S 499 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_S 500 #define NRF_RADIOCORE_PPIB020 NRF_RADIOCORE_PPIB020_S 501 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_S 502 #define NRF_RADIOCORE_AAR020 NRF_RADIOCORE_AAR020_S 503 #define NRF_RADIOCORE_CCM020 NRF_RADIOCORE_CCM020_S 504 #define NRF_RADIOCORE_ECB020 NRF_RADIOCORE_ECB020_S 505 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_S 506 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_S 507 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_S 508 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_S 509 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_S 510 #define NRF_RADIOCORE_LRCCONF020 NRF_RADIOCORE_LRCCONF020_S 511 #define NRF_RADIOCORE_SPU030 NRF_RADIOCORE_SPU030_S 512 #define NRF_RADIOCORE_PPIB030 NRF_RADIOCORE_PPIB030_S 513 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_S 514 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_S 515 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_S 516 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_S 517 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_S 518 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_S 519 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_S 520 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 521 522 /* =========================================================================================================================== */ 523 /* ================ Local Domain Remapping ================ */ 524 /* =========================================================================================================================== */ 525 526 #ifdef NRF_RADIOCORE /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 527 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 528 #define NRF_UICR NRF_RADIOCORE_UICR 529 #define NRF_ETM NRF_RADIOCORE_ETM 530 #define NRF_MVDMA NRF_RADIOCORE_MVDMA 531 #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 532 #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF 533 #define NRF_WDT010 NRF_RADIOCORE_WDT010 534 #define NRF_WDT011 NRF_RADIOCORE_WDT011 535 #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 536 #define NRF_EGU020 NRF_RADIOCORE_EGU020 537 #define NRF_AAR020 NRF_RADIOCORE_AAR020 538 #define NRF_CCM020 NRF_RADIOCORE_CCM020 539 #define NRF_ECB020 NRF_RADIOCORE_ECB020 540 #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 541 #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 542 #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 543 #define NRF_RTC NRF_RADIOCORE_RTC 544 #define NRF_RADIO NRF_RADIOCORE_RADIO 545 #define NRF_VPR NRF_RADIOCORE_VPR 546 #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 547 #define NRF_AAR030 NRF_RADIOCORE_AAR030 548 #define NRF_CCM030 NRF_RADIOCORE_CCM030 549 #define NRF_ECB030 NRF_RADIOCORE_ECB030 550 #define NRF_IPCT NRF_RADIOCORE_IPCT 551 #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD 552 #else /*!< Remap all instances. */ 553 #define NRF_UICR NRF_RADIOCORE_UICR 554 #define NRF_ICACHEDATA NRF_RADIOCORE_ICACHEDATA 555 #define NRF_ICACHEINFO NRF_RADIOCORE_ICACHEINFO 556 #define NRF_DCACHEDATA NRF_RADIOCORE_DCACHEDATA 557 #define NRF_DCACHEINFO NRF_RADIOCORE_DCACHEINFO 558 #define NRF_ETM NRF_RADIOCORE_ETM 559 #define NRF_CTI NRF_RADIOCORE_CTI 560 #define NRF_CPUC NRF_RADIOCORE_CPUC 561 #define NRF_ICACHE NRF_RADIOCORE_ICACHE 562 #define NRF_DCACHE NRF_RADIOCORE_DCACHE 563 #define NRF_SPU000 NRF_RADIOCORE_SPU000 564 #define NRF_MPC NRF_RADIOCORE_MPC 565 #define NRF_MVDMA NRF_RADIOCORE_MVDMA 566 #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 567 #define NRF_HSFLL NRF_RADIOCORE_HSFLL 568 #define NRF_LRCCONF000 NRF_RADIOCORE_LRCCONF000 569 #define NRF_SPU010 NRF_RADIOCORE_SPU010 570 #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF 571 #define NRF_WDT010 NRF_RADIOCORE_WDT010 572 #define NRF_WDT011 NRF_RADIOCORE_WDT011 573 #define NRF_LRCCONF010 NRF_RADIOCORE_LRCCONF010 574 #define NRF_RESETINFO NRF_RADIOCORE_RESETINFO 575 #define NRF_SPU020 NRF_RADIOCORE_SPU020 576 #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 577 #define NRF_PPIB020 NRF_RADIOCORE_PPIB020 578 #define NRF_EGU020 NRF_RADIOCORE_EGU020 579 #define NRF_AAR020 NRF_RADIOCORE_AAR020 580 #define NRF_CCM020 NRF_RADIOCORE_CCM020 581 #define NRF_ECB020 NRF_RADIOCORE_ECB020 582 #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 583 #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 584 #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 585 #define NRF_RTC NRF_RADIOCORE_RTC 586 #define NRF_RADIO NRF_RADIOCORE_RADIO 587 #define NRF_LRCCONF020 NRF_RADIOCORE_LRCCONF020 588 #define NRF_SPU030 NRF_RADIOCORE_SPU030 589 #define NRF_PPIB030 NRF_RADIOCORE_PPIB030 590 #define NRF_VPR NRF_RADIOCORE_VPR 591 #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 592 #define NRF_AAR030 NRF_RADIOCORE_AAR030 593 #define NRF_CCM030 NRF_RADIOCORE_CCM030 594 #define NRF_ECB030 NRF_RADIOCORE_ECB030 595 #define NRF_IPCT NRF_RADIOCORE_IPCT 596 #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD 597 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 598 #endif /*!< NRF_RADIOCORE */ 599 600 /* ========================================== End of section using anonymous unions ========================================== */ 601 602 #if defined (__CC_ARM) 603 #pragma pop 604 #elif defined (__ICCARM__) 605 /* leave anonymous unions enabled */ 606 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 607 #pragma clang diagnostic pop 608 #elif defined (__GNUC__) 609 /* anonymous unions are enabled by default */ 610 #elif defined (__TMS470__) 611 /* anonymous unions are enabled by default */ 612 #elif defined (__TASKING__) 613 #pragma warning restore 614 #elif defined (__CSMC__) 615 /* anonymous unions are enabled by default */ 616 #endif 617 618 619 #ifdef __cplusplus 620 } 621 #endif 622 #endif /* NRF54H20_ENGA_RADIOCORE_H */ 623 624
