1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_PPR_PERIPHERALS_H 36 #define NRF54H20_ENGA_PPR_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*VPR CSR registers*/ 44 #define VPRCSR_PRESENT 1 45 #define VPRCSR_COUNT 1 46 47 #define VPRCSR_HARTNUM 11 /*!< HARTNUM: 11 */ 48 #define VPRCSR_MCLICBASERESET 0x5F909000 /*!< MCLICBASE: 0x5F909000 */ 49 #define VPRCSR_MULDIV 1 /*!< MULDIV: 1 */ 50 #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ 51 #define VPRCSR_DBG 1 /*!< DBG: 1 */ 52 #define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ 53 #define VPRCSR_BUSWIDTH 32 /*!< BUSWIDTH: 32 */ 54 #define VPRCSR_BKPT 1 /*!< BKPT: 1 */ 55 #define VPRCSR_VIOPINS 0x0000000F /*!< CSR VIOPINS value: 0x0000000F */ 56 #define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 57 #define VPRCSR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 58 #define VPRCSR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 59 #define VPRCSR_VEVIF_TASKS_MASK 0xFFFFFFF0 /*!< Mask of supported VEVIF tasks: 0xFFFFFFF0 */ 60 #define VPRCSR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 61 #define VPRCSR_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 62 #define VPRCSR_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 63 #define VPRCSR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 64 #define VPRCSR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 65 #define VPRCSR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 66 #define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ 67 #define VPRCSR_CACHE_EN 0 /*!< (unspecified) */ 68 #define VPRCSR_OUTMODE_VPR1_2 0 /*!< (unspecified) */ 69 #define VPRCSR_VPR_BUS_PRIO 0 /*!< (unspecified) */ 70 #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ 71 72 /*VPR CLIC registers*/ 73 #define CLIC_PRESENT 1 74 #define CLIC_COUNT 1 75 76 #define VPRCLIC_IRQ_COUNT 16 77 #define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ 78 #define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ 79 #define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ 80 #define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 81 #define VPRCLIC_CLIC_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 82 #define VPRCLIC_CLIC_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 83 #define VPRCLIC_CLIC_TASKS_MASK 0xFFFFFFF0 /*!< Mask of supported VEVIF tasks: 0xFFFFFFF0 */ 84 #define VPRCLIC_COUNTER_IRQ_NUM 32 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 32 */ 85 #define VPRCLIC_CLIC_VPR_1_2 0 /*!< (unspecified) */ 86 87 /*VTIM CSR registers*/ 88 #define VTIM_PRESENT 1 89 #define VTIM_COUNT 1 90 91 /*Factory Information Configuration Registers*/ 92 #define FICR_PRESENT 1 93 #define FICR_COUNT 1 94 95 /*USBHSCORE*/ 96 #define USBHSCORE_PRESENT 1 97 #define USBHSCORE_COUNT 1 98 99 /*I3CCORE*/ 100 #define I3CCORE_PRESENT 1 101 #define I3CCORE_COUNT 2 102 103 /*DMU*/ 104 #define DMU_PRESENT 1 105 #define DMU_COUNT 1 106 107 /*MCAN*/ 108 #define MCAN_PRESENT 1 109 #define MCAN_COUNT 1 110 111 /*System Trace Macrocell data buffer*/ 112 #define STMDATA_PRESENT 1 113 #define STMDATA_COUNT 1 114 115 /*TDDCONF*/ 116 #define TDDCONF_PRESENT 1 117 #define TDDCONF_COUNT 1 118 119 /*System Trace Macrocell*/ 120 #define STM_PRESENT 1 121 #define STM_COUNT 1 122 123 /*Trace Port Interface Unit*/ 124 #define TPIU_PRESENT 1 125 #define TPIU_COUNT 1 126 127 /*Cross-Trigger Interface control*/ 128 #define CTI_PRESENT 1 129 #define CTI_COUNT 2 130 131 /*ATB Replicator module*/ 132 #define ATBREPLICATOR_PRESENT 1 133 #define ATBREPLICATOR_COUNT 4 134 135 /*ATB funnel module*/ 136 #define ATBFUNNEL_PRESENT 1 137 #define ATBFUNNEL_COUNT 4 138 139 /*GPIO Tasks and Events*/ 140 #define GPIOTE_PRESENT 1 141 #define GPIOTE_COUNT 1 142 143 #define GPIOTE130_IRQ_COUNT 2 144 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 145 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 146 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 147 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 148 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 149 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 150 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 151 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 152 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 153 154 /*Global Real-time counter*/ 155 #define GRTC_PRESENT 1 156 #define GRTC_COUNT 1 157 158 #define GRTC_IRQ_COUNT 2 159 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 160 0..14*/ 161 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 162 0..14*/ 163 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 164 0..14*/ 165 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 166 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 167 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 168 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 169 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 170 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 171 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 172 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 173 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 174 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..1 */ 175 #define GRTC_GRTC_NINTERRUPTS_MAX 1 /*!< Number of GRTC interrupts : 0..1 */ 176 #define GRTC_GRTC_NINTERRUPTS_SIZE 2 /*!< Number of GRTC interrupts : 0..1 */ 177 #define GRTC_PWMREGS 0 /*!< (unspecified) */ 178 #define GRTC_CLKOUTREG 0 /*!< (unspecified) */ 179 180 /*Trace buffer monitor*/ 181 #define TBM_PRESENT 1 182 #define TBM_COUNT 1 183 184 /*USBHS*/ 185 #define USBHS_PRESENT 1 186 #define USBHS_COUNT 1 187 188 /*External Memory Interface*/ 189 #define EXMIF_PRESENT 1 190 #define EXMIF_COUNT 1 191 192 /*BELLBOARD public registers*/ 193 #define BELLBOARDPUBLIC_PRESENT 1 194 #define BELLBOARDPUBLIC_COUNT 1 195 196 /*VPR peripheral registers*/ 197 #define VPRPUBLIC_PRESENT 1 198 #define VPRPUBLIC_COUNT 1 199 200 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 201 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 202 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 203 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 204 205 /*IPCT APB registers*/ 206 #define IPCT_PRESENT 1 207 #define IPCT_COUNT 2 208 209 #define IPCT120_IRQ_COUNT 1 210 211 #define IPCT130_IRQ_COUNT 1 212 213 /*MUTEX*/ 214 #define MUTEX_PRESENT 1 215 #define MUTEX_COUNT 2 216 217 /*I3C*/ 218 #define I3C_PRESENT 1 219 #define I3C_COUNT 2 220 221 /*VPR peripheral registers*/ 222 #define VPR_PRESENT 1 223 #define VPR_COUNT 2 224 225 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 226 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 227 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 228 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 229 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 230 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 231 #define VPR121_RETAINED 0 /*!< (unspecified) */ 232 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 233 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 234 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 235 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 236 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 237 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 238 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 239 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 240 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 241 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 242 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 243 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 244 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 245 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 246 247 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 248 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 249 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 250 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 251 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 252 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 253 #define VPR130_RETAINED 0 /*!< (unspecified) */ 254 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 255 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 256 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 257 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 258 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 259 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 260 #define VPR130_VEVIF_TASKS_MASK 0xFFFFFFF0 /*!< Mask of supported VEVIF tasks: 0xFFFFFFF0 */ 261 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 262 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 263 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 264 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 265 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 266 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 267 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 268 269 /*Controller Area Network*/ 270 #define CAN_PRESENT 1 271 #define CAN_COUNT 1 272 273 /*Distributed programmable peripheral interconnect controller*/ 274 #define DPPIC_PRESENT 1 275 #define DPPIC_COUNT 8 276 277 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 278 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 279 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 280 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 281 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 282 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 283 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 284 285 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 286 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 287 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 288 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 289 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 290 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 291 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 292 293 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 294 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 295 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 296 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 297 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 298 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 299 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 300 301 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 302 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 303 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 304 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 305 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 306 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 307 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 308 309 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 310 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 311 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 312 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 313 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 314 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 315 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 316 317 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 318 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 319 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 320 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 321 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 322 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 323 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 324 325 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 326 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 327 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 328 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 329 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 330 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 331 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 332 333 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 334 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 335 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 336 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 337 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 338 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 339 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 340 341 /*Timer/Counter*/ 342 #define TIMER_PRESENT 1 343 #define TIMER_COUNT 10 344 345 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 346 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 347 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 348 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 349 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 350 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 351 352 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 353 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 354 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 355 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 356 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 357 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 358 359 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 360 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 361 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 362 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 363 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 364 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 365 366 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 367 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 368 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 369 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 370 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 371 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 372 373 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 374 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 375 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 376 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 377 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 378 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 379 380 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 381 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 382 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 383 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 384 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 385 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 386 387 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 388 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 389 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 390 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 391 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 392 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 393 394 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 395 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 396 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 397 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 398 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 399 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 400 401 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 402 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 403 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 404 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 405 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 406 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 407 408 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 409 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 410 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 411 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 412 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 413 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 414 415 /*Pulse width modulation unit*/ 416 #define PWM_PRESENT 1 417 #define PWM_COUNT 5 418 419 /*SPI Slave*/ 420 #define SPIS_PRESENT 1 421 #define SPIS_COUNT 9 422 423 #define SPIS120_LEGACYPSEL 0 /*!< (unspecified) */ 424 #define SPIS120_LEGACYEDMA 0 /*!< (unspecified) */ 425 426 #define SPIS130_LEGACYPSEL 0 /*!< (unspecified) */ 427 #define SPIS130_LEGACYEDMA 0 /*!< (unspecified) */ 428 429 #define SPIS131_LEGACYPSEL 0 /*!< (unspecified) */ 430 #define SPIS131_LEGACYEDMA 0 /*!< (unspecified) */ 431 432 #define SPIS132_LEGACYPSEL 0 /*!< (unspecified) */ 433 #define SPIS132_LEGACYEDMA 0 /*!< (unspecified) */ 434 435 #define SPIS133_LEGACYPSEL 0 /*!< (unspecified) */ 436 #define SPIS133_LEGACYEDMA 0 /*!< (unspecified) */ 437 438 #define SPIS134_LEGACYPSEL 0 /*!< (unspecified) */ 439 #define SPIS134_LEGACYEDMA 0 /*!< (unspecified) */ 440 441 #define SPIS135_LEGACYPSEL 0 /*!< (unspecified) */ 442 #define SPIS135_LEGACYEDMA 0 /*!< (unspecified) */ 443 444 #define SPIS136_LEGACYPSEL 0 /*!< (unspecified) */ 445 #define SPIS136_LEGACYEDMA 0 /*!< (unspecified) */ 446 447 #define SPIS137_LEGACYPSEL 0 /*!< (unspecified) */ 448 #define SPIS137_LEGACYEDMA 0 /*!< (unspecified) */ 449 450 /*UART with EasyDMA*/ 451 #define UARTE_PRESENT 1 452 #define UARTE_COUNT 9 453 454 #define UARTE120_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 455 #define UARTE120_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 456 #define UARTE120_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 457 458 #define UARTE130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 459 #define UARTE130_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 460 #define UARTE130_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 461 462 #define UARTE131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 463 #define UARTE131_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 464 #define UARTE131_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 465 466 #define UARTE132_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 467 #define UARTE132_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 468 #define UARTE132_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 469 470 #define UARTE133_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 471 #define UARTE133_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 472 #define UARTE133_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 473 474 #define UARTE134_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 475 #define UARTE134_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 476 #define UARTE134_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 477 478 #define UARTE135_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 479 #define UARTE135_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 480 #define UARTE135_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 481 482 #define UARTE136_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 483 #define UARTE136_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 484 #define UARTE136_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 485 486 #define UARTE137_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 487 #define UARTE137_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 488 #define UARTE137_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 489 490 /*Serial Peripheral Interface Master with EasyDMA*/ 491 #define SPIM_PRESENT 1 492 #define SPIM_COUNT 10 493 494 #define SPIM120_HSSPI 1 /*!< (unspecified) */ 495 496 #define SPIM121_HSSPI 1 /*!< (unspecified) */ 497 498 #define SPIM130_HSSPI 1 /*!< (unspecified) */ 499 500 #define SPIM131_HSSPI 1 /*!< (unspecified) */ 501 502 #define SPIM132_HSSPI 1 /*!< (unspecified) */ 503 504 #define SPIM133_HSSPI 1 /*!< (unspecified) */ 505 506 #define SPIM134_HSSPI 1 /*!< (unspecified) */ 507 508 #define SPIM135_HSSPI 1 /*!< (unspecified) */ 509 510 #define SPIM136_HSSPI 1 /*!< (unspecified) */ 511 512 #define SPIM137_HSSPI 1 /*!< (unspecified) */ 513 514 /*Real-time counter*/ 515 #define RTC_PRESENT 1 516 #define RTC_COUNT 2 517 518 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 519 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 520 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 521 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 522 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 523 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 524 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 525 526 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 527 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 528 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 529 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 530 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 531 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 532 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 533 534 /*Watchdog Timer*/ 535 #define WDT_PRESENT 1 536 #define WDT_COUNT 2 537 538 /*GPIO Port*/ 539 #define GPIO_PRESENT 1 540 #define GPIO_COUNT 6 541 542 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 543 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 544 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 545 #define P0_PIN_NUM_MAX 11 /*!< (unspecified) */ 546 #define P0_PIN_NUM_SIZE 12 /*!< (unspecified) */ 547 #define P0_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 548 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 549 #define P0_RETAIN 1 /*!< (unspecified) */ 550 #define P0_PWRCTRL 0 /*!< (unspecified) */ 551 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 552 #define P0_BIASCTRL 0 /*!< (unspecified) */ 553 554 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 555 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 556 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 557 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 558 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 559 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 560 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 561 #define P1_RETAIN 1 /*!< (unspecified) */ 562 #define P1_PWRCTRL 0 /*!< (unspecified) */ 563 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 564 #define P1_BIASCTRL 0 /*!< (unspecified) */ 565 566 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 567 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 568 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 569 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 570 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 571 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 572 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 573 #define P2_RETAIN 1 /*!< (unspecified) */ 574 #define P2_PWRCTRL 0 /*!< (unspecified) */ 575 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 576 #define P2_BIASCTRL 0 /*!< (unspecified) */ 577 578 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 579 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 580 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 581 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 582 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 583 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 584 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 585 #define P6_RETAIN 1 /*!< (unspecified) */ 586 #define P6_PWRCTRL 0 /*!< (unspecified) */ 587 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 588 #define P6_BIASCTRL 0 /*!< (unspecified) */ 589 590 #define P7_CTRLSEL_MAP1 1 /*!< (unspecified) */ 591 #define P7_CTRLSEL_MAP2 0 /*!< (unspecified) */ 592 #define P7_PIN_NUM_MIN 0 /*!< (unspecified) */ 593 #define P7_PIN_NUM_MAX 7 /*!< (unspecified) */ 594 #define P7_PIN_NUM_SIZE 8 /*!< (unspecified) */ 595 #define P7_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 596 #define P7_DRIVECTRL 1 /*!< (unspecified) */ 597 #define P7_RETAIN 1 /*!< (unspecified) */ 598 #define P7_PWRCTRL 0 /*!< (unspecified) */ 599 #define P7_PIN_OWNER_SEC 0 /*!< (unspecified) */ 600 #define P7_BIASCTRL 0 /*!< (unspecified) */ 601 602 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 603 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 604 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 605 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 606 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 607 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 608 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 609 #define P9_RETAIN 1 /*!< (unspecified) */ 610 #define P9_PWRCTRL 1 /*!< (unspecified) */ 611 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 612 #define P9_BIASCTRL 0 /*!< (unspecified) */ 613 614 /*Analog to Digital Converter*/ 615 #define SAADC_PRESENT 1 616 #define SAADC_COUNT 1 617 618 /*Comparator*/ 619 #define COMP_PRESENT 1 620 #define COMP_COUNT 1 621 622 /*Low-power comparator*/ 623 #define LPCOMP_PRESENT 1 624 #define LPCOMP_COUNT 1 625 626 /*Temperature Sensor*/ 627 #define TEMP_PRESENT 1 628 #define TEMP_COUNT 1 629 630 /*NFC-A compatible radio NFC-A compatible radio*/ 631 #define NFCT_PRESENT 1 632 #define NFCT_COUNT 1 633 634 /*Inter-IC Sound*/ 635 #define I2S_PRESENT 1 636 #define I2S_COUNT 2 637 638 #define I2S130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 639 #define I2S130_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 640 #define I2S130_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 641 642 #define I2S131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 643 #define I2S131_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 644 #define I2S131_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 645 646 /*Pulse Density Modulation (Digital Microphone) Interface*/ 647 #define PDM_PRESENT 1 648 #define PDM_COUNT 1 649 650 /*Quadrature Decoder*/ 651 #define QDEC_PRESENT 1 652 #define QDEC_COUNT 2 653 654 #define QDEC130_LEGACYPSEL 0 /*!< (unspecified) */ 655 656 #define QDEC131_LEGACYPSEL 0 /*!< (unspecified) */ 657 658 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 659 #define TWIM_PRESENT 1 660 #define TWIM_COUNT 8 661 662 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 663 #define TWIS_PRESENT 1 664 #define TWIS_COUNT 8 665 666 667 #ifdef __cplusplus 668 } 669 #endif 670 #endif /* NRF54H20_ENGA_PPR_PERIPHERALS_H */ 671 672
