1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_INTERIM_H__ 36 #define NRF54H20_ENGA_INTERIM_H__ 37 38 #include "haltium_interim.h" 39 40 #if defined(NRF54H20_ENGA_XXAA) 41 42 #if defined(NRF_TRUSTZONE_NONSECURE) 43 #if defined(NRF_APPLICATION) 44 #define GRTC_IRQ_GROUP 2 45 #define GPIOTE_IRQ_GROUP 2 46 #elif defined(NRF_RADIOCORE) 47 #define GRTC_IRQ_GROUP 4 48 #define GPIOTE_IRQ_GROUP 4 49 #else 50 #error Unknown core. 51 #endif 52 #elif defined(NRF_PPR) || defined(NRF_FLPR) 53 #define GRTC_IRQ_GROUP 2 54 #define GPIOTE_IRQ_GROUP 2 55 #else 56 #if defined(NRF_APPLICATION) 57 #define GRTC_IRQ_GROUP 3 58 #define GPIOTE_IRQ_GROUP 3 59 #elif defined(NRF_RADIOCORE) 60 #define GRTC_IRQ_GROUP 5 61 #define GPIOTE_IRQ_GROUP 5 62 #else 63 #error Unknown core. 64 #endif 65 #endif 66 67 #define EASYVDMA_PRESENT 68 #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL) /*!< Position of CNT field. */ 69 #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field. */ 70 #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field. */ 71 72 #define SPIS120_EASYDMA_MAXCNT_SIZE 16 73 #define SPIS130_EASYDMA_MAXCNT_SIZE 16 74 #define SPIS131_EASYDMA_MAXCNT_SIZE 16 75 #define SPIS132_EASYDMA_MAXCNT_SIZE 16 76 #define SPIS133_EASYDMA_MAXCNT_SIZE 16 77 #define SPIS134_EASYDMA_MAXCNT_SIZE 16 78 #define SPIS135_EASYDMA_MAXCNT_SIZE 16 79 #define SPIS136_EASYDMA_MAXCNT_SIZE 16 80 #define SPIS137_EASYDMA_MAXCNT_SIZE 16 81 82 #define TWIM130_EASYDMA_MAXCNT_SIZE 16 83 #define TWIM131_EASYDMA_MAXCNT_SIZE 16 84 #define TWIM132_EASYDMA_MAXCNT_SIZE 16 85 #define TWIM133_EASYDMA_MAXCNT_SIZE 16 86 #define TWIM134_EASYDMA_MAXCNT_SIZE 16 87 #define TWIM135_EASYDMA_MAXCNT_SIZE 16 88 #define TWIM136_EASYDMA_MAXCNT_SIZE 16 89 #define TWIM137_EASYDMA_MAXCNT_SIZE 16 90 91 #define TWIS130_EASYDMA_MAXCNT_SIZE 16 92 #define TWIS131_EASYDMA_MAXCNT_SIZE 16 93 #define TWIS132_EASYDMA_MAXCNT_SIZE 16 94 #define TWIS133_EASYDMA_MAXCNT_SIZE 16 95 #define TWIS134_EASYDMA_MAXCNT_SIZE 16 96 #define TWIS135_EASYDMA_MAXCNT_SIZE 16 97 #define TWIS136_EASYDMA_MAXCNT_SIZE 16 98 #define TWIS137_EASYDMA_MAXCNT_SIZE 16 99 100 #define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 101 #define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ 102 #define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 103 #define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 104 #define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 105 #define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 106 #define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 107 #define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 108 #define SPIM120_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 109 #define SPIM120_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 110 #define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 111 #define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 112 #define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 113 #define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 114 #define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ 115 #define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 116 #define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 117 #define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 118 #define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 119 #define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 120 #define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 121 #define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 122 #define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 123 #define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 124 #define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 125 126 #define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 127 #define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ 128 #define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 129 #define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 130 #define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 131 #define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 132 #define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 133 #define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 134 #define SPIM121_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 135 #define SPIM121_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 136 #define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 137 #define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 138 #define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 139 #define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 140 #define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ 141 #define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 142 #define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 143 #define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 144 #define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 145 #define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 146 #define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 147 #define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 148 #define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 149 #define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 150 #define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 151 152 #define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 153 #define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ 154 #define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 155 #define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 156 #define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 157 #define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 158 #define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 159 #define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 160 #define SPIM130_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 161 #define SPIM130_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 162 #define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 163 #define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 164 #define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 165 #define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 166 #define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ 167 #define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 168 #define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 169 #define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 170 #define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 171 #define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 172 #define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 173 #define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 174 #define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 175 #define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 176 #define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 177 178 #define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 179 #define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ 180 #define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 181 #define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 182 #define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 183 #define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 184 #define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 185 #define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 186 #define SPIM131_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 187 #define SPIM131_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 188 #define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 189 #define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 190 #define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 191 #define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 192 #define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ 193 #define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 194 #define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 195 #define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 196 #define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 197 #define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 198 #define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 199 #define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 200 #define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 201 #define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 202 #define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 203 204 #define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 205 #define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ 206 #define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 207 #define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 208 #define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 209 #define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 210 #define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 211 #define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 212 #define SPIM132_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 213 #define SPIM132_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 214 #define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 215 #define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 216 #define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 217 #define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 218 #define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ 219 #define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 220 #define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 221 #define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 222 #define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 223 #define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 224 #define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 225 #define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 226 #define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 227 #define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 228 #define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 229 230 #define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 231 #define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ 232 #define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 233 #define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 234 #define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 235 #define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 236 #define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 237 #define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 238 #define SPIM133_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 239 #define SPIM133_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 240 #define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 241 #define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 242 #define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 243 #define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 244 #define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ 245 #define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 246 #define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 247 #define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 248 #define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 249 #define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 250 #define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 251 #define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 252 #define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 253 #define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 254 #define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 255 256 #define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 257 #define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ 258 #define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 259 #define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 260 #define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 261 #define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 262 #define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 263 #define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 264 #define SPIM134_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 265 #define SPIM134_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 266 #define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 267 #define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 268 #define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 269 #define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 270 #define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ 271 #define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 272 #define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 273 #define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 274 #define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 275 #define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 276 #define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 277 #define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 278 #define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 279 #define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 280 #define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 281 282 #define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 283 #define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ 284 #define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 285 #define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 286 #define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 287 #define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 288 #define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 289 #define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 290 #define SPIM135_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 291 #define SPIM135_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 292 #define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 293 #define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 294 #define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 295 #define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 296 #define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ 297 #define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 298 #define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 299 #define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 300 #define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 301 #define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 302 #define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 303 #define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 304 #define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 305 #define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 306 #define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 307 308 #define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 309 #define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ 310 #define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 311 #define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 312 #define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 313 #define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 314 #define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 315 #define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 316 #define SPIM136_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 317 #define SPIM136_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 318 #define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 319 #define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 320 #define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 321 #define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 322 #define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ 323 #define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 324 #define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 325 #define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 326 #define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 327 #define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 328 #define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 329 #define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 330 #define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 331 #define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 332 #define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 333 334 #define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 335 #define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ 336 #define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 337 #define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ 338 #define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ 339 #define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 340 #define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 341 #define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 342 #define SPIM137_STALL_STATUS_PRESENT 1 /*!< (unspecified) */ 343 #define SPIM137_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 344 #define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 345 #define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 346 #define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 347 #define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 348 #define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ 349 #define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 350 #define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 351 #define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 352 #define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 353 #define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 354 #define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 355 #define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 356 #define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 357 #define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 358 #define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 359 360 361 #define RTC_CC_NUM RTC_CC_NUM_SIZE 362 #define RTC130_CC_NUM RTC130_CC_NUM_SIZE 363 #define RTC131_CC_NUM RTC131_CC_NUM_SIZE 364 365 #define TIMER020_MAX_SIZE TIMER020_MAX_SIZE_SIZE 366 #define TIMER021_MAX_SIZE TIMER021_MAX_SIZE_SIZE 367 #define TIMER022_MAX_SIZE TIMER022_MAX_SIZE_SIZE 368 #define TIMER120_MAX_SIZE TIMER120_MAX_SIZE_SIZE 369 #define TIMER121_MAX_SIZE TIMER121_MAX_SIZE_SIZE 370 #define TIMER130_MAX_SIZE TIMER130_MAX_SIZE_SIZE 371 #define TIMER131_MAX_SIZE TIMER131_MAX_SIZE_SIZE 372 #define TIMER132_MAX_SIZE TIMER132_MAX_SIZE_SIZE 373 #define TIMER133_MAX_SIZE TIMER133_MAX_SIZE_SIZE 374 #define TIMER134_MAX_SIZE TIMER134_MAX_SIZE_SIZE 375 #define TIMER135_MAX_SIZE TIMER135_MAX_SIZE_SIZE 376 #define TIMER136_MAX_SIZE TIMER136_MAX_SIZE_SIZE 377 #define TIMER137_MAX_SIZE TIMER137_MAX_SIZE_SIZE 378 379 #define TIMER020_CC_NUM TIMER020_CC_NUM_SIZE 380 #define TIMER021_CC_NUM TIMER021_CC_NUM_SIZE 381 #define TIMER022_CC_NUM TIMER022_CC_NUM_SIZE 382 #define TIMER120_CC_NUM TIMER120_CC_NUM_SIZE 383 #define TIMER121_CC_NUM TIMER121_CC_NUM_SIZE 384 #define TIMER130_CC_NUM TIMER130_CC_NUM_SIZE 385 #define TIMER131_CC_NUM TIMER131_CC_NUM_SIZE 386 #define TIMER132_CC_NUM TIMER132_CC_NUM_SIZE 387 #define TIMER133_CC_NUM TIMER133_CC_NUM_SIZE 388 #define TIMER134_CC_NUM TIMER134_CC_NUM_SIZE 389 #define TIMER135_CC_NUM TIMER135_CC_NUM_SIZE 390 #define TIMER136_CC_NUM TIMER136_CC_NUM_SIZE 391 #define TIMER137_CC_NUM TIMER137_CC_NUM_SIZE 392 393 #define DPPIC020_CH_NUM DPPIC020_CH_NUM_SIZE 394 #define DPPIC120_CH_NUM DPPIC120_CH_NUM_SIZE 395 #define DPPIC130_CH_NUM DPPIC130_CH_NUM_SIZE 396 #define DPPIC131_CH_NUM DPPIC131_CH_NUM_SIZE 397 #define DPPIC132_CH_NUM DPPIC132_CH_NUM_SIZE 398 #define DPPIC133_CH_NUM DPPIC133_CH_NUM_SIZE 399 #define DPPIC134_CH_NUM DPPIC134_CH_NUM_SIZE 400 #define DPPIC135_CH_NUM DPPIC135_CH_NUM_SIZE 401 #define DPPIC136_CH_NUM DPPIC136_CH_NUM_SIZE 402 403 #define DPPIC020_GROUP_NUM DPPIC020_GROUP_NUM_SIZE 404 #define DPPIC120_GROUP_NUM DPPIC120_GROUP_NUM_SIZE 405 #define DPPIC130_GROUP_NUM DPPIC130_GROUP_NUM_SIZE 406 #define DPPIC131_GROUP_NUM DPPIC131_GROUP_NUM_SIZE 407 #define DPPIC132_GROUP_NUM DPPIC132_GROUP_NUM_SIZE 408 #define DPPIC133_GROUP_NUM DPPIC133_GROUP_NUM_SIZE 409 #define DPPIC134_GROUP_NUM DPPIC134_GROUP_NUM_SIZE 410 #define DPPIC135_GROUP_NUM DPPIC135_GROUP_NUM_SIZE 411 #define DPPIC136_GROUP_NUM DPPIC136_GROUP_NUM_SIZE 412 413 #define UARTE120_EASYDMA_MAXCNT_SIZE UARTE120_EASYDMA_MAXCNT_SIZE_SIZE 414 #define UARTE130_EASYDMA_MAXCNT_SIZE UARTE130_EASYDMA_MAXCNT_SIZE_SIZE 415 #define UARTE131_EASYDMA_MAXCNT_SIZE UARTE131_EASYDMA_MAXCNT_SIZE_SIZE 416 #define UARTE132_EASYDMA_MAXCNT_SIZE UARTE132_EASYDMA_MAXCNT_SIZE_SIZE 417 #define UARTE133_EASYDMA_MAXCNT_SIZE UARTE133_EASYDMA_MAXCNT_SIZE_SIZE 418 #define UARTE134_EASYDMA_MAXCNT_SIZE UARTE134_EASYDMA_MAXCNT_SIZE_SIZE 419 #define UARTE135_EASYDMA_MAXCNT_SIZE UARTE135_EASYDMA_MAXCNT_SIZE_SIZE 420 #define UARTE136_EASYDMA_MAXCNT_SIZE UARTE136_EASYDMA_MAXCNT_SIZE_SIZE 421 #define UARTE137_EASYDMA_MAXCNT_SIZE UARTE137_EASYDMA_MAXCNT_SIZE_SIZE 422 423 #define I2S130_EASYDMA_MAXCNT_SIZE I2S130_EASYDMA_MAXCNT_SIZE_SIZE 424 #define I2S131_EASYDMA_MAXCNT_SIZE I2S131_EASYDMA_MAXCNT_SIZE_SIZE 425 426 #define P0_PIN_NUM P0_PIN_NUM_SIZE 427 #define P1_PIN_NUM P1_PIN_NUM_SIZE 428 #define P2_PIN_NUM P2_PIN_NUM_SIZE 429 #define P6_PIN_NUM P6_PIN_NUM_SIZE 430 #define P7_PIN_NUM P7_PIN_NUM_SIZE 431 #define P9_PIN_NUM P9_PIN_NUM_SIZE 432 433 #define EGU020_CH_NUM EGU020_CH_NUM_SIZE 434 435 #endif 436 437 #endif // NRF54H20_ENGA_INTERIM_H__ 438
