1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_FLPR_H 36 #define NRF54H20_ENGA_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 VPRTIM_IRQn = 32, /*!< 32 VPRTIM */ 86 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 87 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 88 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 89 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 90 TBM_IRQn = 127, /*!< 127 TBM */ 91 USBHS_IRQn = 134, /*!< 134 USBHS */ 92 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 93 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 94 I3C120_IRQn = 211, /*!< 211 I3C120 */ 95 VPR121_IRQn = 212, /*!< 212 VPR121 */ 96 CAN_IRQn = 216, /*!< 216 CAN */ 97 I3C121_IRQn = 222, /*!< 222 I3C121 */ 98 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 99 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 100 PWM120_IRQn = 228, /*!< 228 PWM120 */ 101 SPIS120_UARTE120_IRQn = 229, /*!< 229 SPIS120_UARTE120 */ 102 SPIM120_IRQn = 230, /*!< 230 SPIM120 */ 103 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 104 VPR130_IRQn = 264, /*!< 264 VPR130 */ 105 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 106 RTC130_IRQn = 296, /*!< 296 RTC130 */ 107 RTC131_IRQn = 297, /*!< 297 RTC131 */ 108 WDT131_IRQn = 299, /*!< 299 WDT131 */ 109 WDT132_IRQn = 300, /*!< 300 WDT132 */ 110 SAADC_IRQn = 386, /*!< 386 SAADC */ 111 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 112 TEMP_IRQn = 388, /*!< 388 TEMP */ 113 NFCT_IRQn = 389, /*!< 389 NFCT */ 114 I2S130_IRQn = 402, /*!< 402 I2S130 */ 115 PDM_IRQn = 403, /*!< 403 PDM */ 116 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 117 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 118 I2S131_IRQn = 407, /*!< 407 I2S131 */ 119 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 120 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 121 PWM130_IRQn = 420, /*!< 420 PWM130 */ 122 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 123 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 124 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 125 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 126 PWM131_IRQn = 436, /*!< 436 PWM131 */ 127 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 128 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 129 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 130 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 131 PWM132_IRQn = 452, /*!< 452 PWM132 */ 132 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 133 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 134 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 135 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 136 PWM133_IRQn = 468, /*!< 468 PWM133 */ 137 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 138 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 139 } IRQn_Type; 140 141 /* ==================================================== Interrupt Aliases ==================================================== */ 142 #define SPIS120_IRQn SPIS120_UARTE120_IRQn 143 #define SPIS120_IRQHandler SPIS120_UARTE120_IRQHandler 144 #define UARTE120_IRQn SPIS120_UARTE120_IRQn 145 #define UARTE120_IRQHandler SPIS120_UARTE120_IRQHandler 146 #define COMP_IRQn COMP_LPCOMP_IRQn 147 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 148 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 149 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 150 #define SPIM130_IRQn SERIAL0_IRQn 151 #define SPIM130_IRQHandler SERIAL0_IRQHandler 152 #define SPIS130_IRQn SERIAL0_IRQn 153 #define SPIS130_IRQHandler SERIAL0_IRQHandler 154 #define TWIM130_IRQn SERIAL0_IRQn 155 #define TWIM130_IRQHandler SERIAL0_IRQHandler 156 #define TWIS130_IRQn SERIAL0_IRQn 157 #define TWIS130_IRQHandler SERIAL0_IRQHandler 158 #define UARTE130_IRQn SERIAL0_IRQn 159 #define UARTE130_IRQHandler SERIAL0_IRQHandler 160 #define SPIM131_IRQn SERIAL1_IRQn 161 #define SPIM131_IRQHandler SERIAL1_IRQHandler 162 #define SPIS131_IRQn SERIAL1_IRQn 163 #define SPIS131_IRQHandler SERIAL1_IRQHandler 164 #define TWIM131_IRQn SERIAL1_IRQn 165 #define TWIM131_IRQHandler SERIAL1_IRQHandler 166 #define TWIS131_IRQn SERIAL1_IRQn 167 #define TWIS131_IRQHandler SERIAL1_IRQHandler 168 #define UARTE131_IRQn SERIAL1_IRQn 169 #define UARTE131_IRQHandler SERIAL1_IRQHandler 170 #define SPIM132_IRQn SERIAL2_IRQn 171 #define SPIM132_IRQHandler SERIAL2_IRQHandler 172 #define SPIS132_IRQn SERIAL2_IRQn 173 #define SPIS132_IRQHandler SERIAL2_IRQHandler 174 #define TWIM132_IRQn SERIAL2_IRQn 175 #define TWIM132_IRQHandler SERIAL2_IRQHandler 176 #define TWIS132_IRQn SERIAL2_IRQn 177 #define TWIS132_IRQHandler SERIAL2_IRQHandler 178 #define UARTE132_IRQn SERIAL2_IRQn 179 #define UARTE132_IRQHandler SERIAL2_IRQHandler 180 #define SPIM133_IRQn SERIAL3_IRQn 181 #define SPIM133_IRQHandler SERIAL3_IRQHandler 182 #define SPIS133_IRQn SERIAL3_IRQn 183 #define SPIS133_IRQHandler SERIAL3_IRQHandler 184 #define TWIM133_IRQn SERIAL3_IRQn 185 #define TWIM133_IRQHandler SERIAL3_IRQHandler 186 #define TWIS133_IRQn SERIAL3_IRQn 187 #define TWIS133_IRQHandler SERIAL3_IRQHandler 188 #define UARTE133_IRQn SERIAL3_IRQn 189 #define UARTE133_IRQHandler SERIAL3_IRQHandler 190 #define SPIM134_IRQn SERIAL4_IRQn 191 #define SPIM134_IRQHandler SERIAL4_IRQHandler 192 #define SPIS134_IRQn SERIAL4_IRQn 193 #define SPIS134_IRQHandler SERIAL4_IRQHandler 194 #define TWIM134_IRQn SERIAL4_IRQn 195 #define TWIM134_IRQHandler SERIAL4_IRQHandler 196 #define TWIS134_IRQn SERIAL4_IRQn 197 #define TWIS134_IRQHandler SERIAL4_IRQHandler 198 #define UARTE134_IRQn SERIAL4_IRQn 199 #define UARTE134_IRQHandler SERIAL4_IRQHandler 200 #define SPIM135_IRQn SERIAL5_IRQn 201 #define SPIM135_IRQHandler SERIAL5_IRQHandler 202 #define SPIS135_IRQn SERIAL5_IRQn 203 #define SPIS135_IRQHandler SERIAL5_IRQHandler 204 #define TWIM135_IRQn SERIAL5_IRQn 205 #define TWIM135_IRQHandler SERIAL5_IRQHandler 206 #define TWIS135_IRQn SERIAL5_IRQn 207 #define TWIS135_IRQHandler SERIAL5_IRQHandler 208 #define UARTE135_IRQn SERIAL5_IRQn 209 #define UARTE135_IRQHandler SERIAL5_IRQHandler 210 #define SPIM136_IRQn SERIAL6_IRQn 211 #define SPIM136_IRQHandler SERIAL6_IRQHandler 212 #define SPIS136_IRQn SERIAL6_IRQn 213 #define SPIS136_IRQHandler SERIAL6_IRQHandler 214 #define TWIM136_IRQn SERIAL6_IRQn 215 #define TWIM136_IRQHandler SERIAL6_IRQHandler 216 #define TWIS136_IRQn SERIAL6_IRQn 217 #define TWIS136_IRQHandler SERIAL6_IRQHandler 218 #define UARTE136_IRQn SERIAL6_IRQn 219 #define UARTE136_IRQHandler SERIAL6_IRQHandler 220 #define SPIM137_IRQn SERIAL7_IRQn 221 #define SPIM137_IRQHandler SERIAL7_IRQHandler 222 #define SPIS137_IRQn SERIAL7_IRQn 223 #define SPIS137_IRQHandler SERIAL7_IRQHandler 224 #define TWIM137_IRQn SERIAL7_IRQn 225 #define TWIM137_IRQHandler SERIAL7_IRQHandler 226 #define TWIS137_IRQn SERIAL7_IRQn 227 #define TWIS137_IRQHandler SERIAL7_IRQHandler 228 #define UARTE137_IRQn SERIAL7_IRQn 229 #define UARTE137_IRQHandler SERIAL7_IRQHandler 230 231 /* =========================================================================================================================== */ 232 /* ================ Processor and Core Peripheral Section ================ */ 233 /* =========================================================================================================================== */ 234 235 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 236 #define __VPR_REV 0.7 /*!< VPR Core Revision */ 237 #define __VPR_REV_MAJOR 0 /*!< VPR Core Major Revision */ 238 #define __VPR_REV_MINOR 7 /*!< VPR Core Minor Revision */ 239 #define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ 240 #define __DSP_PRESENT 0 /*!< DSP present or not */ 241 #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 242 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 243 #define __MPU_PRESENT 1 /*!< MPU present */ 244 #define __FPU_PRESENT 0 /*!< FPU present */ 245 #define __FPU_DP 0 /*!< Double Precision FPU */ 246 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 247 248 #define NRF_VPR NRF_VPR121 /*!< VPR instance name */ 249 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 250 #include "system_nrf.h" /*!< nrf54h20_enga_flpr System Library */ 251 252 #endif /*!< NRF_FLPR */ 253 254 255 #ifdef NRF_FLPR 256 257 #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST 258 #define NRF_PROCESSOR NRF_PROCESSOR_FLPR 259 #ifndef NRF_OWNER 260 #define NRF_OWNER NRF_OWNER_APPLICATION 261 #endif 262 263 #endif /*!< NRF_FLPR */ 264 265 266 /* ========================================= Start of section using anonymous unions ========================================= */ 267 268 #include "compiler_abstraction.h" 269 270 #if defined (__CC_ARM) 271 #pragma push 272 #pragma anon_unions 273 #elif defined (__ICCARM__) 274 #pragma language=extended 275 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 276 #pragma clang diagnostic push 277 #pragma clang diagnostic ignored "-Wc11-extensions" 278 #pragma clang diagnostic ignored "-Wreserved-id-macro" 279 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 280 #pragma clang diagnostic ignored "-Wnested-anon-types" 281 #elif defined (__GNUC__) 282 /* anonymous unions are enabled by default */ 283 #elif defined (__TMS470__) 284 /* anonymous unions are enabled by default */ 285 #elif defined (__TASKING__) 286 #pragma warning 586 287 #elif defined (__CSMC__) 288 /* anonymous unions are enabled by default */ 289 #else 290 #warning Unsupported compiler type 291 #endif 292 293 /* =========================================================================================================================== */ 294 /* ================ Peripheral Address Map ================ */ 295 /* =========================================================================================================================== */ 296 297 #define NRF_FLPR_VPRCLIC_NS_BASE 0x4F8D5000UL 298 #define NRF_FLPR_VPRCLIC_S_BASE 0x5F8D5000UL 299 300 /* =========================================================================================================================== */ 301 /* ================ Peripheral Declaration ================ */ 302 /* =========================================================================================================================== */ 303 304 #define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) 305 #define NRF_FLPR_VPRCLIC_S ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_S_BASE) 306 307 /* =========================================================================================================================== */ 308 /* ================ TrustZone Remapping ================ */ 309 /* =========================================================================================================================== */ 310 311 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 312 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 313 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 314 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_S 315 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 316 317 /* =========================================================================================================================== */ 318 /* ================ Local Domain Remapping ================ */ 319 /* =========================================================================================================================== */ 320 321 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 322 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 323 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 324 #else /*!< Remap all instances. */ 325 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 326 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 327 #endif /*!< NRF_FLPR */ 328 329 /* ========================================== End of section using anonymous unions ========================================== */ 330 331 #if defined (__CC_ARM) 332 #pragma pop 333 #elif defined (__ICCARM__) 334 /* leave anonymous unions enabled */ 335 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 336 #pragma clang diagnostic pop 337 #elif defined (__GNUC__) 338 /* anonymous unions are enabled by default */ 339 #elif defined (__TMS470__) 340 /* anonymous unions are enabled by default */ 341 #elif defined (__TASKING__) 342 #pragma warning restore 343 #elif defined (__CSMC__) 344 /* anonymous unions are enabled by default */ 345 #endif 346 347 348 #ifdef __cplusplus 349 } 350 #endif 351 #endif /* NRF54H20_ENGA_FLPR_H */ 352 353
