1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_APPLICATION_PERIPHERALS_H 36 #define NRF54H20_ENGA_APPLICATION_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*User information configuration registers*/ 44 #define UICR_PRESENT 1 45 #define UICR_COUNT 1 46 47 /*Board information configuration registers*/ 48 #define BICR_PRESENT 1 49 #define BICR_COUNT 1 50 51 #define BICR_P0_EXISTS 1 /*!< (unspecified) */ 52 #define BICR_P1_EXISTS 1 /*!< (unspecified) */ 53 #define BICR_P2_EXISTS 1 /*!< (unspecified) */ 54 #define BICR_P3_EXISTS 0 /*!< (unspecified) */ 55 #define BICR_P4_EXISTS 0 /*!< (unspecified) */ 56 #define BICR_P5_EXISTS 0 /*!< (unspecified) */ 57 #define BICR_P6_EXISTS 1 /*!< (unspecified) */ 58 #define BICR_P7_EXISTS 1 /*!< (unspecified) */ 59 #define BICR_P8_EXISTS 0 /*!< (unspecified) */ 60 #define BICR_P9_EXISTS 1 /*!< (unspecified) */ 61 #define BICR_P10_EXISTS 0 /*!< (unspecified) */ 62 #define BICR_P11_EXISTS 0 /*!< (unspecified) */ 63 #define BICR_P12_EXISTS 0 /*!< (unspecified) */ 64 #define BICR_P13_EXISTS 0 /*!< (unspecified) */ 65 #define BICR_P14_EXISTS 0 /*!< (unspecified) */ 66 #define BICR_P15_EXISTS 0 /*!< (unspecified) */ 67 #define BICR_P0_3V 0 /*!< (unspecified) */ 68 #define BICR_P1_3V 0 /*!< (unspecified) */ 69 #define BICR_P2_3V 0 /*!< (unspecified) */ 70 #define BICR_P3_3V 0 /*!< (unspecified) */ 71 #define BICR_P4_3V 0 /*!< (unspecified) */ 72 #define BICR_P5_3V 0 /*!< (unspecified) */ 73 #define BICR_P6_3V 0 /*!< (unspecified) */ 74 #define BICR_P7_3V 0 /*!< (unspecified) */ 75 #define BICR_P8_3V 0 /*!< (unspecified) */ 76 #define BICR_P9_3V 1 /*!< (unspecified) */ 77 #define BICR_P10_3V 0 /*!< (unspecified) */ 78 #define BICR_P11_3V 0 /*!< (unspecified) */ 79 #define BICR_P12_3V 0 /*!< (unspecified) */ 80 #define BICR_P13_3V 0 /*!< (unspecified) */ 81 #define BICR_P14_3V 0 /*!< (unspecified) */ 82 #define BICR_P15_3V 0 /*!< (unspecified) */ 83 #define BICR_P0_DRIVECTRL 0 /*!< (unspecified) */ 84 #define BICR_P1_DRIVECTRL 0 /*!< (unspecified) */ 85 #define BICR_P2_DRIVECTRL 0 /*!< (unspecified) */ 86 #define BICR_P3_DRIVECTRL 0 /*!< (unspecified) */ 87 #define BICR_P4_DRIVECTRL 0 /*!< (unspecified) */ 88 #define BICR_P5_DRIVECTRL 0 /*!< (unspecified) */ 89 #define BICR_P6_DRIVECTRL 1 /*!< (unspecified) */ 90 #define BICR_P7_DRIVECTRL 1 /*!< (unspecified) */ 91 #define BICR_P8_DRIVECTRL 0 /*!< (unspecified) */ 92 #define BICR_P9_DRIVECTRL 0 /*!< (unspecified) */ 93 #define BICR_P10_DRIVECTRL 0 /*!< (unspecified) */ 94 #define BICR_P11_DRIVECTRL 0 /*!< (unspecified) */ 95 #define BICR_P12_DRIVECTRL 0 /*!< (unspecified) */ 96 #define BICR_P13_DRIVECTRL 0 /*!< (unspecified) */ 97 #define BICR_P14_DRIVECTRL 0 /*!< (unspecified) */ 98 #define BICR_P15_DRIVECTRL 0 /*!< (unspecified) */ 99 #define BICR_PMICLDO 0 /*!< (unspecified) */ 100 101 /*CACHEDATA*/ 102 #define CACHEDATA_PRESENT 1 103 #define CACHEDATA_COUNT 2 104 105 /*CACHEINFO*/ 106 #define CACHEINFO_PRESENT 1 107 #define CACHEINFO_COUNT 2 108 109 /*Embedded Trace Macrocell*/ 110 #define ETM_PRESENT 1 111 #define ETM_COUNT 1 112 113 /*Cross-Trigger Interface control*/ 114 #define CTI_PRESENT 1 115 #define CTI_COUNT 3 116 117 /*CM33 SubSystem*/ 118 #define CM33SS_PRESENT 1 119 #define CM33SS_COUNT 1 120 121 #define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ 122 123 /*Cache*/ 124 #define CACHE_PRESENT 1 125 #define CACHE_COUNT 2 126 127 #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 128 #define ICACHE_FLUSH 1 /*!< (unspecified) */ 129 #define ICACHE_CLEAN 0 /*!< (unspecified) */ 130 131 #define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 132 #define DCACHE_FLUSH 1 /*!< (unspecified) */ 133 #define DCACHE_CLEAN 1 /*!< (unspecified) */ 134 135 /*System protection unit*/ 136 #define SPU_PRESENT 1 137 #define SPU_COUNT 2 138 139 #define SPU000_BELLS 0 /*!< (unspecified) */ 140 #define SPU000_IPCT 0 /*!< (unspecified) */ 141 #define SPU000_DPPI 0 /*!< (unspecified) */ 142 #define SPU000_GPIOTE 0 /*!< (unspecified) */ 143 #define SPU000_GRTC 1 /*!< (unspecified) */ 144 #define SPU000_GPIO 0 /*!< (unspecified) */ 145 146 #define SPU010_BELLS 0 /*!< (unspecified) */ 147 #define SPU010_IPCT 1 /*!< (unspecified) */ 148 #define SPU010_DPPI 0 /*!< (unspecified) */ 149 #define SPU010_GPIOTE 0 /*!< (unspecified) */ 150 #define SPU010_GRTC 1 /*!< (unspecified) */ 151 #define SPU010_GPIO 0 /*!< (unspecified) */ 152 153 /*Memory Privilege Controller*/ 154 #define MPC_PRESENT 1 155 #define MPC_COUNT 1 156 157 #define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 158 #define MPC_RTCHOKE 1 /*!< (unspecified) */ 159 #define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 160 161 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 162 163 #define MVDMA_PRESENT 1 164 #define MVDMA_COUNT 1 165 166 /*RAM Controller*/ 167 #define RAMC_PRESENT 1 168 #define RAMC_COUNT 1 169 170 #define RAMC_ECC 0 /*!< (unspecified) */ 171 #define RAMC_SEC 1 /*!< (unspecified) */ 172 173 /*HSFLL*/ 174 #define HSFLL_PRESENT 1 175 #define HSFLL_COUNT 1 176 177 #define HSFLL_DITHER_32B 0 /*!< (unspecified) */ 178 #define HSFLL_CLOCKCTRL_MULT_RESET 6 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ 179 180 /*LRCCONF*/ 181 #define LRCCONF_PRESENT 1 182 #define LRCCONF_COUNT 2 183 184 #define LRCCONF000_POWERON 0 /*!< (unspecified) */ 185 #define LRCCONF000_RETAIN 0 /*!< (unspecified) */ 186 #define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ 187 #define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ 188 #define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ 189 #define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ 190 #define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ 191 #define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ 192 #define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ 193 #define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ 194 #define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ 195 #define LRCCONF000_PDACT 0 /*!< (unspecified) */ 196 #define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ 197 #define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ 198 #define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ 199 #define LRCCONF000_OTHERON 0 /*!< (unspecified) */ 200 #define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ 201 #define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ 202 #define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ 203 #define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ 204 #define LRCCONF000_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 205 #define LRCCONF000_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 206 #define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 207 #define LRCCONF000_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 208 209 #define LRCCONF010_POWERON 1 /*!< (unspecified) */ 210 #define LRCCONF010_RETAIN 1 /*!< (unspecified) */ 211 #define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ 212 #define LRCCONF010_LRCREQHFXO 0 /*!< (unspecified) */ 213 #define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ 214 #define LRCCONF010_NCLK_MAX 7 /*!< (unspecified) */ 215 #define LRCCONF010_NCLK_SIZE 8 /*!< (unspecified) */ 216 #define LRCCONF010_CLKCTRL 0 /*!< (unspecified) */ 217 #define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ 218 #define LRCCONF010_NACTPD_MAX 0 /*!< (unspecified) */ 219 #define LRCCONF010_NACTPD_SIZE 1 /*!< (unspecified) */ 220 #define LRCCONF010_PDACT 1 /*!< (unspecified) */ 221 #define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ 222 #define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ 223 #define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ 224 #define LRCCONF010_OTHERON 0 /*!< (unspecified) */ 225 #define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ 226 #define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ 227 #define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ 228 #define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ 229 #define LRCCONF010_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 230 #define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 231 #define LRCCONF010_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 232 #define LRCCONF010_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 233 234 /*Memory configuration*/ 235 #define MEMCONF_PRESENT 1 236 #define MEMCONF_COUNT 1 237 238 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 239 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 240 #define MEMCONF_POWER 1 /*!< (unspecified) */ 241 242 /*Watchdog Timer*/ 243 #define WDT_PRESENT 1 244 #define WDT_COUNT 4 245 246 /*ABB peripheral*/ 247 #define ABB_PRESENT 1 248 #define ABB_COUNT 1 249 250 /*RESETINFO*/ 251 #define RESETINFO_PRESENT 1 252 #define RESETINFO_COUNT 1 253 254 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ 255 256 /*IPCT APB registers*/ 257 #define IPCT_PRESENT 1 258 #define IPCT_COUNT 3 259 260 #define IPCT_IRQ_COUNT 2 261 262 #define IPCT120_IRQ_COUNT 1 263 264 #define IPCT130_IRQ_COUNT 1 265 266 /*BELLBOARD APB registers*/ 267 #define BELLBOARD_PRESENT 1 268 #define BELLBOARD_COUNT 1 269 270 #define BELLBOARD_IRQ_COUNT 4 271 272 /*Factory Information Configuration Registers*/ 273 #define FICR_PRESENT 1 274 #define FICR_COUNT 1 275 276 /*USBHSCORE*/ 277 #define USBHSCORE_PRESENT 1 278 #define USBHSCORE_COUNT 1 279 280 /*I3CCORE*/ 281 #define I3CCORE_PRESENT 1 282 #define I3CCORE_COUNT 2 283 284 /*DMU*/ 285 #define DMU_PRESENT 1 286 #define DMU_COUNT 1 287 288 /*MCAN*/ 289 #define MCAN_PRESENT 1 290 #define MCAN_COUNT 1 291 292 /*System Trace Macrocell data buffer*/ 293 #define STMDATA_PRESENT 1 294 #define STMDATA_COUNT 1 295 296 /*TDDCONF*/ 297 #define TDDCONF_PRESENT 1 298 #define TDDCONF_COUNT 1 299 300 /*System Trace Macrocell*/ 301 #define STM_PRESENT 1 302 #define STM_COUNT 1 303 304 /*Trace Port Interface Unit*/ 305 #define TPIU_PRESENT 1 306 #define TPIU_COUNT 1 307 308 /*ATB Replicator module*/ 309 #define ATBREPLICATOR_PRESENT 1 310 #define ATBREPLICATOR_COUNT 4 311 312 /*ATB funnel module*/ 313 #define ATBFUNNEL_PRESENT 1 314 #define ATBFUNNEL_COUNT 4 315 316 /*GPIO Tasks and Events*/ 317 #define GPIOTE_PRESENT 1 318 #define GPIOTE_COUNT 1 319 320 #define GPIOTE130_IRQ_COUNT 2 321 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 322 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 323 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 324 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 325 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 326 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 327 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 328 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 329 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 330 331 /*Global Real-time counter*/ 332 #define GRTC_PRESENT 1 333 #define GRTC_COUNT 1 334 335 #define GRTC_IRQ_COUNT 2 336 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 337 0..14*/ 338 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 339 0..14*/ 340 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 341 0..14*/ 342 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 343 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 344 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 345 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 346 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 347 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 348 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 349 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 350 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 351 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..1 */ 352 #define GRTC_GRTC_NINTERRUPTS_MAX 1 /*!< Number of GRTC interrupts : 0..1 */ 353 #define GRTC_GRTC_NINTERRUPTS_SIZE 2 /*!< Number of GRTC interrupts : 0..1 */ 354 #define GRTC_PWMREGS 0 /*!< (unspecified) */ 355 #define GRTC_CLKOUTREG 0 /*!< (unspecified) */ 356 357 /*Trace buffer monitor*/ 358 #define TBM_PRESENT 1 359 #define TBM_COUNT 1 360 361 /*USBHS*/ 362 #define USBHS_PRESENT 1 363 #define USBHS_COUNT 1 364 365 /*External Memory Interface*/ 366 #define EXMIF_PRESENT 1 367 #define EXMIF_COUNT 1 368 369 /*BELLBOARD public registers*/ 370 #define BELLBOARDPUBLIC_PRESENT 1 371 #define BELLBOARDPUBLIC_COUNT 1 372 373 /*VPR peripheral registers*/ 374 #define VPRPUBLIC_PRESENT 1 375 #define VPRPUBLIC_COUNT 1 376 377 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 378 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 379 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 380 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 381 382 /*MUTEX*/ 383 #define MUTEX_PRESENT 1 384 #define MUTEX_COUNT 2 385 386 /*I3C*/ 387 #define I3C_PRESENT 1 388 #define I3C_COUNT 2 389 390 /*VPR peripheral registers*/ 391 #define VPR_PRESENT 1 392 #define VPR_COUNT 2 393 394 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 395 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 396 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 397 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 398 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 399 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 400 #define VPR121_RETAINED 0 /*!< (unspecified) */ 401 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 402 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 403 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 404 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 405 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 406 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 407 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 408 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 409 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 410 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 411 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 412 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 413 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 414 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 415 416 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 417 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 418 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 419 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 420 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 421 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 422 #define VPR130_RETAINED 0 /*!< (unspecified) */ 423 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 424 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 425 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 426 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 427 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 428 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 429 #define VPR130_VEVIF_TASKS_MASK 0xFFFFFFF0 /*!< Mask of supported VEVIF tasks: 0xFFFFFFF0 */ 430 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 431 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 432 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 433 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 434 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 435 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 436 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 437 438 /*Controller Area Network*/ 439 #define CAN_PRESENT 1 440 #define CAN_COUNT 1 441 442 /*Distributed programmable peripheral interconnect controller*/ 443 #define DPPIC_PRESENT 1 444 #define DPPIC_COUNT 8 445 446 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 447 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 448 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 449 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 450 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 451 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 452 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 453 454 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 455 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 456 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 457 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 458 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 459 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 460 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 461 462 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 463 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 464 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 465 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 466 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 467 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 468 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 469 470 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 471 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 472 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 473 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 474 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 475 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 476 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 477 478 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 479 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 480 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 481 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 482 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 483 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 484 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 485 486 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 487 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 488 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 489 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 490 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 491 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 492 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 493 494 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 495 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 496 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 497 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 498 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 499 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 500 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 501 502 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 503 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 504 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 505 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 506 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 507 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 508 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 509 510 /*Timer/Counter*/ 511 #define TIMER_PRESENT 1 512 #define TIMER_COUNT 10 513 514 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 515 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 516 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 517 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 518 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 519 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 520 521 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 522 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 523 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 524 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 525 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 526 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 527 528 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 529 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 530 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 531 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 532 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 533 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 534 535 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 536 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 537 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 538 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 539 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 540 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 541 542 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 543 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 544 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 545 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 546 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 547 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 548 549 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 550 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 551 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 552 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 553 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 554 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 555 556 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 557 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 558 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 559 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 560 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 561 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 562 563 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 564 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 565 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 566 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 567 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 568 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 569 570 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 571 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 572 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 573 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 574 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 575 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 576 577 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 578 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 579 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 580 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 581 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 582 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 583 584 /*Pulse width modulation unit*/ 585 #define PWM_PRESENT 1 586 #define PWM_COUNT 5 587 588 /*SPI Slave*/ 589 #define SPIS_PRESENT 1 590 #define SPIS_COUNT 9 591 592 #define SPIS120_LEGACYPSEL 0 /*!< (unspecified) */ 593 #define SPIS120_LEGACYEDMA 0 /*!< (unspecified) */ 594 595 #define SPIS130_LEGACYPSEL 0 /*!< (unspecified) */ 596 #define SPIS130_LEGACYEDMA 0 /*!< (unspecified) */ 597 598 #define SPIS131_LEGACYPSEL 0 /*!< (unspecified) */ 599 #define SPIS131_LEGACYEDMA 0 /*!< (unspecified) */ 600 601 #define SPIS132_LEGACYPSEL 0 /*!< (unspecified) */ 602 #define SPIS132_LEGACYEDMA 0 /*!< (unspecified) */ 603 604 #define SPIS133_LEGACYPSEL 0 /*!< (unspecified) */ 605 #define SPIS133_LEGACYEDMA 0 /*!< (unspecified) */ 606 607 #define SPIS134_LEGACYPSEL 0 /*!< (unspecified) */ 608 #define SPIS134_LEGACYEDMA 0 /*!< (unspecified) */ 609 610 #define SPIS135_LEGACYPSEL 0 /*!< (unspecified) */ 611 #define SPIS135_LEGACYEDMA 0 /*!< (unspecified) */ 612 613 #define SPIS136_LEGACYPSEL 0 /*!< (unspecified) */ 614 #define SPIS136_LEGACYEDMA 0 /*!< (unspecified) */ 615 616 #define SPIS137_LEGACYPSEL 0 /*!< (unspecified) */ 617 #define SPIS137_LEGACYEDMA 0 /*!< (unspecified) */ 618 619 /*UART with EasyDMA*/ 620 #define UARTE_PRESENT 1 621 #define UARTE_COUNT 9 622 623 #define UARTE120_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 624 #define UARTE120_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 625 #define UARTE120_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 626 627 #define UARTE130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 628 #define UARTE130_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 629 #define UARTE130_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 630 631 #define UARTE131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 632 #define UARTE131_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 633 #define UARTE131_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 634 635 #define UARTE132_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 636 #define UARTE132_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 637 #define UARTE132_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 638 639 #define UARTE133_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 640 #define UARTE133_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 641 #define UARTE133_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 642 643 #define UARTE134_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 644 #define UARTE134_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 645 #define UARTE134_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 646 647 #define UARTE135_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 648 #define UARTE135_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 649 #define UARTE135_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 650 651 #define UARTE136_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 652 #define UARTE136_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 653 #define UARTE136_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 654 655 #define UARTE137_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 656 #define UARTE137_EASYDMA_MAXCNT_SIZE_MAX 14 /*!< (unspecified) */ 657 #define UARTE137_EASYDMA_MAXCNT_SIZE_SIZE 15 /*!< (unspecified) */ 658 659 /*Serial Peripheral Interface Master with EasyDMA*/ 660 #define SPIM_PRESENT 1 661 #define SPIM_COUNT 10 662 663 #define SPIM120_HSSPI 1 /*!< (unspecified) */ 664 665 #define SPIM121_HSSPI 1 /*!< (unspecified) */ 666 667 #define SPIM130_HSSPI 1 /*!< (unspecified) */ 668 669 #define SPIM131_HSSPI 1 /*!< (unspecified) */ 670 671 #define SPIM132_HSSPI 1 /*!< (unspecified) */ 672 673 #define SPIM133_HSSPI 1 /*!< (unspecified) */ 674 675 #define SPIM134_HSSPI 1 /*!< (unspecified) */ 676 677 #define SPIM135_HSSPI 1 /*!< (unspecified) */ 678 679 #define SPIM136_HSSPI 1 /*!< (unspecified) */ 680 681 #define SPIM137_HSSPI 1 /*!< (unspecified) */ 682 683 /*Real-time counter*/ 684 #define RTC_PRESENT 1 685 #define RTC_COUNT 2 686 687 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 688 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 689 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 690 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 691 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 692 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 693 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 694 695 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 696 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 697 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 698 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 699 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 700 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 701 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 702 703 /*GPIO Port*/ 704 #define GPIO_PRESENT 1 705 #define GPIO_COUNT 6 706 707 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 708 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 709 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 710 #define P0_PIN_NUM_MAX 11 /*!< (unspecified) */ 711 #define P0_PIN_NUM_SIZE 12 /*!< (unspecified) */ 712 #define P0_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 713 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 714 #define P0_RETAIN 1 /*!< (unspecified) */ 715 #define P0_PWRCTRL 0 /*!< (unspecified) */ 716 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 717 #define P0_BIASCTRL 0 /*!< (unspecified) */ 718 719 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 720 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 721 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 722 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 723 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 724 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 725 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 726 #define P1_RETAIN 1 /*!< (unspecified) */ 727 #define P1_PWRCTRL 0 /*!< (unspecified) */ 728 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 729 #define P1_BIASCTRL 0 /*!< (unspecified) */ 730 731 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 732 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 733 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 734 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 735 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 736 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 737 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 738 #define P2_RETAIN 1 /*!< (unspecified) */ 739 #define P2_PWRCTRL 0 /*!< (unspecified) */ 740 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 741 #define P2_BIASCTRL 0 /*!< (unspecified) */ 742 743 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 744 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 745 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 746 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 747 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 748 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 749 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 750 #define P6_RETAIN 1 /*!< (unspecified) */ 751 #define P6_PWRCTRL 0 /*!< (unspecified) */ 752 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 753 #define P6_BIASCTRL 0 /*!< (unspecified) */ 754 755 #define P7_CTRLSEL_MAP1 1 /*!< (unspecified) */ 756 #define P7_CTRLSEL_MAP2 0 /*!< (unspecified) */ 757 #define P7_PIN_NUM_MIN 0 /*!< (unspecified) */ 758 #define P7_PIN_NUM_MAX 7 /*!< (unspecified) */ 759 #define P7_PIN_NUM_SIZE 8 /*!< (unspecified) */ 760 #define P7_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 761 #define P7_DRIVECTRL 1 /*!< (unspecified) */ 762 #define P7_RETAIN 1 /*!< (unspecified) */ 763 #define P7_PWRCTRL 0 /*!< (unspecified) */ 764 #define P7_PIN_OWNER_SEC 0 /*!< (unspecified) */ 765 #define P7_BIASCTRL 0 /*!< (unspecified) */ 766 767 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 768 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 769 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 770 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 771 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 772 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 773 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 774 #define P9_RETAIN 1 /*!< (unspecified) */ 775 #define P9_PWRCTRL 1 /*!< (unspecified) */ 776 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 777 #define P9_BIASCTRL 0 /*!< (unspecified) */ 778 779 /*Analog to Digital Converter*/ 780 #define SAADC_PRESENT 1 781 #define SAADC_COUNT 1 782 783 /*Comparator*/ 784 #define COMP_PRESENT 1 785 #define COMP_COUNT 1 786 787 /*Low-power comparator*/ 788 #define LPCOMP_PRESENT 1 789 #define LPCOMP_COUNT 1 790 791 /*Temperature Sensor*/ 792 #define TEMP_PRESENT 1 793 #define TEMP_COUNT 1 794 795 /*NFC-A compatible radio NFC-A compatible radio*/ 796 #define NFCT_PRESENT 1 797 #define NFCT_COUNT 1 798 799 /*Inter-IC Sound*/ 800 #define I2S_PRESENT 1 801 #define I2S_COUNT 2 802 803 #define I2S130_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 804 #define I2S130_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 805 #define I2S130_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 806 807 #define I2S131_EASYDMA_MAXCNT_SIZE_MIN 0 /*!< (unspecified) */ 808 #define I2S131_EASYDMA_MAXCNT_SIZE_MAX 13 /*!< (unspecified) */ 809 #define I2S131_EASYDMA_MAXCNT_SIZE_SIZE 14 /*!< (unspecified) */ 810 811 /*Pulse Density Modulation (Digital Microphone) Interface*/ 812 #define PDM_PRESENT 1 813 #define PDM_COUNT 1 814 815 /*Quadrature Decoder*/ 816 #define QDEC_PRESENT 1 817 #define QDEC_COUNT 2 818 819 #define QDEC130_LEGACYPSEL 0 /*!< (unspecified) */ 820 821 #define QDEC131_LEGACYPSEL 0 /*!< (unspecified) */ 822 823 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 824 #define TWIM_PRESENT 1 825 #define TWIM_COUNT 8 826 827 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 828 #define TWIS_PRESENT 1 829 #define TWIS_COUNT 8 830 831 832 #ifdef __cplusplus 833 } 834 #endif 835 #endif /* NRF54H20_ENGA_APPLICATION_PERIPHERALS_H */ 836 837
