1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_APPLICATION_PERIPHERALS_H 36 #define NRF54H20_APPLICATION_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*Extended UICR.*/ 44 #define UICREXTENDED_PRESENT 1 45 #define UICREXTENDED_COUNT 1 46 47 /*CACHEDATA*/ 48 #define ICACHEDATA_PRESENT 1 49 #define ICACHEDATA_COUNT 1 50 51 #define ICACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ 52 #define ICACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ 53 #define ICACHEDATA_NUMDATAUNIT 4 /*!< Number of data units : 4 */ 54 #define ICACHEDATA_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ 55 56 /*CACHEINFO*/ 57 #define ICACHEINFO_PRESENT 1 58 #define ICACHEINFO_COUNT 1 59 60 #define ICACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ 61 #define ICACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ 62 #define ICACHEINFO_NUMDATAUNIT 4 /*!< Number of data units : 4 */ 63 #define ICACHEINFO_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ 64 #define ICACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ 65 #define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ 66 67 /*User information configuration registers*/ 68 #define UICR_PRESENT 1 69 #define UICR_COUNT 1 70 71 /*Board information configuration registers*/ 72 #define BICR_PRESENT 1 73 #define BICR_COUNT 1 74 75 #define BICR_P0_INTERNAL 1 /*!< (unspecified) */ 76 #define BICR_P0_POWER 0 /*!< (unspecified) */ 77 #define BICR_P1_POWER 1 /*!< (unspecified) */ 78 #define BICR_P2_POWER 1 /*!< (unspecified) */ 79 #define BICR_P3_POWER 0 /*!< (unspecified) */ 80 #define BICR_P4_POWER 0 /*!< (unspecified) */ 81 #define BICR_P5_POWER 0 /*!< (unspecified) */ 82 #define BICR_P6_POWER 1 /*!< (unspecified) */ 83 #define BICR_P7_POWER 1 /*!< (unspecified) */ 84 #define BICR_P8_POWER 0 /*!< (unspecified) */ 85 #define BICR_P9_POWER 1 /*!< (unspecified) */ 86 #define BICR_P10_POWER 0 /*!< (unspecified) */ 87 #define BICR_P11_POWER 0 /*!< (unspecified) */ 88 #define BICR_P12_POWER 0 /*!< (unspecified) */ 89 #define BICR_P13_POWER 0 /*!< (unspecified) */ 90 #define BICR_P14_POWER 0 /*!< (unspecified) */ 91 #define BICR_P15_POWER 0 /*!< (unspecified) */ 92 #define BICR_P0_POWER_3V 0 /*!< (unspecified) */ 93 #define BICR_P1_POWER_3V 0 /*!< (unspecified) */ 94 #define BICR_P2_POWER_3V 0 /*!< (unspecified) */ 95 #define BICR_P3_POWER_3V 0 /*!< (unspecified) */ 96 #define BICR_P4_POWER_3V 0 /*!< (unspecified) */ 97 #define BICR_P5_POWER_3V 0 /*!< (unspecified) */ 98 #define BICR_P6_POWER_3V 0 /*!< (unspecified) */ 99 #define BICR_P7_POWER_3V 0 /*!< (unspecified) */ 100 #define BICR_P8_POWER_3V 0 /*!< (unspecified) */ 101 #define BICR_P9_POWER_3V 1 /*!< (unspecified) */ 102 #define BICR_P10_POWER_3V 0 /*!< (unspecified) */ 103 #define BICR_P11_POWER_3V 0 /*!< (unspecified) */ 104 #define BICR_P12_POWER_3V 0 /*!< (unspecified) */ 105 #define BICR_P13_POWER_3V 0 /*!< (unspecified) */ 106 #define BICR_P14_POWER_3V 0 /*!< (unspecified) */ 107 #define BICR_P15_POWER_3V 0 /*!< (unspecified) */ 108 #define BICR_P0_DRIVECTRL 0 /*!< (unspecified) */ 109 #define BICR_P1_DRIVECTRL 0 /*!< (unspecified) */ 110 #define BICR_P2_DRIVECTRL 0 /*!< (unspecified) */ 111 #define BICR_P3_DRIVECTRL 0 /*!< (unspecified) */ 112 #define BICR_P4_DRIVECTRL 0 /*!< (unspecified) */ 113 #define BICR_P5_DRIVECTRL 0 /*!< (unspecified) */ 114 #define BICR_P6_DRIVECTRL 1 /*!< (unspecified) */ 115 #define BICR_P7_DRIVECTRL 1 /*!< (unspecified) */ 116 #define BICR_P8_DRIVECTRL 0 /*!< (unspecified) */ 117 #define BICR_P9_DRIVECTRL 0 /*!< (unspecified) */ 118 #define BICR_P10_DRIVECTRL 0 /*!< (unspecified) */ 119 #define BICR_P11_DRIVECTRL 0 /*!< (unspecified) */ 120 #define BICR_P12_DRIVECTRL 0 /*!< (unspecified) */ 121 #define BICR_P13_DRIVECTRL 0 /*!< (unspecified) */ 122 #define BICR_P14_DRIVECTRL 0 /*!< (unspecified) */ 123 #define BICR_P15_DRIVECTRL 0 /*!< (unspecified) */ 124 #define BICR_P0_BIASCTRL 0 /*!< (unspecified) */ 125 #define BICR_P1_BIASCTRL 0 /*!< (unspecified) */ 126 #define BICR_P2_BIASCTRL 0 /*!< (unspecified) */ 127 #define BICR_P3_BIASCTRL 0 /*!< (unspecified) */ 128 #define BICR_P4_BIASCTRL 0 /*!< (unspecified) */ 129 #define BICR_P5_BIASCTRL 0 /*!< (unspecified) */ 130 #define BICR_P6_BIASCTRL 0 /*!< (unspecified) */ 131 #define BICR_P7_BIASCTRL 0 /*!< (unspecified) */ 132 #define BICR_P8_BIASCTRL 0 /*!< (unspecified) */ 133 #define BICR_P9_BIASCTRL 0 /*!< (unspecified) */ 134 #define BICR_P10_BIASCTRL 0 /*!< (unspecified) */ 135 #define BICR_P11_BIASCTRL 0 /*!< (unspecified) */ 136 #define BICR_P12_BIASCTRL 0 /*!< (unspecified) */ 137 #define BICR_P13_BIASCTRL 0 /*!< (unspecified) */ 138 #define BICR_P14_BIASCTRL 0 /*!< (unspecified) */ 139 #define BICR_P15_BIASCTRL 0 /*!< (unspecified) */ 140 #define BICR_PMICLDO 0 /*!< (unspecified) */ 141 142 /*CACHEDATA*/ 143 #define DCACHEDATA_PRESENT 1 144 #define DCACHEDATA_COUNT 1 145 146 #define DCACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ 147 #define DCACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ 148 #define DCACHEDATA_NUMDATAUNIT 8 /*!< Number of data units : 8 */ 149 #define DCACHEDATA_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ 150 151 /*CACHEINFO*/ 152 #define DCACHEINFO_PRESENT 1 153 #define DCACHEINFO_COUNT 1 154 155 #define DCACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ 156 #define DCACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ 157 #define DCACHEINFO_NUMDATAUNIT 8 /*!< Number of data units : 8 */ 158 #define DCACHEINFO_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ 159 #define DCACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ 160 #define DCACHEINFO_DU_EXTENSION 1 /*!< (unspecified) */ 161 162 /*Embedded Trace Macrocell*/ 163 #define ETM_PRESENT 1 164 #define ETM_COUNT 1 165 166 /*Cross-Trigger Interface control*/ 167 #define CTI_PRESENT 1 168 #define CTI_COUNT 3 169 170 /*Cache*/ 171 #define CACHE_PRESENT 1 172 #define CACHE_COUNT 2 173 174 #define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 175 #define ICACHE_FLUSH 0 /*!< (unspecified) */ 176 #define ICACHE_CLEAN 0 /*!< (unspecified) */ 177 #define ICACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ 178 #define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ 179 #define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ 180 #define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ 181 #define ICACHE_SECUREINVALIDATE 1 /*!< (unspecified) */ 182 183 #define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ 184 #define DCACHE_FLUSH 1 /*!< (unspecified) */ 185 #define DCACHE_CLEAN 1 /*!< (unspecified) */ 186 #define DCACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ 187 #define DCACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ 188 #define DCACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ 189 #define DCACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ 190 #define DCACHE_SECUREINVALIDATE 1 /*!< (unspecified) */ 191 192 /*System protection unit*/ 193 #define SPU_PRESENT 1 194 #define SPU_COUNT 2 195 196 #define SPU000_BELLS 0 /*!< (unspecified) */ 197 #define SPU000_IPCT 0 /*!< (unspecified) */ 198 #define SPU000_DPPI 0 /*!< (unspecified) */ 199 #define SPU000_GPIOTE 0 /*!< (unspecified) */ 200 #define SPU000_GRTC 0 /*!< (unspecified) */ 201 #define SPU000_GPIO 0 /*!< (unspecified) */ 202 #define SPU000_CRACEN 0 /*!< (unspecified) */ 203 #define SPU000_MRAMC 0 /*!< (unspecified) */ 204 #define SPU000_COEXC 0 /*!< (unspecified) */ 205 #define SPU000_ANTSWC 0 /*!< (unspecified) */ 206 #define SPU000_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 207 peripheral slave index)*/ 208 209 #define SPU010_BELLS 0 /*!< (unspecified) */ 210 #define SPU010_IPCT 1 /*!< (unspecified) */ 211 #define SPU010_DPPI 0 /*!< (unspecified) */ 212 #define SPU010_GPIOTE 0 /*!< (unspecified) */ 213 #define SPU010_GRTC 0 /*!< (unspecified) */ 214 #define SPU010_GPIO 0 /*!< (unspecified) */ 215 #define SPU010_CRACEN 0 /*!< (unspecified) */ 216 #define SPU010_MRAMC 0 /*!< (unspecified) */ 217 #define SPU010_COEXC 0 /*!< (unspecified) */ 218 #define SPU010_ANTSWC 0 /*!< (unspecified) */ 219 #define SPU010_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 220 peripheral slave index)*/ 221 222 /*Memory Privilege Controller*/ 223 #define MPC_PRESENT 1 224 #define MPC_COUNT 1 225 226 #define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 227 #define MPC_RTCHOKE 1 /*!< (unspecified) */ 228 #define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 229 230 /*CM33 SubSystem*/ 231 #define CM33SS_PRESENT 1 232 #define CM33SS_COUNT 1 233 234 #define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ 235 236 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 237 238 #define MVDMA_PRESENT 1 239 #define MVDMA_COUNT 2 240 241 #define MVDMA_COMPLETED_EVENT 1 /*!< (unspecified) */ 242 #define MVDMA_DPPI_DISCONNECTED 0 /*!< (unspecified) */ 243 #define MVDMA_INSTANCE_IN_WRAPPER 0 /*!< (unspecified) */ 244 245 #define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ 246 #define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ 247 #define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ 248 249 /*RAM Controller*/ 250 #define RAMC_PRESENT 1 251 #define RAMC_COUNT 2 252 253 #define RAMC_ECC 0 /*!< (unspecified) */ 254 #define RAMC_SEC 1 /*!< (unspecified) */ 255 256 #define RAMC122_ECC 0 /*!< (unspecified) */ 257 #define RAMC122_SEC 0 /*!< (unspecified) */ 258 259 /*HSFLL*/ 260 #define HSFLL_PRESENT 1 261 #define HSFLL_COUNT 1 262 263 #define HSFLL_DITHER_32B 1 /*!< (unspecified) */ 264 #define HSFLL_CLOCKCTRL_MULT_RESET 4 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ 265 #define HSFLL_CLOCKCTRL_INTEGER_DIVISION 0 /*!< (unspecified) */ 266 267 /*LRCCONF*/ 268 #define LRCCONF_PRESENT 1 269 #define LRCCONF_COUNT 2 270 271 #define LRCCONF000_POWERON 0 /*!< (unspecified) */ 272 #define LRCCONF000_RETAIN 0 /*!< (unspecified) */ 273 #define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ 274 #define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ 275 #define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ 276 #define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ 277 #define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ 278 #define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ 279 #define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ 280 #define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ 281 #define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ 282 #define LRCCONF000_PDACT 0 /*!< (unspecified) */ 283 #define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ 284 #define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ 285 #define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ 286 #define LRCCONF000_OTHERON 0 /*!< (unspecified) */ 287 #define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ 288 #define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ 289 #define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ 290 #define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ 291 #define LRCCONF000_POWERON_MAIN_RESET 0 /*!< (unspecified) */ 292 #define LRCCONF000_POWERON_ACT_RESET 0 /*!< (unspecified) */ 293 #define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ 294 #define LRCCONF000_RETAIN_ACT_RESET 1 /*!< (unspecified) */ 295 296 #define LRCCONF010_POWERON 1 /*!< (unspecified) */ 297 #define LRCCONF010_RETAIN 1 /*!< (unspecified) */ 298 #define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ 299 #define LRCCONF010_LRCREQHFXO 1 /*!< (unspecified) */ 300 #define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ 301 #define LRCCONF010_NCLK_MAX 0 /*!< (unspecified) */ 302 #define LRCCONF010_NCLK_SIZE 1 /*!< (unspecified) */ 303 #define LRCCONF010_CLKCTRL 1 /*!< (unspecified) */ 304 #define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ 305 #define LRCCONF010_NACTPD_MAX 0 /*!< (unspecified) */ 306 #define LRCCONF010_NACTPD_SIZE 1 /*!< (unspecified) */ 307 #define LRCCONF010_PDACT 1 /*!< (unspecified) */ 308 #define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ 309 #define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ 310 #define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ 311 #define LRCCONF010_OTHERON 0 /*!< (unspecified) */ 312 #define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ 313 #define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ 314 #define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ 315 #define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ 316 #define LRCCONF010_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 317 #define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 318 #define LRCCONF010_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 319 #define LRCCONF010_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 320 321 /*Memory configuration*/ 322 #define MEMCONF_PRESENT 1 323 #define MEMCONF_COUNT 1 324 325 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 326 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 327 #define MEMCONF_POWER 1 /*!< (unspecified) */ 328 329 /*Watchdog Timer*/ 330 #define WDT_PRESENT 1 331 #define WDT_COUNT 4 332 333 #define WDT010_ALLOW_STOP 0 /*!< (unspecified) */ 334 #define WDT010_HAS_INTEN 1 /*!< (unspecified) */ 335 336 #define WDT011_ALLOW_STOP 0 /*!< (unspecified) */ 337 #define WDT011_HAS_INTEN 1 /*!< (unspecified) */ 338 339 #define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ 340 #define WDT131_HAS_INTEN 1 /*!< (unspecified) */ 341 342 #define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ 343 #define WDT132_HAS_INTEN 1 /*!< (unspecified) */ 344 345 /*ABB peripheral*/ 346 #define ABB_PRESENT 1 347 #define ABB_COUNT 1 348 349 /*RESETINFO*/ 350 #define RESETINFO_PRESENT 1 351 #define RESETINFO_COUNT 1 352 353 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ 354 #define RESETINFO_CROSSDOMAINRESET 0 /*!< (unspecified) */ 355 356 /*IPCT APB registers*/ 357 #define IPCT_PRESENT 1 358 #define IPCT_COUNT 3 359 360 #define IPCT_IRQ_COUNT 2 361 362 #define IPCT120_IRQ_COUNT 1 363 364 #define IPCT130_IRQ_COUNT 1 365 366 /*Software interrupt*/ 367 #define SWI_PRESENT 1 368 #define SWI_COUNT 8 369 370 /*BELLBOARD APB registers*/ 371 #define BELLBOARD_PRESENT 1 372 #define BELLBOARD_COUNT 1 373 374 #define BELLBOARD_IRQ_COUNT 4 375 376 /*Factory Information Configuration Registers*/ 377 #define FICR_PRESENT 1 378 #define FICR_COUNT 1 379 380 /*USBHSCORE*/ 381 #define USBHSCORE_PRESENT 1 382 #define USBHSCORE_COUNT 1 383 384 /*I3CCORE*/ 385 #define I3CCORE_PRESENT 1 386 #define I3CCORE_COUNT 2 387 388 /*DMU*/ 389 #define DMU_PRESENT 1 390 #define DMU_COUNT 1 391 392 /*MCAN*/ 393 #define MCAN_PRESENT 1 394 #define MCAN_COUNT 1 395 396 /*System Trace Macrocell data buffer*/ 397 #define STMDATA_PRESENT 1 398 #define STMDATA_COUNT 1 399 400 /*TDDCONF*/ 401 #define TDDCONF_PRESENT 1 402 #define TDDCONF_COUNT 1 403 404 #define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 1 /*!< (unspecified) */ 405 #define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 0 /*!< (unspecified) */ 406 407 /*System Trace Macrocell*/ 408 #define STM_PRESENT 1 409 #define STM_COUNT 1 410 411 /*Trace Port Interface Unit*/ 412 #define TPIU_PRESENT 1 413 #define TPIU_COUNT 1 414 415 /*ATB Replicator module*/ 416 #define ATBREPLICATOR_PRESENT 1 417 #define ATBREPLICATOR_COUNT 4 418 419 /*ATB funnel module*/ 420 #define ATBFUNNEL_PRESENT 1 421 #define ATBFUNNEL_COUNT 4 422 423 /*GPIO Tasks and Events*/ 424 #define GPIOTE_PRESENT 1 425 #define GPIOTE_COUNT 1 426 427 #define GPIOTE130_IRQ_COUNT 2 428 #define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 429 #define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 430 #define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 431 #define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ 432 #define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ 433 #define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ 434 #define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 435 #define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 436 #define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 437 #define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ 438 439 /*Global Real-time counter*/ 440 #define GRTC_PRESENT 1 441 #define GRTC_COUNT 1 442 443 #define GRTC_IRQ_COUNT 3 444 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 445 0..14*/ 446 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 447 0..14*/ 448 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 449 0..14*/ 450 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 451 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 452 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 453 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 454 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 455 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 456 #define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 457 #define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 458 #define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ 459 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ 460 #define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ 461 #define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ 462 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 463 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 464 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 465 #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ 466 #define GRTC_CCADD_WRITE_ONLY 1 /*!< (unspecified) */ 467 #define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ 468 469 /*Trace buffer monitor*/ 470 #define TBM_PRESENT 1 471 #define TBM_COUNT 1 472 473 /*USBHS*/ 474 #define USBHS_PRESENT 1 475 #define USBHS_COUNT 1 476 477 /*External Memory Interface*/ 478 #define EXMIF_PRESENT 1 479 #define EXMIF_COUNT 1 480 481 /*BELLBOARD public registers*/ 482 #define BELLBOARDPUBLIC_PRESENT 1 483 #define BELLBOARDPUBLIC_COUNT 1 484 485 /*VPR peripheral registers*/ 486 #define VPRPUBLIC_PRESENT 1 487 #define VPRPUBLIC_COUNT 1 488 489 #define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 490 #define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 491 #define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 492 #define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ 493 494 /*MUTEX*/ 495 #define MUTEX_PRESENT 1 496 #define MUTEX_COUNT 2 497 498 /*I3C*/ 499 #define I3C_PRESENT 1 500 #define I3C_COUNT 2 501 502 /*VPR peripheral registers*/ 503 #define VPR_PRESENT 1 504 #define VPR_COUNT 2 505 506 #define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 507 #define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 508 #define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ 509 #define VPR121_RAM_SZ 15 /*!< (unspecified) */ 510 #define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ 511 #define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ 512 #define VPR121_RETAINED 0 /*!< (unspecified) */ 513 #define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ 514 #define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 515 #define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 516 #define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ 517 #define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ 518 #define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ 519 #define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ 520 #define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ 521 #define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ 522 #define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ 523 #define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ 524 #define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ 525 #define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ 526 #define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ 527 528 #define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ 529 #define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 530 #define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ 531 #define VPR130_RAM_SZ 15 /*!< (unspecified) */ 532 #define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ 533 #define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ 534 #define VPR130_RETAINED 1 /*!< (unspecified) */ 535 #define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ 536 #define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ 537 #define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ 538 #define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ 539 #define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ 540 #define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ 541 #define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ 542 #define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ 543 #define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ 544 #define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ 545 #define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ 546 #define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ 547 #define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ 548 #define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ 549 550 /*Controller Area Network*/ 551 #define CAN_PRESENT 1 552 #define CAN_COUNT 1 553 554 /*Distributed programmable peripheral interconnect controller*/ 555 #define DPPIC_PRESENT 1 556 #define DPPIC_COUNT 8 557 558 #define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ 559 #define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ 560 #define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ 561 #define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ 562 #define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ 563 #define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ 564 #define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 565 566 #define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ 567 #define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ 568 #define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ 569 #define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ 570 #define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ 571 #define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ 572 #define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 573 574 #define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ 575 #define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ 576 #define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ 577 #define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ 578 #define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ 579 #define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ 580 #define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 581 582 #define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ 583 #define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ 584 #define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ 585 #define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ 586 #define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ 587 #define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ 588 #define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 589 590 #define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ 591 #define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ 592 #define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ 593 #define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ 594 #define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ 595 #define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ 596 #define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 597 598 #define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ 599 #define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ 600 #define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ 601 #define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ 602 #define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ 603 #define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ 604 #define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 605 606 #define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ 607 #define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ 608 #define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ 609 #define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ 610 #define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ 611 #define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ 612 #define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 613 614 #define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ 615 #define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ 616 #define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ 617 #define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ 618 #define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ 619 #define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ 620 #define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 621 622 /*Timer/Counter*/ 623 #define TIMER_PRESENT 1 624 #define TIMER_COUNT 10 625 626 #define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ 627 #define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ 628 #define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ 629 #define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ 630 #define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ 631 #define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 632 #define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 633 #define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ 634 635 #define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ 636 #define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ 637 #define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ 638 #define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ 639 #define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ 640 #define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 641 #define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ 642 #define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ 643 644 #define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ 645 #define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ 646 #define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ 647 #define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ 648 #define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ 649 #define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 650 #define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 651 #define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ 652 653 #define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ 654 #define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ 655 #define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ 656 #define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ 657 #define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ 658 #define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 659 #define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 660 #define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ 661 662 #define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ 663 #define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ 664 #define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ 665 #define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ 666 #define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ 667 #define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 668 #define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 669 #define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ 670 671 #define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ 672 #define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ 673 #define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ 674 #define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ 675 #define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ 676 #define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 677 #define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 678 #define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ 679 680 #define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ 681 #define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ 682 #define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ 683 #define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ 684 #define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ 685 #define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 686 #define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 687 #define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ 688 689 #define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ 690 #define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ 691 #define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ 692 #define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ 693 #define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ 694 #define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 695 #define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 696 #define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ 697 698 #define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ 699 #define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ 700 #define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ 701 #define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ 702 #define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ 703 #define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 704 #define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 705 #define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ 706 707 #define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ 708 #define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ 709 #define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ 710 #define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ 711 #define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ 712 #define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 713 #define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 714 #define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ 715 716 /*Pulse width modulation unit*/ 717 #define PWM_PRESENT 1 718 #define PWM_COUNT 5 719 720 #define PWM120_IDLE_OUT 1 /*!< (unspecified) */ 721 #define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ 722 #define PWM120_FEATURES_V2 0 /*!< (unspecified) */ 723 #define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ 724 #define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 725 726 #define PWM130_IDLE_OUT 1 /*!< (unspecified) */ 727 #define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ 728 #define PWM130_FEATURES_V2 0 /*!< (unspecified) */ 729 #define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ 730 #define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 731 732 #define PWM131_IDLE_OUT 1 /*!< (unspecified) */ 733 #define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ 734 #define PWM131_FEATURES_V2 0 /*!< (unspecified) */ 735 #define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ 736 #define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 737 738 #define PWM132_IDLE_OUT 1 /*!< (unspecified) */ 739 #define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ 740 #define PWM132_FEATURES_V2 0 /*!< (unspecified) */ 741 #define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ 742 #define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 743 744 #define PWM133_IDLE_OUT 1 /*!< (unspecified) */ 745 #define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ 746 #define PWM133_FEATURES_V2 0 /*!< (unspecified) */ 747 #define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ 748 #define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 749 750 /*SPI Slave*/ 751 #define SPIS_PRESENT 1 752 #define SPIS_COUNT 9 753 754 #define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 755 #define SPIS120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 756 #define SPIS120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 757 #define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 758 759 #define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 760 #define SPIS130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 761 #define SPIS130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 762 #define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 763 764 #define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 765 #define SPIS131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 766 #define SPIS131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 767 #define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 768 769 #define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 770 #define SPIS132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 771 #define SPIS132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 772 #define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 773 774 #define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 775 #define SPIS133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 776 #define SPIS133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 777 #define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 778 779 #define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 780 #define SPIS134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 781 #define SPIS134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 782 #define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 783 784 #define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 785 #define SPIS135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 786 #define SPIS135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 787 #define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 788 789 #define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 790 #define SPIS136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 791 #define SPIS136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 792 #define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 793 794 #define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 795 #define SPIS137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 796 #define SPIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 797 #define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 798 799 /*Serial Peripheral Interface Master with EasyDMA*/ 800 #define SPIM_PRESENT 1 801 #define SPIM_COUNT 10 802 803 #define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 804 #define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ 805 #define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 806 #define SPIM120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 807 #define SPIM120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 808 #define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 809 #define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 810 #define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 811 #define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 812 #define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 813 #define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 814 #define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 815 #define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 816 #define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 817 #define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ 818 #define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 819 #define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 820 #define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 821 #define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 822 #define SPIM120_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 823 #define SPIM120_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 824 #define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 825 #define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 826 #define SPIM120_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 827 #define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 828 829 #define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 830 #define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ 831 #define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 832 #define SPIM121_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 833 #define SPIM121_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 834 #define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 835 #define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 836 #define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 837 #define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 838 #define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 839 #define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 840 #define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 841 #define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 842 #define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ 843 #define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ 844 #define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 845 #define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 846 #define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 847 #define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 848 #define SPIM121_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 849 #define SPIM121_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 850 #define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 851 #define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 852 #define SPIM121_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 853 #define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 854 855 #define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 856 #define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ 857 #define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 858 #define SPIM130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 859 #define SPIM130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 860 #define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 861 #define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 862 #define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 863 #define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 864 #define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 865 #define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 866 #define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 867 #define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 868 #define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 869 #define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ 870 #define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 871 #define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 872 #define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 873 #define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 874 #define SPIM130_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 875 #define SPIM130_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 876 #define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 877 #define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 878 #define SPIM130_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 879 #define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 880 881 #define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 882 #define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ 883 #define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 884 #define SPIM131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 885 #define SPIM131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 886 #define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 887 #define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 888 #define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 889 #define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 890 #define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 891 #define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 892 #define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 893 #define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 894 #define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 895 #define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ 896 #define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 897 #define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 898 #define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 899 #define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 900 #define SPIM131_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 901 #define SPIM131_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 902 #define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 903 #define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 904 #define SPIM131_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 905 #define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 906 907 #define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 908 #define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ 909 #define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 910 #define SPIM132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 911 #define SPIM132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 912 #define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 913 #define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 914 #define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 915 #define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 916 #define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 917 #define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 918 #define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 919 #define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 920 #define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 921 #define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ 922 #define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 923 #define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 924 #define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 925 #define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 926 #define SPIM132_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 927 #define SPIM132_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 928 #define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 929 #define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 930 #define SPIM132_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 931 #define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 932 933 #define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 934 #define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ 935 #define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 936 #define SPIM133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 937 #define SPIM133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 938 #define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 939 #define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 940 #define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 941 #define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 942 #define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 943 #define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 944 #define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 945 #define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 946 #define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 947 #define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ 948 #define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 949 #define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 950 #define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 951 #define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 952 #define SPIM133_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 953 #define SPIM133_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 954 #define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 955 #define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 956 #define SPIM133_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 957 #define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 958 959 #define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 960 #define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ 961 #define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 962 #define SPIM134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 963 #define SPIM134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 964 #define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 965 #define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 966 #define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 967 #define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 968 #define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 969 #define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 970 #define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 971 #define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 972 #define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 973 #define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ 974 #define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 975 #define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 976 #define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 977 #define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 978 #define SPIM134_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 979 #define SPIM134_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 980 #define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 981 #define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 982 #define SPIM134_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 983 #define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 984 985 #define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 986 #define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ 987 #define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 988 #define SPIM135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 989 #define SPIM135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 990 #define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 991 #define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 992 #define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 993 #define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 994 #define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 995 #define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 996 #define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 997 #define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 998 #define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 999 #define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1000 #define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1001 #define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1002 #define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1003 #define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1004 #define SPIM135_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1005 #define SPIM135_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1006 #define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1007 #define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1008 #define SPIM135_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1009 #define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1010 1011 #define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1012 #define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ 1013 #define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1014 #define SPIM136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1015 #define SPIM136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1016 #define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1017 #define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1018 #define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1019 #define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1020 #define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1021 #define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1022 #define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1023 #define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1024 #define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1025 #define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1026 #define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1027 #define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1028 #define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1029 #define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1030 #define SPIM136_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1031 #define SPIM136_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1032 #define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1033 #define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1034 #define SPIM136_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1035 #define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1036 1037 #define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1038 #define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ 1039 #define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1040 #define SPIM137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1041 #define SPIM137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1042 #define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 1043 #define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 1044 #define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 1045 #define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 1046 #define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 1047 #define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 1048 #define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 1049 #define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 1050 #define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 1051 #define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1052 #define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 1053 #define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 1054 #define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 1055 #define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1056 #define SPIM137_RXDELAY_VALUE_RANGE_MAX 40 /*!< (unspecified) */ 1057 #define SPIM137_RXDELAY_VALUE_RANGE_SIZE 41 /*!< (unspecified) */ 1058 #define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 1059 #define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 1060 #define SPIM137_RXDELAY_FIELD_WIDTH_MAX 5 /*!< (unspecified) */ 1061 #define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 6 /*!< (unspecified) */ 1062 1063 /*UART with EasyDMA*/ 1064 #define UARTE_PRESENT 1 1065 #define UARTE_COUNT 9 1066 1067 #define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1068 #define UARTE120_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1069 #define UARTE120_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1070 #define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1071 #define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1072 #define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ 1073 #define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ 1074 #define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1075 #define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1076 1077 #define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1078 #define UARTE130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1079 #define UARTE130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1080 #define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1081 #define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1082 #define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1083 #define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ 1084 #define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1085 #define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1086 1087 #define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1088 #define UARTE131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1089 #define UARTE131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1090 #define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1091 #define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1092 #define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1093 #define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ 1094 #define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1095 #define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1096 1097 #define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1098 #define UARTE132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1099 #define UARTE132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1100 #define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1101 #define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1102 #define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1103 #define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ 1104 #define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1105 #define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1106 1107 #define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1108 #define UARTE133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1109 #define UARTE133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1110 #define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1111 #define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1112 #define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1113 #define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ 1114 #define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1115 #define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1116 1117 #define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1118 #define UARTE134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1119 #define UARTE134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1120 #define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1121 #define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1122 #define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1123 #define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ 1124 #define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1125 #define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1126 1127 #define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1128 #define UARTE135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1129 #define UARTE135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1130 #define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1131 #define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1132 #define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1133 #define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ 1134 #define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1135 #define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1136 1137 #define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1138 #define UARTE136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1139 #define UARTE136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1140 #define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1141 #define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1142 #define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1143 #define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ 1144 #define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1145 #define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1146 1147 #define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1148 #define UARTE137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1149 #define UARTE137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1150 #define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 1151 #define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 1152 #define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 1153 #define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ 1154 #define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 1155 #define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1156 1157 /*Real-time counter*/ 1158 #define RTC_PRESENT 1 1159 #define RTC_COUNT 2 1160 1161 #define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ 1162 #define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ 1163 #define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ 1164 #define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 1165 #define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 1166 #define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 1167 #define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ 1168 1169 #define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ 1170 #define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ 1171 #define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ 1172 #define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ 1173 #define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ 1174 #define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ 1175 #define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ 1176 1177 /*Event generator unit*/ 1178 #define EGU_PRESENT 1 1179 #define EGU_COUNT 1 1180 1181 #define EGU130_PEND 0 /*!< (unspecified) */ 1182 #define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ 1183 #define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ 1184 #define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ 1185 1186 /*GPIO Port*/ 1187 #define GPIO_PRESENT 1 1188 #define GPIO_COUNT 6 1189 1190 #define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1191 #define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1192 #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1193 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 1194 #define P0_PIN_NUM_MAX 11 /*!< (unspecified) */ 1195 #define P0_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1196 #define P0_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1197 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 1198 #define P0_RETAIN 1 /*!< (unspecified) */ 1199 #define P0_PWRCTRL 0 /*!< (unspecified) */ 1200 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1201 #define P0_BIASCTRL 0 /*!< (unspecified) */ 1202 1203 #define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1204 #define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1205 #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1206 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 1207 #define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ 1208 #define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1209 #define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1210 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 1211 #define P1_RETAIN 1 /*!< (unspecified) */ 1212 #define P1_PWRCTRL 0 /*!< (unspecified) */ 1213 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1214 #define P1_BIASCTRL 0 /*!< (unspecified) */ 1215 1216 #define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1217 #define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1218 #define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1219 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 1220 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 1221 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 1222 #define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ 1223 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 1224 #define P2_RETAIN 1 /*!< (unspecified) */ 1225 #define P2_PWRCTRL 0 /*!< (unspecified) */ 1226 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1227 #define P2_BIASCTRL 0 /*!< (unspecified) */ 1228 1229 #define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1230 #define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1231 #define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1232 #define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ 1233 #define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ 1234 #define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ 1235 #define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ 1236 #define P6_DRIVECTRL 1 /*!< (unspecified) */ 1237 #define P6_RETAIN 1 /*!< (unspecified) */ 1238 #define P6_PWRCTRL 0 /*!< (unspecified) */ 1239 #define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1240 #define P6_BIASCTRL 0 /*!< (unspecified) */ 1241 1242 #define P7_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1243 #define P7_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1244 #define P7_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1245 #define P7_PIN_NUM_MIN 0 /*!< (unspecified) */ 1246 #define P7_PIN_NUM_MAX 7 /*!< (unspecified) */ 1247 #define P7_PIN_NUM_SIZE 8 /*!< (unspecified) */ 1248 #define P7_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ 1249 #define P7_DRIVECTRL 1 /*!< (unspecified) */ 1250 #define P7_RETAIN 1 /*!< (unspecified) */ 1251 #define P7_PWRCTRL 0 /*!< (unspecified) */ 1252 #define P7_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1253 #define P7_BIASCTRL 0 /*!< (unspecified) */ 1254 1255 #define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ 1256 #define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ 1257 #define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ 1258 #define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ 1259 #define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ 1260 #define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ 1261 #define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ 1262 #define P9_DRIVECTRL 0 /*!< (unspecified) */ 1263 #define P9_RETAIN 1 /*!< (unspecified) */ 1264 #define P9_PWRCTRL 1 /*!< (unspecified) */ 1265 #define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ 1266 #define P9_BIASCTRL 0 /*!< (unspecified) */ 1267 1268 /*Analog to Digital Converter*/ 1269 #define SAADC_PRESENT 1 1270 #define SAADC_COUNT 1 1271 1272 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 1273 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 1274 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 4 /*!< (unspecified) */ 1275 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 1276 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 1277 #define SAADC_TACQ_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1278 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 1279 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 1280 #define SAADC_TCONV_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 1281 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 1282 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 1283 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1284 1285 /*Comparator*/ 1286 #define COMP_PRESENT 1 1287 #define COMP_COUNT 1 1288 1289 /*Low-power comparator*/ 1290 #define LPCOMP_PRESENT 1 1291 #define LPCOMP_COUNT 1 1292 1293 /*Temperature Sensor*/ 1294 #define TEMP_PRESENT 1 1295 #define TEMP_COUNT 1 1296 1297 /*NFC-A compatible radio NFC-A compatible radio*/ 1298 #define NFCT_PRESENT 1 1299 #define NFCT_COUNT 1 1300 1301 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 1302 1303 /*Time division multiplexed audio interface*/ 1304 #define TDM_PRESENT 1 1305 #define TDM_COUNT 2 1306 1307 #define TDM130_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1308 #define TDM130_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1309 #define TDM130_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1310 #define TDM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1311 1312 #define TDM131_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1313 #define TDM131_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1314 #define TDM131_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1315 #define TDM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1316 1317 /*Pulse Density Modulation (Digital Microphone) Interface*/ 1318 #define PDM_PRESENT 1 1319 #define PDM_COUNT 1 1320 1321 #define PDM_SAMPLE16 0 /*!< (unspecified) */ 1322 #define PDM_SAMPLE48 1 /*!< (unspecified) */ 1323 #define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1324 1325 /*Quadrature Decoder*/ 1326 #define QDEC_PRESENT 1 1327 #define QDEC_COUNT 2 1328 1329 /*SIM card interface*/ 1330 #define SIMIF_PRESENT 1 1331 #define SIMIF_COUNT 1 1332 1333 #define SIMIF130_SWOVERRIDE_REGS 0 /*!< (unspecified) */ 1334 1335 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 1336 #define TWIM_PRESENT 1 1337 #define TWIM_COUNT 8 1338 1339 #define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1340 #define TWIM130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1341 #define TWIM130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1342 #define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1343 1344 #define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1345 #define TWIM131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1346 #define TWIM131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1347 #define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1348 1349 #define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1350 #define TWIM132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1351 #define TWIM132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1352 #define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1353 1354 #define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1355 #define TWIM133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1356 #define TWIM133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1357 #define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1358 1359 #define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1360 #define TWIM134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1361 #define TWIM134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1362 #define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1363 1364 #define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1365 #define TWIM135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1366 #define TWIM135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1367 #define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1368 1369 #define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1370 #define TWIM136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1371 #define TWIM136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1372 #define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1373 1374 #define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1375 #define TWIM137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1376 #define TWIM137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1377 #define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1378 1379 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 1380 #define TWIS_PRESENT 1 1381 #define TWIS_COUNT 8 1382 1383 #define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1384 #define TWIS130_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1385 #define TWIS130_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1386 #define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1387 1388 #define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1389 #define TWIS131_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1390 #define TWIS131_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1391 #define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1392 1393 #define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1394 #define TWIS132_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1395 #define TWIS132_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1396 #define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1397 1398 #define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1399 #define TWIS133_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1400 #define TWIS133_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1401 #define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1402 1403 #define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1404 #define TWIS134_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1405 #define TWIS134_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1406 #define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1407 1408 #define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1409 #define TWIS135_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1410 #define TWIS135_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1411 #define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1412 1413 #define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1414 #define TWIS136_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1415 #define TWIS136_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1416 #define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1417 1418 #define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1419 #define TWIS137_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1420 #define TWIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1421 #define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1422 1423 /* ============================================= SPU010 Split Security Features ============================================== */ 1424 /** 1425 * @brief Indexes in SPU010.FEATURES controlling access permissions of features with split security 1426 */ 1427 typedef enum { 1428 NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_0 = 0, /*!< Index of access permissions for channel 0 of IPCT */ 1429 NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_1 = 1, /*!< Index of access permissions for channel 1 of IPCT */ 1430 NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_2 = 2, /*!< Index of access permissions for channel 2 of IPCT */ 1431 NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_3 = 3, /*!< Index of access permissions for channel 3 of IPCT */ 1432 NRF_APPLICATION_SPU010_FEATURES_IPCT_INTERRUPT_0 = 24, /*!< Index of access permissions for interrupt 0 of IPCT */ 1433 NRF_APPLICATION_SPU010_FEATURES_IPCT_INTERRUPT_1 = 25, /*!< Index of access permissions for interrupt 1 of IPCT */ 1434 } NRF_APPLICATION_SPU010_FEATURES_ENUM_t; 1435 1436 1437 #ifdef __cplusplus 1438 } 1439 #endif 1440 #endif /* NRF54H20_APPLICATION_PERIPHERALS_H */ 1441 1442
