1 /*
2 
3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF5340_NETWORK_BITS_H
36 #define __NRF5340_NETWORK_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_SUBSCRIBE_START */
60 /* Description: Subscribe configuration for task START */
61 
62 /* Bit 31 :   */
63 #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
64 #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
65 #define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
66 #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
67 
68 /* Bits 7..0 : DPPI channel that task START will subscribe to */
69 #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
70 #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
71 
72 /* Register: AAR_SUBSCRIBE_STOP */
73 /* Description: Subscribe configuration for task STOP */
74 
75 /* Bit 31 :   */
76 #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
77 #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
78 #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
79 #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
80 
81 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
82 #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
83 #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
84 
85 /* Register: AAR_EVENTS_END */
86 /* Description: Address resolution procedure complete */
87 
88 /* Bit 0 : Address resolution procedure complete */
89 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
90 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
91 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
92 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
93 
94 /* Register: AAR_EVENTS_RESOLVED */
95 /* Description: Address resolved */
96 
97 /* Bit 0 : Address resolved */
98 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
99 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
100 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
101 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
102 
103 /* Register: AAR_EVENTS_NOTRESOLVED */
104 /* Description: Address not resolved */
105 
106 /* Bit 0 : Address not resolved */
107 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
108 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
109 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
110 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
111 
112 /* Register: AAR_PUBLISH_END */
113 /* Description: Publish configuration for event END */
114 
115 /* Bit 31 :   */
116 #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
117 #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
118 #define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
119 #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
120 
121 /* Bits 7..0 : DPPI channel that event END will publish to. */
122 #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
123 #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
124 
125 /* Register: AAR_PUBLISH_RESOLVED */
126 /* Description: Publish configuration for event RESOLVED */
127 
128 /* Bit 31 :   */
129 #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
130 #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */
131 #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
132 #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
133 
134 /* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */
135 #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
136 #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
137 
138 /* Register: AAR_PUBLISH_NOTRESOLVED */
139 /* Description: Publish configuration for event NOTRESOLVED */
140 
141 /* Bit 31 :   */
142 #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
143 #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */
144 #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
145 #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
146 
147 /* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */
148 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
149 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
150 
151 /* Register: AAR_INTENSET */
152 /* Description: Enable interrupt */
153 
154 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
155 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
156 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
157 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
158 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
159 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
160 
161 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
162 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
163 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
164 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
165 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
166 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
167 
168 /* Bit 0 : Write '1' to enable interrupt for event END */
169 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
170 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
171 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
172 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
173 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
174 
175 /* Register: AAR_INTENCLR */
176 /* Description: Disable interrupt */
177 
178 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
179 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
180 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
181 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
182 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
183 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
184 
185 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
186 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
187 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
188 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
189 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
190 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
191 
192 /* Bit 0 : Write '1' to disable interrupt for event END */
193 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
194 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
195 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
196 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
197 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
198 
199 /* Register: AAR_STATUS */
200 /* Description: Resolution status */
201 
202 /* Bits 3..0 : The IRK that was used last time an address was resolved */
203 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
204 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
205 
206 /* Register: AAR_ENABLE */
207 /* Description: Enable AAR */
208 
209 /* Bits 1..0 : Enable or disable AAR */
210 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
211 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
212 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
213 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
214 
215 /* Register: AAR_NIRK */
216 /* Description: Number of IRKs */
217 
218 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
219 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
220 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
221 
222 /* Register: AAR_IRKPTR */
223 /* Description: Pointer to IRK data structure */
224 
225 /* Bits 31..0 : Pointer to the IRK data structure */
226 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
227 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
228 
229 /* Register: AAR_ADDRPTR */
230 /* Description: Pointer to the resolvable address */
231 
232 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
233 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
234 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
235 
236 /* Register: AAR_SCRATCHPTR */
237 /* Description: Pointer to data area used for temporary storage */
238 
239 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
240 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
241 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
242 
243 
244 /* Peripheral: ACL */
245 /* Description: Access control lists */
246 
247 /* Register: ACL_ACL_ADDR */
248 /* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */
249 
250 /* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */
251 #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
252 #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
253 
254 /* Register: ACL_ACL_SIZE */
255 /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
256 
257 /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
258 #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
259 #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
260 
261 /* Register: ACL_ACL_PERM */
262 /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
263 
264 /* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
265 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
266 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
267 #define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
268 #define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
269 
270 /* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
271 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
272 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
273 #define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
274 #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
275 
276 
277 /* Peripheral: MUTEX */
278 /* Description: MUTEX 0 */
279 
280 /* Register: MUTEX_MUTEX */
281 /* Description: Description collection: Mutex register */
282 
283 /* Bit 0 : Mutex register n */
284 #define MUTEX_MUTEX_MUTEX_Pos (0UL) /*!< Position of MUTEX field. */
285 #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos) /*!< Bit mask of MUTEX field. */
286 #define MUTEX_MUTEX_MUTEX_Unlocked (0UL) /*!< Mutex n is in unlocked state */
287 #define MUTEX_MUTEX_MUTEX_Locked (1UL) /*!< Mutex n is in locked state */
288 
289 
290 /* Peripheral: CCM */
291 /* Description: AES CCM mode encryption */
292 
293 /* Register: CCM_TASKS_KSGEN */
294 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
295 
296 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
297 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
298 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
299 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
300 
301 /* Register: CCM_TASKS_CRYPT */
302 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
303 
304 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
305 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
306 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
307 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
308 
309 /* Register: CCM_TASKS_STOP */
310 /* Description: Stop encryption/decryption */
311 
312 /* Bit 0 : Stop encryption/decryption */
313 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
314 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
315 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
316 
317 /* Register: CCM_TASKS_RATEOVERRIDE */
318 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
319 
320 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
321 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
322 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
323 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
324 
325 /* Register: CCM_SUBSCRIBE_KSGEN */
326 /* Description: Subscribe configuration for task KSGEN */
327 
328 /* Bit 31 :   */
329 #define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL) /*!< Position of EN field. */
330 #define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos) /*!< Bit mask of EN field. */
331 #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */
332 #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */
333 
334 /* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */
335 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
336 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
337 
338 /* Register: CCM_SUBSCRIBE_CRYPT */
339 /* Description: Subscribe configuration for task CRYPT */
340 
341 /* Bit 31 :   */
342 #define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL) /*!< Position of EN field. */
343 #define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos) /*!< Bit mask of EN field. */
344 #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */
345 #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */
346 
347 /* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */
348 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
349 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
350 
351 /* Register: CCM_SUBSCRIBE_STOP */
352 /* Description: Subscribe configuration for task STOP */
353 
354 /* Bit 31 :   */
355 #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
356 #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
357 #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
358 #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
359 
360 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
361 #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
362 #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
363 
364 /* Register: CCM_SUBSCRIBE_RATEOVERRIDE */
365 /* Description: Subscribe configuration for task RATEOVERRIDE */
366 
367 /* Bit 31 :   */
368 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */
369 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */
370 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */
371 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */
372 
373 /* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */
374 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
375 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
376 
377 /* Register: CCM_EVENTS_ENDKSGEN */
378 /* Description: Keystream generation complete */
379 
380 /* Bit 0 : Keystream generation complete */
381 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
382 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
383 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
384 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
385 
386 /* Register: CCM_EVENTS_ENDCRYPT */
387 /* Description: Encrypt/decrypt complete */
388 
389 /* Bit 0 : Encrypt/decrypt complete */
390 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
391 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
392 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
393 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
394 
395 /* Register: CCM_EVENTS_ERROR */
396 /* Description: Deprecated register - CCM error event */
397 
398 /* Bit 0 : Deprecated field -  CCM error event */
399 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
400 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
401 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
402 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
403 
404 /* Register: CCM_PUBLISH_ENDKSGEN */
405 /* Description: Publish configuration for event ENDKSGEN */
406 
407 /* Bit 31 :   */
408 #define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL) /*!< Position of EN field. */
409 #define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos) /*!< Bit mask of EN field. */
410 #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */
411 #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */
412 
413 /* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */
414 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
415 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
416 
417 /* Register: CCM_PUBLISH_ENDCRYPT */
418 /* Description: Publish configuration for event ENDCRYPT */
419 
420 /* Bit 31 :   */
421 #define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL) /*!< Position of EN field. */
422 #define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos) /*!< Bit mask of EN field. */
423 #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */
424 #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */
425 
426 /* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */
427 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
428 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
429 
430 /* Register: CCM_PUBLISH_ERROR */
431 /* Description: Deprecated register - Publish configuration for event ERROR */
432 
433 /* Bit 31 :   */
434 #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
435 #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
436 #define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
437 #define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
438 
439 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
440 #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
441 #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
442 
443 /* Register: CCM_SHORTS */
444 /* Description: Shortcuts between local events and tasks */
445 
446 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
447 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
448 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
449 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
450 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
451 
452 /* Register: CCM_INTENSET */
453 /* Description: Enable interrupt */
454 
455 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
456 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
457 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
458 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
459 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
460 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
461 
462 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
463 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
464 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
465 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
466 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
467 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
468 
469 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
470 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
471 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
472 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
473 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
474 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
475 
476 /* Register: CCM_INTENCLR */
477 /* Description: Disable interrupt */
478 
479 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
480 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
481 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
482 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
483 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
484 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
485 
486 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
487 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
488 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
489 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
490 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
491 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
492 
493 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
494 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
495 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
496 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
497 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
498 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
499 
500 /* Register: CCM_MICSTATUS */
501 /* Description: MIC check result */
502 
503 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
504 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
505 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
506 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
507 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
508 
509 /* Register: CCM_ENABLE */
510 /* Description: Enable */
511 
512 /* Bits 1..0 : Enable or disable CCM */
513 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
514 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
515 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
516 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
517 
518 /* Register: CCM_MODE */
519 /* Description: Operation mode */
520 
521 /* Bit 24 : Packet length configuration */
522 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
523 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
524 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
525 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
526 
527 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
528 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
529 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
530 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
531 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
532 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
533 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
534 
535 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
536 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
537 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
538 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
539 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
540 
541 /* Register: CCM_CNFPTR */
542 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
543 
544 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
545 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
546 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
547 
548 /* Register: CCM_INPTR */
549 /* Description: Input pointer */
550 
551 /* Bits 31..0 : Input pointer */
552 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
553 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
554 
555 /* Register: CCM_OUTPTR */
556 /* Description: Output pointer */
557 
558 /* Bits 31..0 : Output pointer */
559 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
560 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
561 
562 /* Register: CCM_SCRATCHPTR */
563 /* Description: Pointer to data area used for temporary storage */
564 
565 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
566         MIC generation and encryption/decryption. */
567 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
568 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
569 
570 /* Register: CCM_MAXPACKETSIZE */
571 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
572 
573 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
574 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
575 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
576 
577 /* Register: CCM_RATEOVERRIDE */
578 /* Description: Data rate override setting. */
579 
580 /* Bits 1..0 : Data rate override setting */
581 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
582 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
583 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
584 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
585 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
586 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
587 
588 /* Register: CCM_HEADERMASK */
589 /* Description: Header (S0) mask. */
590 
591 /* Bits 7..0 : Header (S0) mask */
592 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
593 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
594 
595 
596 /* Peripheral: CLOCK */
597 /* Description: Clock management */
598 
599 /* Register: CLOCK_TASKS_HFCLKSTART */
600 /* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
601 
602 /* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
603 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
604 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
605 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
606 
607 /* Register: CLOCK_TASKS_HFCLKSTOP */
608 /* Description: Stop HFCLK128M/HFCLK64M source */
609 
610 /* Bit 0 : Stop HFCLK128M/HFCLK64M source */
611 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
612 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
613 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
614 
615 /* Register: CLOCK_TASKS_LFCLKSTART */
616 /* Description: Start LFCLK source as selected in LFCLKSRC */
617 
618 /* Bit 0 : Start LFCLK source as selected in LFCLKSRC */
619 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
620 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
621 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
622 
623 /* Register: CLOCK_TASKS_LFCLKSTOP */
624 /* Description: Stop LFCLK source */
625 
626 /* Bit 0 : Stop LFCLK source */
627 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
628 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
629 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
630 
631 /* Register: CLOCK_TASKS_CAL */
632 /* Description: Start calibration of LFRC oscillator */
633 
634 /* Bit 0 : Start calibration of LFRC oscillator */
635 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
636 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
637 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
638 
639 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
640 /* Description: Subscribe configuration for task HFCLKSTART */
641 
642 /* Bit 31 :   */
643 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
644 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
645 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
646 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
647 
648 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
649 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
650 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
651 
652 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
653 /* Description: Subscribe configuration for task HFCLKSTOP */
654 
655 /* Bit 31 :   */
656 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
657 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
658 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
659 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
660 
661 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
662 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
663 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
664 
665 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
666 /* Description: Subscribe configuration for task LFCLKSTART */
667 
668 /* Bit 31 :   */
669 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
670 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
671 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
672 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
673 
674 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
675 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
676 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
677 
678 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
679 /* Description: Subscribe configuration for task LFCLKSTOP */
680 
681 /* Bit 31 :   */
682 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
683 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
684 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
685 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
686 
687 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
688 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
689 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
690 
691 /* Register: CLOCK_SUBSCRIBE_CAL */
692 /* Description: Subscribe configuration for task CAL */
693 
694 /* Bit 31 :   */
695 #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */
696 #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */
697 #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */
698 #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */
699 
700 /* Bits 7..0 : DPPI channel that task CAL will subscribe to */
701 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
702 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
703 
704 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
705 /* Description: HFCLK128M/HFCLK64M source started */
706 
707 /* Bit 0 : HFCLK128M/HFCLK64M source started */
708 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
709 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
710 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
711 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
712 
713 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
714 /* Description: LFCLK source started */
715 
716 /* Bit 0 : LFCLK source started */
717 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
718 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
719 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
720 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
721 
722 /* Register: CLOCK_EVENTS_DONE */
723 /* Description: Calibration of LFRC oscillator complete event */
724 
725 /* Bit 0 : Calibration of LFRC oscillator complete event */
726 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
727 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
728 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
729 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
730 
731 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
732 /* Description: Publish configuration for event HFCLKSTARTED */
733 
734 /* Bit 31 :   */
735 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
736 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
737 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
738 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
739 
740 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */
741 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
742 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
743 
744 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
745 /* Description: Publish configuration for event LFCLKSTARTED */
746 
747 /* Bit 31 :   */
748 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
749 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
750 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
751 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
752 
753 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */
754 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
755 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
756 
757 /* Register: CLOCK_PUBLISH_DONE */
758 /* Description: Publish configuration for event DONE */
759 
760 /* Bit 31 :   */
761 #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
762 #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
763 #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
764 #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
765 
766 /* Bits 7..0 : DPPI channel that event DONE will publish to. */
767 #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
768 #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
769 
770 /* Register: CLOCK_INTEN */
771 /* Description: Enable or disable interrupt */
772 
773 /* Bit 7 : Enable or disable interrupt for event DONE */
774 #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */
775 #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
776 #define CLOCK_INTEN_DONE_Disabled (0UL) /*!< Disable */
777 #define CLOCK_INTEN_DONE_Enabled (1UL) /*!< Enable */
778 
779 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
780 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
781 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
782 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
783 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
784 
785 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
786 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
787 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
788 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
789 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
790 
791 /* Register: CLOCK_INTENSET */
792 /* Description: Enable interrupt */
793 
794 /* Bit 7 : Write '1' to enable interrupt for event DONE */
795 #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */
796 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
797 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
798 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
799 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
800 
801 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
802 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
803 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
804 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
805 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
806 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
807 
808 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
809 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
810 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
811 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
812 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
813 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
814 
815 /* Register: CLOCK_INTENCLR */
816 /* Description: Disable interrupt */
817 
818 /* Bit 7 : Write '1' to disable interrupt for event DONE */
819 #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */
820 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
821 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
822 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
823 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
824 
825 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
826 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
827 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
828 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
829 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
830 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
831 
832 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
833 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
834 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
835 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
836 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
837 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
838 
839 /* Register: CLOCK_INTPEND */
840 /* Description: Pending interrupts */
841 
842 /* Bit 7 : Read pending status of interrupt for event DONE */
843 #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */
844 #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */
845 #define CLOCK_INTPEND_DONE_NotPending (0UL) /*!< Read: Not pending */
846 #define CLOCK_INTPEND_DONE_Pending (1UL) /*!< Read: Pending */
847 
848 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
849 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
850 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
851 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
852 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
853 
854 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
855 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
856 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
857 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
858 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
859 
860 /* Register: CLOCK_HFCLKRUN */
861 /* Description: Status indicating that HFCLKSTART task has been triggered */
862 
863 /* Bit 0 : HFCLKSTART task triggered or not */
864 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
865 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
866 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
867 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
868 
869 /* Register: CLOCK_HFCLKSTAT */
870 /* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
871 
872 /* Bit 16 : HFCLK state */
873 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
874 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
875 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
876 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
877 
878 /* Bit 4 : ALWAYSRUN activated */
879 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
880 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
881 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
882 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
883 
884 /* Bit 0 : Active clock source */
885 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
886 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
887 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */
888 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */
889 
890 /* Register: CLOCK_LFCLKRUN */
891 /* Description: Status indicating that LFCLKSTART task has been triggered */
892 
893 /* Bit 0 : LFCLKSTART task triggered or not */
894 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
895 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
896 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
897 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
898 
899 /* Register: CLOCK_LFCLKSTAT */
900 /* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
901 
902 /* Bit 16 : LFCLK state */
903 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
904 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
905 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
906 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
907 
908 /* Bit 4 : ALWAYSRUN activated */
909 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
910 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
911 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
912 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
913 
914 /* Bits 1..0 : Active clock source */
915 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
916 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
917 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
918 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
919 #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
920 
921 /* Register: CLOCK_LFCLKSRCCOPY */
922 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
923 
924 /* Bits 1..0 : Clock source */
925 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
926 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
927 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
928 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
929 #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
930 
931 /* Register: CLOCK_HFCLKSRC */
932 /* Description: Clock source for HFCLK128M/HFCLK64M */
933 
934 /* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */
935 #define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
936 #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
937 #define CLOCK_HFCLKSRC_SRC_HFINT (0UL) /*!< HFCLKSTART task starts HFINT oscillator */
938 #define CLOCK_HFCLKSRC_SRC_HFXO (1UL) /*!< HFCLKSTART task starts HFXO oscillator */
939 
940 /* Register: CLOCK_LFCLKSRC */
941 /* Description: Clock source for LFCLK */
942 
943 /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */
944 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
945 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
946 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
947 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
948 #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
949 
950 /* Register: CLOCK_HFCLKCTRL */
951 /* Description: HFCLK128M frequency configuration */
952 
953 /* Bits 1..0 : High frequency clock HCLK */
954 #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */
955 #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */
956 #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */
957 #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */
958 
959 /* Register: CLOCK_HFCLKALWAYSRUN */
960 /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */
961 
962 /* Bit 0 : Ensure clock is always running */
963 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
964 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
965 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
966 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
967 
968 /* Register: CLOCK_LFCLKALWAYSRUN */
969 /* Description: Automatic or manual control of LFCLK */
970 
971 /* Bit 0 : Ensure clock is always running */
972 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
973 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
974 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
975 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
976 
977 
978 /* Peripheral: CTI */
979 /* Description: Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. */
980 
981 /* Register: CTI_CTICONTROL */
982 /* Description: CTI Control register */
983 
984 /* Bit 0 : Enables or disables the CTI. */
985 #define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */
986 #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */
987 #define CTI_CTICONTROL_GLBEN_Disabled (0UL) /*!< All cross-triggering mapping logic functionality is disabled. */
988 #define CTI_CTICONTROL_GLBEN_Enabled (1UL) /*!< Cross-triggering mapping logic functionality is enabled. */
989 
990 /* Register: CTI_CTIINTACK */
991 /* Description: CTI Interrupt Acknowledge register */
992 
993 /* Bit 7 : N/A */
994 #define CTI_CTIINTACK_UNUSED5_Pos (7UL) /*!< Position of UNUSED5 field. */
995 #define CTI_CTIINTACK_UNUSED5_Msk (0x1UL << CTI_CTIINTACK_UNUSED5_Pos) /*!< Bit mask of UNUSED5 field. */
996 #define CTI_CTIINTACK_UNUSED5_Acknowledge (1UL) /*!< Clears the ctitrigout. */
997 
998 /* Bit 6 : N/A */
999 #define CTI_CTIINTACK_UNUSED4_Pos (6UL) /*!< Position of UNUSED4 field. */
1000 #define CTI_CTIINTACK_UNUSED4_Msk (0x1UL << CTI_CTIINTACK_UNUSED4_Pos) /*!< Bit mask of UNUSED4 field. */
1001 #define CTI_CTIINTACK_UNUSED4_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1002 
1003 /* Bit 5 : N/A */
1004 #define CTI_CTIINTACK_UNUSED3_Pos (5UL) /*!< Position of UNUSED3 field. */
1005 #define CTI_CTIINTACK_UNUSED3_Msk (0x1UL << CTI_CTIINTACK_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */
1006 #define CTI_CTIINTACK_UNUSED3_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1007 
1008 /* Bit 4 : N/A */
1009 #define CTI_CTIINTACK_UNUSED2_Pos (4UL) /*!< Position of UNUSED2 field. */
1010 #define CTI_CTIINTACK_UNUSED2_Msk (0x1UL << CTI_CTIINTACK_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */
1011 #define CTI_CTIINTACK_UNUSED2_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1012 
1013 /* Bit 3 : N/A */
1014 #define CTI_CTIINTACK_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */
1015 #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1016 #define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1017 
1018 /* Bit 2 : N/A */
1019 #define CTI_CTIINTACK_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */
1020 #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1021 #define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1022 
1023 /* Bit 1 : Processor Restart */
1024 #define CTI_CTIINTACK_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */
1025 #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */
1026 #define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1027 
1028 /* Bit 0 : Processor debug request */
1029 #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */
1030 #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */
1031 #define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1032 
1033 /* Register: CTI_CTIAPPSET */
1034 /* Description: CTI Application Trigger Set register */
1035 
1036 /* Bit 3 : Application trigger event for channel 3. */
1037 #define CTI_CTIAPPSET_APPSET_3_Pos (3UL) /*!< Position of APPSET_3 field. */
1038 #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos) /*!< Bit mask of APPSET_3 field. */
1039 #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL) /*!< Application trigger 3 is inactive. */
1040 #define CTI_CTIAPPSET_APPSET_3_Active (1UL) /*!< Application trigger 3 is active. */
1041 #define CTI_CTIAPPSET_APPSET_3_Activate (1UL) /*!< Generate channel event for channel 3. */
1042 
1043 /* Bit 2 : Application trigger event for channel 2. */
1044 #define CTI_CTIAPPSET_APPSET_2_Pos (2UL) /*!< Position of APPSET_2 field. */
1045 #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos) /*!< Bit mask of APPSET_2 field. */
1046 #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL) /*!< Application trigger 2 is inactive. */
1047 #define CTI_CTIAPPSET_APPSET_2_Active (1UL) /*!< Application trigger 2 is active. */
1048 #define CTI_CTIAPPSET_APPSET_2_Activate (1UL) /*!< Generate channel event for channel 2. */
1049 
1050 /* Bit 1 : Application trigger event for channel 1. */
1051 #define CTI_CTIAPPSET_APPSET_1_Pos (1UL) /*!< Position of APPSET_1 field. */
1052 #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos) /*!< Bit mask of APPSET_1 field. */
1053 #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL) /*!< Application trigger 1 is inactive. */
1054 #define CTI_CTIAPPSET_APPSET_1_Active (1UL) /*!< Application trigger 1 is active. */
1055 #define CTI_CTIAPPSET_APPSET_1_Activate (1UL) /*!< Generate channel event for channel 1. */
1056 
1057 /* Bit 0 : Application trigger event for channel 0. */
1058 #define CTI_CTIAPPSET_APPSET_0_Pos (0UL) /*!< Position of APPSET_0 field. */
1059 #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos) /*!< Bit mask of APPSET_0 field. */
1060 #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL) /*!< Application trigger 0 is inactive. */
1061 #define CTI_CTIAPPSET_APPSET_0_Active (1UL) /*!< Application trigger 0 is active. */
1062 #define CTI_CTIAPPSET_APPSET_0_Activate (1UL) /*!< Generate channel event for channel 0. */
1063 
1064 /* Register: CTI_CTIAPPCLEAR */
1065 /* Description: CTI Application Trigger Clear register */
1066 
1067 /* Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1068 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL) /*!< Position of APPCLEAR_3 field. */
1069 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos) /*!< Bit mask of APPCLEAR_3 field. */
1070 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3. */
1071 
1072 /* Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1073 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL) /*!< Position of APPCLEAR_2 field. */
1074 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos) /*!< Bit mask of APPCLEAR_2 field. */
1075 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2. */
1076 
1077 /* Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1078 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL) /*!< Position of APPCLEAR_1 field. */
1079 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos) /*!< Bit mask of APPCLEAR_1 field. */
1080 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1. */
1081 
1082 /* Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1083 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL) /*!< Position of APPCLEAR_0 field. */
1084 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos) /*!< Bit mask of APPCLEAR_0 field. */
1085 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0. */
1086 
1087 /* Register: CTI_CTIAPPPULSE */
1088 /* Description: CTI Application Pulse register */
1089 
1090 /* Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1091 #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL) /*!< Position of APPULSE_3 field. */
1092 #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos) /*!< Bit mask of APPULSE_3 field. */
1093 #define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3. */
1094 
1095 /* Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1096 #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL) /*!< Position of APPULSE_2 field. */
1097 #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos) /*!< Bit mask of APPULSE_2 field. */
1098 #define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2. */
1099 
1100 /* Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1101 #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL) /*!< Position of APPULSE_1 field. */
1102 #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos) /*!< Bit mask of APPULSE_1 field. */
1103 #define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1. */
1104 
1105 /* Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1106 #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL) /*!< Position of APPULSE_0 field. */
1107 #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos) /*!< Bit mask of APPULSE_0 field. */
1108 #define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0. */
1109 
1110 /* Register: CTI_CTIINEN */
1111 /* Description: Description collection: CTI Trigger input */
1112 
1113 /* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */
1114 #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL) /*!< Position of TRIGINEN_3 field. */
1115 #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos) /*!< Bit mask of TRIGINEN_3 field. */
1116 #define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3. */
1117 #define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. */
1118 
1119 /* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */
1120 #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL) /*!< Position of TRIGINEN_2 field. */
1121 #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos) /*!< Bit mask of TRIGINEN_2 field. */
1122 #define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2. */
1123 #define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. */
1124 
1125 /* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */
1126 #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL) /*!< Position of TRIGINEN_1 field. */
1127 #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos) /*!< Bit mask of TRIGINEN_1 field. */
1128 #define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1. */
1129 #define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. */
1130 
1131 /* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */
1132 #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL) /*!< Position of TRIGINEN_0 field. */
1133 #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos) /*!< Bit mask of TRIGINEN_0 field. */
1134 #define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0. */
1135 #define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. */
1136 
1137 /* Register: CTI_CTIOUTEN */
1138 /* Description: Description collection: CTI Trigger output */
1139 
1140 /* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */
1141 #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL) /*!< Position of TRIGOUTEN_3 field. */
1142 #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos) /*!< Bit mask of TRIGOUTEN_3 field. */
1143 #define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n. */
1144 #define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). */
1145 
1146 /* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */
1147 #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL) /*!< Position of TRIGOUTEN_2 field. */
1148 #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos) /*!< Bit mask of TRIGOUTEN_2 field. */
1149 #define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n. */
1150 #define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). */
1151 
1152 /* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */
1153 #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL) /*!< Position of TRIGOUTEN_1 field. */
1154 #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos) /*!< Bit mask of TRIGOUTEN_1 field. */
1155 #define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n. */
1156 #define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). */
1157 
1158 /* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */
1159 #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL) /*!< Position of TRIGOUTEN_0 field. */
1160 #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos) /*!< Bit mask of TRIGOUTEN_0 field. */
1161 #define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n. */
1162 #define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). */
1163 
1164 /* Register: CTI_CTITRIGINSTATUS */
1165 /* Description: CTI Trigger In Status register */
1166 
1167 /* Bit 7 : N/A */
1168 #define CTI_CTITRIGINSTATUS_UNUSED3_Pos (7UL) /*!< Position of UNUSED3 field. */
1169 #define CTI_CTITRIGINSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */
1170 #define CTI_CTITRIGINSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigin 7 is inactive. */
1171 #define CTI_CTITRIGINSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigin 7 is active. */
1172 
1173 /* Bit 6 : N/A */
1174 #define CTI_CTITRIGINSTATUS_UNUSED2_Pos (6UL) /*!< Position of UNUSED2 field. */
1175 #define CTI_CTITRIGINSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */
1176 #define CTI_CTITRIGINSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigin 6 is inactive. */
1177 #define CTI_CTITRIGINSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigin 6 is active. */
1178 
1179 /* Bit 5 : N/A */
1180 #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (5UL) /*!< Position of UNUSED1 field. */
1181 #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1182 #define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 5 is inactive. */
1183 #define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 5 is active. */
1184 
1185 /* Bit 4 : N/A */
1186 #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (4UL) /*!< Position of UNUSED0 field. */
1187 #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1188 #define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 4 is inactive. */
1189 #define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 4 is active. */
1190 
1191 /* Bit 3 : DWT Comparator Output 2 */
1192 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL) /*!< Position of DWTCOMPOUT2 field. */
1193 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos) /*!< Bit mask of DWTCOMPOUT2 field. */
1194 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive. */
1195 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active. */
1196 
1197 /* Bit 2 : DWT Comparator Output 1 */
1198 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL) /*!< Position of DWTCOMPOUT1 field. */
1199 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos) /*!< Bit mask of DWTCOMPOUT1 field. */
1200 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive. */
1201 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active. */
1202 
1203 /* Bit 1 : DWT Comparator Output 0 */
1204 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL) /*!< Position of DWTCOMPOUT0 field. */
1205 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos) /*!< Bit mask of DWTCOMPOUT0 field. */
1206 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive. */
1207 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active. */
1208 
1209 /* Bit 0 : Processor Halted */
1210 #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL) /*!< Position of CPUHALTED field. */
1211 #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos) /*!< Bit mask of CPUHALTED field. */
1212 #define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive. */
1213 #define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active. */
1214 
1215 /* Register: CTI_CTITRIGOUTSTATUS */
1216 /* Description: CTI Trigger Out Status register */
1217 
1218 /* Bit 7 : N/A */
1219 #define CTI_CTITRIGOUTSTATUS_UNUSED5_Pos (7UL) /*!< Position of UNUSED5 field. */
1220 #define CTI_CTITRIGOUTSTATUS_UNUSED5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED5_Pos) /*!< Bit mask of UNUSED5 field. */
1221 #define CTI_CTITRIGOUTSTATUS_UNUSED5_Inactive (0UL) /*!< Ctitrigout 7 is inactive. */
1222 #define CTI_CTITRIGOUTSTATUS_UNUSED5_Active (1UL) /*!< Ctitrigout 7 is active. */
1223 
1224 /* Bit 6 : N/A */
1225 #define CTI_CTITRIGOUTSTATUS_UNUSED4_Pos (6UL) /*!< Position of UNUSED4 field. */
1226 #define CTI_CTITRIGOUTSTATUS_UNUSED4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED4_Pos) /*!< Bit mask of UNUSED4 field. */
1227 #define CTI_CTITRIGOUTSTATUS_UNUSED4_Inactive (0UL) /*!< Ctitrigout 6 is inactive. */
1228 #define CTI_CTITRIGOUTSTATUS_UNUSED4_Active (1UL) /*!< Ctitrigout 6 is active. */
1229 
1230 /* Bit 5 : N/A */
1231 #define CTI_CTITRIGOUTSTATUS_UNUSED3_Pos (5UL) /*!< Position of UNUSED3 field. */
1232 #define CTI_CTITRIGOUTSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */
1233 #define CTI_CTITRIGOUTSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigout 5 is inactive. */
1234 #define CTI_CTITRIGOUTSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigout 5 is active. */
1235 
1236 /* Bit 4 : N/A */
1237 #define CTI_CTITRIGOUTSTATUS_UNUSED2_Pos (4UL) /*!< Position of UNUSED2 field. */
1238 #define CTI_CTITRIGOUTSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */
1239 #define CTI_CTITRIGOUTSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigout 4 is inactive. */
1240 #define CTI_CTITRIGOUTSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigout 4 is active. */
1241 
1242 /* Bit 3 : N/A */
1243 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */
1244 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1245 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive. */
1246 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active. */
1247 
1248 /* Bit 2 : N/A */
1249 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */
1250 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1251 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive. */
1252 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active. */
1253 
1254 /* Bit 1 : Processor Restart */
1255 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */
1256 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */
1257 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive. */
1258 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active. */
1259 
1260 /* Bit 0 : Processor debug request */
1261 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */
1262 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */
1263 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive. */
1264 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active. */
1265 
1266 /* Register: CTI_CTICHINSTATUS */
1267 /* Description: CTI Channel In Status register */
1268 
1269 /* Bit 3 : Shows the status of the ctitrigin 3 input. */
1270 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL) /*!< Position of CTICHINSTATUS_3 field. */
1271 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos) /*!< Bit mask of CTICHINSTATUS_3 field. */
1272 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive. */
1273 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active. */
1274 
1275 /* Bit 2 : Shows the status of the ctitrigin 2 input. */
1276 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL) /*!< Position of CTICHINSTATUS_2 field. */
1277 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos) /*!< Bit mask of CTICHINSTATUS_2 field. */
1278 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive. */
1279 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active. */
1280 
1281 /* Bit 1 : Shows the status of the ctitrigin 1 input. */
1282 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL) /*!< Position of CTICHINSTATUS_1 field. */
1283 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos) /*!< Bit mask of CTICHINSTATUS_1 field. */
1284 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive. */
1285 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active. */
1286 
1287 /* Bit 0 : Shows the status of the ctitrigin 0 input. */
1288 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL) /*!< Position of CTICHINSTATUS_0 field. */
1289 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos) /*!< Bit mask of CTICHINSTATUS_0 field. */
1290 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive. */
1291 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active. */
1292 
1293 /* Register: CTI_CTIGATE */
1294 /* Description: Enable CTI Channel Gate register */
1295 
1296 /* Bit 3 : Enable ctichout3. */
1297 #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL) /*!< Position of CTIGATEEN_3 field. */
1298 #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos) /*!< Bit mask of CTIGATEEN_3 field. */
1299 #define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation. */
1300 #define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation. */
1301 
1302 /* Bit 2 : Enable ctichout2. */
1303 #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL) /*!< Position of CTIGATEEN_2 field. */
1304 #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos) /*!< Bit mask of CTIGATEEN_2 field. */
1305 #define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation. */
1306 #define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation. */
1307 
1308 /* Bit 1 : Enable ctichout1. */
1309 #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL) /*!< Position of CTIGATEEN_1 field. */
1310 #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos) /*!< Bit mask of CTIGATEEN_1 field. */
1311 #define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation. */
1312 #define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation. */
1313 
1314 /* Bit 0 : Enable ctichout0. */
1315 #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL) /*!< Position of CTIGATEEN_0 field. */
1316 #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos) /*!< Bit mask of CTIGATEEN_0 field. */
1317 #define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation. */
1318 #define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation. */
1319 
1320 /* Register: CTI_DEVARCH */
1321 /* Description: Device Architecture register */
1322 
1323 /* Bit 0 : Contains the CTI device architecture. */
1324 #define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */
1325 #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */
1326 
1327 /* Register: CTI_DEVID */
1328 /* Description: Device Configuration register */
1329 
1330 /* Bits 19..16 : Number of ECT channels available. */
1331 #define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */
1332 #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */
1333 
1334 /* Bits 15..8 : Number of ECT triggers available. */
1335 #define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */
1336 #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */
1337 
1338 /* Bits 4..0 : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl.
1339                     The default value of 0b00000 indicates that no multiplexing is present. */
1340 #define CTI_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */
1341 #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */
1342 
1343 /* Register: CTI_DEVTYPE */
1344 /* Description: Device Type Identifier register */
1345 
1346 /* Bits 7..4 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within
1347                     the major classification as specified in the MAJOR field. */
1348 #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
1349 #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
1350 #define CTI_DEVTYPE_SUB_Crosstrigger (1UL) /*!< Indicates that this component is a sub-triggering component. */
1351 
1352 /* Bits 3..0 : Major classification of the type of the debug component as specified in the Arm Architecture Specification for this
1353                     debug and trace component. */
1354 #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
1355 #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
1356 #define CTI_DEVTYPE_MAJOR_Controller (4UL) /*!< Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. */
1357 
1358 /* Register: CTI_PIDR4 */
1359 /* Description: Peripheral ID4 Register */
1360 
1361 /* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */
1362 #define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */
1363 #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */
1364 
1365 /* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1366 #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */
1367 #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */
1368 #define CTI_PIDR4_DES_2_Code (4UL) /*!< JEDEC continuation code. */
1369 
1370 /* Register: CTI_PIDR0 */
1371 /* Description: Peripheral ID0 Register */
1372 
1373 /* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. */
1374 #define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */
1375 #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */
1376 #define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */
1377 
1378 /* Register: CTI_PIDR1 */
1379 /* Description: Peripheral ID1 Register */
1380 
1381 /* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1382 #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */
1383 #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */
1384 #define CTI_PIDR1_DES_0_Arm (11UL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */
1385 
1386 /* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */
1387 #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */
1388 #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */
1389 #define CTI_PIDR1_PART_1_PartnumberH (13UL) /*!< Indicates bits[11:8] of the part number of the component. */
1390 
1391 /* Register: CTI_PIDR2 */
1392 /* Description: Peripheral ID2 Register */
1393 
1394 /* Bits 7..4 : Peripheral revision */
1395 #define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */
1396 #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */
1397 #define CTI_PIDR2_REVISION_Rev0p0 (0UL) /*!< This device is at r0p0 */
1398 
1399 /* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */
1400 #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */
1401 #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */
1402 
1403 /* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1404 #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */
1405 #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */
1406 #define CTI_PIDR2_DES_1_Arm (3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */
1407 
1408 /* Register: CTI_PIDR3 */
1409 /* Description: Peripheral ID3 Register */
1410 
1411 /* Bits 7..4 : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after
1412                     implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a
1413                     metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */
1414 #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */
1415 #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */
1416 #define CTI_PIDR3_REVAND_NoErrata (0UL) /*!< Indicates that there are no errata fixes to this component. */
1417 
1418 /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases,
1419                     this field is 0b0000. Customers change this value when they make authorized modifications to this component. */
1420 #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */
1421 #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */
1422 #define CTI_PIDR3_CMOD_Unmodified (0UL) /*!< Indicates that the customer has not modified this component. */
1423 
1424 /* Register: CTI_CIDR0 */
1425 /* Description: Component ID0 Register */
1426 
1427 /* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code. */
1428 #define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */
1429 #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */
1430 #define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */
1431 
1432 /* Register: CTI_CIDR1 */
1433 /* Description: Component ID1 Register */
1434 
1435 /* Bits 7..4 : Class of the component, for example, whether the component is a ROM table or a generic CoreSight component.
1436                     Contains bits[15:12] of the component identification code */
1437 #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */
1438 #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */
1439 #define CTI_CIDR1_CLASS_Coresight (9UL) /*!< Indicates that the component is a CoreSight component. */
1440 
1441 /* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */
1442 #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */
1443 #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */
1444 #define CTI_CIDR1_PRMBL_1_Value (0UL) /*!< Bits[11:8] of the identification code. */
1445 
1446 /* Register: CTI_CIDR2 */
1447 /* Description: Component ID2 Register */
1448 
1449 /* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code. */
1450 #define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */
1451 #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */
1452 #define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */
1453 
1454 /* Register: CTI_CIDR3 */
1455 /* Description: Component ID3 Register */
1456 
1457 /* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code. */
1458 #define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */
1459 #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */
1460 #define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */
1461 
1462 
1463 /* Peripheral: CTRLAPPERI */
1464 /* Description: Control access port */
1465 
1466 /* Register: CTRLAPPERI_MAILBOX_RXDATA */
1467 /* Description: Data sent from the debugger to the CPU. */
1468 
1469 /* Bits 31..0 : Data received from debugger */
1470 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
1471 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
1472 
1473 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
1474 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
1475 
1476 /* Bit 0 : Status of data in register RXDATA */
1477 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
1478 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
1479 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */
1480 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
1481 
1482 /* Register: CTRLAPPERI_MAILBOX_TXDATA */
1483 /* Description: Data sent from the CPU to the debugger. */
1484 
1485 /* Bits 31..0 : Data sent to debugger */
1486 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
1487 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
1488 
1489 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
1490 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
1491 
1492 /* Bit 0 : Status of data in register TXDATA */
1493 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
1494 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
1495 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */
1496 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
1497 
1498 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
1499 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
1500 
1501 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
1502 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
1503 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
1504 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
1505 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
1506 
1507 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
1508 /* Description: This register disables the ERASEPROTECT register and performs an  ERASEALL operation. */
1509 
1510 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
1511 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
1512 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
1513 
1514 /* Register: CTRLAPPERI_APPROTECT_LOCK */
1515 /* Description: This register locks the APPROTECT.DISABLE register from being written to until next reset. */
1516 
1517 /* Bit 0 : Lock the APPROTECT.DISABLE register from being written to until next reset */
1518 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
1519 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
1520 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register APPROTECT.DISABLE is writeable */
1521 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register APPROTECT.DISABLE is read-only */
1522 
1523 /* Register: CTRLAPPERI_APPROTECT_DISABLE */
1524 /* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */
1525 
1526 /* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the
1527         CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until
1528         the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. */
1529 #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
1530 #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
1531 
1532 /* Register: CTRLAPPERI_STATUS */
1533 /* Description: Status bits for CTRL-AP peripheral. */
1534 
1535 /* Bit 2 : Status bit for device debug interface mode */
1536 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */
1537 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */
1538 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */
1539 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */
1540 
1541 /* Bit 0 : Status bit for UICR part of access port protection at last reset. */
1542 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Pos (0UL) /*!< Position of UICRAPPROTECT field. */
1543 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRAPPROTECT_Pos) /*!< Bit mask of UICRAPPROTECT field. */
1544 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Enabled (0UL) /*!< APPROTECT was enabled in UICR */
1545 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Disabled (1UL) /*!< APPROTECT wasdisabled in UICR */
1546 
1547 
1548 /* Peripheral: DCNF */
1549 /* Description: Domain configuration management */
1550 
1551 /* Register: DCNF_CPUID */
1552 /* Description: CPU ID of this subsystem */
1553 
1554 /* Bits 7..0 : CPU ID */
1555 #define DCNF_CPUID_CPUID_Pos (0UL) /*!< Position of CPUID field. */
1556 #define DCNF_CPUID_CPUID_Msk (0xFFUL << DCNF_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field. */
1557 
1558 
1559 /* Peripheral: DPPIC */
1560 /* Description: Distributed programmable peripheral interconnect controller */
1561 
1562 /* Register: DPPIC_TASKS_CHG_EN */
1563 /* Description: Description cluster: Enable channel group n */
1564 
1565 /* Bit 0 : Enable channel group n */
1566 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
1567 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
1568 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
1569 
1570 /* Register: DPPIC_TASKS_CHG_DIS */
1571 /* Description: Description cluster: Disable channel group n */
1572 
1573 /* Bit 0 : Disable channel group n */
1574 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
1575 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
1576 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
1577 
1578 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
1579 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
1580 
1581 /* Bit 31 :   */
1582 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
1583 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
1584 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
1585 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
1586 
1587 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
1588 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1589 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1590 
1591 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
1592 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
1593 
1594 /* Bit 31 :   */
1595 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
1596 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
1597 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
1598 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
1599 
1600 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
1601 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1602 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1603 
1604 /* Register: DPPIC_CHEN */
1605 /* Description: Channel enable register */
1606 
1607 /* Bit 31 : Enable or disable channel 31 */
1608 #define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
1609 #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
1610 #define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
1611 #define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
1612 
1613 /* Bit 30 : Enable or disable channel 30 */
1614 #define DPPIC_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
1615 #define DPPIC_CHEN_CH30_Msk (0x1UL << DPPIC_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
1616 #define DPPIC_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
1617 #define DPPIC_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
1618 
1619 /* Bit 29 : Enable or disable channel 29 */
1620 #define DPPIC_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
1621 #define DPPIC_CHEN_CH29_Msk (0x1UL << DPPIC_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
1622 #define DPPIC_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
1623 #define DPPIC_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
1624 
1625 /* Bit 28 : Enable or disable channel 28 */
1626 #define DPPIC_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
1627 #define DPPIC_CHEN_CH28_Msk (0x1UL << DPPIC_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
1628 #define DPPIC_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
1629 #define DPPIC_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
1630 
1631 /* Bit 27 : Enable or disable channel 27 */
1632 #define DPPIC_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
1633 #define DPPIC_CHEN_CH27_Msk (0x1UL << DPPIC_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
1634 #define DPPIC_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
1635 #define DPPIC_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
1636 
1637 /* Bit 26 : Enable or disable channel 26 */
1638 #define DPPIC_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
1639 #define DPPIC_CHEN_CH26_Msk (0x1UL << DPPIC_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
1640 #define DPPIC_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
1641 #define DPPIC_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
1642 
1643 /* Bit 25 : Enable or disable channel 25 */
1644 #define DPPIC_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
1645 #define DPPIC_CHEN_CH25_Msk (0x1UL << DPPIC_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
1646 #define DPPIC_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
1647 #define DPPIC_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
1648 
1649 /* Bit 24 : Enable or disable channel 24 */
1650 #define DPPIC_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
1651 #define DPPIC_CHEN_CH24_Msk (0x1UL << DPPIC_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
1652 #define DPPIC_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
1653 #define DPPIC_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
1654 
1655 /* Bit 23 : Enable or disable channel 23 */
1656 #define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
1657 #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
1658 #define DPPIC_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
1659 #define DPPIC_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
1660 
1661 /* Bit 22 : Enable or disable channel 22 */
1662 #define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
1663 #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
1664 #define DPPIC_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
1665 #define DPPIC_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
1666 
1667 /* Bit 21 : Enable or disable channel 21 */
1668 #define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
1669 #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
1670 #define DPPIC_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
1671 #define DPPIC_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
1672 
1673 /* Bit 20 : Enable or disable channel 20 */
1674 #define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
1675 #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
1676 #define DPPIC_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
1677 #define DPPIC_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
1678 
1679 /* Bit 19 : Enable or disable channel 19 */
1680 #define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
1681 #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
1682 #define DPPIC_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
1683 #define DPPIC_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
1684 
1685 /* Bit 18 : Enable or disable channel 18 */
1686 #define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
1687 #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
1688 #define DPPIC_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
1689 #define DPPIC_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
1690 
1691 /* Bit 17 : Enable or disable channel 17 */
1692 #define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
1693 #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
1694 #define DPPIC_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
1695 #define DPPIC_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
1696 
1697 /* Bit 16 : Enable or disable channel 16 */
1698 #define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
1699 #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
1700 #define DPPIC_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
1701 #define DPPIC_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
1702 
1703 /* Bit 15 : Enable or disable channel 15 */
1704 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
1705 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
1706 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
1707 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
1708 
1709 /* Bit 14 : Enable or disable channel 14 */
1710 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
1711 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
1712 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
1713 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
1714 
1715 /* Bit 13 : Enable or disable channel 13 */
1716 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
1717 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
1718 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
1719 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
1720 
1721 /* Bit 12 : Enable or disable channel 12 */
1722 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
1723 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
1724 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
1725 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
1726 
1727 /* Bit 11 : Enable or disable channel 11 */
1728 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
1729 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
1730 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
1731 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
1732 
1733 /* Bit 10 : Enable or disable channel 10 */
1734 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
1735 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
1736 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
1737 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
1738 
1739 /* Bit 9 : Enable or disable channel 9 */
1740 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
1741 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
1742 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
1743 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
1744 
1745 /* Bit 8 : Enable or disable channel 8 */
1746 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
1747 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
1748 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
1749 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
1750 
1751 /* Bit 7 : Enable or disable channel 7 */
1752 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
1753 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
1754 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
1755 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
1756 
1757 /* Bit 6 : Enable or disable channel 6 */
1758 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
1759 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
1760 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
1761 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
1762 
1763 /* Bit 5 : Enable or disable channel 5 */
1764 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
1765 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
1766 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
1767 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
1768 
1769 /* Bit 4 : Enable or disable channel 4 */
1770 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
1771 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
1772 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
1773 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
1774 
1775 /* Bit 3 : Enable or disable channel 3 */
1776 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
1777 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
1778 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
1779 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
1780 
1781 /* Bit 2 : Enable or disable channel 2 */
1782 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
1783 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
1784 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
1785 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
1786 
1787 /* Bit 1 : Enable or disable channel 1 */
1788 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
1789 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
1790 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
1791 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
1792 
1793 /* Bit 0 : Enable or disable channel 0 */
1794 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
1795 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
1796 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
1797 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
1798 
1799 /* Register: DPPIC_CHENSET */
1800 /* Description: Channel enable set register */
1801 
1802 /* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */
1803 #define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
1804 #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
1805 #define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */
1806 #define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */
1807 #define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
1808 
1809 /* Bit 30 : Channel 30 enable set register. Writing 0 has no effect. */
1810 #define DPPIC_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
1811 #define DPPIC_CHENSET_CH30_Msk (0x1UL << DPPIC_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
1812 #define DPPIC_CHENSET_CH30_Disabled (0UL) /*!< Read: Channel disabled */
1813 #define DPPIC_CHENSET_CH30_Enabled (1UL) /*!< Read: Channel enabled */
1814 #define DPPIC_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
1815 
1816 /* Bit 29 : Channel 29 enable set register. Writing 0 has no effect. */
1817 #define DPPIC_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
1818 #define DPPIC_CHENSET_CH29_Msk (0x1UL << DPPIC_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
1819 #define DPPIC_CHENSET_CH29_Disabled (0UL) /*!< Read: Channel disabled */
1820 #define DPPIC_CHENSET_CH29_Enabled (1UL) /*!< Read: Channel enabled */
1821 #define DPPIC_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
1822 
1823 /* Bit 28 : Channel 28 enable set register. Writing 0 has no effect. */
1824 #define DPPIC_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
1825 #define DPPIC_CHENSET_CH28_Msk (0x1UL << DPPIC_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
1826 #define DPPIC_CHENSET_CH28_Disabled (0UL) /*!< Read: Channel disabled */
1827 #define DPPIC_CHENSET_CH28_Enabled (1UL) /*!< Read: Channel enabled */
1828 #define DPPIC_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
1829 
1830 /* Bit 27 : Channel 27 enable set register. Writing 0 has no effect. */
1831 #define DPPIC_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
1832 #define DPPIC_CHENSET_CH27_Msk (0x1UL << DPPIC_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
1833 #define DPPIC_CHENSET_CH27_Disabled (0UL) /*!< Read: Channel disabled */
1834 #define DPPIC_CHENSET_CH27_Enabled (1UL) /*!< Read: Channel enabled */
1835 #define DPPIC_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
1836 
1837 /* Bit 26 : Channel 26 enable set register. Writing 0 has no effect. */
1838 #define DPPIC_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
1839 #define DPPIC_CHENSET_CH26_Msk (0x1UL << DPPIC_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
1840 #define DPPIC_CHENSET_CH26_Disabled (0UL) /*!< Read: Channel disabled */
1841 #define DPPIC_CHENSET_CH26_Enabled (1UL) /*!< Read: Channel enabled */
1842 #define DPPIC_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
1843 
1844 /* Bit 25 : Channel 25 enable set register. Writing 0 has no effect. */
1845 #define DPPIC_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
1846 #define DPPIC_CHENSET_CH25_Msk (0x1UL << DPPIC_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
1847 #define DPPIC_CHENSET_CH25_Disabled (0UL) /*!< Read: Channel disabled */
1848 #define DPPIC_CHENSET_CH25_Enabled (1UL) /*!< Read: Channel enabled */
1849 #define DPPIC_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
1850 
1851 /* Bit 24 : Channel 24 enable set register. Writing 0 has no effect. */
1852 #define DPPIC_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
1853 #define DPPIC_CHENSET_CH24_Msk (0x1UL << DPPIC_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
1854 #define DPPIC_CHENSET_CH24_Disabled (0UL) /*!< Read: Channel disabled */
1855 #define DPPIC_CHENSET_CH24_Enabled (1UL) /*!< Read: Channel enabled */
1856 #define DPPIC_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
1857 
1858 /* Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */
1859 #define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
1860 #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
1861 #define DPPIC_CHENSET_CH23_Disabled (0UL) /*!< Read: Channel disabled */
1862 #define DPPIC_CHENSET_CH23_Enabled (1UL) /*!< Read: Channel enabled */
1863 #define DPPIC_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
1864 
1865 /* Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */
1866 #define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
1867 #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
1868 #define DPPIC_CHENSET_CH22_Disabled (0UL) /*!< Read: Channel disabled */
1869 #define DPPIC_CHENSET_CH22_Enabled (1UL) /*!< Read: Channel enabled */
1870 #define DPPIC_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
1871 
1872 /* Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */
1873 #define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
1874 #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
1875 #define DPPIC_CHENSET_CH21_Disabled (0UL) /*!< Read: Channel disabled */
1876 #define DPPIC_CHENSET_CH21_Enabled (1UL) /*!< Read: Channel enabled */
1877 #define DPPIC_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
1878 
1879 /* Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */
1880 #define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
1881 #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
1882 #define DPPIC_CHENSET_CH20_Disabled (0UL) /*!< Read: Channel disabled */
1883 #define DPPIC_CHENSET_CH20_Enabled (1UL) /*!< Read: Channel enabled */
1884 #define DPPIC_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
1885 
1886 /* Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */
1887 #define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
1888 #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
1889 #define DPPIC_CHENSET_CH19_Disabled (0UL) /*!< Read: Channel disabled */
1890 #define DPPIC_CHENSET_CH19_Enabled (1UL) /*!< Read: Channel enabled */
1891 #define DPPIC_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
1892 
1893 /* Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */
1894 #define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
1895 #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
1896 #define DPPIC_CHENSET_CH18_Disabled (0UL) /*!< Read: Channel disabled */
1897 #define DPPIC_CHENSET_CH18_Enabled (1UL) /*!< Read: Channel enabled */
1898 #define DPPIC_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
1899 
1900 /* Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */
1901 #define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
1902 #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
1903 #define DPPIC_CHENSET_CH17_Disabled (0UL) /*!< Read: Channel disabled */
1904 #define DPPIC_CHENSET_CH17_Enabled (1UL) /*!< Read: Channel enabled */
1905 #define DPPIC_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
1906 
1907 /* Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */
1908 #define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
1909 #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
1910 #define DPPIC_CHENSET_CH16_Disabled (0UL) /*!< Read: Channel disabled */
1911 #define DPPIC_CHENSET_CH16_Enabled (1UL) /*!< Read: Channel enabled */
1912 #define DPPIC_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
1913 
1914 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
1915 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
1916 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
1917 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */
1918 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */
1919 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
1920 
1921 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
1922 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
1923 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
1924 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */
1925 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */
1926 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
1927 
1928 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
1929 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
1930 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
1931 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */
1932 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */
1933 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
1934 
1935 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
1936 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
1937 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
1938 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */
1939 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */
1940 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
1941 
1942 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
1943 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
1944 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
1945 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */
1946 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */
1947 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
1948 
1949 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
1950 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
1951 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
1952 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */
1953 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */
1954 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
1955 
1956 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
1957 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
1958 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
1959 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */
1960 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */
1961 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
1962 
1963 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
1964 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
1965 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
1966 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */
1967 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */
1968 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
1969 
1970 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
1971 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
1972 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
1973 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */
1974 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */
1975 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
1976 
1977 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
1978 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
1979 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
1980 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */
1981 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */
1982 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
1983 
1984 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
1985 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
1986 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
1987 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */
1988 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */
1989 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
1990 
1991 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
1992 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
1993 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
1994 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */
1995 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */
1996 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
1997 
1998 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
1999 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
2000 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
2001 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */
2002 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */
2003 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
2004 
2005 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
2006 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
2007 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
2008 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */
2009 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */
2010 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
2011 
2012 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
2013 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
2014 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
2015 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */
2016 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */
2017 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
2018 
2019 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
2020 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
2021 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
2022 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2023 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2024 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
2025 
2026 /* Register: DPPIC_CHENCLR */
2027 /* Description: Channel enable clear register */
2028 
2029 /* Bit 31 : Channel 31 enable clear register.  Writing 0 has no effect. */
2030 #define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
2031 #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
2032 #define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */
2033 #define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */
2034 #define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */
2035 
2036 /* Bit 30 : Channel 30 enable clear register.  Writing 0 has no effect. */
2037 #define DPPIC_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
2038 #define DPPIC_CHENCLR_CH30_Msk (0x1UL << DPPIC_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
2039 #define DPPIC_CHENCLR_CH30_Disabled (0UL) /*!< Read: Channel disabled */
2040 #define DPPIC_CHENCLR_CH30_Enabled (1UL) /*!< Read: Channel enabled */
2041 #define DPPIC_CHENCLR_CH30_Clear (1UL) /*!< Write: Disable channel */
2042 
2043 /* Bit 29 : Channel 29 enable clear register.  Writing 0 has no effect. */
2044 #define DPPIC_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
2045 #define DPPIC_CHENCLR_CH29_Msk (0x1UL << DPPIC_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
2046 #define DPPIC_CHENCLR_CH29_Disabled (0UL) /*!< Read: Channel disabled */
2047 #define DPPIC_CHENCLR_CH29_Enabled (1UL) /*!< Read: Channel enabled */
2048 #define DPPIC_CHENCLR_CH29_Clear (1UL) /*!< Write: Disable channel */
2049 
2050 /* Bit 28 : Channel 28 enable clear register.  Writing 0 has no effect. */
2051 #define DPPIC_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
2052 #define DPPIC_CHENCLR_CH28_Msk (0x1UL << DPPIC_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
2053 #define DPPIC_CHENCLR_CH28_Disabled (0UL) /*!< Read: Channel disabled */
2054 #define DPPIC_CHENCLR_CH28_Enabled (1UL) /*!< Read: Channel enabled */
2055 #define DPPIC_CHENCLR_CH28_Clear (1UL) /*!< Write: Disable channel */
2056 
2057 /* Bit 27 : Channel 27 enable clear register.  Writing 0 has no effect. */
2058 #define DPPIC_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
2059 #define DPPIC_CHENCLR_CH27_Msk (0x1UL << DPPIC_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
2060 #define DPPIC_CHENCLR_CH27_Disabled (0UL) /*!< Read: Channel disabled */
2061 #define DPPIC_CHENCLR_CH27_Enabled (1UL) /*!< Read: Channel enabled */
2062 #define DPPIC_CHENCLR_CH27_Clear (1UL) /*!< Write: Disable channel */
2063 
2064 /* Bit 26 : Channel 26 enable clear register.  Writing 0 has no effect. */
2065 #define DPPIC_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
2066 #define DPPIC_CHENCLR_CH26_Msk (0x1UL << DPPIC_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
2067 #define DPPIC_CHENCLR_CH26_Disabled (0UL) /*!< Read: Channel disabled */
2068 #define DPPIC_CHENCLR_CH26_Enabled (1UL) /*!< Read: Channel enabled */
2069 #define DPPIC_CHENCLR_CH26_Clear (1UL) /*!< Write: Disable channel */
2070 
2071 /* Bit 25 : Channel 25 enable clear register.  Writing 0 has no effect. */
2072 #define DPPIC_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
2073 #define DPPIC_CHENCLR_CH25_Msk (0x1UL << DPPIC_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
2074 #define DPPIC_CHENCLR_CH25_Disabled (0UL) /*!< Read: Channel disabled */
2075 #define DPPIC_CHENCLR_CH25_Enabled (1UL) /*!< Read: Channel enabled */
2076 #define DPPIC_CHENCLR_CH25_Clear (1UL) /*!< Write: Disable channel */
2077 
2078 /* Bit 24 : Channel 24 enable clear register.  Writing 0 has no effect. */
2079 #define DPPIC_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
2080 #define DPPIC_CHENCLR_CH24_Msk (0x1UL << DPPIC_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
2081 #define DPPIC_CHENCLR_CH24_Disabled (0UL) /*!< Read: Channel disabled */
2082 #define DPPIC_CHENCLR_CH24_Enabled (1UL) /*!< Read: Channel enabled */
2083 #define DPPIC_CHENCLR_CH24_Clear (1UL) /*!< Write: Disable channel */
2084 
2085 /* Bit 23 : Channel 23 enable clear register.  Writing 0 has no effect. */
2086 #define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
2087 #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
2088 #define DPPIC_CHENCLR_CH23_Disabled (0UL) /*!< Read: Channel disabled */
2089 #define DPPIC_CHENCLR_CH23_Enabled (1UL) /*!< Read: Channel enabled */
2090 #define DPPIC_CHENCLR_CH23_Clear (1UL) /*!< Write: Disable channel */
2091 
2092 /* Bit 22 : Channel 22 enable clear register.  Writing 0 has no effect. */
2093 #define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
2094 #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
2095 #define DPPIC_CHENCLR_CH22_Disabled (0UL) /*!< Read: Channel disabled */
2096 #define DPPIC_CHENCLR_CH22_Enabled (1UL) /*!< Read: Channel enabled */
2097 #define DPPIC_CHENCLR_CH22_Clear (1UL) /*!< Write: Disable channel */
2098 
2099 /* Bit 21 : Channel 21 enable clear register.  Writing 0 has no effect. */
2100 #define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
2101 #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
2102 #define DPPIC_CHENCLR_CH21_Disabled (0UL) /*!< Read: Channel disabled */
2103 #define DPPIC_CHENCLR_CH21_Enabled (1UL) /*!< Read: Channel enabled */
2104 #define DPPIC_CHENCLR_CH21_Clear (1UL) /*!< Write: Disable channel */
2105 
2106 /* Bit 20 : Channel 20 enable clear register.  Writing 0 has no effect. */
2107 #define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
2108 #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
2109 #define DPPIC_CHENCLR_CH20_Disabled (0UL) /*!< Read: Channel disabled */
2110 #define DPPIC_CHENCLR_CH20_Enabled (1UL) /*!< Read: Channel enabled */
2111 #define DPPIC_CHENCLR_CH20_Clear (1UL) /*!< Write: Disable channel */
2112 
2113 /* Bit 19 : Channel 19 enable clear register.  Writing 0 has no effect. */
2114 #define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
2115 #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
2116 #define DPPIC_CHENCLR_CH19_Disabled (0UL) /*!< Read: Channel disabled */
2117 #define DPPIC_CHENCLR_CH19_Enabled (1UL) /*!< Read: Channel enabled */
2118 #define DPPIC_CHENCLR_CH19_Clear (1UL) /*!< Write: Disable channel */
2119 
2120 /* Bit 18 : Channel 18 enable clear register.  Writing 0 has no effect. */
2121 #define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
2122 #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
2123 #define DPPIC_CHENCLR_CH18_Disabled (0UL) /*!< Read: Channel disabled */
2124 #define DPPIC_CHENCLR_CH18_Enabled (1UL) /*!< Read: Channel enabled */
2125 #define DPPIC_CHENCLR_CH18_Clear (1UL) /*!< Write: Disable channel */
2126 
2127 /* Bit 17 : Channel 17 enable clear register.  Writing 0 has no effect. */
2128 #define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
2129 #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
2130 #define DPPIC_CHENCLR_CH17_Disabled (0UL) /*!< Read: Channel disabled */
2131 #define DPPIC_CHENCLR_CH17_Enabled (1UL) /*!< Read: Channel enabled */
2132 #define DPPIC_CHENCLR_CH17_Clear (1UL) /*!< Write: Disable channel */
2133 
2134 /* Bit 16 : Channel 16 enable clear register.  Writing 0 has no effect. */
2135 #define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
2136 #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
2137 #define DPPIC_CHENCLR_CH16_Disabled (0UL) /*!< Read: Channel disabled */
2138 #define DPPIC_CHENCLR_CH16_Enabled (1UL) /*!< Read: Channel enabled */
2139 #define DPPIC_CHENCLR_CH16_Clear (1UL) /*!< Write: Disable channel */
2140 
2141 /* Bit 15 : Channel 15 enable clear register.  Writing 0 has no effect. */
2142 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
2143 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
2144 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */
2145 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */
2146 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */
2147 
2148 /* Bit 14 : Channel 14 enable clear register.  Writing 0 has no effect. */
2149 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
2150 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
2151 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */
2152 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */
2153 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */
2154 
2155 /* Bit 13 : Channel 13 enable clear register.  Writing 0 has no effect. */
2156 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
2157 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
2158 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */
2159 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */
2160 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */
2161 
2162 /* Bit 12 : Channel 12 enable clear register.  Writing 0 has no effect. */
2163 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
2164 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
2165 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */
2166 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */
2167 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */
2168 
2169 /* Bit 11 : Channel 11 enable clear register.  Writing 0 has no effect. */
2170 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
2171 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
2172 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */
2173 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */
2174 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */
2175 
2176 /* Bit 10 : Channel 10 enable clear register.  Writing 0 has no effect. */
2177 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
2178 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
2179 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */
2180 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */
2181 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */
2182 
2183 /* Bit 9 : Channel 9 enable clear register.  Writing 0 has no effect. */
2184 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
2185 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
2186 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */
2187 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */
2188 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */
2189 
2190 /* Bit 8 : Channel 8 enable clear register.  Writing 0 has no effect. */
2191 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
2192 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
2193 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */
2194 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */
2195 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */
2196 
2197 /* Bit 7 : Channel 7 enable clear register.  Writing 0 has no effect. */
2198 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
2199 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
2200 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */
2201 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */
2202 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */
2203 
2204 /* Bit 6 : Channel 6 enable clear register.  Writing 0 has no effect. */
2205 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
2206 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
2207 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */
2208 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */
2209 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */
2210 
2211 /* Bit 5 : Channel 5 enable clear register.  Writing 0 has no effect. */
2212 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
2213 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
2214 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */
2215 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */
2216 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */
2217 
2218 /* Bit 4 : Channel 4 enable clear register.  Writing 0 has no effect. */
2219 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
2220 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
2221 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */
2222 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */
2223 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */
2224 
2225 /* Bit 3 : Channel 3 enable clear register.  Writing 0 has no effect. */
2226 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
2227 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
2228 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */
2229 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */
2230 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */
2231 
2232 /* Bit 2 : Channel 2 enable clear register.  Writing 0 has no effect. */
2233 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
2234 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
2235 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */
2236 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */
2237 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */
2238 
2239 /* Bit 1 : Channel 1 enable clear register.  Writing 0 has no effect. */
2240 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
2241 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
2242 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */
2243 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */
2244 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */
2245 
2246 /* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
2247 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
2248 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
2249 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2250 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2251 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
2252 
2253 /* Register: DPPIC_CHG */
2254 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
2255 
2256 /* Bit 31 : Include or exclude channel 31 */
2257 #define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
2258 #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
2259 #define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */
2260 #define DPPIC_CHG_CH31_Included (1UL) /*!< Include */
2261 
2262 /* Bit 30 : Include or exclude channel 30 */
2263 #define DPPIC_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
2264 #define DPPIC_CHG_CH30_Msk (0x1UL << DPPIC_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
2265 #define DPPIC_CHG_CH30_Excluded (0UL) /*!< Exclude */
2266 #define DPPIC_CHG_CH30_Included (1UL) /*!< Include */
2267 
2268 /* Bit 29 : Include or exclude channel 29 */
2269 #define DPPIC_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
2270 #define DPPIC_CHG_CH29_Msk (0x1UL << DPPIC_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
2271 #define DPPIC_CHG_CH29_Excluded (0UL) /*!< Exclude */
2272 #define DPPIC_CHG_CH29_Included (1UL) /*!< Include */
2273 
2274 /* Bit 28 : Include or exclude channel 28 */
2275 #define DPPIC_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
2276 #define DPPIC_CHG_CH28_Msk (0x1UL << DPPIC_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
2277 #define DPPIC_CHG_CH28_Excluded (0UL) /*!< Exclude */
2278 #define DPPIC_CHG_CH28_Included (1UL) /*!< Include */
2279 
2280 /* Bit 27 : Include or exclude channel 27 */
2281 #define DPPIC_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
2282 #define DPPIC_CHG_CH27_Msk (0x1UL << DPPIC_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
2283 #define DPPIC_CHG_CH27_Excluded (0UL) /*!< Exclude */
2284 #define DPPIC_CHG_CH27_Included (1UL) /*!< Include */
2285 
2286 /* Bit 26 : Include or exclude channel 26 */
2287 #define DPPIC_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
2288 #define DPPIC_CHG_CH26_Msk (0x1UL << DPPIC_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
2289 #define DPPIC_CHG_CH26_Excluded (0UL) /*!< Exclude */
2290 #define DPPIC_CHG_CH26_Included (1UL) /*!< Include */
2291 
2292 /* Bit 25 : Include or exclude channel 25 */
2293 #define DPPIC_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
2294 #define DPPIC_CHG_CH25_Msk (0x1UL << DPPIC_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
2295 #define DPPIC_CHG_CH25_Excluded (0UL) /*!< Exclude */
2296 #define DPPIC_CHG_CH25_Included (1UL) /*!< Include */
2297 
2298 /* Bit 24 : Include or exclude channel 24 */
2299 #define DPPIC_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
2300 #define DPPIC_CHG_CH24_Msk (0x1UL << DPPIC_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
2301 #define DPPIC_CHG_CH24_Excluded (0UL) /*!< Exclude */
2302 #define DPPIC_CHG_CH24_Included (1UL) /*!< Include */
2303 
2304 /* Bit 23 : Include or exclude channel 23 */
2305 #define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
2306 #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
2307 #define DPPIC_CHG_CH23_Excluded (0UL) /*!< Exclude */
2308 #define DPPIC_CHG_CH23_Included (1UL) /*!< Include */
2309 
2310 /* Bit 22 : Include or exclude channel 22 */
2311 #define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
2312 #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
2313 #define DPPIC_CHG_CH22_Excluded (0UL) /*!< Exclude */
2314 #define DPPIC_CHG_CH22_Included (1UL) /*!< Include */
2315 
2316 /* Bit 21 : Include or exclude channel 21 */
2317 #define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
2318 #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
2319 #define DPPIC_CHG_CH21_Excluded (0UL) /*!< Exclude */
2320 #define DPPIC_CHG_CH21_Included (1UL) /*!< Include */
2321 
2322 /* Bit 20 : Include or exclude channel 20 */
2323 #define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
2324 #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
2325 #define DPPIC_CHG_CH20_Excluded (0UL) /*!< Exclude */
2326 #define DPPIC_CHG_CH20_Included (1UL) /*!< Include */
2327 
2328 /* Bit 19 : Include or exclude channel 19 */
2329 #define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
2330 #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
2331 #define DPPIC_CHG_CH19_Excluded (0UL) /*!< Exclude */
2332 #define DPPIC_CHG_CH19_Included (1UL) /*!< Include */
2333 
2334 /* Bit 18 : Include or exclude channel 18 */
2335 #define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
2336 #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
2337 #define DPPIC_CHG_CH18_Excluded (0UL) /*!< Exclude */
2338 #define DPPIC_CHG_CH18_Included (1UL) /*!< Include */
2339 
2340 /* Bit 17 : Include or exclude channel 17 */
2341 #define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
2342 #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
2343 #define DPPIC_CHG_CH17_Excluded (0UL) /*!< Exclude */
2344 #define DPPIC_CHG_CH17_Included (1UL) /*!< Include */
2345 
2346 /* Bit 16 : Include or exclude channel 16 */
2347 #define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
2348 #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
2349 #define DPPIC_CHG_CH16_Excluded (0UL) /*!< Exclude */
2350 #define DPPIC_CHG_CH16_Included (1UL) /*!< Include */
2351 
2352 /* Bit 15 : Include or exclude channel 15 */
2353 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
2354 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
2355 #define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */
2356 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
2357 
2358 /* Bit 14 : Include or exclude channel 14 */
2359 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
2360 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
2361 #define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */
2362 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
2363 
2364 /* Bit 13 : Include or exclude channel 13 */
2365 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
2366 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
2367 #define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */
2368 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
2369 
2370 /* Bit 12 : Include or exclude channel 12 */
2371 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
2372 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
2373 #define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */
2374 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
2375 
2376 /* Bit 11 : Include or exclude channel 11 */
2377 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
2378 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
2379 #define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */
2380 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
2381 
2382 /* Bit 10 : Include or exclude channel 10 */
2383 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
2384 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
2385 #define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */
2386 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
2387 
2388 /* Bit 9 : Include or exclude channel 9 */
2389 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
2390 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
2391 #define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */
2392 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
2393 
2394 /* Bit 8 : Include or exclude channel 8 */
2395 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
2396 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
2397 #define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */
2398 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
2399 
2400 /* Bit 7 : Include or exclude channel 7 */
2401 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
2402 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
2403 #define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */
2404 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
2405 
2406 /* Bit 6 : Include or exclude channel 6 */
2407 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
2408 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
2409 #define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */
2410 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
2411 
2412 /* Bit 5 : Include or exclude channel 5 */
2413 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
2414 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
2415 #define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */
2416 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
2417 
2418 /* Bit 4 : Include or exclude channel 4 */
2419 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
2420 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
2421 #define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */
2422 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
2423 
2424 /* Bit 3 : Include or exclude channel 3 */
2425 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
2426 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
2427 #define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */
2428 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
2429 
2430 /* Bit 2 : Include or exclude channel 2 */
2431 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
2432 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
2433 #define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */
2434 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
2435 
2436 /* Bit 1 : Include or exclude channel 1 */
2437 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
2438 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
2439 #define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */
2440 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
2441 
2442 /* Bit 0 : Include or exclude channel 0 */
2443 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
2444 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
2445 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
2446 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
2447 
2448 
2449 /* Peripheral: ECB */
2450 /* Description: AES ECB Mode Encryption */
2451 
2452 /* Register: ECB_TASKS_STARTECB */
2453 /* Description: Start ECB block encrypt */
2454 
2455 /* Bit 0 : Start ECB block encrypt */
2456 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
2457 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
2458 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
2459 
2460 /* Register: ECB_TASKS_STOPECB */
2461 /* Description: Abort a possible executing ECB operation */
2462 
2463 /* Bit 0 : Abort a possible executing ECB operation */
2464 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
2465 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
2466 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
2467 
2468 /* Register: ECB_SUBSCRIBE_STARTECB */
2469 /* Description: Subscribe configuration for task STARTECB */
2470 
2471 /* Bit 31 :   */
2472 #define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL) /*!< Position of EN field. */
2473 #define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos) /*!< Bit mask of EN field. */
2474 #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */
2475 #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */
2476 
2477 /* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */
2478 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2479 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2480 
2481 /* Register: ECB_SUBSCRIBE_STOPECB */
2482 /* Description: Subscribe configuration for task STOPECB */
2483 
2484 /* Bit 31 :   */
2485 #define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL) /*!< Position of EN field. */
2486 #define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos) /*!< Bit mask of EN field. */
2487 #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */
2488 #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */
2489 
2490 /* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */
2491 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2492 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2493 
2494 /* Register: ECB_EVENTS_ENDECB */
2495 /* Description: ECB block encrypt complete */
2496 
2497 /* Bit 0 : ECB block encrypt complete */
2498 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
2499 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
2500 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
2501 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
2502 
2503 /* Register: ECB_EVENTS_ERRORECB */
2504 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
2505 
2506 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
2507 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
2508 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
2509 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
2510 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
2511 
2512 /* Register: ECB_PUBLISH_ENDECB */
2513 /* Description: Publish configuration for event ENDECB */
2514 
2515 /* Bit 31 :   */
2516 #define ECB_PUBLISH_ENDECB_EN_Pos (31UL) /*!< Position of EN field. */
2517 #define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos) /*!< Bit mask of EN field. */
2518 #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */
2519 #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */
2520 
2521 /* Bits 7..0 : DPPI channel that event ENDECB will publish to. */
2522 #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2523 #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2524 
2525 /* Register: ECB_PUBLISH_ERRORECB */
2526 /* Description: Publish configuration for event ERRORECB */
2527 
2528 /* Bit 31 :   */
2529 #define ECB_PUBLISH_ERRORECB_EN_Pos (31UL) /*!< Position of EN field. */
2530 #define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos) /*!< Bit mask of EN field. */
2531 #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */
2532 #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */
2533 
2534 /* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */
2535 #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2536 #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2537 
2538 /* Register: ECB_INTENSET */
2539 /* Description: Enable interrupt */
2540 
2541 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
2542 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
2543 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
2544 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
2545 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
2546 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
2547 
2548 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
2549 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
2550 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
2551 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
2552 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
2553 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
2554 
2555 /* Register: ECB_INTENCLR */
2556 /* Description: Disable interrupt */
2557 
2558 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
2559 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
2560 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
2561 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
2562 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
2563 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
2564 
2565 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
2566 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
2567 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
2568 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
2569 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
2570 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
2571 
2572 /* Register: ECB_ECBDATAPTR */
2573 /* Description: ECB block encrypt memory pointers */
2574 
2575 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
2576 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
2577 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
2578 
2579 
2580 /* Peripheral: EGU */
2581 /* Description: Event generator unit */
2582 
2583 /* Register: EGU_TASKS_TRIGGER */
2584 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
2585 
2586 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
2587 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
2588 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
2589 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
2590 
2591 /* Register: EGU_SUBSCRIBE_TRIGGER */
2592 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
2593 
2594 /* Bit 31 :   */
2595 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
2596 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
2597 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
2598 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
2599 
2600 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
2601 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2602 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2603 
2604 /* Register: EGU_EVENTS_TRIGGERED */
2605 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
2606 
2607 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
2608 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
2609 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
2610 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
2611 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
2612 
2613 /* Register: EGU_PUBLISH_TRIGGERED */
2614 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
2615 
2616 /* Bit 31 :   */
2617 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
2618 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
2619 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
2620 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
2621 
2622 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */
2623 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2624 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2625 
2626 /* Register: EGU_INTEN */
2627 /* Description: Enable or disable interrupt */
2628 
2629 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
2630 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2631 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2632 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
2633 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
2634 
2635 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
2636 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2637 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2638 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
2639 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
2640 
2641 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
2642 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2643 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2644 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
2645 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
2646 
2647 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
2648 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2649 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2650 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
2651 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
2652 
2653 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
2654 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2655 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2656 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
2657 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
2658 
2659 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
2660 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2661 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2662 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
2663 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
2664 
2665 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
2666 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2667 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2668 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
2669 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
2670 
2671 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
2672 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2673 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2674 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
2675 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
2676 
2677 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
2678 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2679 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2680 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
2681 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
2682 
2683 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
2684 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2685 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2686 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
2687 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
2688 
2689 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
2690 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2691 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2692 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
2693 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
2694 
2695 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
2696 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2697 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2698 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
2699 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
2700 
2701 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
2702 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2703 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2704 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
2705 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
2706 
2707 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
2708 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2709 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2710 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
2711 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
2712 
2713 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
2714 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2715 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2716 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
2717 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
2718 
2719 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
2720 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2721 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2722 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
2723 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
2724 
2725 /* Register: EGU_INTENSET */
2726 /* Description: Enable interrupt */
2727 
2728 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
2729 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2730 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2731 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
2732 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
2733 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
2734 
2735 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
2736 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2737 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2738 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
2739 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
2740 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
2741 
2742 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
2743 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2744 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2745 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
2746 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
2747 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
2748 
2749 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
2750 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2751 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2752 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
2753 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
2754 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
2755 
2756 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
2757 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2758 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2759 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
2760 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
2761 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
2762 
2763 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
2764 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2765 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2766 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
2767 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
2768 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
2769 
2770 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
2771 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2772 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2773 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
2774 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
2775 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
2776 
2777 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
2778 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2779 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2780 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
2781 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
2782 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
2783 
2784 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
2785 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2786 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2787 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
2788 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
2789 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
2790 
2791 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
2792 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2793 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2794 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
2795 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
2796 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
2797 
2798 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
2799 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2800 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2801 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
2802 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
2803 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
2804 
2805 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
2806 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2807 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2808 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
2809 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
2810 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
2811 
2812 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
2813 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2814 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2815 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
2816 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
2817 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
2818 
2819 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
2820 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2821 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2822 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
2823 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
2824 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
2825 
2826 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
2827 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2828 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2829 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
2830 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
2831 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
2832 
2833 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
2834 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2835 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2836 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
2837 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2838 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
2839 
2840 /* Register: EGU_INTENCLR */
2841 /* Description: Disable interrupt */
2842 
2843 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
2844 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2845 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2846 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
2847 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
2848 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
2849 
2850 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
2851 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2852 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2853 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
2854 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
2855 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
2856 
2857 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
2858 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2859 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2860 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
2861 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
2862 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
2863 
2864 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
2865 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2866 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2867 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
2868 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
2869 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
2870 
2871 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
2872 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2873 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2874 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
2875 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
2876 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
2877 
2878 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
2879 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2880 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2881 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
2882 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
2883 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
2884 
2885 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
2886 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2887 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2888 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
2889 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
2890 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
2891 
2892 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
2893 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2894 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2895 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
2896 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
2897 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
2898 
2899 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
2900 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2901 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2902 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
2903 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
2904 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
2905 
2906 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
2907 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2908 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2909 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
2910 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
2911 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
2912 
2913 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
2914 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2915 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2916 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
2917 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
2918 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
2919 
2920 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
2921 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2922 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2923 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
2924 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
2925 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
2926 
2927 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
2928 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2929 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2930 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
2931 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
2932 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
2933 
2934 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
2935 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2936 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2937 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
2938 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
2939 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
2940 
2941 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
2942 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2943 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2944 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
2945 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
2946 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
2947 
2948 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
2949 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2950 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2951 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
2952 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2953 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
2954 
2955 
2956 /* Peripheral: FICR */
2957 /* Description: Factory Information Configuration Registers */
2958 
2959 /* Register: FICR_INFO_CONFIGID */
2960 /* Description: Configuration identifier */
2961 
2962 /* Bits 15..0 : Identification number for the HW */
2963 #define FICR_INFO_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
2964 #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
2965 
2966 /* Register: FICR_INFO_DEVICEID */
2967 /* Description: Description collection: Device identifier */
2968 
2969 /* Bits 31..0 : 64 bit unique device identifier */
2970 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
2971 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
2972 
2973 /* Register: FICR_INFO_PART */
2974 /* Description: Part code */
2975 
2976 /* Bits 31..0 : Part code */
2977 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
2978 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
2979 #define FICR_INFO_PART_PART_N5340 (0x5340UL) /*!< nRF5340 */
2980 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2981 
2982 /* Register: FICR_INFO_VARIANT */
2983 /* Description: Part Variant, Hardware version and Production configuration */
2984 
2985 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
2986 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
2987 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
2988 #define FICR_INFO_VARIANT_VARIANT_CLAA (0x434C4141UL) /*!< CLAA */
2989 #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */
2990 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2991 
2992 /* Register: FICR_INFO_PACKAGE */
2993 /* Description: Package option */
2994 
2995 /* Bits 31..0 : Package option */
2996 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
2997 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
2998 #define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */
2999 #define FICR_INFO_PACKAGE_PACKAGE_CL (0x2005UL) /*!< CLxx - WLCSP */
3000 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3001 
3002 /* Register: FICR_INFO_RAM */
3003 /* Description: RAM variant */
3004 
3005 /* Bits 31..0 : RAM variant */
3006 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
3007 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
3008 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
3009 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
3010 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
3011 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
3012 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
3013 #define FICR_INFO_RAM_RAM_K512 (0x200UL) /*!< 512 kByte RAM */
3014 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3015 
3016 /* Register: FICR_INFO_FLASH */
3017 /* Description: Flash variant */
3018 
3019 /* Bits 31..0 : Flash variant */
3020 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
3021 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
3022 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
3023 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
3024 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
3025 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
3026 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
3027 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3028 
3029 /* Register: FICR_INFO_CODEPAGESIZE */
3030 /* Description: Code memory page size in bytes */
3031 
3032 /* Bits 31..0 : Code memory page size in bytes */
3033 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
3034 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
3035 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K2048 (0x800UL) /*!< 2 kByte */
3036 
3037 /* Register: FICR_INFO_CODESIZE */
3038 /* Description: Code memory size */
3039 
3040 /* Bits 31..0 : Code memory size in number of pages */
3041 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
3042 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
3043 #define FICR_INFO_CODESIZE_CODESIZE_P128 (128UL) /*!< 128 pages */
3044 
3045 /* Register: FICR_INFO_DEVICETYPE */
3046 /* Description: Device type */
3047 
3048 /* Bits 31..0 : Device type */
3049 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
3050 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
3051 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */
3052 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
3053 
3054 /* Register: FICR_ER */
3055 /* Description: Description collection: Encryption Root, word n */
3056 
3057 /* Bits 31..0 : Encryption Root, word n */
3058 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
3059 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
3060 
3061 /* Register: FICR_IR */
3062 /* Description: Description collection: Identity Root, word n */
3063 
3064 /* Bits 31..0 : Identity Root, word n */
3065 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
3066 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
3067 
3068 /* Register: FICR_DEVICEADDRTYPE */
3069 /* Description: Device address type */
3070 
3071 /* Bit 0 : Device address type */
3072 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
3073 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
3074 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
3075 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
3076 
3077 /* Register: FICR_DEVICEADDR */
3078 /* Description: Description collection: Device address n */
3079 
3080 /* Bits 31..0 : 48 bit device address */
3081 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
3082 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
3083 
3084 /* Register: FICR_TRIMCNF_ADDR */
3085 /* Description: Description cluster: Address */
3086 
3087 /* Bits 31..0 : Address */
3088 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
3089 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
3090 
3091 /* Register: FICR_TRIMCNF_DATA */
3092 /* Description: Description cluster: Data */
3093 
3094 /* Bits 31..0 : Data */
3095 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
3096 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
3097 
3098 
3099 /* Peripheral: GPIOTE */
3100 /* Description: GPIO Tasks and Events */
3101 
3102 /* Register: GPIOTE_TASKS_OUT */
3103 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3104 
3105 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3106 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
3107 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
3108 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
3109 
3110 /* Register: GPIOTE_TASKS_SET */
3111 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3112 
3113 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3114 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
3115 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
3116 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
3117 
3118 /* Register: GPIOTE_TASKS_CLR */
3119 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3120 
3121 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3122 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
3123 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
3124 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
3125 
3126 /* Register: GPIOTE_SUBSCRIBE_OUT */
3127 /* Description: Description collection: Subscribe configuration for task OUT[n] */
3128 
3129 /* Bit 31 :   */
3130 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
3131 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
3132 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
3133 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
3134 
3135 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
3136 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3137 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3138 
3139 /* Register: GPIOTE_SUBSCRIBE_SET */
3140 /* Description: Description collection: Subscribe configuration for task SET[n] */
3141 
3142 /* Bit 31 :   */
3143 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
3144 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
3145 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
3146 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
3147 
3148 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
3149 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3150 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3151 
3152 /* Register: GPIOTE_SUBSCRIBE_CLR */
3153 /* Description: Description collection: Subscribe configuration for task CLR[n] */
3154 
3155 /* Bit 31 :   */
3156 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
3157 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
3158 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
3159 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
3160 
3161 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
3162 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3163 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3164 
3165 /* Register: GPIOTE_EVENTS_IN */
3166 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
3167 
3168 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
3169 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
3170 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
3171 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
3172 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
3173 
3174 /* Register: GPIOTE_EVENTS_PORT */
3175 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3176 
3177 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3178 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
3179 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
3180 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
3181 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
3182 
3183 /* Register: GPIOTE_PUBLISH_IN */
3184 /* Description: Description collection: Publish configuration for event IN[n] */
3185 
3186 /* Bit 31 :   */
3187 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
3188 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
3189 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
3190 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
3191 
3192 /* Bits 7..0 : DPPI channel that event IN[n] will publish to. */
3193 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3194 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3195 
3196 /* Register: GPIOTE_PUBLISH_PORT */
3197 /* Description: Publish configuration for event PORT */
3198 
3199 /* Bit 31 :   */
3200 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
3201 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
3202 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
3203 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
3204 
3205 /* Bits 7..0 : DPPI channel that event PORT will publish to. */
3206 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3207 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3208 
3209 /* Register: GPIOTE_INTENSET */
3210 /* Description: Enable interrupt */
3211 
3212 /* Bit 31 : Write '1' to enable interrupt for event PORT */
3213 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
3214 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
3215 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
3216 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
3217 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
3218 
3219 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
3220 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
3221 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
3222 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
3223 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
3224 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
3225 
3226 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
3227 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
3228 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
3229 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
3230 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
3231 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
3232 
3233 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
3234 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
3235 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
3236 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
3237 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
3238 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
3239 
3240 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
3241 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
3242 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
3243 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
3244 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
3245 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
3246 
3247 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
3248 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
3249 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
3250 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
3251 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
3252 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
3253 
3254 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
3255 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
3256 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
3257 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
3258 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
3259 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
3260 
3261 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
3262 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
3263 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
3264 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
3265 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
3266 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
3267 
3268 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
3269 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
3270 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
3271 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
3272 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
3273 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
3274 
3275 /* Register: GPIOTE_INTENCLR */
3276 /* Description: Disable interrupt */
3277 
3278 /* Bit 31 : Write '1' to disable interrupt for event PORT */
3279 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
3280 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
3281 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
3282 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
3283 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
3284 
3285 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
3286 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
3287 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
3288 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
3289 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
3290 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
3291 
3292 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
3293 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
3294 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
3295 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
3296 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
3297 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
3298 
3299 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
3300 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
3301 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
3302 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
3303 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
3304 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
3305 
3306 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
3307 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
3308 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
3309 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
3310 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
3311 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
3312 
3313 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
3314 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
3315 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
3316 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
3317 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
3318 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
3319 
3320 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
3321 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
3322 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
3323 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
3324 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
3325 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
3326 
3327 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
3328 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
3329 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
3330 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
3331 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
3332 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
3333 
3334 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
3335 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
3336 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
3337 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
3338 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
3339 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
3340 
3341 /* Register: GPIOTE_LATENCY */
3342 /* Description: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */
3343 
3344 /* Bit 0 : Latency setting */
3345 #define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */
3346 #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */
3347 #define GPIOTE_LATENCY_LATENCY_LowPower (0UL) /*!< Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section */
3348 #define GPIOTE_LATENCY_LATENCY_LowLatency (1UL) /*!< Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section */
3349 
3350 /* Register: GPIOTE_CONFIG */
3351 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
3352 
3353 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
3354 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
3355 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
3356 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
3357 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
3358 
3359 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
3360 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
3361 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
3362 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
3363 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
3364 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
3365 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
3366 
3367 /* Bit 13 : Port number */
3368 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
3369 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
3370 
3371 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
3372 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
3373 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
3374 
3375 /* Bits 1..0 : Mode */
3376 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
3377 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
3378 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
3379 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
3380 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
3381 
3382 
3383 /* Peripheral: IPC */
3384 /* Description: Interprocessor communication */
3385 
3386 /* Register: IPC_TASKS_SEND */
3387 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
3388 
3389 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
3390 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
3391 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
3392 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
3393 
3394 /* Register: IPC_SUBSCRIBE_SEND */
3395 /* Description: Description collection: Subscribe configuration for task SEND[n] */
3396 
3397 /* Bit 31 :   */
3398 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
3399 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
3400 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
3401 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
3402 
3403 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
3404 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3405 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3406 
3407 /* Register: IPC_EVENTS_RECEIVE */
3408 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
3409 
3410 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
3411 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
3412 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
3413 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
3414 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
3415 
3416 /* Register: IPC_PUBLISH_RECEIVE */
3417 /* Description: Description collection: Publish configuration for event RECEIVE[n] */
3418 
3419 /* Bit 31 :   */
3420 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
3421 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
3422 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
3423 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
3424 
3425 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to. */
3426 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3427 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3428 
3429 /* Register: IPC_INTEN */
3430 /* Description: Enable or disable interrupt */
3431 
3432 /* Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
3433 #define IPC_INTEN_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
3434 #define IPC_INTEN_RECEIVE15_Msk (0x1UL << IPC_INTEN_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
3435 #define IPC_INTEN_RECEIVE15_Disabled (0UL) /*!< Disable */
3436 #define IPC_INTEN_RECEIVE15_Enabled (1UL) /*!< Enable */
3437 
3438 /* Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
3439 #define IPC_INTEN_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
3440 #define IPC_INTEN_RECEIVE14_Msk (0x1UL << IPC_INTEN_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
3441 #define IPC_INTEN_RECEIVE14_Disabled (0UL) /*!< Disable */
3442 #define IPC_INTEN_RECEIVE14_Enabled (1UL) /*!< Enable */
3443 
3444 /* Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
3445 #define IPC_INTEN_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
3446 #define IPC_INTEN_RECEIVE13_Msk (0x1UL << IPC_INTEN_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
3447 #define IPC_INTEN_RECEIVE13_Disabled (0UL) /*!< Disable */
3448 #define IPC_INTEN_RECEIVE13_Enabled (1UL) /*!< Enable */
3449 
3450 /* Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
3451 #define IPC_INTEN_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
3452 #define IPC_INTEN_RECEIVE12_Msk (0x1UL << IPC_INTEN_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
3453 #define IPC_INTEN_RECEIVE12_Disabled (0UL) /*!< Disable */
3454 #define IPC_INTEN_RECEIVE12_Enabled (1UL) /*!< Enable */
3455 
3456 /* Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
3457 #define IPC_INTEN_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
3458 #define IPC_INTEN_RECEIVE11_Msk (0x1UL << IPC_INTEN_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
3459 #define IPC_INTEN_RECEIVE11_Disabled (0UL) /*!< Disable */
3460 #define IPC_INTEN_RECEIVE11_Enabled (1UL) /*!< Enable */
3461 
3462 /* Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
3463 #define IPC_INTEN_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
3464 #define IPC_INTEN_RECEIVE10_Msk (0x1UL << IPC_INTEN_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
3465 #define IPC_INTEN_RECEIVE10_Disabled (0UL) /*!< Disable */
3466 #define IPC_INTEN_RECEIVE10_Enabled (1UL) /*!< Enable */
3467 
3468 /* Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
3469 #define IPC_INTEN_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
3470 #define IPC_INTEN_RECEIVE9_Msk (0x1UL << IPC_INTEN_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
3471 #define IPC_INTEN_RECEIVE9_Disabled (0UL) /*!< Disable */
3472 #define IPC_INTEN_RECEIVE9_Enabled (1UL) /*!< Enable */
3473 
3474 /* Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
3475 #define IPC_INTEN_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
3476 #define IPC_INTEN_RECEIVE8_Msk (0x1UL << IPC_INTEN_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
3477 #define IPC_INTEN_RECEIVE8_Disabled (0UL) /*!< Disable */
3478 #define IPC_INTEN_RECEIVE8_Enabled (1UL) /*!< Enable */
3479 
3480 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
3481 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
3482 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
3483 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
3484 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
3485 
3486 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
3487 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
3488 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
3489 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
3490 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
3491 
3492 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
3493 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
3494 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
3495 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
3496 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
3497 
3498 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
3499 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
3500 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
3501 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
3502 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
3503 
3504 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
3505 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
3506 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
3507 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
3508 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
3509 
3510 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
3511 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
3512 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
3513 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
3514 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
3515 
3516 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
3517 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
3518 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
3519 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
3520 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
3521 
3522 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
3523 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
3524 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
3525 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
3526 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
3527 
3528 /* Register: IPC_INTENSET */
3529 /* Description: Enable interrupt */
3530 
3531 /* Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
3532 #define IPC_INTENSET_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
3533 #define IPC_INTENSET_RECEIVE15_Msk (0x1UL << IPC_INTENSET_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
3534 #define IPC_INTENSET_RECEIVE15_Disabled (0UL) /*!< Read: Disabled */
3535 #define IPC_INTENSET_RECEIVE15_Enabled (1UL) /*!< Read: Enabled */
3536 #define IPC_INTENSET_RECEIVE15_Set (1UL) /*!< Enable */
3537 
3538 /* Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
3539 #define IPC_INTENSET_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
3540 #define IPC_INTENSET_RECEIVE14_Msk (0x1UL << IPC_INTENSET_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
3541 #define IPC_INTENSET_RECEIVE14_Disabled (0UL) /*!< Read: Disabled */
3542 #define IPC_INTENSET_RECEIVE14_Enabled (1UL) /*!< Read: Enabled */
3543 #define IPC_INTENSET_RECEIVE14_Set (1UL) /*!< Enable */
3544 
3545 /* Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
3546 #define IPC_INTENSET_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
3547 #define IPC_INTENSET_RECEIVE13_Msk (0x1UL << IPC_INTENSET_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
3548 #define IPC_INTENSET_RECEIVE13_Disabled (0UL) /*!< Read: Disabled */
3549 #define IPC_INTENSET_RECEIVE13_Enabled (1UL) /*!< Read: Enabled */
3550 #define IPC_INTENSET_RECEIVE13_Set (1UL) /*!< Enable */
3551 
3552 /* Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
3553 #define IPC_INTENSET_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
3554 #define IPC_INTENSET_RECEIVE12_Msk (0x1UL << IPC_INTENSET_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
3555 #define IPC_INTENSET_RECEIVE12_Disabled (0UL) /*!< Read: Disabled */
3556 #define IPC_INTENSET_RECEIVE12_Enabled (1UL) /*!< Read: Enabled */
3557 #define IPC_INTENSET_RECEIVE12_Set (1UL) /*!< Enable */
3558 
3559 /* Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
3560 #define IPC_INTENSET_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
3561 #define IPC_INTENSET_RECEIVE11_Msk (0x1UL << IPC_INTENSET_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
3562 #define IPC_INTENSET_RECEIVE11_Disabled (0UL) /*!< Read: Disabled */
3563 #define IPC_INTENSET_RECEIVE11_Enabled (1UL) /*!< Read: Enabled */
3564 #define IPC_INTENSET_RECEIVE11_Set (1UL) /*!< Enable */
3565 
3566 /* Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
3567 #define IPC_INTENSET_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
3568 #define IPC_INTENSET_RECEIVE10_Msk (0x1UL << IPC_INTENSET_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
3569 #define IPC_INTENSET_RECEIVE10_Disabled (0UL) /*!< Read: Disabled */
3570 #define IPC_INTENSET_RECEIVE10_Enabled (1UL) /*!< Read: Enabled */
3571 #define IPC_INTENSET_RECEIVE10_Set (1UL) /*!< Enable */
3572 
3573 /* Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
3574 #define IPC_INTENSET_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
3575 #define IPC_INTENSET_RECEIVE9_Msk (0x1UL << IPC_INTENSET_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
3576 #define IPC_INTENSET_RECEIVE9_Disabled (0UL) /*!< Read: Disabled */
3577 #define IPC_INTENSET_RECEIVE9_Enabled (1UL) /*!< Read: Enabled */
3578 #define IPC_INTENSET_RECEIVE9_Set (1UL) /*!< Enable */
3579 
3580 /* Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
3581 #define IPC_INTENSET_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
3582 #define IPC_INTENSET_RECEIVE8_Msk (0x1UL << IPC_INTENSET_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
3583 #define IPC_INTENSET_RECEIVE8_Disabled (0UL) /*!< Read: Disabled */
3584 #define IPC_INTENSET_RECEIVE8_Enabled (1UL) /*!< Read: Enabled */
3585 #define IPC_INTENSET_RECEIVE8_Set (1UL) /*!< Enable */
3586 
3587 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
3588 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
3589 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
3590 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
3591 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
3592 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
3593 
3594 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
3595 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
3596 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
3597 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
3598 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
3599 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
3600 
3601 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
3602 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
3603 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
3604 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
3605 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
3606 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
3607 
3608 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
3609 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
3610 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
3611 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
3612 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
3613 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
3614 
3615 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
3616 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
3617 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
3618 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
3619 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
3620 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
3621 
3622 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
3623 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
3624 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
3625 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
3626 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
3627 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
3628 
3629 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
3630 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
3631 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
3632 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
3633 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
3634 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
3635 
3636 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
3637 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
3638 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
3639 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
3640 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
3641 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
3642 
3643 /* Register: IPC_INTENCLR */
3644 /* Description: Disable interrupt */
3645 
3646 /* Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
3647 #define IPC_INTENCLR_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
3648 #define IPC_INTENCLR_RECEIVE15_Msk (0x1UL << IPC_INTENCLR_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
3649 #define IPC_INTENCLR_RECEIVE15_Disabled (0UL) /*!< Read: Disabled */
3650 #define IPC_INTENCLR_RECEIVE15_Enabled (1UL) /*!< Read: Enabled */
3651 #define IPC_INTENCLR_RECEIVE15_Clear (1UL) /*!< Disable */
3652 
3653 /* Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
3654 #define IPC_INTENCLR_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
3655 #define IPC_INTENCLR_RECEIVE14_Msk (0x1UL << IPC_INTENCLR_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
3656 #define IPC_INTENCLR_RECEIVE14_Disabled (0UL) /*!< Read: Disabled */
3657 #define IPC_INTENCLR_RECEIVE14_Enabled (1UL) /*!< Read: Enabled */
3658 #define IPC_INTENCLR_RECEIVE14_Clear (1UL) /*!< Disable */
3659 
3660 /* Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
3661 #define IPC_INTENCLR_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
3662 #define IPC_INTENCLR_RECEIVE13_Msk (0x1UL << IPC_INTENCLR_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
3663 #define IPC_INTENCLR_RECEIVE13_Disabled (0UL) /*!< Read: Disabled */
3664 #define IPC_INTENCLR_RECEIVE13_Enabled (1UL) /*!< Read: Enabled */
3665 #define IPC_INTENCLR_RECEIVE13_Clear (1UL) /*!< Disable */
3666 
3667 /* Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
3668 #define IPC_INTENCLR_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
3669 #define IPC_INTENCLR_RECEIVE12_Msk (0x1UL << IPC_INTENCLR_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
3670 #define IPC_INTENCLR_RECEIVE12_Disabled (0UL) /*!< Read: Disabled */
3671 #define IPC_INTENCLR_RECEIVE12_Enabled (1UL) /*!< Read: Enabled */
3672 #define IPC_INTENCLR_RECEIVE12_Clear (1UL) /*!< Disable */
3673 
3674 /* Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
3675 #define IPC_INTENCLR_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
3676 #define IPC_INTENCLR_RECEIVE11_Msk (0x1UL << IPC_INTENCLR_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
3677 #define IPC_INTENCLR_RECEIVE11_Disabled (0UL) /*!< Read: Disabled */
3678 #define IPC_INTENCLR_RECEIVE11_Enabled (1UL) /*!< Read: Enabled */
3679 #define IPC_INTENCLR_RECEIVE11_Clear (1UL) /*!< Disable */
3680 
3681 /* Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
3682 #define IPC_INTENCLR_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
3683 #define IPC_INTENCLR_RECEIVE10_Msk (0x1UL << IPC_INTENCLR_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
3684 #define IPC_INTENCLR_RECEIVE10_Disabled (0UL) /*!< Read: Disabled */
3685 #define IPC_INTENCLR_RECEIVE10_Enabled (1UL) /*!< Read: Enabled */
3686 #define IPC_INTENCLR_RECEIVE10_Clear (1UL) /*!< Disable */
3687 
3688 /* Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
3689 #define IPC_INTENCLR_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
3690 #define IPC_INTENCLR_RECEIVE9_Msk (0x1UL << IPC_INTENCLR_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
3691 #define IPC_INTENCLR_RECEIVE9_Disabled (0UL) /*!< Read: Disabled */
3692 #define IPC_INTENCLR_RECEIVE9_Enabled (1UL) /*!< Read: Enabled */
3693 #define IPC_INTENCLR_RECEIVE9_Clear (1UL) /*!< Disable */
3694 
3695 /* Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
3696 #define IPC_INTENCLR_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
3697 #define IPC_INTENCLR_RECEIVE8_Msk (0x1UL << IPC_INTENCLR_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
3698 #define IPC_INTENCLR_RECEIVE8_Disabled (0UL) /*!< Read: Disabled */
3699 #define IPC_INTENCLR_RECEIVE8_Enabled (1UL) /*!< Read: Enabled */
3700 #define IPC_INTENCLR_RECEIVE8_Clear (1UL) /*!< Disable */
3701 
3702 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
3703 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
3704 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
3705 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
3706 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
3707 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
3708 
3709 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
3710 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
3711 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
3712 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
3713 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
3714 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
3715 
3716 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
3717 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
3718 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
3719 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
3720 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
3721 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
3722 
3723 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
3724 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
3725 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
3726 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
3727 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
3728 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
3729 
3730 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
3731 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
3732 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
3733 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
3734 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
3735 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
3736 
3737 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
3738 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
3739 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
3740 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
3741 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
3742 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
3743 
3744 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
3745 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
3746 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
3747 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
3748 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
3749 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
3750 
3751 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
3752 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
3753 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
3754 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
3755 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
3756 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
3757 
3758 /* Register: IPC_INTPEND */
3759 /* Description: Pending interrupts */
3760 
3761 /* Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
3762 #define IPC_INTPEND_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
3763 #define IPC_INTPEND_RECEIVE15_Msk (0x1UL << IPC_INTPEND_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
3764 #define IPC_INTPEND_RECEIVE15_NotPending (0UL) /*!< Read: Not pending */
3765 #define IPC_INTPEND_RECEIVE15_Pending (1UL) /*!< Read: Pending */
3766 
3767 /* Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
3768 #define IPC_INTPEND_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
3769 #define IPC_INTPEND_RECEIVE14_Msk (0x1UL << IPC_INTPEND_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
3770 #define IPC_INTPEND_RECEIVE14_NotPending (0UL) /*!< Read: Not pending */
3771 #define IPC_INTPEND_RECEIVE14_Pending (1UL) /*!< Read: Pending */
3772 
3773 /* Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
3774 #define IPC_INTPEND_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
3775 #define IPC_INTPEND_RECEIVE13_Msk (0x1UL << IPC_INTPEND_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
3776 #define IPC_INTPEND_RECEIVE13_NotPending (0UL) /*!< Read: Not pending */
3777 #define IPC_INTPEND_RECEIVE13_Pending (1UL) /*!< Read: Pending */
3778 
3779 /* Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
3780 #define IPC_INTPEND_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
3781 #define IPC_INTPEND_RECEIVE12_Msk (0x1UL << IPC_INTPEND_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
3782 #define IPC_INTPEND_RECEIVE12_NotPending (0UL) /*!< Read: Not pending */
3783 #define IPC_INTPEND_RECEIVE12_Pending (1UL) /*!< Read: Pending */
3784 
3785 /* Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
3786 #define IPC_INTPEND_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
3787 #define IPC_INTPEND_RECEIVE11_Msk (0x1UL << IPC_INTPEND_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
3788 #define IPC_INTPEND_RECEIVE11_NotPending (0UL) /*!< Read: Not pending */
3789 #define IPC_INTPEND_RECEIVE11_Pending (1UL) /*!< Read: Pending */
3790 
3791 /* Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
3792 #define IPC_INTPEND_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
3793 #define IPC_INTPEND_RECEIVE10_Msk (0x1UL << IPC_INTPEND_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
3794 #define IPC_INTPEND_RECEIVE10_NotPending (0UL) /*!< Read: Not pending */
3795 #define IPC_INTPEND_RECEIVE10_Pending (1UL) /*!< Read: Pending */
3796 
3797 /* Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
3798 #define IPC_INTPEND_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
3799 #define IPC_INTPEND_RECEIVE9_Msk (0x1UL << IPC_INTPEND_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
3800 #define IPC_INTPEND_RECEIVE9_NotPending (0UL) /*!< Read: Not pending */
3801 #define IPC_INTPEND_RECEIVE9_Pending (1UL) /*!< Read: Pending */
3802 
3803 /* Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
3804 #define IPC_INTPEND_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
3805 #define IPC_INTPEND_RECEIVE8_Msk (0x1UL << IPC_INTPEND_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
3806 #define IPC_INTPEND_RECEIVE8_NotPending (0UL) /*!< Read: Not pending */
3807 #define IPC_INTPEND_RECEIVE8_Pending (1UL) /*!< Read: Pending */
3808 
3809 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
3810 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
3811 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
3812 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
3813 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
3814 
3815 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
3816 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
3817 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
3818 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
3819 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
3820 
3821 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
3822 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
3823 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
3824 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
3825 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
3826 
3827 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
3828 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
3829 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
3830 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
3831 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
3832 
3833 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
3834 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
3835 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
3836 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
3837 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
3838 
3839 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
3840 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
3841 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
3842 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
3843 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
3844 
3845 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
3846 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
3847 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
3848 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
3849 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
3850 
3851 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
3852 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
3853 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
3854 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
3855 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
3856 
3857 /* Register: IPC_SEND_CNF */
3858 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */
3859 
3860 /* Bit 15 : Enable broadcasting on IPC channel 15 */
3861 #define IPC_SEND_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
3862 #define IPC_SEND_CNF_CHEN15_Msk (0x1UL << IPC_SEND_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
3863 #define IPC_SEND_CNF_CHEN15_Disable (0UL) /*!< Disable broadcast */
3864 #define IPC_SEND_CNF_CHEN15_Enable (1UL) /*!< Enable broadcast */
3865 
3866 /* Bit 14 : Enable broadcasting on IPC channel 14 */
3867 #define IPC_SEND_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
3868 #define IPC_SEND_CNF_CHEN14_Msk (0x1UL << IPC_SEND_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
3869 #define IPC_SEND_CNF_CHEN14_Disable (0UL) /*!< Disable broadcast */
3870 #define IPC_SEND_CNF_CHEN14_Enable (1UL) /*!< Enable broadcast */
3871 
3872 /* Bit 13 : Enable broadcasting on IPC channel 13 */
3873 #define IPC_SEND_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
3874 #define IPC_SEND_CNF_CHEN13_Msk (0x1UL << IPC_SEND_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
3875 #define IPC_SEND_CNF_CHEN13_Disable (0UL) /*!< Disable broadcast */
3876 #define IPC_SEND_CNF_CHEN13_Enable (1UL) /*!< Enable broadcast */
3877 
3878 /* Bit 12 : Enable broadcasting on IPC channel 12 */
3879 #define IPC_SEND_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
3880 #define IPC_SEND_CNF_CHEN12_Msk (0x1UL << IPC_SEND_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
3881 #define IPC_SEND_CNF_CHEN12_Disable (0UL) /*!< Disable broadcast */
3882 #define IPC_SEND_CNF_CHEN12_Enable (1UL) /*!< Enable broadcast */
3883 
3884 /* Bit 11 : Enable broadcasting on IPC channel 11 */
3885 #define IPC_SEND_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
3886 #define IPC_SEND_CNF_CHEN11_Msk (0x1UL << IPC_SEND_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
3887 #define IPC_SEND_CNF_CHEN11_Disable (0UL) /*!< Disable broadcast */
3888 #define IPC_SEND_CNF_CHEN11_Enable (1UL) /*!< Enable broadcast */
3889 
3890 /* Bit 10 : Enable broadcasting on IPC channel 10 */
3891 #define IPC_SEND_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
3892 #define IPC_SEND_CNF_CHEN10_Msk (0x1UL << IPC_SEND_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
3893 #define IPC_SEND_CNF_CHEN10_Disable (0UL) /*!< Disable broadcast */
3894 #define IPC_SEND_CNF_CHEN10_Enable (1UL) /*!< Enable broadcast */
3895 
3896 /* Bit 9 : Enable broadcasting on IPC channel 9 */
3897 #define IPC_SEND_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
3898 #define IPC_SEND_CNF_CHEN9_Msk (0x1UL << IPC_SEND_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
3899 #define IPC_SEND_CNF_CHEN9_Disable (0UL) /*!< Disable broadcast */
3900 #define IPC_SEND_CNF_CHEN9_Enable (1UL) /*!< Enable broadcast */
3901 
3902 /* Bit 8 : Enable broadcasting on IPC channel 8 */
3903 #define IPC_SEND_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
3904 #define IPC_SEND_CNF_CHEN8_Msk (0x1UL << IPC_SEND_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
3905 #define IPC_SEND_CNF_CHEN8_Disable (0UL) /*!< Disable broadcast */
3906 #define IPC_SEND_CNF_CHEN8_Enable (1UL) /*!< Enable broadcast */
3907 
3908 /* Bit 7 : Enable broadcasting on IPC channel 7 */
3909 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
3910 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
3911 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */
3912 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */
3913 
3914 /* Bit 6 : Enable broadcasting on IPC channel 6 */
3915 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
3916 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
3917 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */
3918 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */
3919 
3920 /* Bit 5 : Enable broadcasting on IPC channel 5 */
3921 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
3922 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
3923 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */
3924 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */
3925 
3926 /* Bit 4 : Enable broadcasting on IPC channel 4 */
3927 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
3928 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
3929 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */
3930 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */
3931 
3932 /* Bit 3 : Enable broadcasting on IPC channel 3 */
3933 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
3934 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
3935 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */
3936 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */
3937 
3938 /* Bit 2 : Enable broadcasting on IPC channel 2 */
3939 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
3940 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
3941 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */
3942 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */
3943 
3944 /* Bit 1 : Enable broadcasting on IPC channel 1 */
3945 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
3946 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
3947 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */
3948 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */
3949 
3950 /* Bit 0 : Enable broadcasting on IPC channel 0 */
3951 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
3952 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
3953 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */
3954 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */
3955 
3956 /* Register: IPC_RECEIVE_CNF */
3957 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
3958 
3959 /* Bit 15 : Enable subscription to IPC channel 15 */
3960 #define IPC_RECEIVE_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
3961 #define IPC_RECEIVE_CNF_CHEN15_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
3962 #define IPC_RECEIVE_CNF_CHEN15_Disable (0UL) /*!< Disable events */
3963 #define IPC_RECEIVE_CNF_CHEN15_Enable (1UL) /*!< Enable events */
3964 
3965 /* Bit 14 : Enable subscription to IPC channel 14 */
3966 #define IPC_RECEIVE_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
3967 #define IPC_RECEIVE_CNF_CHEN14_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
3968 #define IPC_RECEIVE_CNF_CHEN14_Disable (0UL) /*!< Disable events */
3969 #define IPC_RECEIVE_CNF_CHEN14_Enable (1UL) /*!< Enable events */
3970 
3971 /* Bit 13 : Enable subscription to IPC channel 13 */
3972 #define IPC_RECEIVE_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
3973 #define IPC_RECEIVE_CNF_CHEN13_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
3974 #define IPC_RECEIVE_CNF_CHEN13_Disable (0UL) /*!< Disable events */
3975 #define IPC_RECEIVE_CNF_CHEN13_Enable (1UL) /*!< Enable events */
3976 
3977 /* Bit 12 : Enable subscription to IPC channel 12 */
3978 #define IPC_RECEIVE_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
3979 #define IPC_RECEIVE_CNF_CHEN12_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
3980 #define IPC_RECEIVE_CNF_CHEN12_Disable (0UL) /*!< Disable events */
3981 #define IPC_RECEIVE_CNF_CHEN12_Enable (1UL) /*!< Enable events */
3982 
3983 /* Bit 11 : Enable subscription to IPC channel 11 */
3984 #define IPC_RECEIVE_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
3985 #define IPC_RECEIVE_CNF_CHEN11_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
3986 #define IPC_RECEIVE_CNF_CHEN11_Disable (0UL) /*!< Disable events */
3987 #define IPC_RECEIVE_CNF_CHEN11_Enable (1UL) /*!< Enable events */
3988 
3989 /* Bit 10 : Enable subscription to IPC channel 10 */
3990 #define IPC_RECEIVE_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
3991 #define IPC_RECEIVE_CNF_CHEN10_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
3992 #define IPC_RECEIVE_CNF_CHEN10_Disable (0UL) /*!< Disable events */
3993 #define IPC_RECEIVE_CNF_CHEN10_Enable (1UL) /*!< Enable events */
3994 
3995 /* Bit 9 : Enable subscription to IPC channel 9 */
3996 #define IPC_RECEIVE_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
3997 #define IPC_RECEIVE_CNF_CHEN9_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
3998 #define IPC_RECEIVE_CNF_CHEN9_Disable (0UL) /*!< Disable events */
3999 #define IPC_RECEIVE_CNF_CHEN9_Enable (1UL) /*!< Enable events */
4000 
4001 /* Bit 8 : Enable subscription to IPC channel 8 */
4002 #define IPC_RECEIVE_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
4003 #define IPC_RECEIVE_CNF_CHEN8_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
4004 #define IPC_RECEIVE_CNF_CHEN8_Disable (0UL) /*!< Disable events */
4005 #define IPC_RECEIVE_CNF_CHEN8_Enable (1UL) /*!< Enable events */
4006 
4007 /* Bit 7 : Enable subscription to IPC channel 7 */
4008 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
4009 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
4010 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */
4011 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */
4012 
4013 /* Bit 6 : Enable subscription to IPC channel 6 */
4014 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
4015 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
4016 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */
4017 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */
4018 
4019 /* Bit 5 : Enable subscription to IPC channel 5 */
4020 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
4021 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
4022 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */
4023 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */
4024 
4025 /* Bit 4 : Enable subscription to IPC channel 4 */
4026 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
4027 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
4028 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */
4029 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */
4030 
4031 /* Bit 3 : Enable subscription to IPC channel 3 */
4032 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
4033 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
4034 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */
4035 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */
4036 
4037 /* Bit 2 : Enable subscription to IPC channel 2 */
4038 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
4039 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
4040 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */
4041 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */
4042 
4043 /* Bit 1 : Enable subscription to IPC channel 1 */
4044 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
4045 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
4046 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */
4047 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */
4048 
4049 /* Bit 0 : Enable subscription to IPC channel 0 */
4050 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
4051 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
4052 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */
4053 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */
4054 
4055 /* Register: IPC_GPMEM */
4056 /* Description: Description collection: General purpose memory */
4057 
4058 /* Bits 31..0 : General purpose memory */
4059 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
4060 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
4061 
4062 
4063 /* Peripheral: NVMC */
4064 /* Description: Non-volatile memory controller */
4065 
4066 /* Register: NVMC_READY */
4067 /* Description: Ready flag */
4068 
4069 /* Bit 0 : NVMC is ready or busy */
4070 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4071 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4072 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
4073 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4074 
4075 /* Register: NVMC_READYNEXT */
4076 /* Description: Ready flag */
4077 
4078 /* Bit 0 : NVMC can accept a new write operation */
4079 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
4080 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
4081 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
4082 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
4083 
4084 /* Register: NVMC_CONFIG */
4085 /* Description: Configuration register */
4086 
4087 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4088 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4089 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4090 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4091 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
4092 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4093 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
4094 
4095 /* Register: NVMC_ERASEALL */
4096 /* Description: Register for erasing all non-volatile user memory */
4097 
4098 /* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */
4099 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
4100 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
4101 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
4102 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4103 
4104 /* Register: NVMC_ERASEPAGEPARTIALCFG */
4105 /* Description: Register for partial erase configuration */
4106 
4107 /* Bits 6..0 : Duration of the partial erase in milliseconds */
4108 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
4109 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
4110 
4111 /* Register: NVMC_ICACHECNF */
4112 /* Description: I-code cache configuration register */
4113 
4114 /* Bit 8 : Cache profiling enable */
4115 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
4116 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
4117 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4118 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4119 
4120 /* Bit 0 : Cache enable */
4121 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
4122 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
4123 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4124 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4125 
4126 /* Register: NVMC_IHIT */
4127 /* Description: I-code cache hit counter */
4128 
4129 /* Bits 31..0 : Number of cache hits Write zero to clear */
4130 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
4131 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
4132 
4133 /* Register: NVMC_IMISS */
4134 /* Description: I-code cache miss counter */
4135 
4136 /* Bits 31..0 : Number of cache misses Write zero to clear */
4137 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
4138 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
4139 
4140 
4141 /* Peripheral: GPIO */
4142 /* Description: GPIO Port 0 */
4143 
4144 /* Register: GPIO_OUT */
4145 /* Description: Write GPIO port */
4146 
4147 /* Bit 31 : Pin 31 */
4148 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4149 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4150 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
4151 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4152 
4153 /* Bit 30 : Pin 30 */
4154 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4155 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4156 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
4157 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4158 
4159 /* Bit 29 : Pin 29 */
4160 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4161 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4162 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
4163 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4164 
4165 /* Bit 28 : Pin 28 */
4166 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4167 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4168 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
4169 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4170 
4171 /* Bit 27 : Pin 27 */
4172 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4173 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4174 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
4175 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4176 
4177 /* Bit 26 : Pin 26 */
4178 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4179 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4180 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
4181 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4182 
4183 /* Bit 25 : Pin 25 */
4184 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4185 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4186 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
4187 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4188 
4189 /* Bit 24 : Pin 24 */
4190 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4191 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4192 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
4193 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4194 
4195 /* Bit 23 : Pin 23 */
4196 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4197 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4198 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
4199 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4200 
4201 /* Bit 22 : Pin 22 */
4202 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4203 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4204 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
4205 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4206 
4207 /* Bit 21 : Pin 21 */
4208 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4209 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4210 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
4211 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4212 
4213 /* Bit 20 : Pin 20 */
4214 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4215 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4216 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
4217 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4218 
4219 /* Bit 19 : Pin 19 */
4220 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4221 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4222 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
4223 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
4224 
4225 /* Bit 18 : Pin 18 */
4226 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4227 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4228 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
4229 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
4230 
4231 /* Bit 17 : Pin 17 */
4232 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4233 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4234 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
4235 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
4236 
4237 /* Bit 16 : Pin 16 */
4238 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4239 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4240 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
4241 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
4242 
4243 /* Bit 15 : Pin 15 */
4244 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4245 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4246 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
4247 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
4248 
4249 /* Bit 14 : Pin 14 */
4250 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4251 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4252 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
4253 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
4254 
4255 /* Bit 13 : Pin 13 */
4256 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4257 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4258 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
4259 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
4260 
4261 /* Bit 12 : Pin 12 */
4262 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4263 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4264 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
4265 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
4266 
4267 /* Bit 11 : Pin 11 */
4268 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4269 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4270 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
4271 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
4272 
4273 /* Bit 10 : Pin 10 */
4274 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4275 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4276 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
4277 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
4278 
4279 /* Bit 9 : Pin 9 */
4280 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4281 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4282 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
4283 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
4284 
4285 /* Bit 8 : Pin 8 */
4286 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4287 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4288 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
4289 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
4290 
4291 /* Bit 7 : Pin 7 */
4292 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4293 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4294 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
4295 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
4296 
4297 /* Bit 6 : Pin 6 */
4298 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4299 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4300 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
4301 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
4302 
4303 /* Bit 5 : Pin 5 */
4304 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4305 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4306 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
4307 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
4308 
4309 /* Bit 4 : Pin 4 */
4310 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4311 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4312 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
4313 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
4314 
4315 /* Bit 3 : Pin 3 */
4316 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4317 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4318 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
4319 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
4320 
4321 /* Bit 2 : Pin 2 */
4322 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4323 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4324 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
4325 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
4326 
4327 /* Bit 1 : Pin 1 */
4328 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4329 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4330 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
4331 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
4332 
4333 /* Bit 0 : Pin 0 */
4334 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4335 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4336 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
4337 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
4338 
4339 /* Register: GPIO_OUTSET */
4340 /* Description: Set individual bits in GPIO port */
4341 
4342 /* Bit 31 : Pin 31 */
4343 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4344 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4345 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
4346 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
4347 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4348 
4349 /* Bit 30 : Pin 30 */
4350 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4351 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4352 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
4353 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
4354 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4355 
4356 /* Bit 29 : Pin 29 */
4357 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4358 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4359 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
4360 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
4361 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4362 
4363 /* Bit 28 : Pin 28 */
4364 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4365 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4366 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
4367 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
4368 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4369 
4370 /* Bit 27 : Pin 27 */
4371 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4372 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4373 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
4374 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
4375 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4376 
4377 /* Bit 26 : Pin 26 */
4378 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4379 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4380 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
4381 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
4382 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4383 
4384 /* Bit 25 : Pin 25 */
4385 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4386 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4387 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
4388 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
4389 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4390 
4391 /* Bit 24 : Pin 24 */
4392 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4393 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4394 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
4395 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
4396 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4397 
4398 /* Bit 23 : Pin 23 */
4399 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4400 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4401 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
4402 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
4403 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4404 
4405 /* Bit 22 : Pin 22 */
4406 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4407 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4408 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
4409 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
4410 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4411 
4412 /* Bit 21 : Pin 21 */
4413 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4414 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4415 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
4416 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
4417 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4418 
4419 /* Bit 20 : Pin 20 */
4420 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4421 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4422 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
4423 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
4424 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4425 
4426 /* Bit 19 : Pin 19 */
4427 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4428 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4429 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
4430 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
4431 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4432 
4433 /* Bit 18 : Pin 18 */
4434 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4435 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4436 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
4437 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
4438 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4439 
4440 /* Bit 17 : Pin 17 */
4441 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4442 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4443 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
4444 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
4445 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4446 
4447 /* Bit 16 : Pin 16 */
4448 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4449 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4450 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
4451 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
4452 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4453 
4454 /* Bit 15 : Pin 15 */
4455 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4456 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4457 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
4458 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
4459 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4460 
4461 /* Bit 14 : Pin 14 */
4462 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4463 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4464 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
4465 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
4466 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4467 
4468 /* Bit 13 : Pin 13 */
4469 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4470 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4471 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
4472 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
4473 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4474 
4475 /* Bit 12 : Pin 12 */
4476 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4477 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4478 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
4479 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
4480 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4481 
4482 /* Bit 11 : Pin 11 */
4483 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4484 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4485 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
4486 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
4487 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4488 
4489 /* Bit 10 : Pin 10 */
4490 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4491 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4492 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
4493 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
4494 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4495 
4496 /* Bit 9 : Pin 9 */
4497 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4498 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4499 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
4500 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
4501 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4502 
4503 /* Bit 8 : Pin 8 */
4504 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4505 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4506 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
4507 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
4508 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4509 
4510 /* Bit 7 : Pin 7 */
4511 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4512 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4513 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
4514 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
4515 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4516 
4517 /* Bit 6 : Pin 6 */
4518 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4519 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4520 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
4521 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
4522 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4523 
4524 /* Bit 5 : Pin 5 */
4525 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4526 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4527 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
4528 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
4529 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4530 
4531 /* Bit 4 : Pin 4 */
4532 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4533 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4534 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
4535 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
4536 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4537 
4538 /* Bit 3 : Pin 3 */
4539 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4540 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4541 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
4542 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
4543 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4544 
4545 /* Bit 2 : Pin 2 */
4546 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4547 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4548 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
4549 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
4550 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4551 
4552 /* Bit 1 : Pin 1 */
4553 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4554 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4555 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
4556 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
4557 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4558 
4559 /* Bit 0 : Pin 0 */
4560 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4561 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4562 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
4563 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
4564 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
4565 
4566 /* Register: GPIO_OUTCLR */
4567 /* Description: Clear individual bits in GPIO port */
4568 
4569 /* Bit 31 : Pin 31 */
4570 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4571 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4572 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
4573 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
4574 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4575 
4576 /* Bit 30 : Pin 30 */
4577 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4578 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4579 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
4580 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
4581 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4582 
4583 /* Bit 29 : Pin 29 */
4584 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4585 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4586 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
4587 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
4588 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4589 
4590 /* Bit 28 : Pin 28 */
4591 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4592 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4593 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
4594 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
4595 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4596 
4597 /* Bit 27 : Pin 27 */
4598 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4599 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4600 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
4601 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
4602 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4603 
4604 /* Bit 26 : Pin 26 */
4605 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4606 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4607 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
4608 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
4609 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4610 
4611 /* Bit 25 : Pin 25 */
4612 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4613 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4614 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
4615 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
4616 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4617 
4618 /* Bit 24 : Pin 24 */
4619 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4620 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4621 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
4622 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
4623 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4624 
4625 /* Bit 23 : Pin 23 */
4626 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4627 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4628 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
4629 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
4630 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4631 
4632 /* Bit 22 : Pin 22 */
4633 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4634 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4635 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
4636 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
4637 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4638 
4639 /* Bit 21 : Pin 21 */
4640 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4641 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4642 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
4643 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
4644 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4645 
4646 /* Bit 20 : Pin 20 */
4647 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4648 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4649 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
4650 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
4651 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4652 
4653 /* Bit 19 : Pin 19 */
4654 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4655 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4656 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
4657 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
4658 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4659 
4660 /* Bit 18 : Pin 18 */
4661 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4662 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4663 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
4664 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
4665 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4666 
4667 /* Bit 17 : Pin 17 */
4668 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4669 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4670 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
4671 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
4672 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4673 
4674 /* Bit 16 : Pin 16 */
4675 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4676 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4677 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
4678 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
4679 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4680 
4681 /* Bit 15 : Pin 15 */
4682 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4683 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4684 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
4685 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
4686 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4687 
4688 /* Bit 14 : Pin 14 */
4689 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4690 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4691 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
4692 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
4693 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4694 
4695 /* Bit 13 : Pin 13 */
4696 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4697 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4698 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
4699 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
4700 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4701 
4702 /* Bit 12 : Pin 12 */
4703 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4704 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4705 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
4706 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
4707 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4708 
4709 /* Bit 11 : Pin 11 */
4710 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4711 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4712 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
4713 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
4714 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4715 
4716 /* Bit 10 : Pin 10 */
4717 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4718 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4719 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
4720 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
4721 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4722 
4723 /* Bit 9 : Pin 9 */
4724 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4725 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4726 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
4727 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
4728 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4729 
4730 /* Bit 8 : Pin 8 */
4731 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4732 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4733 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
4734 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
4735 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4736 
4737 /* Bit 7 : Pin 7 */
4738 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4739 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4740 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
4741 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
4742 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4743 
4744 /* Bit 6 : Pin 6 */
4745 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4746 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4747 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
4748 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
4749 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4750 
4751 /* Bit 5 : Pin 5 */
4752 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4753 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4754 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
4755 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
4756 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4757 
4758 /* Bit 4 : Pin 4 */
4759 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4760 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4761 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
4762 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
4763 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4764 
4765 /* Bit 3 : Pin 3 */
4766 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4767 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4768 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
4769 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
4770 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4771 
4772 /* Bit 2 : Pin 2 */
4773 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4774 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4775 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
4776 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
4777 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4778 
4779 /* Bit 1 : Pin 1 */
4780 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4781 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4782 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
4783 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
4784 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4785 
4786 /* Bit 0 : Pin 0 */
4787 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4788 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4789 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
4790 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
4791 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
4792 
4793 /* Register: GPIO_IN */
4794 /* Description: Read GPIO port */
4795 
4796 /* Bit 31 : Pin 31 */
4797 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4798 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4799 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
4800 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
4801 
4802 /* Bit 30 : Pin 30 */
4803 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4804 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4805 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
4806 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
4807 
4808 /* Bit 29 : Pin 29 */
4809 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4810 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4811 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
4812 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
4813 
4814 /* Bit 28 : Pin 28 */
4815 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4816 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4817 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
4818 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
4819 
4820 /* Bit 27 : Pin 27 */
4821 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4822 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4823 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
4824 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
4825 
4826 /* Bit 26 : Pin 26 */
4827 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4828 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4829 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
4830 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
4831 
4832 /* Bit 25 : Pin 25 */
4833 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4834 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4835 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
4836 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
4837 
4838 /* Bit 24 : Pin 24 */
4839 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4840 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4841 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
4842 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
4843 
4844 /* Bit 23 : Pin 23 */
4845 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4846 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4847 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
4848 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
4849 
4850 /* Bit 22 : Pin 22 */
4851 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4852 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4853 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
4854 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
4855 
4856 /* Bit 21 : Pin 21 */
4857 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4858 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4859 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
4860 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
4861 
4862 /* Bit 20 : Pin 20 */
4863 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4864 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4865 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
4866 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
4867 
4868 /* Bit 19 : Pin 19 */
4869 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4870 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4871 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
4872 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
4873 
4874 /* Bit 18 : Pin 18 */
4875 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4876 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4877 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
4878 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
4879 
4880 /* Bit 17 : Pin 17 */
4881 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4882 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4883 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
4884 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
4885 
4886 /* Bit 16 : Pin 16 */
4887 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4888 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4889 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
4890 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
4891 
4892 /* Bit 15 : Pin 15 */
4893 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4894 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4895 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
4896 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
4897 
4898 /* Bit 14 : Pin 14 */
4899 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4900 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4901 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
4902 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
4903 
4904 /* Bit 13 : Pin 13 */
4905 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4906 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4907 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
4908 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
4909 
4910 /* Bit 12 : Pin 12 */
4911 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4912 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4913 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
4914 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
4915 
4916 /* Bit 11 : Pin 11 */
4917 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4918 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4919 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
4920 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
4921 
4922 /* Bit 10 : Pin 10 */
4923 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4924 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4925 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
4926 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
4927 
4928 /* Bit 9 : Pin 9 */
4929 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4930 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4931 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
4932 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
4933 
4934 /* Bit 8 : Pin 8 */
4935 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4936 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4937 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
4938 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
4939 
4940 /* Bit 7 : Pin 7 */
4941 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4942 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4943 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
4944 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
4945 
4946 /* Bit 6 : Pin 6 */
4947 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4948 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4949 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
4950 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
4951 
4952 /* Bit 5 : Pin 5 */
4953 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4954 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4955 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
4956 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
4957 
4958 /* Bit 4 : Pin 4 */
4959 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4960 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4961 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
4962 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
4963 
4964 /* Bit 3 : Pin 3 */
4965 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4966 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4967 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
4968 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
4969 
4970 /* Bit 2 : Pin 2 */
4971 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4972 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4973 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
4974 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
4975 
4976 /* Bit 1 : Pin 1 */
4977 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4978 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4979 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
4980 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
4981 
4982 /* Bit 0 : Pin 0 */
4983 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4984 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4985 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
4986 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
4987 
4988 /* Register: GPIO_DIR */
4989 /* Description: Direction of GPIO pins */
4990 
4991 /* Bit 31 : Pin 31 */
4992 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4993 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4994 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
4995 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
4996 
4997 /* Bit 30 : Pin 30 */
4998 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4999 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5000 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5001 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5002 
5003 /* Bit 29 : Pin 29 */
5004 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5005 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5006 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5007 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5008 
5009 /* Bit 28 : Pin 28 */
5010 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5011 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5012 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5013 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5014 
5015 /* Bit 27 : Pin 27 */
5016 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5017 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5018 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5019 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5020 
5021 /* Bit 26 : Pin 26 */
5022 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5023 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5024 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5025 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5026 
5027 /* Bit 25 : Pin 25 */
5028 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5029 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5030 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5031 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5032 
5033 /* Bit 24 : Pin 24 */
5034 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5035 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5036 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5037 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5038 
5039 /* Bit 23 : Pin 23 */
5040 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5041 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5042 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5043 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5044 
5045 /* Bit 22 : Pin 22 */
5046 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5047 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5048 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5049 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5050 
5051 /* Bit 21 : Pin 21 */
5052 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5053 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5054 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5055 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5056 
5057 /* Bit 20 : Pin 20 */
5058 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5059 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5060 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5061 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5062 
5063 /* Bit 19 : Pin 19 */
5064 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5065 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5066 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
5067 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5068 
5069 /* Bit 18 : Pin 18 */
5070 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5071 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5072 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
5073 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5074 
5075 /* Bit 17 : Pin 17 */
5076 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5077 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5078 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
5079 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5080 
5081 /* Bit 16 : Pin 16 */
5082 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5083 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5084 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
5085 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5086 
5087 /* Bit 15 : Pin 15 */
5088 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5089 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5090 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
5091 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5092 
5093 /* Bit 14 : Pin 14 */
5094 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5095 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5096 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
5097 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5098 
5099 /* Bit 13 : Pin 13 */
5100 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5101 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5102 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
5103 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5104 
5105 /* Bit 12 : Pin 12 */
5106 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5107 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5108 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
5109 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5110 
5111 /* Bit 11 : Pin 11 */
5112 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5113 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5114 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
5115 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5116 
5117 /* Bit 10 : Pin 10 */
5118 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5119 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5120 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
5121 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5122 
5123 /* Bit 9 : Pin 9 */
5124 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5125 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5126 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
5127 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5128 
5129 /* Bit 8 : Pin 8 */
5130 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5131 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5132 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
5133 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5134 
5135 /* Bit 7 : Pin 7 */
5136 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5137 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5138 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
5139 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5140 
5141 /* Bit 6 : Pin 6 */
5142 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5143 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5144 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
5145 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5146 
5147 /* Bit 5 : Pin 5 */
5148 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5149 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5150 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
5151 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5152 
5153 /* Bit 4 : Pin 4 */
5154 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5155 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5156 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
5157 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5158 
5159 /* Bit 3 : Pin 3 */
5160 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5161 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5162 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
5163 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5164 
5165 /* Bit 2 : Pin 2 */
5166 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5167 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5168 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
5169 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5170 
5171 /* Bit 1 : Pin 1 */
5172 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5173 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5174 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
5175 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5176 
5177 /* Bit 0 : Pin 0 */
5178 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5179 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5180 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
5181 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
5182 
5183 /* Register: GPIO_DIRSET */
5184 /* Description: DIR set register */
5185 
5186 /* Bit 31 : Set as output pin 31 */
5187 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5188 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5189 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5190 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5191 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5192 
5193 /* Bit 30 : Set as output pin 30 */
5194 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5195 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5196 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5197 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5198 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5199 
5200 /* Bit 29 : Set as output pin 29 */
5201 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5202 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5203 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5204 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5205 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5206 
5207 /* Bit 28 : Set as output pin 28 */
5208 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5209 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5210 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5211 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5212 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5213 
5214 /* Bit 27 : Set as output pin 27 */
5215 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5216 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5217 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5218 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5219 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5220 
5221 /* Bit 26 : Set as output pin 26 */
5222 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5223 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5224 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
5225 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5226 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5227 
5228 /* Bit 25 : Set as output pin 25 */
5229 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5230 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5231 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
5232 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5233 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5234 
5235 /* Bit 24 : Set as output pin 24 */
5236 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5237 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5238 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
5239 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5240 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5241 
5242 /* Bit 23 : Set as output pin 23 */
5243 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5244 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5245 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
5246 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5247 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5248 
5249 /* Bit 22 : Set as output pin 22 */
5250 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5251 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5252 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
5253 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5254 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5255 
5256 /* Bit 21 : Set as output pin 21 */
5257 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5258 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5259 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
5260 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5261 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5262 
5263 /* Bit 20 : Set as output pin 20 */
5264 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5265 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5266 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
5267 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5268 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5269 
5270 /* Bit 19 : Set as output pin 19 */
5271 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5272 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5273 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
5274 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5275 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5276 
5277 /* Bit 18 : Set as output pin 18 */
5278 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5279 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5280 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
5281 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5282 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5283 
5284 /* Bit 17 : Set as output pin 17 */
5285 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5286 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5287 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
5288 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5289 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5290 
5291 /* Bit 16 : Set as output pin 16 */
5292 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5293 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5294 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
5295 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
5296 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5297 
5298 /* Bit 15 : Set as output pin 15 */
5299 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5300 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5301 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
5302 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
5303 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5304 
5305 /* Bit 14 : Set as output pin 14 */
5306 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5307 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5308 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
5309 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
5310 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5311 
5312 /* Bit 13 : Set as output pin 13 */
5313 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5314 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5315 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
5316 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
5317 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5318 
5319 /* Bit 12 : Set as output pin 12 */
5320 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5321 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5322 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
5323 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
5324 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5325 
5326 /* Bit 11 : Set as output pin 11 */
5327 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5328 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5329 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
5330 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
5331 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5332 
5333 /* Bit 10 : Set as output pin 10 */
5334 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5335 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5336 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
5337 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
5338 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5339 
5340 /* Bit 9 : Set as output pin 9 */
5341 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5342 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5343 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
5344 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
5345 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5346 
5347 /* Bit 8 : Set as output pin 8 */
5348 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5349 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5350 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
5351 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
5352 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5353 
5354 /* Bit 7 : Set as output pin 7 */
5355 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5356 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5357 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
5358 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
5359 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5360 
5361 /* Bit 6 : Set as output pin 6 */
5362 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5363 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5364 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
5365 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
5366 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5367 
5368 /* Bit 5 : Set as output pin 5 */
5369 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5370 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5371 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
5372 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
5373 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5374 
5375 /* Bit 4 : Set as output pin 4 */
5376 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5377 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5378 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
5379 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
5380 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5381 
5382 /* Bit 3 : Set as output pin 3 */
5383 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5384 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5385 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
5386 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
5387 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5388 
5389 /* Bit 2 : Set as output pin 2 */
5390 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5391 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5392 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
5393 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
5394 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5395 
5396 /* Bit 1 : Set as output pin 1 */
5397 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5398 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5399 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
5400 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
5401 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5402 
5403 /* Bit 0 : Set as output pin 0 */
5404 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5405 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5406 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
5407 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
5408 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5409 
5410 /* Register: GPIO_DIRCLR */
5411 /* Description: DIR clear register */
5412 
5413 /* Bit 31 : Set as input pin 31 */
5414 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5415 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5416 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
5417 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
5418 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5419 
5420 /* Bit 30 : Set as input pin 30 */
5421 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5422 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5423 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
5424 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
5425 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5426 
5427 /* Bit 29 : Set as input pin 29 */
5428 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5429 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5430 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
5431 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
5432 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5433 
5434 /* Bit 28 : Set as input pin 28 */
5435 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5436 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5437 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
5438 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
5439 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5440 
5441 /* Bit 27 : Set as input pin 27 */
5442 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5443 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5444 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
5445 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
5446 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5447 
5448 /* Bit 26 : Set as input pin 26 */
5449 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5450 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5451 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
5452 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
5453 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5454 
5455 /* Bit 25 : Set as input pin 25 */
5456 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5457 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5458 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
5459 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
5460 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5461 
5462 /* Bit 24 : Set as input pin 24 */
5463 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5464 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5465 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
5466 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
5467 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5468 
5469 /* Bit 23 : Set as input pin 23 */
5470 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5471 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5472 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
5473 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
5474 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5475 
5476 /* Bit 22 : Set as input pin 22 */
5477 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5478 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5479 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
5480 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
5481 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5482 
5483 /* Bit 21 : Set as input pin 21 */
5484 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5485 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5486 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
5487 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
5488 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5489 
5490 /* Bit 20 : Set as input pin 20 */
5491 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5492 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5493 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
5494 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
5495 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5496 
5497 /* Bit 19 : Set as input pin 19 */
5498 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5499 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5500 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
5501 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
5502 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5503 
5504 /* Bit 18 : Set as input pin 18 */
5505 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5506 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5507 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
5508 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
5509 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5510 
5511 /* Bit 17 : Set as input pin 17 */
5512 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5513 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5514 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
5515 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
5516 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5517 
5518 /* Bit 16 : Set as input pin 16 */
5519 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5520 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5521 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
5522 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
5523 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5524 
5525 /* Bit 15 : Set as input pin 15 */
5526 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5527 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5528 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
5529 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
5530 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5531 
5532 /* Bit 14 : Set as input pin 14 */
5533 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5534 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5535 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
5536 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
5537 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5538 
5539 /* Bit 13 : Set as input pin 13 */
5540 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5541 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5542 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
5543 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
5544 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5545 
5546 /* Bit 12 : Set as input pin 12 */
5547 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5548 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5549 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
5550 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
5551 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5552 
5553 /* Bit 11 : Set as input pin 11 */
5554 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5555 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5556 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
5557 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
5558 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5559 
5560 /* Bit 10 : Set as input pin 10 */
5561 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5562 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5563 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
5564 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
5565 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5566 
5567 /* Bit 9 : Set as input pin 9 */
5568 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5569 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5570 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
5571 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
5572 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5573 
5574 /* Bit 8 : Set as input pin 8 */
5575 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5576 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5577 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
5578 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
5579 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5580 
5581 /* Bit 7 : Set as input pin 7 */
5582 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5583 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5584 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
5585 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
5586 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5587 
5588 /* Bit 6 : Set as input pin 6 */
5589 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5590 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5591 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
5592 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
5593 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5594 
5595 /* Bit 5 : Set as input pin 5 */
5596 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5597 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5598 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
5599 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
5600 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5601 
5602 /* Bit 4 : Set as input pin 4 */
5603 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5604 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5605 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
5606 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
5607 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5608 
5609 /* Bit 3 : Set as input pin 3 */
5610 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5611 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5612 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
5613 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
5614 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5615 
5616 /* Bit 2 : Set as input pin 2 */
5617 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5618 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5619 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
5620 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
5621 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5622 
5623 /* Bit 1 : Set as input pin 1 */
5624 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5625 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5626 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
5627 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
5628 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5629 
5630 /* Bit 0 : Set as input pin 0 */
5631 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5632 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5633 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
5634 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
5635 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
5636 
5637 /* Register: GPIO_LATCH */
5638 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
5639 
5640 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
5641 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5642 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5643 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
5644 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
5645 
5646 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
5647 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5648 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5649 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
5650 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
5651 
5652 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
5653 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5654 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5655 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
5656 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
5657 
5658 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
5659 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5660 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5661 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
5662 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
5663 
5664 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
5665 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5666 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5667 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
5668 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
5669 
5670 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
5671 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5672 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5673 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
5674 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
5675 
5676 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
5677 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5678 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5679 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
5680 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
5681 
5682 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
5683 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5684 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5685 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
5686 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
5687 
5688 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
5689 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5690 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5691 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
5692 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
5693 
5694 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
5695 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5696 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5697 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
5698 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
5699 
5700 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
5701 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5702 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5703 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
5704 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
5705 
5706 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
5707 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5708 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5709 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
5710 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
5711 
5712 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
5713 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5714 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5715 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
5716 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
5717 
5718 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
5719 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5720 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5721 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
5722 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
5723 
5724 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
5725 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5726 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5727 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
5728 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
5729 
5730 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
5731 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5732 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5733 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
5734 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
5735 
5736 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
5737 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5738 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5739 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
5740 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
5741 
5742 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
5743 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5744 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5745 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
5746 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
5747 
5748 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
5749 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5750 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5751 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
5752 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
5753 
5754 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
5755 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5756 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5757 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
5758 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
5759 
5760 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
5761 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5762 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5763 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
5764 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
5765 
5766 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
5767 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5768 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5769 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
5770 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
5771 
5772 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
5773 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5774 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5775 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
5776 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
5777 
5778 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
5779 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5780 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5781 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
5782 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
5783 
5784 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
5785 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5786 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5787 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
5788 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
5789 
5790 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
5791 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5792 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5793 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
5794 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
5795 
5796 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
5797 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5798 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5799 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
5800 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
5801 
5802 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
5803 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5804 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5805 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
5806 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
5807 
5808 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
5809 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5810 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5811 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
5812 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
5813 
5814 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
5815 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5816 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5817 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
5818 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
5819 
5820 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
5821 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5822 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5823 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
5824 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
5825 
5826 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
5827 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5828 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5829 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
5830 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
5831 
5832 /* Register: GPIO_DETECTMODE */
5833 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
5834 
5835 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
5836 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
5837 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
5838 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
5839 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
5840 
5841 /* Register: GPIO_DETECTMODE_SEC */
5842 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
5843 
5844 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
5845 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
5846 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
5847 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
5848 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
5849 
5850 /* Register: GPIO_PIN_CNF */
5851 /* Description: Description collection: Configuration of GPIO pins */
5852 
5853 /* Bits 30..28 : Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. */
5854 #define GPIO_PIN_CNF_MCUSEL_Pos (28UL) /*!< Position of MCUSEL field. */
5855 #define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos) /*!< Bit mask of MCUSEL field. */
5856 #define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL) /*!< Application MCU */
5857 #define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL) /*!< Network MCU */
5858 #define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL) /*!< Peripheral with dedicated pins */
5859 #define GPIO_PIN_CNF_MCUSEL_TND (0x7UL) /*!< Trace and Debug Subsystem */
5860 
5861 /* Bits 17..16 : Pin sensing mechanism */
5862 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
5863 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
5864 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
5865 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
5866 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
5867 
5868 /* Bits 11..8 : Drive configuration */
5869 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
5870 #define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
5871 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
5872 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
5873 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
5874 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
5875 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
5876 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
5877 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
5878 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
5879 #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL) /*!< Extra high drive '0', extra high drive '1' */
5880 
5881 /* Bits 3..2 : Pull configuration */
5882 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
5883 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
5884 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
5885 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
5886 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
5887 
5888 /* Bit 1 : Connect or disconnect input buffer */
5889 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
5890 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
5891 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
5892 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
5893 
5894 /* Bit 0 : Pin direction. Same physical register as DIR register */
5895 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
5896 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
5897 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
5898 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
5899 
5900 
5901 /* Peripheral: POWER */
5902 /* Description: Power control */
5903 
5904 /* Register: POWER_TASKS_CONSTLAT */
5905 /* Description: Enable Constant Latency mode */
5906 
5907 /* Bit 0 : Enable Constant Latency mode */
5908 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
5909 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
5910 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
5911 
5912 /* Register: POWER_TASKS_LOWPWR */
5913 /* Description: Enable Low-Power mode (variable latency) */
5914 
5915 /* Bit 0 : Enable Low-Power mode (variable latency) */
5916 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
5917 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
5918 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
5919 
5920 /* Register: POWER_SUBSCRIBE_CONSTLAT */
5921 /* Description: Subscribe configuration for task CONSTLAT */
5922 
5923 /* Bit 31 :   */
5924 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
5925 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
5926 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
5927 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
5928 
5929 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
5930 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5931 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5932 
5933 /* Register: POWER_SUBSCRIBE_LOWPWR */
5934 /* Description: Subscribe configuration for task LOWPWR */
5935 
5936 /* Bit 31 :   */
5937 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
5938 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
5939 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
5940 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
5941 
5942 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
5943 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5944 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5945 
5946 /* Register: POWER_EVENTS_POFWARN */
5947 /* Description: Power failure warning */
5948 
5949 /* Bit 0 : Power failure warning */
5950 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
5951 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
5952 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
5953 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
5954 
5955 /* Register: POWER_EVENTS_SLEEPENTER */
5956 /* Description: CPU entered WFI/WFE sleep */
5957 
5958 /* Bit 0 : CPU entered WFI/WFE sleep */
5959 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
5960 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
5961 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
5962 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
5963 
5964 /* Register: POWER_EVENTS_SLEEPEXIT */
5965 /* Description: CPU exited WFI/WFE sleep */
5966 
5967 /* Bit 0 : CPU exited WFI/WFE sleep */
5968 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
5969 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
5970 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
5971 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
5972 
5973 /* Register: POWER_PUBLISH_POFWARN */
5974 /* Description: Publish configuration for event POFWARN */
5975 
5976 /* Bit 31 :   */
5977 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
5978 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
5979 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
5980 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
5981 
5982 /* Bits 7..0 : DPPI channel that event POFWARN will publish to. */
5983 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5984 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5985 
5986 /* Register: POWER_PUBLISH_SLEEPENTER */
5987 /* Description: Publish configuration for event SLEEPENTER */
5988 
5989 /* Bit 31 :   */
5990 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
5991 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
5992 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
5993 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
5994 
5995 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to. */
5996 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5997 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5998 
5999 /* Register: POWER_PUBLISH_SLEEPEXIT */
6000 /* Description: Publish configuration for event SLEEPEXIT */
6001 
6002 /* Bit 31 :   */
6003 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
6004 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
6005 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
6006 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
6007 
6008 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to. */
6009 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6010 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6011 
6012 /* Register: POWER_INTEN */
6013 /* Description: Enable or disable interrupt */
6014 
6015 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
6016 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6017 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6018 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
6019 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
6020 
6021 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
6022 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6023 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6024 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
6025 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
6026 
6027 /* Bit 2 : Enable or disable interrupt for event POFWARN */
6028 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6029 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6030 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
6031 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
6032 
6033 /* Register: POWER_INTENSET */
6034 /* Description: Enable interrupt */
6035 
6036 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
6037 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6038 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6039 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6040 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6041 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6042 
6043 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
6044 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6045 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6046 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6047 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6048 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6049 
6050 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
6051 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6052 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6053 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6054 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6055 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6056 
6057 /* Register: POWER_INTENCLR */
6058 /* Description: Disable interrupt */
6059 
6060 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
6061 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6062 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6063 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6064 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6065 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6066 
6067 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
6068 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6069 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6070 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6071 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6072 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6073 
6074 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
6075 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6076 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6077 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6078 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6079 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6080 
6081 /* Register: POWER_GPREGRET */
6082 /* Description: Description collection: General purpose retention register */
6083 
6084 /* Bits 7..0 : General purpose retention register */
6085 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6086 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6087 
6088 
6089 /* Peripheral: RADIO */
6090 /* Description: 2.4 GHz radio */
6091 
6092 /* Register: RADIO_TASKS_TXEN */
6093 /* Description: Enable RADIO in TX mode */
6094 
6095 /* Bit 0 : Enable RADIO in TX mode */
6096 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
6097 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
6098 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
6099 
6100 /* Register: RADIO_TASKS_RXEN */
6101 /* Description: Enable RADIO in RX mode */
6102 
6103 /* Bit 0 : Enable RADIO in RX mode */
6104 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
6105 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
6106 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
6107 
6108 /* Register: RADIO_TASKS_START */
6109 /* Description: Start RADIO */
6110 
6111 /* Bit 0 : Start RADIO */
6112 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6113 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6114 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6115 
6116 /* Register: RADIO_TASKS_STOP */
6117 /* Description: Stop RADIO */
6118 
6119 /* Bit 0 : Stop RADIO */
6120 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6121 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6122 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6123 
6124 /* Register: RADIO_TASKS_DISABLE */
6125 /* Description: Disable RADIO */
6126 
6127 /* Bit 0 : Disable RADIO */
6128 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
6129 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
6130 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
6131 
6132 /* Register: RADIO_TASKS_RSSISTART */
6133 /* Description: Start the RSSI and take one single sample of the receive signal strength */
6134 
6135 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
6136 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
6137 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
6138 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
6139 
6140 /* Register: RADIO_TASKS_RSSISTOP */
6141 /* Description: Stop the RSSI measurement */
6142 
6143 /* Bit 0 : Stop the RSSI measurement */
6144 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
6145 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
6146 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
6147 
6148 /* Register: RADIO_TASKS_BCSTART */
6149 /* Description: Start the bit counter */
6150 
6151 /* Bit 0 : Start the bit counter */
6152 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
6153 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
6154 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
6155 
6156 /* Register: RADIO_TASKS_BCSTOP */
6157 /* Description: Stop the bit counter */
6158 
6159 /* Bit 0 : Stop the bit counter */
6160 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
6161 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
6162 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
6163 
6164 /* Register: RADIO_TASKS_EDSTART */
6165 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
6166 
6167 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
6168 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
6169 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
6170 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
6171 
6172 /* Register: RADIO_TASKS_EDSTOP */
6173 /* Description: Stop the energy detect measurement */
6174 
6175 /* Bit 0 : Stop the energy detect measurement */
6176 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
6177 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
6178 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
6179 
6180 /* Register: RADIO_TASKS_CCASTART */
6181 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
6182 
6183 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
6184 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
6185 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
6186 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
6187 
6188 /* Register: RADIO_TASKS_CCASTOP */
6189 /* Description: Stop the clear channel assessment */
6190 
6191 /* Bit 0 : Stop the clear channel assessment */
6192 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
6193 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
6194 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
6195 
6196 /* Register: RADIO_SUBSCRIBE_TXEN */
6197 /* Description: Subscribe configuration for task TXEN */
6198 
6199 /* Bit 31 :   */
6200 #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */
6201 #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */
6202 #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL) /*!< Disable subscription */
6203 #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL) /*!< Enable subscription */
6204 
6205 /* Bits 7..0 : DPPI channel that task TXEN will subscribe to */
6206 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6207 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6208 
6209 /* Register: RADIO_SUBSCRIBE_RXEN */
6210 /* Description: Subscribe configuration for task RXEN */
6211 
6212 /* Bit 31 :   */
6213 #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */
6214 #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */
6215 #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL) /*!< Disable subscription */
6216 #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL) /*!< Enable subscription */
6217 
6218 /* Bits 7..0 : DPPI channel that task RXEN will subscribe to */
6219 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6220 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6221 
6222 /* Register: RADIO_SUBSCRIBE_START */
6223 /* Description: Subscribe configuration for task START */
6224 
6225 /* Bit 31 :   */
6226 #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
6227 #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
6228 #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
6229 #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
6230 
6231 /* Bits 7..0 : DPPI channel that task START will subscribe to */
6232 #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6233 #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6234 
6235 /* Register: RADIO_SUBSCRIBE_STOP */
6236 /* Description: Subscribe configuration for task STOP */
6237 
6238 /* Bit 31 :   */
6239 #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
6240 #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
6241 #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
6242 #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6243 
6244 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
6245 #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6246 #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6247 
6248 /* Register: RADIO_SUBSCRIBE_DISABLE */
6249 /* Description: Subscribe configuration for task DISABLE */
6250 
6251 /* Bit 31 :   */
6252 #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */
6253 #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */
6254 #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */
6255 #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */
6256 
6257 /* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */
6258 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6259 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6260 
6261 /* Register: RADIO_SUBSCRIBE_RSSISTART */
6262 /* Description: Subscribe configuration for task RSSISTART */
6263 
6264 /* Bit 31 :   */
6265 #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */
6266 #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */
6267 #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL) /*!< Disable subscription */
6268 #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL) /*!< Enable subscription */
6269 
6270 /* Bits 7..0 : DPPI channel that task RSSISTART will subscribe to */
6271 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6272 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6273 
6274 /* Register: RADIO_SUBSCRIBE_RSSISTOP */
6275 /* Description: Subscribe configuration for task RSSISTOP */
6276 
6277 /* Bit 31 :   */
6278 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Pos (31UL) /*!< Position of EN field. */
6279 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTOP_EN_Pos) /*!< Bit mask of EN field. */
6280 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL) /*!< Disable subscription */
6281 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL) /*!< Enable subscription */
6282 
6283 /* Bits 7..0 : DPPI channel that task RSSISTOP will subscribe to */
6284 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6285 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6286 
6287 /* Register: RADIO_SUBSCRIBE_BCSTART */
6288 /* Description: Subscribe configuration for task BCSTART */
6289 
6290 /* Bit 31 :   */
6291 #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */
6292 #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */
6293 #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL) /*!< Disable subscription */
6294 #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL) /*!< Enable subscription */
6295 
6296 /* Bits 7..0 : DPPI channel that task BCSTART will subscribe to */
6297 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6298 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6299 
6300 /* Register: RADIO_SUBSCRIBE_BCSTOP */
6301 /* Description: Subscribe configuration for task BCSTOP */
6302 
6303 /* Bit 31 :   */
6304 #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */
6305 #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */
6306 #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL) /*!< Disable subscription */
6307 #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL) /*!< Enable subscription */
6308 
6309 /* Bits 7..0 : DPPI channel that task BCSTOP will subscribe to */
6310 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6311 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6312 
6313 /* Register: RADIO_SUBSCRIBE_EDSTART */
6314 /* Description: Subscribe configuration for task EDSTART */
6315 
6316 /* Bit 31 :   */
6317 #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */
6318 #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */
6319 #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL) /*!< Disable subscription */
6320 #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL) /*!< Enable subscription */
6321 
6322 /* Bits 7..0 : DPPI channel that task EDSTART will subscribe to */
6323 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6324 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6325 
6326 /* Register: RADIO_SUBSCRIBE_EDSTOP */
6327 /* Description: Subscribe configuration for task EDSTOP */
6328 
6329 /* Bit 31 :   */
6330 #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */
6331 #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */
6332 #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL) /*!< Disable subscription */
6333 #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL) /*!< Enable subscription */
6334 
6335 /* Bits 7..0 : DPPI channel that task EDSTOP will subscribe to */
6336 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6337 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6338 
6339 /* Register: RADIO_SUBSCRIBE_CCASTART */
6340 /* Description: Subscribe configuration for task CCASTART */
6341 
6342 /* Bit 31 :   */
6343 #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */
6344 #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */
6345 #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL) /*!< Disable subscription */
6346 #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL) /*!< Enable subscription */
6347 
6348 /* Bits 7..0 : DPPI channel that task CCASTART will subscribe to */
6349 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6350 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6351 
6352 /* Register: RADIO_SUBSCRIBE_CCASTOP */
6353 /* Description: Subscribe configuration for task CCASTOP */
6354 
6355 /* Bit 31 :   */
6356 #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */
6357 #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */
6358 #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL) /*!< Disable subscription */
6359 #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL) /*!< Enable subscription */
6360 
6361 /* Bits 7..0 : DPPI channel that task CCASTOP will subscribe to */
6362 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6363 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6364 
6365 /* Register: RADIO_EVENTS_READY */
6366 /* Description: RADIO has ramped up and is ready to be started */
6367 
6368 /* Bit 0 : RADIO has ramped up and is ready to be started */
6369 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
6370 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
6371 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
6372 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
6373 
6374 /* Register: RADIO_EVENTS_ADDRESS */
6375 /* Description: Address sent or received */
6376 
6377 /* Bit 0 : Address sent or received */
6378 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
6379 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
6380 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
6381 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
6382 
6383 /* Register: RADIO_EVENTS_PAYLOAD */
6384 /* Description: Packet payload sent or received */
6385 
6386 /* Bit 0 : Packet payload sent or received */
6387 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
6388 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
6389 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
6390 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
6391 
6392 /* Register: RADIO_EVENTS_END */
6393 /* Description: Packet sent or received */
6394 
6395 /* Bit 0 : Packet sent or received */
6396 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6397 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6398 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6399 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6400 
6401 /* Register: RADIO_EVENTS_DISABLED */
6402 /* Description: RADIO has been disabled */
6403 
6404 /* Bit 0 : RADIO has been disabled */
6405 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
6406 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
6407 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
6408 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
6409 
6410 /* Register: RADIO_EVENTS_DEVMATCH */
6411 /* Description: A device address match occurred on the last received packet */
6412 
6413 /* Bit 0 : A device address match occurred on the last received packet */
6414 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
6415 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
6416 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
6417 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
6418 
6419 /* Register: RADIO_EVENTS_DEVMISS */
6420 /* Description: No device address match occurred on the last received packet */
6421 
6422 /* Bit 0 : No device address match occurred on the last received packet */
6423 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
6424 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
6425 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
6426 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
6427 
6428 /* Register: RADIO_EVENTS_RSSIEND */
6429 /* Description: Sampling of receive signal strength complete */
6430 
6431 /* Bit 0 : Sampling of receive signal strength complete */
6432 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
6433 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
6434 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
6435 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
6436 
6437 /* Register: RADIO_EVENTS_BCMATCH */
6438 /* Description: Bit counter reached bit count value */
6439 
6440 /* Bit 0 : Bit counter reached bit count value */
6441 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
6442 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
6443 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
6444 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
6445 
6446 /* Register: RADIO_EVENTS_CRCOK */
6447 /* Description: Packet received with CRC ok */
6448 
6449 /* Bit 0 : Packet received with CRC ok */
6450 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
6451 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
6452 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
6453 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
6454 
6455 /* Register: RADIO_EVENTS_CRCERROR */
6456 /* Description: Packet received with CRC error */
6457 
6458 /* Bit 0 : Packet received with CRC error */
6459 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
6460 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
6461 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
6462 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
6463 
6464 /* Register: RADIO_EVENTS_FRAMESTART */
6465 /* Description: IEEE 802.15.4 length field received */
6466 
6467 /* Bit 0 : IEEE 802.15.4 length field received */
6468 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
6469 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
6470 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
6471 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
6472 
6473 /* Register: RADIO_EVENTS_EDEND */
6474 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
6475 
6476 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
6477 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
6478 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
6479 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
6480 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
6481 
6482 /* Register: RADIO_EVENTS_EDSTOPPED */
6483 /* Description: The sampling of energy detection has stopped */
6484 
6485 /* Bit 0 : The sampling of energy detection has stopped */
6486 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
6487 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
6488 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
6489 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
6490 
6491 /* Register: RADIO_EVENTS_CCAIDLE */
6492 /* Description: Wireless medium in idle - clear to send */
6493 
6494 /* Bit 0 : Wireless medium in idle - clear to send */
6495 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
6496 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
6497 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
6498 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
6499 
6500 /* Register: RADIO_EVENTS_CCABUSY */
6501 /* Description: Wireless medium busy - do not send */
6502 
6503 /* Bit 0 : Wireless medium busy - do not send */
6504 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
6505 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
6506 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
6507 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
6508 
6509 /* Register: RADIO_EVENTS_CCASTOPPED */
6510 /* Description: The CCA has stopped */
6511 
6512 /* Bit 0 : The CCA has stopped */
6513 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
6514 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
6515 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
6516 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
6517 
6518 /* Register: RADIO_EVENTS_RATEBOOST */
6519 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
6520 
6521 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
6522 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
6523 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
6524 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
6525 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
6526 
6527 /* Register: RADIO_EVENTS_TXREADY */
6528 /* Description: RADIO has ramped up and is ready to be started TX path */
6529 
6530 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
6531 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
6532 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
6533 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
6534 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
6535 
6536 /* Register: RADIO_EVENTS_RXREADY */
6537 /* Description: RADIO has ramped up and is ready to be started RX path */
6538 
6539 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
6540 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
6541 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
6542 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
6543 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
6544 
6545 /* Register: RADIO_EVENTS_MHRMATCH */
6546 /* Description: MAC header match found */
6547 
6548 /* Bit 0 : MAC header match found */
6549 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
6550 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
6551 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
6552 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
6553 
6554 /* Register: RADIO_EVENTS_SYNC */
6555 /* Description: Preamble indicator */
6556 
6557 /* Bit 0 : Preamble indicator */
6558 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
6559 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
6560 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */
6561 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */
6562 
6563 /* Register: RADIO_EVENTS_PHYEND */
6564 /* Description: Generated when last bit is sent on air, or received from air */
6565 
6566 /* Bit 0 : Generated when last bit is sent on air, or received from air */
6567 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
6568 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
6569 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
6570 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
6571 
6572 /* Register: RADIO_EVENTS_CTEPRESENT */
6573 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */
6574 
6575 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
6576 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
6577 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
6578 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
6579 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
6580 
6581 /* Register: RADIO_PUBLISH_READY */
6582 /* Description: Publish configuration for event READY */
6583 
6584 /* Bit 31 :   */
6585 #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
6586 #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
6587 #define RADIO_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
6588 #define RADIO_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
6589 
6590 /* Bits 7..0 : DPPI channel that event READY will publish to. */
6591 #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6592 #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6593 
6594 /* Register: RADIO_PUBLISH_ADDRESS */
6595 /* Description: Publish configuration for event ADDRESS */
6596 
6597 /* Bit 31 :   */
6598 #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */
6599 #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */
6600 #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL) /*!< Disable publishing */
6601 #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL) /*!< Enable publishing */
6602 
6603 /* Bits 7..0 : DPPI channel that event ADDRESS will publish to. */
6604 #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6605 #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6606 
6607 /* Register: RADIO_PUBLISH_PAYLOAD */
6608 /* Description: Publish configuration for event PAYLOAD */
6609 
6610 /* Bit 31 :   */
6611 #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */
6612 #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */
6613 #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL) /*!< Disable publishing */
6614 #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL) /*!< Enable publishing */
6615 
6616 /* Bits 7..0 : DPPI channel that event PAYLOAD will publish to. */
6617 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6618 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6619 
6620 /* Register: RADIO_PUBLISH_END */
6621 /* Description: Publish configuration for event END */
6622 
6623 /* Bit 31 :   */
6624 #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
6625 #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
6626 #define RADIO_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6627 #define RADIO_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6628 
6629 /* Bits 7..0 : DPPI channel that event END will publish to. */
6630 #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6631 #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6632 
6633 /* Register: RADIO_PUBLISH_DISABLED */
6634 /* Description: Publish configuration for event DISABLED */
6635 
6636 /* Bit 31 :   */
6637 #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */
6638 #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */
6639 #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL) /*!< Disable publishing */
6640 #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL) /*!< Enable publishing */
6641 
6642 /* Bits 7..0 : DPPI channel that event DISABLED will publish to. */
6643 #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6644 #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6645 
6646 /* Register: RADIO_PUBLISH_DEVMATCH */
6647 /* Description: Publish configuration for event DEVMATCH */
6648 
6649 /* Bit 31 :   */
6650 #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */
6651 #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */
6652 #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL) /*!< Disable publishing */
6653 #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL) /*!< Enable publishing */
6654 
6655 /* Bits 7..0 : DPPI channel that event DEVMATCH will publish to. */
6656 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6657 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6658 
6659 /* Register: RADIO_PUBLISH_DEVMISS */
6660 /* Description: Publish configuration for event DEVMISS */
6661 
6662 /* Bit 31 :   */
6663 #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */
6664 #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */
6665 #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL) /*!< Disable publishing */
6666 #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL) /*!< Enable publishing */
6667 
6668 /* Bits 7..0 : DPPI channel that event DEVMISS will publish to. */
6669 #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6670 #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6671 
6672 /* Register: RADIO_PUBLISH_RSSIEND */
6673 /* Description: Publish configuration for event RSSIEND */
6674 
6675 /* Bit 31 :   */
6676 #define RADIO_PUBLISH_RSSIEND_EN_Pos (31UL) /*!< Position of EN field. */
6677 #define RADIO_PUBLISH_RSSIEND_EN_Msk (0x1UL << RADIO_PUBLISH_RSSIEND_EN_Pos) /*!< Bit mask of EN field. */
6678 #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL) /*!< Disable publishing */
6679 #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL) /*!< Enable publishing */
6680 
6681 /* Bits 7..0 : DPPI channel that event RSSIEND will publish to. */
6682 #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6683 #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6684 
6685 /* Register: RADIO_PUBLISH_BCMATCH */
6686 /* Description: Publish configuration for event BCMATCH */
6687 
6688 /* Bit 31 :   */
6689 #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */
6690 #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */
6691 #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL) /*!< Disable publishing */
6692 #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL) /*!< Enable publishing */
6693 
6694 /* Bits 7..0 : DPPI channel that event BCMATCH will publish to. */
6695 #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6696 #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6697 
6698 /* Register: RADIO_PUBLISH_CRCOK */
6699 /* Description: Publish configuration for event CRCOK */
6700 
6701 /* Bit 31 :   */
6702 #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */
6703 #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */
6704 #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL) /*!< Disable publishing */
6705 #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL) /*!< Enable publishing */
6706 
6707 /* Bits 7..0 : DPPI channel that event CRCOK will publish to. */
6708 #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6709 #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6710 
6711 /* Register: RADIO_PUBLISH_CRCERROR */
6712 /* Description: Publish configuration for event CRCERROR */
6713 
6714 /* Bit 31 :   */
6715 #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */
6716 #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */
6717 #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL) /*!< Disable publishing */
6718 #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL) /*!< Enable publishing */
6719 
6720 /* Bits 7..0 : DPPI channel that event CRCERROR will publish to. */
6721 #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6722 #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6723 
6724 /* Register: RADIO_PUBLISH_FRAMESTART */
6725 /* Description: Publish configuration for event FRAMESTART */
6726 
6727 /* Bit 31 :   */
6728 #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
6729 #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
6730 #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */
6731 #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */
6732 
6733 /* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */
6734 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6735 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6736 
6737 /* Register: RADIO_PUBLISH_EDEND */
6738 /* Description: Publish configuration for event EDEND */
6739 
6740 /* Bit 31 :   */
6741 #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */
6742 #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */
6743 #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL) /*!< Disable publishing */
6744 #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL) /*!< Enable publishing */
6745 
6746 /* Bits 7..0 : DPPI channel that event EDEND will publish to. */
6747 #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6748 #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6749 
6750 /* Register: RADIO_PUBLISH_EDSTOPPED */
6751 /* Description: Publish configuration for event EDSTOPPED */
6752 
6753 /* Bit 31 :   */
6754 #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6755 #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
6756 #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6757 #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6758 
6759 /* Bits 7..0 : DPPI channel that event EDSTOPPED will publish to. */
6760 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6761 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6762 
6763 /* Register: RADIO_PUBLISH_CCAIDLE */
6764 /* Description: Publish configuration for event CCAIDLE */
6765 
6766 /* Bit 31 :   */
6767 #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */
6768 #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */
6769 #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL) /*!< Disable publishing */
6770 #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL) /*!< Enable publishing */
6771 
6772 /* Bits 7..0 : DPPI channel that event CCAIDLE will publish to. */
6773 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6774 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6775 
6776 /* Register: RADIO_PUBLISH_CCABUSY */
6777 /* Description: Publish configuration for event CCABUSY */
6778 
6779 /* Bit 31 :   */
6780 #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */
6781 #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */
6782 #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL) /*!< Disable publishing */
6783 #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL) /*!< Enable publishing */
6784 
6785 /* Bits 7..0 : DPPI channel that event CCABUSY will publish to. */
6786 #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6787 #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6788 
6789 /* Register: RADIO_PUBLISH_CCASTOPPED */
6790 /* Description: Publish configuration for event CCASTOPPED */
6791 
6792 /* Bit 31 :   */
6793 #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6794 #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */
6795 #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6796 #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6797 
6798 /* Bits 7..0 : DPPI channel that event CCASTOPPED will publish to. */
6799 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6800 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6801 
6802 /* Register: RADIO_PUBLISH_RATEBOOST */
6803 /* Description: Publish configuration for event RATEBOOST */
6804 
6805 /* Bit 31 :   */
6806 #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */
6807 #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */
6808 #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL) /*!< Disable publishing */
6809 #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL) /*!< Enable publishing */
6810 
6811 /* Bits 7..0 : DPPI channel that event RATEBOOST will publish to. */
6812 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6813 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6814 
6815 /* Register: RADIO_PUBLISH_TXREADY */
6816 /* Description: Publish configuration for event TXREADY */
6817 
6818 /* Bit 31 :   */
6819 #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */
6820 #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */
6821 #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL) /*!< Disable publishing */
6822 #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL) /*!< Enable publishing */
6823 
6824 /* Bits 7..0 : DPPI channel that event TXREADY will publish to. */
6825 #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6826 #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6827 
6828 /* Register: RADIO_PUBLISH_RXREADY */
6829 /* Description: Publish configuration for event RXREADY */
6830 
6831 /* Bit 31 :   */
6832 #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */
6833 #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */
6834 #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL) /*!< Disable publishing */
6835 #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL) /*!< Enable publishing */
6836 
6837 /* Bits 7..0 : DPPI channel that event RXREADY will publish to. */
6838 #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6839 #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6840 
6841 /* Register: RADIO_PUBLISH_MHRMATCH */
6842 /* Description: Publish configuration for event MHRMATCH */
6843 
6844 /* Bit 31 :   */
6845 #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */
6846 #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */
6847 #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL) /*!< Disable publishing */
6848 #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL) /*!< Enable publishing */
6849 
6850 /* Bits 7..0 : DPPI channel that event MHRMATCH will publish to. */
6851 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6852 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6853 
6854 /* Register: RADIO_PUBLISH_SYNC */
6855 /* Description: Publish configuration for event SYNC */
6856 
6857 /* Bit 31 :   */
6858 #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */
6859 #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */
6860 #define RADIO_PUBLISH_SYNC_EN_Disabled (0UL) /*!< Disable publishing */
6861 #define RADIO_PUBLISH_SYNC_EN_Enabled (1UL) /*!< Enable publishing */
6862 
6863 /* Bits 7..0 : DPPI channel that event SYNC will publish to. */
6864 #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6865 #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6866 
6867 /* Register: RADIO_PUBLISH_PHYEND */
6868 /* Description: Publish configuration for event PHYEND */
6869 
6870 /* Bit 31 :   */
6871 #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */
6872 #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */
6873 #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL) /*!< Disable publishing */
6874 #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL) /*!< Enable publishing */
6875 
6876 /* Bits 7..0 : DPPI channel that event PHYEND will publish to. */
6877 #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6878 #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6879 
6880 /* Register: RADIO_PUBLISH_CTEPRESENT */
6881 /* Description: Publish configuration for event CTEPRESENT */
6882 
6883 /* Bit 31 :   */
6884 #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */
6885 #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */
6886 #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL) /*!< Disable publishing */
6887 #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL) /*!< Enable publishing */
6888 
6889 /* Bits 7..0 : DPPI channel that event CTEPRESENT will publish to. */
6890 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6891 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6892 
6893 /* Register: RADIO_SHORTS */
6894 /* Description: Shortcuts between local events and tasks */
6895 
6896 /* Bit 21 : Shortcut between event PHYEND and task START */
6897 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
6898 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
6899 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
6900 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
6901 
6902 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
6903 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
6904 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
6905 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
6906 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
6907 
6908 /* Bit 19 : Shortcut between event RXREADY and task START */
6909 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
6910 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
6911 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
6912 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
6913 
6914 /* Bit 18 : Shortcut between event TXREADY and task START */
6915 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
6916 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
6917 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
6918 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
6919 
6920 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
6921 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
6922 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
6923 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
6924 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
6925 
6926 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
6927 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
6928 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
6929 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
6930 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
6931 
6932 /* Bit 15 : Shortcut between event READY and task EDSTART */
6933 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
6934 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
6935 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
6936 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
6937 
6938 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
6939 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
6940 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
6941 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
6942 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
6943 
6944 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
6945 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
6946 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
6947 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
6948 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
6949 
6950 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
6951 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
6952 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
6953 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
6954 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
6955 
6956 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
6957 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
6958 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
6959 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
6960 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
6961 
6962 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
6963 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
6964 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
6965 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
6966 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
6967 
6968 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
6969 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
6970 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
6971 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
6972 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
6973 
6974 /* Bit 5 : Shortcut between event END and task START */
6975 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
6976 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
6977 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
6978 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6979 
6980 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
6981 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
6982 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
6983 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
6984 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
6985 
6986 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
6987 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
6988 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
6989 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
6990 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
6991 
6992 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
6993 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
6994 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
6995 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
6996 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
6997 
6998 /* Bit 1 : Shortcut between event END and task DISABLE */
6999 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
7000 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
7001 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
7002 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
7003 
7004 /* Bit 0 : Shortcut between event READY and task START */
7005 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
7006 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
7007 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
7008 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
7009 
7010 /* Register: RADIO_INTENSET */
7011 /* Description: Enable interrupt */
7012 
7013 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
7014 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
7015 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
7016 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
7017 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
7018 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
7019 
7020 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
7021 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
7022 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
7023 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
7024 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
7025 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
7026 
7027 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
7028 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
7029 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
7030 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */
7031 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */
7032 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */
7033 
7034 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
7035 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
7036 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
7037 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
7038 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
7039 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
7040 
7041 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
7042 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
7043 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
7044 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
7045 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
7046 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
7047 
7048 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
7049 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
7050 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
7051 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
7052 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
7053 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
7054 
7055 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
7056 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
7057 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
7058 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
7059 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
7060 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
7061 
7062 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
7063 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
7064 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
7065 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
7066 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
7067 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
7068 
7069 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
7070 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
7071 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
7072 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
7073 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
7074 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
7075 
7076 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
7077 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
7078 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
7079 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
7080 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
7081 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
7082 
7083 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
7084 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
7085 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
7086 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
7087 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
7088 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
7089 
7090 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
7091 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
7092 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
7093 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
7094 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
7095 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
7096 
7097 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
7098 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
7099 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
7100 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
7101 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
7102 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
7103 
7104 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
7105 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
7106 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
7107 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
7108 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
7109 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
7110 
7111 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
7112 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
7113 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
7114 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
7115 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
7116 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
7117 
7118 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
7119 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
7120 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
7121 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
7122 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
7123 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
7124 
7125 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
7126 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
7127 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
7128 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
7129 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
7130 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
7131 
7132 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
7133 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
7134 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
7135 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
7136 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
7137 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
7138 
7139 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
7140 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
7141 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
7142 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
7143 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
7144 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
7145 
7146 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
7147 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
7148 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
7149 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
7150 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
7151 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
7152 
7153 /* Bit 3 : Write '1' to enable interrupt for event END */
7154 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
7155 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
7156 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7157 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7158 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
7159 
7160 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
7161 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
7162 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
7163 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
7164 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
7165 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
7166 
7167 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
7168 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
7169 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
7170 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
7171 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
7172 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
7173 
7174 /* Bit 0 : Write '1' to enable interrupt for event READY */
7175 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
7176 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
7177 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
7178 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
7179 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
7180 
7181 /* Register: RADIO_INTENCLR */
7182 /* Description: Disable interrupt */
7183 
7184 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
7185 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
7186 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
7187 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
7188 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
7189 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
7190 
7191 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
7192 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
7193 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
7194 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
7195 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
7196 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
7197 
7198 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
7199 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
7200 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
7201 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */
7202 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */
7203 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */
7204 
7205 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
7206 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
7207 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
7208 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
7209 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
7210 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
7211 
7212 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
7213 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
7214 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
7215 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
7216 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
7217 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
7218 
7219 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
7220 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
7221 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
7222 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
7223 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
7224 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
7225 
7226 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
7227 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
7228 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
7229 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
7230 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
7231 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
7232 
7233 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
7234 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
7235 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
7236 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
7237 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
7238 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
7239 
7240 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
7241 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
7242 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
7243 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
7244 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
7245 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
7246 
7247 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
7248 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
7249 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
7250 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
7251 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
7252 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
7253 
7254 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
7255 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
7256 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
7257 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
7258 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
7259 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
7260 
7261 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
7262 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
7263 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
7264 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
7265 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
7266 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
7267 
7268 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
7269 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
7270 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
7271 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
7272 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
7273 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
7274 
7275 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
7276 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
7277 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
7278 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
7279 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
7280 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
7281 
7282 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
7283 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
7284 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
7285 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
7286 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
7287 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
7288 
7289 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
7290 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
7291 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
7292 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
7293 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
7294 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
7295 
7296 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
7297 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
7298 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
7299 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
7300 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
7301 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
7302 
7303 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
7304 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
7305 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
7306 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
7307 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
7308 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
7309 
7310 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
7311 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
7312 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
7313 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
7314 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
7315 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
7316 
7317 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
7318 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
7319 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
7320 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
7321 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
7322 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
7323 
7324 /* Bit 3 : Write '1' to disable interrupt for event END */
7325 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
7326 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7327 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7328 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7329 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
7330 
7331 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
7332 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
7333 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
7334 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
7335 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
7336 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
7337 
7338 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
7339 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
7340 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
7341 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
7342 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
7343 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
7344 
7345 /* Bit 0 : Write '1' to disable interrupt for event READY */
7346 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
7347 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
7348 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
7349 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
7350 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
7351 
7352 /* Register: RADIO_CRCSTATUS */
7353 /* Description: CRC status */
7354 
7355 /* Bit 0 : CRC status of packet received */
7356 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
7357 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
7358 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
7359 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
7360 
7361 /* Register: RADIO_RXMATCH */
7362 /* Description: Received address */
7363 
7364 /* Bits 2..0 : Received address */
7365 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
7366 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
7367 
7368 /* Register: RADIO_RXCRC */
7369 /* Description: CRC field of previously received packet */
7370 
7371 /* Bits 23..0 : CRC field of previously received packet */
7372 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
7373 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
7374 
7375 /* Register: RADIO_DAI */
7376 /* Description: Device address match index */
7377 
7378 /* Bits 2..0 : Device address match index */
7379 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
7380 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
7381 
7382 /* Register: RADIO_PDUSTAT */
7383 /* Description: Payload status */
7384 
7385 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
7386 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
7387 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
7388 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */
7389 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */
7390 
7391 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
7392 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
7393 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
7394 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
7395 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
7396 
7397 /* Register: RADIO_CTESTATUS */
7398 /* Description: CTEInfo parsed from received packet */
7399 
7400 /* Bits 7..6 : CTEType parsed from packet */
7401 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
7402 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
7403 
7404 /* Bit 5 : RFU parsed from packet */
7405 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
7406 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
7407 
7408 /* Bits 4..0 : CTETime parsed from packet */
7409 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
7410 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
7411 
7412 /* Register: RADIO_DFESTATUS */
7413 /* Description: DFE status information */
7414 
7415 /* Bit 4 : Internal state of sampling state machine */
7416 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
7417 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
7418 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
7419 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
7420 
7421 /* Bits 2..0 : Internal state of switching state machine */
7422 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
7423 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
7424 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
7425 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
7426 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
7427 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
7428 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
7429 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
7430 
7431 /* Register: RADIO_PACKETPTR */
7432 /* Description: Packet pointer */
7433 
7434 /* Bits 31..0 : Packet pointer */
7435 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
7436 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
7437 
7438 /* Register: RADIO_FREQUENCY */
7439 /* Description: Frequency */
7440 
7441 /* Bit 8 : Channel map selection */
7442 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
7443 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
7444 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */
7445 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */
7446 
7447 /* Bits 6..0 : Radio channel frequency */
7448 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7449 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7450 
7451 /* Register: RADIO_TXPOWER */
7452 /* Description: Output power */
7453 
7454 /* Bits 7..0 : RADIO output power */
7455 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
7456 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
7457 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
7458 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
7459 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
7460 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
7461 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
7462 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
7463 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
7464 #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0xF9UL) /*!< -7 dBm */
7465 #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0xFAUL) /*!< -6 dBm */
7466 #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0xFBUL) /*!< -5 dBm */
7467 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
7468 #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0xFDUL) /*!< -3 dBm */
7469 #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL) /*!< -2 dBm */
7470 #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL) /*!< -1 dBm */
7471 
7472 /* Register: RADIO_MODE */
7473 /* Description: Data rate and modulation */
7474 
7475 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
7476 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
7477 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
7478 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
7479 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
7480 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
7481 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
7482 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */
7483 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */
7484 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
7485 
7486 /* Register: RADIO_PCNF0 */
7487 /* Description: Packet configuration register 0 */
7488 
7489 /* Bits 30..29 : Length of TERM field in Long Range operation */
7490 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
7491 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
7492 
7493 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
7494 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
7495 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
7496 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
7497 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
7498 
7499 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
7500 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
7501 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
7502 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
7503 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
7504 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
7505 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */
7506 
7507 /* Bits 23..22 : Length of code indicator - Long Range */
7508 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
7509 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
7510 
7511 /* Bit 20 : Include or exclude S1 field in RAM */
7512 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
7513 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
7514 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
7515 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
7516 
7517 /* Bits 19..16 : Length on air of S1 field in number of bits */
7518 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
7519 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
7520 
7521 /* Bit 8 : Length on air of S0 field in number of bytes */
7522 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
7523 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
7524 
7525 /* Bits 3..0 : Length on air of LENGTH field in number of bits */
7526 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
7527 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
7528 
7529 /* Register: RADIO_PCNF1 */
7530 /* Description: Packet configuration register 1 */
7531 
7532 /* Bit 25 : Enable or disable packet whitening */
7533 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
7534 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
7535 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
7536 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
7537 
7538 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
7539 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
7540 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
7541 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
7542 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
7543 
7544 /* Bits 18..16 : Base address length in number of bytes */
7545 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
7546 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
7547 
7548 /* Bits 15..8 : Static length in number of bytes */
7549 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
7550 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
7551 
7552 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
7553 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
7554 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
7555 
7556 /* Register: RADIO_BASE0 */
7557 /* Description: Base address 0 */
7558 
7559 /* Bits 31..0 : Base address 0 */
7560 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
7561 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
7562 
7563 /* Register: RADIO_BASE1 */
7564 /* Description: Base address 1 */
7565 
7566 /* Bits 31..0 : Base address 1 */
7567 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
7568 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
7569 
7570 /* Register: RADIO_PREFIX0 */
7571 /* Description: Prefixes bytes for logical addresses 0-3 */
7572 
7573 /* Bits 31..24 : Address prefix 3. */
7574 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
7575 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
7576 
7577 /* Bits 23..16 : Address prefix 2. */
7578 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
7579 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
7580 
7581 /* Bits 15..8 : Address prefix 1. */
7582 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
7583 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
7584 
7585 /* Bits 7..0 : Address prefix 0. */
7586 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
7587 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
7588 
7589 /* Register: RADIO_PREFIX1 */
7590 /* Description: Prefixes bytes for logical addresses 4-7 */
7591 
7592 /* Bits 31..24 : Address prefix 7. */
7593 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
7594 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
7595 
7596 /* Bits 23..16 : Address prefix 6. */
7597 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
7598 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
7599 
7600 /* Bits 15..8 : Address prefix 5. */
7601 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
7602 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
7603 
7604 /* Bits 7..0 : Address prefix 4. */
7605 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
7606 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
7607 
7608 /* Register: RADIO_TXADDRESS */
7609 /* Description: Transmit address select */
7610 
7611 /* Bits 2..0 : Transmit address select */
7612 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
7613 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
7614 
7615 /* Register: RADIO_RXADDRESSES */
7616 /* Description: Receive address select */
7617 
7618 /* Bit 7 : Enable or disable reception on logical address 7. */
7619 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
7620 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
7621 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
7622 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
7623 
7624 /* Bit 6 : Enable or disable reception on logical address 6. */
7625 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
7626 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
7627 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
7628 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
7629 
7630 /* Bit 5 : Enable or disable reception on logical address 5. */
7631 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
7632 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
7633 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
7634 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
7635 
7636 /* Bit 4 : Enable or disable reception on logical address 4. */
7637 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
7638 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
7639 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
7640 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
7641 
7642 /* Bit 3 : Enable or disable reception on logical address 3. */
7643 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
7644 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
7645 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
7646 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
7647 
7648 /* Bit 2 : Enable or disable reception on logical address 2. */
7649 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
7650 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
7651 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
7652 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
7653 
7654 /* Bit 1 : Enable or disable reception on logical address 1. */
7655 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
7656 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
7657 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
7658 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
7659 
7660 /* Bit 0 : Enable or disable reception on logical address 0. */
7661 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
7662 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
7663 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
7664 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
7665 
7666 /* Register: RADIO_CRCCNF */
7667 /* Description: CRC configuration */
7668 
7669 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
7670 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
7671 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
7672 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
7673 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
7674 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
7675 
7676 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */
7677 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
7678 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
7679 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
7680 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
7681 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
7682 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
7683 
7684 /* Register: RADIO_CRCPOLY */
7685 /* Description: CRC polynomial */
7686 
7687 /* Bits 23..0 : CRC polynomial */
7688 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
7689 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
7690 
7691 /* Register: RADIO_CRCINIT */
7692 /* Description: CRC initial value */
7693 
7694 /* Bits 23..0 : CRC initial value */
7695 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
7696 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
7697 
7698 /* Register: RADIO_TIFS */
7699 /* Description: Interframe spacing in us */
7700 
7701 /* Bits 9..0 : Interframe spacing in us. */
7702 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
7703 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
7704 
7705 /* Register: RADIO_RSSISAMPLE */
7706 /* Description: RSSI sample */
7707 
7708 /* Bits 6..0 : RSSI sample. */
7709 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
7710 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
7711 
7712 /* Register: RADIO_STATE */
7713 /* Description: Current radio state */
7714 
7715 /* Bits 3..0 : Current radio state */
7716 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
7717 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
7718 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
7719 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
7720 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
7721 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
7722 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
7723 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
7724 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
7725 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
7726 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
7727 
7728 /* Register: RADIO_DATAWHITEIV */
7729 /* Description: Data whitening initial value */
7730 
7731 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
7732 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
7733 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
7734 
7735 /* Register: RADIO_BCC */
7736 /* Description: Bit counter compare */
7737 
7738 /* Bits 31..0 : Bit counter compare */
7739 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
7740 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
7741 
7742 /* Register: RADIO_DAB */
7743 /* Description: Description collection: Device address base segment n */
7744 
7745 /* Bits 31..0 : Device address base segment n */
7746 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
7747 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
7748 
7749 /* Register: RADIO_DAP */
7750 /* Description: Description collection: Device address prefix n */
7751 
7752 /* Bits 15..0 : Device address prefix n */
7753 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
7754 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
7755 
7756 /* Register: RADIO_DACNF */
7757 /* Description: Device address match configuration */
7758 
7759 /* Bit 15 : TxAdd for device address 7 */
7760 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
7761 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
7762 
7763 /* Bit 14 : TxAdd for device address 6 */
7764 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
7765 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
7766 
7767 /* Bit 13 : TxAdd for device address 5 */
7768 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
7769 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
7770 
7771 /* Bit 12 : TxAdd for device address 4 */
7772 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
7773 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
7774 
7775 /* Bit 11 : TxAdd for device address 3 */
7776 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
7777 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
7778 
7779 /* Bit 10 : TxAdd for device address 2 */
7780 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
7781 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
7782 
7783 /* Bit 9 : TxAdd for device address 1 */
7784 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
7785 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
7786 
7787 /* Bit 8 : TxAdd for device address 0 */
7788 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
7789 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
7790 
7791 /* Bit 7 : Enable or disable device address matching using device address 7 */
7792 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
7793 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
7794 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
7795 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
7796 
7797 /* Bit 6 : Enable or disable device address matching using device address 6 */
7798 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
7799 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
7800 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
7801 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
7802 
7803 /* Bit 5 : Enable or disable device address matching using device address 5 */
7804 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
7805 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
7806 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
7807 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
7808 
7809 /* Bit 4 : Enable or disable device address matching using device address 4 */
7810 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
7811 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
7812 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
7813 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
7814 
7815 /* Bit 3 : Enable or disable device address matching using device address 3 */
7816 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
7817 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
7818 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
7819 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
7820 
7821 /* Bit 2 : Enable or disable device address matching using device address 2 */
7822 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
7823 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
7824 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
7825 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
7826 
7827 /* Bit 1 : Enable or disable device address matching using device address 1 */
7828 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
7829 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
7830 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
7831 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
7832 
7833 /* Bit 0 : Enable or disable device address matching using device address 0 */
7834 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
7835 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
7836 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
7837 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
7838 
7839 /* Register: RADIO_MHRMATCHCONF */
7840 /* Description: Search pattern configuration */
7841 
7842 /* Bits 31..0 : Search pattern configuration */
7843 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
7844 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
7845 
7846 /* Register: RADIO_MHRMATCHMAS */
7847 /* Description: Pattern mask */
7848 
7849 /* Bits 31..0 : Pattern mask */
7850 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
7851 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
7852 
7853 /* Register: RADIO_MODECNF0 */
7854 /* Description: Radio mode configuration register 0 */
7855 
7856 /* Bits 9..8 : Default TX value */
7857 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
7858 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
7859 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
7860 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
7861 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
7862 
7863 /* Bit 0 : Radio ramp-up time */
7864 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
7865 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
7866 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
7867 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */
7868 
7869 /* Register: RADIO_SFD */
7870 /* Description: IEEE 802.15.4 start of frame delimiter */
7871 
7872 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
7873 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
7874 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
7875 
7876 /* Register: RADIO_EDCNT */
7877 /* Description: IEEE 802.15.4 energy detect loop count */
7878 
7879 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
7880 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
7881 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
7882 
7883 /* Register: RADIO_EDSAMPLE */
7884 /* Description: IEEE 802.15.4 energy detect level */
7885 
7886 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
7887 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
7888 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
7889 
7890 /* Register: RADIO_CCACTRL */
7891 /* Description: IEEE 802.15.4 clear channel assessment control */
7892 
7893 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
7894 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
7895 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
7896 
7897 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
7898 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
7899 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
7900 
7901 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
7902 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
7903 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
7904 
7905 /* Bits 2..0 : CCA mode of operation */
7906 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
7907 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
7908 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
7909 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
7910 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
7911 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
7912 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
7913 
7914 /* Register: RADIO_DFEMODE */
7915 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
7916 
7917 /* Bits 1..0 : Direction finding operation mode */
7918 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
7919 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
7920 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
7921 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
7922 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
7923 
7924 /* Register: RADIO_CTEINLINECONF */
7925 /* Description: Configuration for CTE inline mode */
7926 
7927 /* Bits 31..24 : S0 bit mask to set which bit to match */
7928 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
7929 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
7930 
7931 /* Bits 23..16 : S0 bit pattern to match */
7932 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
7933 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
7934 
7935 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
7936 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
7937 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
7938 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */
7939 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */
7940 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */
7941 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */
7942 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */
7943 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */
7944 
7945 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
7946 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
7947 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
7948 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */
7949 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */
7950 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */
7951 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */
7952 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */
7953 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */
7954 
7955 /* Bits 7..6 : Max range of CTETime */
7956 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
7957 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
7958 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */
7959 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */
7960 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */
7961 
7962 /* Bit 4 : Sampling/switching if CRC is not OK */
7963 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
7964 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
7965 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
7966 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
7967 
7968 /* Bit 3 : CTEInfo is S1 byte or not */
7969 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
7970 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
7971 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
7972 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
7973 
7974 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
7975 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
7976 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
7977 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
7978 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
7979 
7980 /* Register: RADIO_DFECTRL1 */
7981 /* Description: Various configuration for Direction finding */
7982 
7983 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
7984 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
7985 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
7986 
7987 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */
7988 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */
7989 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */
7990 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */
7991 
7992 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
7993 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
7994 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
7995 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */
7996 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */
7997 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */
7998 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */
7999 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */
8000 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */
8001 
8002 /* Bit 15 : Whether to sample I/Q or magnitude/phase */
8003 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
8004 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
8005 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
8006 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
8007 
8008 /* Bits 14..12 : Interval between samples in the REFERENCE period */
8009 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
8010 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
8011 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */
8012 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */
8013 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */
8014 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */
8015 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */
8016 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */
8017 
8018 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
8019 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
8020 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
8021 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */
8022 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */
8023 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */
8024 
8025 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
8026 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
8027 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
8028 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
8029 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
8030 
8031 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
8032 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
8033 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
8034 
8035 /* Register: RADIO_DFECTRL2 */
8036 /* Description: Start offset for Direction finding */
8037 
8038 /* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */
8039 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
8040 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
8041 
8042 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */
8043 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
8044 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
8045 
8046 /* Register: RADIO_SWITCHPATTERN */
8047 /* Description: GPIO patterns to be used for each antenna */
8048 
8049 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */
8050 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
8051 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
8052 
8053 /* Register: RADIO_CLEARPATTERN */
8054 /* Description: Clear the GPIO pattern array for antenna control */
8055 
8056 /* Bit 0 : Clears GPIO pattern array for antenna control */
8057 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
8058 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
8059 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
8060 
8061 /* Register: RADIO_PSEL_DFEGPIO */
8062 /* Description: Description collection: Pin select for DFE pin n */
8063 
8064 /* Bit 31 : Connection */
8065 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8066 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8067 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
8068 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
8069 
8070 /* Bit 5 : Port number */
8071 #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */
8072 #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */
8073 
8074 /* Bits 4..0 : Pin number */
8075 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
8076 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
8077 
8078 /* Register: RADIO_DFEPACKET_PTR */
8079 /* Description: Data pointer */
8080 
8081 /* Bits 31..0 : Data pointer */
8082 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8083 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8084 
8085 /* Register: RADIO_DFEPACKET_MAXCNT */
8086 /* Description: Maximum number of buffer words to transfer */
8087 
8088 /* Bits 13..0 : Maximum number of buffer words to transfer */
8089 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
8090 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
8091 
8092 /* Register: RADIO_DFEPACKET_AMOUNT */
8093 /* Description: Number of samples transferred in the last transaction */
8094 
8095 /* Bits 15..0 : Number of samples transferred in the last transaction */
8096 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
8097 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
8098 
8099 /* Register: RADIO_POWER */
8100 /* Description: Peripheral power control */
8101 
8102 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
8103 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
8104 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
8105 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
8106 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
8107 
8108 
8109 /* Peripheral: RESET */
8110 /* Description: Reset control */
8111 
8112 /* Register: RESET_RESETREAS */
8113 /* Description: Reset reason */
8114 
8115 /* Bit 27 : Reset from network CTRL-AP detected */
8116 #define RESET_RESETREAS_LCTRLAP_Pos (27UL) /*!< Position of LCTRLAP field. */
8117 #define RESET_RESETREAS_LCTRLAP_Msk (0x1UL << RESET_RESETREAS_LCTRLAP_Pos) /*!< Bit mask of LCTRLAP field. */
8118 #define RESET_RESETREAS_LCTRLAP_NotDetected (0UL) /*!< Not detected */
8119 #define RESET_RESETREAS_LCTRLAP_Detected (1UL) /*!< Detected */
8120 
8121 /* Bit 26 : Reset after wakeup from System OFF mode due to VBUS rising into valid range */
8122 #define RESET_RESETREAS_VBUS_Pos (26UL) /*!< Position of VBUS field. */
8123 #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
8124 #define RESET_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
8125 #define RESET_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
8126 
8127 /* Bit 25 : Reset from application watchdog timer 1 detected */
8128 #define RESET_RESETREAS_DOG1_Pos (25UL) /*!< Position of DOG1 field. */
8129 #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos) /*!< Bit mask of DOG1 field. */
8130 #define RESET_RESETREAS_DOG1_NotDetected (0UL) /*!< Not detected */
8131 #define RESET_RESETREAS_DOG1_Detected (1UL) /*!< Detected */
8132 
8133 /* Bit 24 : Reset after wakeup from System OFF mode due to NFC field being detected */
8134 #define RESET_RESETREAS_NFC_Pos (24UL) /*!< Position of NFC field. */
8135 #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
8136 #define RESET_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
8137 #define RESET_RESETREAS_NFC_Detected (1UL) /*!< Detected */
8138 
8139 /* Bit 23 : Force-OFF reset from application core detected */
8140 #define RESET_RESETREAS_MFORCEOFF_Pos (23UL) /*!< Position of MFORCEOFF field. */
8141 #define RESET_RESETREAS_MFORCEOFF_Msk (0x1UL << RESET_RESETREAS_MFORCEOFF_Pos) /*!< Bit mask of MFORCEOFF field. */
8142 #define RESET_RESETREAS_MFORCEOFF_NotDetected (0UL) /*!< Not detected */
8143 #define RESET_RESETREAS_MFORCEOFF_Detected (1UL) /*!< Detected */
8144 
8145 /* Bit 18 : Reset from network watchdog timer detected */
8146 #define RESET_RESETREAS_LDOG_Pos (18UL) /*!< Position of LDOG field. */
8147 #define RESET_RESETREAS_LDOG_Msk (0x1UL << RESET_RESETREAS_LDOG_Pos) /*!< Bit mask of LDOG field. */
8148 #define RESET_RESETREAS_LDOG_NotDetected (0UL) /*!< Not detected */
8149 #define RESET_RESETREAS_LDOG_Detected (1UL) /*!< Detected */
8150 
8151 /* Bit 17 : Reset from network CPU lockup detected */
8152 #define RESET_RESETREAS_LLOCKUP_Pos (17UL) /*!< Position of LLOCKUP field. */
8153 #define RESET_RESETREAS_LLOCKUP_Msk (0x1UL << RESET_RESETREAS_LLOCKUP_Pos) /*!< Bit mask of LLOCKUP field. */
8154 #define RESET_RESETREAS_LLOCKUP_NotDetected (0UL) /*!< Not detected */
8155 #define RESET_RESETREAS_LLOCKUP_Detected (1UL) /*!< Detected */
8156 
8157 /* Bit 16 : Reset from network soft reset detected */
8158 #define RESET_RESETREAS_LSREQ_Pos (16UL) /*!< Position of LSREQ field. */
8159 #define RESET_RESETREAS_LSREQ_Msk (0x1UL << RESET_RESETREAS_LSREQ_Pos) /*!< Bit mask of LSREQ field. */
8160 #define RESET_RESETREAS_LSREQ_NotDetected (0UL) /*!< Not detected */
8161 #define RESET_RESETREAS_LSREQ_Detected (1UL) /*!< Detected */
8162 
8163 /* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode */
8164 #define RESET_RESETREAS_DIF_Pos (7UL) /*!< Position of DIF field. */
8165 #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
8166 #define RESET_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
8167 #define RESET_RESETREAS_DIF_Detected (1UL) /*!< Detected */
8168 
8169 /* Bit 6 : Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP */
8170 #define RESET_RESETREAS_LPCOMP_Pos (6UL) /*!< Position of LPCOMP field. */
8171 #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
8172 #define RESET_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
8173 #define RESET_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
8174 
8175 /* Bit 5 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO */
8176 #define RESET_RESETREAS_OFF_Pos (5UL) /*!< Position of OFF field. */
8177 #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
8178 #define RESET_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
8179 #define RESET_RESETREAS_OFF_Detected (1UL) /*!< Detected */
8180 
8181 /* Bit 4 : Reset from application CPU lockup detected */
8182 #define RESET_RESETREAS_LOCKUP_Pos (4UL) /*!< Position of LOCKUP field. */
8183 #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
8184 #define RESET_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
8185 #define RESET_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
8186 
8187 /* Bit 3 : Reset from application soft reset detected */
8188 #define RESET_RESETREAS_SREQ_Pos (3UL) /*!< Position of SREQ field. */
8189 #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
8190 #define RESET_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
8191 #define RESET_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
8192 
8193 /* Bit 2 : Reset from application CTRL-AP detected */
8194 #define RESET_RESETREAS_CTRLAP_Pos (2UL) /*!< Position of CTRLAP field. */
8195 #define RESET_RESETREAS_CTRLAP_Msk (0x1UL << RESET_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
8196 #define RESET_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */
8197 #define RESET_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
8198 
8199 /* Bit 1 : Reset from application watchdog timer 0 detected */
8200 #define RESET_RESETREAS_DOG0_Pos (1UL) /*!< Position of DOG0 field. */
8201 #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos) /*!< Bit mask of DOG0 field. */
8202 #define RESET_RESETREAS_DOG0_NotDetected (0UL) /*!< Not detected */
8203 #define RESET_RESETREAS_DOG0_Detected (1UL) /*!< Detected */
8204 
8205 /* Bit 0 : Reset from pin reset detected */
8206 #define RESET_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
8207 #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
8208 #define RESET_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
8209 #define RESET_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
8210 
8211 
8212 /* Peripheral: RNG */
8213 /* Description: Random Number Generator */
8214 
8215 /* Register: RNG_TASKS_START */
8216 /* Description: Task starting the random number generator */
8217 
8218 /* Bit 0 : Task starting the random number generator */
8219 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8220 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8221 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8222 
8223 /* Register: RNG_TASKS_STOP */
8224 /* Description: Task stopping the random number generator */
8225 
8226 /* Bit 0 : Task stopping the random number generator */
8227 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8228 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8229 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8230 
8231 /* Register: RNG_SUBSCRIBE_START */
8232 /* Description: Subscribe configuration for task START */
8233 
8234 /* Bit 31 :   */
8235 #define RNG_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8236 #define RNG_SUBSCRIBE_START_EN_Msk (0x1UL << RNG_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8237 #define RNG_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8238 #define RNG_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8239 
8240 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8241 #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8242 #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8243 
8244 /* Register: RNG_SUBSCRIBE_STOP */
8245 /* Description: Subscribe configuration for task STOP */
8246 
8247 /* Bit 31 :   */
8248 #define RNG_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8249 #define RNG_SUBSCRIBE_STOP_EN_Msk (0x1UL << RNG_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8250 #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8251 #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8252 
8253 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8254 #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8255 #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8256 
8257 /* Register: RNG_EVENTS_VALRDY */
8258 /* Description: Event being generated for every new random number written to the VALUE register */
8259 
8260 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
8261 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
8262 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
8263 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
8264 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
8265 
8266 /* Register: RNG_PUBLISH_VALRDY */
8267 /* Description: Publish configuration for event VALRDY */
8268 
8269 /* Bit 31 :   */
8270 #define RNG_PUBLISH_VALRDY_EN_Pos (31UL) /*!< Position of EN field. */
8271 #define RNG_PUBLISH_VALRDY_EN_Msk (0x1UL << RNG_PUBLISH_VALRDY_EN_Pos) /*!< Bit mask of EN field. */
8272 #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL) /*!< Disable publishing */
8273 #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL) /*!< Enable publishing */
8274 
8275 /* Bits 7..0 : DPPI channel that event VALRDY will publish to. */
8276 #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8277 #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8278 
8279 /* Register: RNG_SHORTS */
8280 /* Description: Shortcuts between local events and tasks */
8281 
8282 /* Bit 0 : Shortcut between event VALRDY and task STOP */
8283 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
8284 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
8285 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8286 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8287 
8288 /* Register: RNG_INTENSET */
8289 /* Description: Enable interrupt */
8290 
8291 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
8292 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
8293 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
8294 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
8295 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
8296 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
8297 
8298 /* Register: RNG_INTENCLR */
8299 /* Description: Disable interrupt */
8300 
8301 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
8302 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
8303 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
8304 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
8305 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
8306 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
8307 
8308 /* Register: RNG_CONFIG */
8309 /* Description: Configuration register */
8310 
8311 /* Bit 0 : Bias correction */
8312 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
8313 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
8314 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
8315 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
8316 
8317 /* Register: RNG_VALUE */
8318 /* Description: Output random number */
8319 
8320 /* Bits 7..0 : Generated random number */
8321 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
8322 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
8323 
8324 
8325 /* Peripheral: RTC */
8326 /* Description: Real-time counter 0 */
8327 
8328 /* Register: RTC_TASKS_START */
8329 /* Description: Start RTC counter */
8330 
8331 /* Bit 0 : Start RTC counter */
8332 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8333 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8334 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8335 
8336 /* Register: RTC_TASKS_STOP */
8337 /* Description: Stop RTC counter */
8338 
8339 /* Bit 0 : Stop RTC counter */
8340 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8341 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8342 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8343 
8344 /* Register: RTC_TASKS_CLEAR */
8345 /* Description: Clear RTC counter */
8346 
8347 /* Bit 0 : Clear RTC counter */
8348 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
8349 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
8350 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8351 
8352 /* Register: RTC_TASKS_TRIGOVRFLW */
8353 /* Description: Set counter to 0xFFFFF0 */
8354 
8355 /* Bit 0 : Set counter to 0xFFFFF0 */
8356 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
8357 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
8358 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
8359 
8360 /* Register: RTC_TASKS_CAPTURE */
8361 /* Description: Description collection: Capture RTC counter to CC[n] register */
8362 
8363 /* Bit 0 : Capture RTC counter to CC[n] register */
8364 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
8365 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
8366 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8367 
8368 /* Register: RTC_SUBSCRIBE_START */
8369 /* Description: Subscribe configuration for task START */
8370 
8371 /* Bit 31 :   */
8372 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8373 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8374 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8375 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8376 
8377 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8378 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8379 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8380 
8381 /* Register: RTC_SUBSCRIBE_STOP */
8382 /* Description: Subscribe configuration for task STOP */
8383 
8384 /* Bit 31 :   */
8385 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8386 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8387 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8388 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8389 
8390 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8391 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8392 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8393 
8394 /* Register: RTC_SUBSCRIBE_CLEAR */
8395 /* Description: Subscribe configuration for task CLEAR */
8396 
8397 /* Bit 31 :   */
8398 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
8399 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
8400 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
8401 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
8402 
8403 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
8404 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8405 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8406 
8407 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
8408 /* Description: Subscribe configuration for task TRIGOVRFLW */
8409 
8410 /* Bit 31 :   */
8411 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
8412 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
8413 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
8414 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
8415 
8416 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
8417 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8418 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8419 
8420 /* Register: RTC_SUBSCRIBE_CAPTURE */
8421 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
8422 
8423 /* Bit 31 :   */
8424 #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
8425 #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
8426 #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
8427 #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
8428 
8429 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
8430 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8431 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8432 
8433 /* Register: RTC_EVENTS_TICK */
8434 /* Description: Event on counter increment */
8435 
8436 /* Bit 0 : Event on counter increment */
8437 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
8438 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
8439 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
8440 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
8441 
8442 /* Register: RTC_EVENTS_OVRFLW */
8443 /* Description: Event on counter overflow */
8444 
8445 /* Bit 0 : Event on counter overflow */
8446 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
8447 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
8448 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
8449 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
8450 
8451 /* Register: RTC_EVENTS_COMPARE */
8452 /* Description: Description collection: Compare event on CC[n] match */
8453 
8454 /* Bit 0 : Compare event on CC[n] match */
8455 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
8456 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
8457 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
8458 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8459 
8460 /* Register: RTC_PUBLISH_TICK */
8461 /* Description: Publish configuration for event TICK */
8462 
8463 /* Bit 31 :   */
8464 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
8465 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
8466 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
8467 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
8468 
8469 /* Bits 7..0 : DPPI channel that event TICK will publish to. */
8470 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8471 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8472 
8473 /* Register: RTC_PUBLISH_OVRFLW */
8474 /* Description: Publish configuration for event OVRFLW */
8475 
8476 /* Bit 31 :   */
8477 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
8478 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
8479 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
8480 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
8481 
8482 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */
8483 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8484 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8485 
8486 /* Register: RTC_PUBLISH_COMPARE */
8487 /* Description: Description collection: Publish configuration for event COMPARE[n] */
8488 
8489 /* Bit 31 :   */
8490 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
8491 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
8492 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
8493 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
8494 
8495 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
8496 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8497 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8498 
8499 /* Register: RTC_SHORTS */
8500 /* Description: Shortcuts between local events and tasks */
8501 
8502 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
8503 #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
8504 #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
8505 #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8506 #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8507 
8508 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8509 #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8510 #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
8511 #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8512 #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8513 
8514 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8515 #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8516 #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
8517 #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8518 #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8519 
8520 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
8521 #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
8522 #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
8523 #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8524 #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8525 
8526 /* Register: RTC_INTENSET */
8527 /* Description: Enable interrupt */
8528 
8529 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8530 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8531 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8532 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8533 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8534 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8535 
8536 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8537 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8538 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8539 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8540 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8541 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8542 
8543 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8544 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8545 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8546 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8547 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8548 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8549 
8550 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8551 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8552 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8553 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8554 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8555 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8556 
8557 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
8558 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
8559 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
8560 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
8561 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
8562 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
8563 
8564 /* Bit 0 : Write '1' to enable interrupt for event TICK */
8565 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
8566 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
8567 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
8568 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
8569 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
8570 
8571 /* Register: RTC_INTENCLR */
8572 /* Description: Disable interrupt */
8573 
8574 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8575 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8576 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8577 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8578 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8579 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8580 
8581 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8582 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8583 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8584 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8585 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8586 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8587 
8588 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8589 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8590 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8591 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8592 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8593 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8594 
8595 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8596 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8597 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8598 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8599 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8600 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8601 
8602 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
8603 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
8604 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
8605 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
8606 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
8607 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
8608 
8609 /* Bit 0 : Write '1' to disable interrupt for event TICK */
8610 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
8611 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
8612 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
8613 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
8614 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
8615 
8616 /* Register: RTC_EVTEN */
8617 /* Description: Enable or disable event routing */
8618 
8619 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
8620 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8621 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8622 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
8623 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
8624 
8625 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
8626 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8627 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8628 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
8629 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
8630 
8631 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
8632 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8633 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8634 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
8635 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
8636 
8637 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
8638 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8639 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8640 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
8641 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
8642 
8643 /* Bit 1 : Enable or disable event routing for event OVRFLW */
8644 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
8645 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
8646 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
8647 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
8648 
8649 /* Bit 0 : Enable or disable event routing for event TICK */
8650 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
8651 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
8652 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
8653 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
8654 
8655 /* Register: RTC_EVTENSET */
8656 /* Description: Enable event routing */
8657 
8658 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
8659 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8660 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8661 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8662 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8663 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
8664 
8665 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
8666 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8667 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8668 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8669 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8670 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
8671 
8672 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
8673 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8674 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8675 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8676 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8677 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
8678 
8679 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
8680 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8681 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8682 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8683 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8684 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
8685 
8686 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
8687 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
8688 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
8689 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
8690 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
8691 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
8692 
8693 /* Bit 0 : Write '1' to enable event routing for event TICK */
8694 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
8695 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
8696 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
8697 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
8698 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
8699 
8700 /* Register: RTC_EVTENCLR */
8701 /* Description: Disable event routing */
8702 
8703 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
8704 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8705 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8706 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8707 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8708 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8709 
8710 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
8711 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8712 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8713 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8714 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8715 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8716 
8717 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
8718 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8719 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8720 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8721 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8722 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8723 
8724 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
8725 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8726 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8727 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8728 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8729 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8730 
8731 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
8732 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
8733 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
8734 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
8735 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
8736 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
8737 
8738 /* Bit 0 : Write '1' to disable event routing for event TICK */
8739 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
8740 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
8741 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
8742 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
8743 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
8744 
8745 /* Register: RTC_COUNTER */
8746 /* Description: Current counter value */
8747 
8748 /* Bits 23..0 : Counter value */
8749 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
8750 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
8751 
8752 /* Register: RTC_PRESCALER */
8753 /* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */
8754 
8755 /* Bits 11..0 : Prescaler value */
8756 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8757 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8758 
8759 /* Register: RTC_CC */
8760 /* Description: Description collection: Compare register n */
8761 
8762 /* Bits 23..0 : Compare value */
8763 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
8764 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
8765 
8766 
8767 /* Peripheral: SPIM */
8768 /* Description: Serial Peripheral Interface Master with EasyDMA */
8769 
8770 /* Register: SPIM_TASKS_START */
8771 /* Description: Start SPI transaction */
8772 
8773 /* Bit 0 : Start SPI transaction */
8774 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8775 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8776 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8777 
8778 /* Register: SPIM_TASKS_STOP */
8779 /* Description: Stop SPI transaction */
8780 
8781 /* Bit 0 : Stop SPI transaction */
8782 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8783 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8784 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8785 
8786 /* Register: SPIM_TASKS_SUSPEND */
8787 /* Description: Suspend SPI transaction */
8788 
8789 /* Bit 0 : Suspend SPI transaction */
8790 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8791 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8792 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8793 
8794 /* Register: SPIM_TASKS_RESUME */
8795 /* Description: Resume SPI transaction */
8796 
8797 /* Bit 0 : Resume SPI transaction */
8798 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8799 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8800 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8801 
8802 /* Register: SPIM_SUBSCRIBE_START */
8803 /* Description: Subscribe configuration for task START */
8804 
8805 /* Bit 31 :   */
8806 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8807 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8808 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8809 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8810 
8811 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8812 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8813 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8814 
8815 /* Register: SPIM_SUBSCRIBE_STOP */
8816 /* Description: Subscribe configuration for task STOP */
8817 
8818 /* Bit 31 :   */
8819 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8820 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8821 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8822 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8823 
8824 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8825 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8826 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8827 
8828 /* Register: SPIM_SUBSCRIBE_SUSPEND */
8829 /* Description: Subscribe configuration for task SUSPEND */
8830 
8831 /* Bit 31 :   */
8832 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
8833 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
8834 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
8835 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
8836 
8837 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
8838 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8839 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8840 
8841 /* Register: SPIM_SUBSCRIBE_RESUME */
8842 /* Description: Subscribe configuration for task RESUME */
8843 
8844 /* Bit 31 :   */
8845 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
8846 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
8847 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
8848 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
8849 
8850 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
8851 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8852 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8853 
8854 /* Register: SPIM_EVENTS_STOPPED */
8855 /* Description: SPI transaction has stopped */
8856 
8857 /* Bit 0 : SPI transaction has stopped */
8858 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8859 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8860 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8861 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8862 
8863 /* Register: SPIM_EVENTS_ENDRX */
8864 /* Description: End of RXD buffer reached */
8865 
8866 /* Bit 0 : End of RXD buffer reached */
8867 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
8868 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
8869 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
8870 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
8871 
8872 /* Register: SPIM_EVENTS_END */
8873 /* Description: End of RXD buffer and TXD buffer reached */
8874 
8875 /* Bit 0 : End of RXD buffer and TXD buffer reached */
8876 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8877 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8878 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
8879 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
8880 
8881 /* Register: SPIM_EVENTS_ENDTX */
8882 /* Description: End of TXD buffer reached */
8883 
8884 /* Bit 0 : End of TXD buffer reached */
8885 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
8886 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
8887 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
8888 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
8889 
8890 /* Register: SPIM_EVENTS_STARTED */
8891 /* Description: Transaction started */
8892 
8893 /* Bit 0 : Transaction started */
8894 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
8895 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
8896 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
8897 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
8898 
8899 /* Register: SPIM_PUBLISH_STOPPED */
8900 /* Description: Publish configuration for event STOPPED */
8901 
8902 /* Bit 31 :   */
8903 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
8904 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
8905 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
8906 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8907 
8908 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
8909 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8910 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8911 
8912 /* Register: SPIM_PUBLISH_ENDRX */
8913 /* Description: Publish configuration for event ENDRX */
8914 
8915 /* Bit 31 :   */
8916 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
8917 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
8918 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
8919 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
8920 
8921 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
8922 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8923 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8924 
8925 /* Register: SPIM_PUBLISH_END */
8926 /* Description: Publish configuration for event END */
8927 
8928 /* Bit 31 :   */
8929 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
8930 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
8931 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
8932 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
8933 
8934 /* Bits 7..0 : DPPI channel that event END will publish to. */
8935 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8936 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8937 
8938 /* Register: SPIM_PUBLISH_ENDTX */
8939 /* Description: Publish configuration for event ENDTX */
8940 
8941 /* Bit 31 :   */
8942 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
8943 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
8944 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
8945 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
8946 
8947 /* Bits 7..0 : DPPI channel that event ENDTX will publish to. */
8948 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8949 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8950 
8951 /* Register: SPIM_PUBLISH_STARTED */
8952 /* Description: Publish configuration for event STARTED */
8953 
8954 /* Bit 31 :   */
8955 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
8956 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
8957 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
8958 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
8959 
8960 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
8961 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8962 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8963 
8964 /* Register: SPIM_SHORTS */
8965 /* Description: Shortcuts between local events and tasks */
8966 
8967 /* Bit 17 : Shortcut between event END and task START */
8968 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
8969 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
8970 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
8971 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8972 
8973 /* Register: SPIM_INTENSET */
8974 /* Description: Enable interrupt */
8975 
8976 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
8977 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
8978 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
8979 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
8980 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
8981 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
8982 
8983 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
8984 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
8985 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
8986 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
8987 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
8988 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
8989 
8990 /* Bit 6 : Write '1' to enable interrupt for event END */
8991 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
8992 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
8993 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8994 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8995 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
8996 
8997 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
8998 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
8999 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
9000 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9001 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9002 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
9003 
9004 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9005 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9006 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9007 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9008 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9009 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9010 
9011 /* Register: SPIM_INTENCLR */
9012 /* Description: Disable interrupt */
9013 
9014 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
9015 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
9016 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
9017 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
9018 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
9019 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
9020 
9021 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
9022 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
9023 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
9024 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
9025 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
9026 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
9027 
9028 /* Bit 6 : Write '1' to disable interrupt for event END */
9029 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
9030 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
9031 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9032 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9033 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
9034 
9035 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
9036 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
9037 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
9038 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9039 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9040 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
9041 
9042 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9043 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9044 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9045 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9046 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9047 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9048 
9049 /* Register: SPIM_STALLSTAT */
9050 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */
9051 
9052 /* Bit 1 : Stall status for EasyDMA RAM writes */
9053 #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
9054 #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
9055 #define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
9056 #define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
9057 
9058 /* Bit 0 : Stall status for EasyDMA RAM reads */
9059 #define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
9060 #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
9061 #define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
9062 #define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
9063 
9064 /* Register: SPIM_ENABLE */
9065 /* Description: Enable SPIM */
9066 
9067 /* Bits 3..0 : Enable or disable SPIM */
9068 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9069 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9070 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
9071 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
9072 
9073 /* Register: SPIM_PSEL_SCK */
9074 /* Description: Pin select for SCK */
9075 
9076 /* Bit 31 : Connection */
9077 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9078 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9079 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
9080 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
9081 
9082 /* Bit 5 : Port number */
9083 #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
9084 #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
9085 
9086 /* Bits 4..0 : Pin number */
9087 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
9088 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
9089 
9090 /* Register: SPIM_PSEL_MOSI */
9091 /* Description: Pin select for MOSI signal */
9092 
9093 /* Bit 31 : Connection */
9094 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9095 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9096 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
9097 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
9098 
9099 /* Bit 5 : Port number */
9100 #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
9101 #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
9102 
9103 /* Bits 4..0 : Pin number */
9104 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
9105 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
9106 
9107 /* Register: SPIM_PSEL_MISO */
9108 /* Description: Pin select for MISO signal */
9109 
9110 /* Bit 31 : Connection */
9111 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9112 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9113 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
9114 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
9115 
9116 /* Bit 5 : Port number */
9117 #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
9118 #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
9119 
9120 /* Bits 4..0 : Pin number */
9121 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
9122 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
9123 
9124 /* Register: SPIM_PSEL_CSN */
9125 /* Description: Pin select for CSN */
9126 
9127 /* Bit 31 : Connection */
9128 #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9129 #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9130 #define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
9131 #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
9132 
9133 /* Bit 5 : Port number */
9134 #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
9135 #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
9136 
9137 /* Bits 4..0 : Pin number */
9138 #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
9139 #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
9140 
9141 /* Register: SPIM_FREQUENCY */
9142 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
9143 
9144 /* Bits 31..0 : SPI master data rate */
9145 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9146 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9147 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
9148 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9149 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
9150 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
9151 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
9152 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
9153 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
9154 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
9155 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
9156 
9157 /* Register: SPIM_RXD_PTR */
9158 /* Description: Data pointer */
9159 
9160 /* Bits 31..0 : Data pointer */
9161 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9162 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9163 
9164 /* Register: SPIM_RXD_MAXCNT */
9165 /* Description: Maximum number of bytes in receive buffer */
9166 
9167 /* Bits 15..0 : Maximum number of bytes in receive buffer */
9168 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9169 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9170 
9171 /* Register: SPIM_RXD_AMOUNT */
9172 /* Description: Number of bytes transferred in the last transaction */
9173 
9174 /* Bits 15..0 : Number of bytes transferred in the last transaction */
9175 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9176 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9177 
9178 /* Register: SPIM_RXD_LIST */
9179 /* Description: EasyDMA list type */
9180 
9181 /* Bits 1..0 : List type */
9182 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9183 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9184 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9185 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9186 
9187 /* Register: SPIM_TXD_PTR */
9188 /* Description: Data pointer */
9189 
9190 /* Bits 31..0 : Data pointer */
9191 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9192 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9193 
9194 /* Register: SPIM_TXD_MAXCNT */
9195 /* Description: Number of bytes in transmit buffer */
9196 
9197 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
9198 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9199 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9200 
9201 /* Register: SPIM_TXD_AMOUNT */
9202 /* Description: Number of bytes transferred in the last transaction */
9203 
9204 /* Bits 15..0 : Number of bytes transferred in the last transaction */
9205 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9206 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9207 
9208 /* Register: SPIM_TXD_LIST */
9209 /* Description: EasyDMA list type */
9210 
9211 /* Bits 1..0 : List type */
9212 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9213 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9214 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9215 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9216 
9217 /* Register: SPIM_CONFIG */
9218 /* Description: Configuration register */
9219 
9220 /* Bit 2 : Serial clock (SCK) polarity */
9221 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
9222 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
9223 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
9224 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
9225 
9226 /* Bit 1 : Serial clock (SCK) phase */
9227 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
9228 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
9229 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
9230 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
9231 
9232 /* Bit 0 : Bit order */
9233 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
9234 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
9235 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
9236 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
9237 
9238 /* Register: SPIM_IFTIMING_RXDELAY */
9239 /* Description: Sample delay for input serial data on MISO */
9240 
9241 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
9242 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
9243 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
9244 
9245 /* Register: SPIM_IFTIMING_CSNDUR */
9246 /* Description: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. */
9247 
9248 /* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
9249 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
9250 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
9251 
9252 /* Register: SPIM_CSNPOL */
9253 /* Description: Polarity of CSN output */
9254 
9255 /* Bit 0 : Polarity of CSN output */
9256 #define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
9257 #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
9258 #define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
9259 #define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
9260 
9261 /* Register: SPIM_PSELDCX */
9262 /* Description: Pin select for DCX signal */
9263 
9264 /* Bit 31 : Connection */
9265 #define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9266 #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9267 #define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
9268 #define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
9269 
9270 /* Bit 5 : Port number */
9271 #define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
9272 #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
9273 
9274 /* Bits 4..0 : Pin number */
9275 #define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
9276 #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
9277 
9278 /* Register: SPIM_DCXCNT */
9279 /* Description: DCX configuration */
9280 
9281 /* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
9282 #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
9283 #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
9284 
9285 /* Register: SPIM_ORC */
9286 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
9287 
9288 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
9289 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
9290 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
9291 
9292 
9293 /* Peripheral: SPIS */
9294 /* Description: SPI Slave */
9295 
9296 /* Register: SPIS_TASKS_ACQUIRE */
9297 /* Description: Acquire SPI semaphore */
9298 
9299 /* Bit 0 : Acquire SPI semaphore */
9300 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
9301 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
9302 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
9303 
9304 /* Register: SPIS_TASKS_RELEASE */
9305 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
9306 
9307 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
9308 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
9309 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
9310 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
9311 
9312 /* Register: SPIS_SUBSCRIBE_ACQUIRE */
9313 /* Description: Subscribe configuration for task ACQUIRE */
9314 
9315 /* Bit 31 :   */
9316 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
9317 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
9318 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
9319 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
9320 
9321 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
9322 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9323 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9324 
9325 /* Register: SPIS_SUBSCRIBE_RELEASE */
9326 /* Description: Subscribe configuration for task RELEASE */
9327 
9328 /* Bit 31 :   */
9329 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
9330 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
9331 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
9332 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
9333 
9334 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
9335 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9336 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9337 
9338 /* Register: SPIS_EVENTS_END */
9339 /* Description: Granted transaction completed */
9340 
9341 /* Bit 0 : Granted transaction completed */
9342 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
9343 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
9344 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
9345 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
9346 
9347 /* Register: SPIS_EVENTS_ENDRX */
9348 /* Description: End of RXD buffer reached */
9349 
9350 /* Bit 0 : End of RXD buffer reached */
9351 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
9352 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
9353 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
9354 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
9355 
9356 /* Register: SPIS_EVENTS_ACQUIRED */
9357 /* Description: Semaphore acquired */
9358 
9359 /* Bit 0 : Semaphore acquired */
9360 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
9361 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
9362 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
9363 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
9364 
9365 /* Register: SPIS_PUBLISH_END */
9366 /* Description: Publish configuration for event END */
9367 
9368 /* Bit 31 :   */
9369 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
9370 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
9371 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
9372 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
9373 
9374 /* Bits 7..0 : DPPI channel that event END will publish to. */
9375 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9376 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9377 
9378 /* Register: SPIS_PUBLISH_ENDRX */
9379 /* Description: Publish configuration for event ENDRX */
9380 
9381 /* Bit 31 :   */
9382 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
9383 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
9384 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
9385 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
9386 
9387 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
9388 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9389 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9390 
9391 /* Register: SPIS_PUBLISH_ACQUIRED */
9392 /* Description: Publish configuration for event ACQUIRED */
9393 
9394 /* Bit 31 :   */
9395 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
9396 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
9397 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
9398 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
9399 
9400 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to. */
9401 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9402 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9403 
9404 /* Register: SPIS_SHORTS */
9405 /* Description: Shortcuts between local events and tasks */
9406 
9407 /* Bit 2 : Shortcut between event END and task ACQUIRE */
9408 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
9409 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
9410 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
9411 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
9412 
9413 /* Register: SPIS_INTENSET */
9414 /* Description: Enable interrupt */
9415 
9416 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
9417 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
9418 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
9419 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
9420 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
9421 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
9422 
9423 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
9424 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
9425 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
9426 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9427 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9428 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
9429 
9430 /* Bit 1 : Write '1' to enable interrupt for event END */
9431 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
9432 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
9433 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9434 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9435 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
9436 
9437 /* Register: SPIS_INTENCLR */
9438 /* Description: Disable interrupt */
9439 
9440 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
9441 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
9442 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
9443 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
9444 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
9445 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
9446 
9447 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
9448 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
9449 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
9450 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9451 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9452 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
9453 
9454 /* Bit 1 : Write '1' to disable interrupt for event END */
9455 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
9456 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
9457 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9458 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9459 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
9460 
9461 /* Register: SPIS_SEMSTAT */
9462 /* Description: Semaphore status register */
9463 
9464 /* Bits 1..0 : Semaphore status */
9465 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
9466 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
9467 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
9468 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
9469 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
9470 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
9471 
9472 /* Register: SPIS_STATUS */
9473 /* Description: Status from last transaction */
9474 
9475 /* Bit 1 : RX buffer overflow detected, and prevented */
9476 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
9477 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
9478 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
9479 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
9480 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
9481 
9482 /* Bit 0 : TX buffer over-read detected, and prevented */
9483 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
9484 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
9485 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
9486 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
9487 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
9488 
9489 /* Register: SPIS_ENABLE */
9490 /* Description: Enable SPI slave */
9491 
9492 /* Bits 3..0 : Enable or disable SPI slave */
9493 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9494 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9495 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
9496 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
9497 
9498 /* Register: SPIS_PSEL_SCK */
9499 /* Description: Pin select for SCK */
9500 
9501 /* Bit 31 : Connection */
9502 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9503 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9504 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
9505 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
9506 
9507 /* Bit 5 : Port number */
9508 #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
9509 #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
9510 
9511 /* Bits 4..0 : Pin number */
9512 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
9513 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
9514 
9515 /* Register: SPIS_PSEL_MISO */
9516 /* Description: Pin select for MISO signal */
9517 
9518 /* Bit 31 : Connection */
9519 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9520 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9521 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
9522 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
9523 
9524 /* Bit 5 : Port number */
9525 #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
9526 #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
9527 
9528 /* Bits 4..0 : Pin number */
9529 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
9530 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
9531 
9532 /* Register: SPIS_PSEL_MOSI */
9533 /* Description: Pin select for MOSI signal */
9534 
9535 /* Bit 31 : Connection */
9536 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9537 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9538 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
9539 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
9540 
9541 /* Bit 5 : Port number */
9542 #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
9543 #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
9544 
9545 /* Bits 4..0 : Pin number */
9546 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
9547 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
9548 
9549 /* Register: SPIS_PSEL_CSN */
9550 /* Description: Pin select for CSN signal */
9551 
9552 /* Bit 31 : Connection */
9553 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9554 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9555 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
9556 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
9557 
9558 /* Bit 5 : Port number */
9559 #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
9560 #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
9561 
9562 /* Bits 4..0 : Pin number */
9563 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
9564 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
9565 
9566 /* Register: SPIS_RXD_PTR */
9567 /* Description: RXD data pointer */
9568 
9569 /* Bits 31..0 : RXD data pointer */
9570 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9571 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9572 
9573 /* Register: SPIS_RXD_MAXCNT */
9574 /* Description: Maximum number of bytes in receive buffer */
9575 
9576 /* Bits 15..0 : Maximum number of bytes in receive buffer */
9577 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9578 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9579 
9580 /* Register: SPIS_RXD_AMOUNT */
9581 /* Description: Number of bytes received in last granted transaction */
9582 
9583 /* Bits 15..0 : Number of bytes received in the last granted transaction */
9584 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9585 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9586 
9587 /* Register: SPIS_RXD_LIST */
9588 /* Description: EasyDMA list type */
9589 
9590 /* Bits 1..0 : List type */
9591 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9592 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9593 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9594 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9595 
9596 /* Register: SPIS_TXD_PTR */
9597 /* Description: TXD data pointer */
9598 
9599 /* Bits 31..0 : TXD data pointer */
9600 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9601 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9602 
9603 /* Register: SPIS_TXD_MAXCNT */
9604 /* Description: Maximum number of bytes in transmit buffer */
9605 
9606 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
9607 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9608 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9609 
9610 /* Register: SPIS_TXD_AMOUNT */
9611 /* Description: Number of bytes transmitted in last granted transaction */
9612 
9613 /* Bits 15..0 : Number of bytes transmitted in last granted transaction */
9614 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9615 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9616 
9617 /* Register: SPIS_TXD_LIST */
9618 /* Description: EasyDMA list type */
9619 
9620 /* Bits 1..0 : List type */
9621 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9622 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9623 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9624 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9625 
9626 /* Register: SPIS_CONFIG */
9627 /* Description: Configuration register */
9628 
9629 /* Bit 2 : Serial clock (SCK) polarity */
9630 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
9631 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
9632 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
9633 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
9634 
9635 /* Bit 1 : Serial clock (SCK) phase */
9636 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
9637 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
9638 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
9639 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
9640 
9641 /* Bit 0 : Bit order */
9642 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
9643 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
9644 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
9645 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
9646 
9647 /* Register: SPIS_DEF */
9648 /* Description: Default character. Character clocked out in case of an ignored transaction. */
9649 
9650 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
9651 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
9652 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
9653 
9654 /* Register: SPIS_ORC */
9655 /* Description: Over-read character */
9656 
9657 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
9658 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
9659 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
9660 
9661 
9662 /* Peripheral: TEMP */
9663 /* Description: Temperature Sensor */
9664 
9665 /* Register: TEMP_TASKS_START */
9666 /* Description: Start temperature measurement */
9667 
9668 /* Bit 0 : Start temperature measurement */
9669 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9670 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9671 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9672 
9673 /* Register: TEMP_TASKS_STOP */
9674 /* Description: Stop temperature measurement */
9675 
9676 /* Bit 0 : Stop temperature measurement */
9677 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9678 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9679 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9680 
9681 /* Register: TEMP_SUBSCRIBE_START */
9682 /* Description: Subscribe configuration for task START */
9683 
9684 /* Bit 31 :   */
9685 #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
9686 #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
9687 #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
9688 #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
9689 
9690 /* Bits 7..0 : DPPI channel that task START will subscribe to */
9691 #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9692 #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9693 
9694 /* Register: TEMP_SUBSCRIBE_STOP */
9695 /* Description: Subscribe configuration for task STOP */
9696 
9697 /* Bit 31 :   */
9698 #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9699 #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9700 #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9701 #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9702 
9703 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9704 #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9705 #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9706 
9707 /* Register: TEMP_EVENTS_DATARDY */
9708 /* Description: Temperature measurement complete, data ready */
9709 
9710 /* Bit 0 : Temperature measurement complete, data ready */
9711 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
9712 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
9713 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
9714 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
9715 
9716 /* Register: TEMP_PUBLISH_DATARDY */
9717 /* Description: Publish configuration for event DATARDY */
9718 
9719 /* Bit 31 :   */
9720 #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */
9721 #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */
9722 #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */
9723 #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */
9724 
9725 /* Bits 7..0 : DPPI channel that event DATARDY will publish to. */
9726 #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9727 #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9728 
9729 /* Register: TEMP_INTENSET */
9730 /* Description: Enable interrupt */
9731 
9732 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
9733 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
9734 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
9735 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
9736 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
9737 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
9738 
9739 /* Register: TEMP_INTENCLR */
9740 /* Description: Disable interrupt */
9741 
9742 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
9743 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
9744 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
9745 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
9746 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
9747 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
9748 
9749 /* Register: TEMP_TEMP */
9750 /* Description: Temperature in degC (0.25deg steps) */
9751 
9752 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
9753 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
9754 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
9755 
9756 /* Register: TEMP_A0 */
9757 /* Description: Slope of first piecewise linear function */
9758 
9759 /* Bits 11..0 : Slope of first piecewise linear function */
9760 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
9761 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
9762 
9763 /* Register: TEMP_A1 */
9764 /* Description: Slope of second piecewise linear function */
9765 
9766 /* Bits 11..0 : Slope of second piecewise linear function */
9767 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
9768 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
9769 
9770 /* Register: TEMP_A2 */
9771 /* Description: Slope of third piecewise linear function */
9772 
9773 /* Bits 11..0 : Slope of third piecewise linear function */
9774 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
9775 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
9776 
9777 /* Register: TEMP_A3 */
9778 /* Description: Slope of fourth piecewise linear function */
9779 
9780 /* Bits 11..0 : Slope of fourth piecewise linear function */
9781 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
9782 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
9783 
9784 /* Register: TEMP_A4 */
9785 /* Description: Slope of fifth piecewise linear function */
9786 
9787 /* Bits 11..0 : Slope of fifth piecewise linear function */
9788 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
9789 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
9790 
9791 /* Register: TEMP_A5 */
9792 /* Description: Slope of sixth piecewise linear function */
9793 
9794 /* Bits 11..0 : Slope of sixth piecewise linear function */
9795 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
9796 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
9797 
9798 /* Register: TEMP_B0 */
9799 /* Description: y-intercept of first piecewise linear function */
9800 
9801 /* Bits 11..0 : y-intercept of first piecewise linear function */
9802 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
9803 #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
9804 
9805 /* Register: TEMP_B1 */
9806 /* Description: y-intercept of second piecewise linear function */
9807 
9808 /* Bits 11..0 : y-intercept of second piecewise linear function */
9809 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
9810 #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
9811 
9812 /* Register: TEMP_B2 */
9813 /* Description: y-intercept of third piecewise linear function */
9814 
9815 /* Bits 11..0 : y-intercept of third piecewise linear function */
9816 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
9817 #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
9818 
9819 /* Register: TEMP_B3 */
9820 /* Description: y-intercept of fourth piecewise linear function */
9821 
9822 /* Bits 11..0 : y-intercept of fourth piecewise linear function */
9823 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
9824 #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
9825 
9826 /* Register: TEMP_B4 */
9827 /* Description: y-intercept of fifth piecewise linear function */
9828 
9829 /* Bits 11..0 : y-intercept of fifth piecewise linear function */
9830 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
9831 #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
9832 
9833 /* Register: TEMP_B5 */
9834 /* Description: y-intercept of sixth piecewise linear function */
9835 
9836 /* Bits 11..0 : y-intercept of sixth piecewise linear function */
9837 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
9838 #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
9839 
9840 /* Register: TEMP_T0 */
9841 /* Description: Endpoint of first piecewise linear function */
9842 
9843 /* Bits 7..0 : Endpoint of first piecewise linear function */
9844 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
9845 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
9846 
9847 /* Register: TEMP_T1 */
9848 /* Description: Endpoint of second piecewise linear function */
9849 
9850 /* Bits 7..0 : Endpoint of second piecewise linear function */
9851 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
9852 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
9853 
9854 /* Register: TEMP_T2 */
9855 /* Description: Endpoint of third piecewise linear function */
9856 
9857 /* Bits 7..0 : Endpoint of third piecewise linear function */
9858 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
9859 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
9860 
9861 /* Register: TEMP_T3 */
9862 /* Description: Endpoint of fourth piecewise linear function */
9863 
9864 /* Bits 7..0 : Endpoint of fourth piecewise linear function */
9865 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
9866 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
9867 
9868 /* Register: TEMP_T4 */
9869 /* Description: Endpoint of fifth piecewise linear function */
9870 
9871 /* Bits 7..0 : Endpoint of fifth piecewise linear function */
9872 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
9873 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
9874 
9875 
9876 /* Peripheral: TIMER */
9877 /* Description: Timer/Counter 0 */
9878 
9879 /* Register: TIMER_TASKS_START */
9880 /* Description: Start Timer */
9881 
9882 /* Bit 0 : Start Timer */
9883 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9884 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9885 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9886 
9887 /* Register: TIMER_TASKS_STOP */
9888 /* Description: Stop Timer */
9889 
9890 /* Bit 0 : Stop Timer */
9891 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9892 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9893 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9894 
9895 /* Register: TIMER_TASKS_COUNT */
9896 /* Description: Increment Timer (Counter mode only) */
9897 
9898 /* Bit 0 : Increment Timer (Counter mode only) */
9899 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
9900 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
9901 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
9902 
9903 /* Register: TIMER_TASKS_CLEAR */
9904 /* Description: Clear time */
9905 
9906 /* Bit 0 : Clear time */
9907 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
9908 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
9909 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
9910 
9911 /* Register: TIMER_TASKS_SHUTDOWN */
9912 /* Description: Deprecated register - Shut down timer */
9913 
9914 /* Bit 0 : Deprecated field -  Shut down timer */
9915 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
9916 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
9917 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
9918 
9919 /* Register: TIMER_TASKS_CAPTURE */
9920 /* Description: Description collection: Capture Timer value to CC[n] register */
9921 
9922 /* Bit 0 : Capture Timer value to CC[n] register */
9923 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
9924 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
9925 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
9926 
9927 /* Register: TIMER_SUBSCRIBE_START */
9928 /* Description: Subscribe configuration for task START */
9929 
9930 /* Bit 31 :   */
9931 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
9932 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
9933 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
9934 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
9935 
9936 /* Bits 7..0 : DPPI channel that task START will subscribe to */
9937 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9938 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9939 
9940 /* Register: TIMER_SUBSCRIBE_STOP */
9941 /* Description: Subscribe configuration for task STOP */
9942 
9943 /* Bit 31 :   */
9944 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9945 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9946 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9947 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9948 
9949 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9950 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9951 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9952 
9953 /* Register: TIMER_SUBSCRIBE_COUNT */
9954 /* Description: Subscribe configuration for task COUNT */
9955 
9956 /* Bit 31 :   */
9957 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
9958 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
9959 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
9960 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
9961 
9962 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
9963 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9964 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9965 
9966 /* Register: TIMER_SUBSCRIBE_CLEAR */
9967 /* Description: Subscribe configuration for task CLEAR */
9968 
9969 /* Bit 31 :   */
9970 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
9971 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
9972 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
9973 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
9974 
9975 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
9976 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9977 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9978 
9979 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
9980 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
9981 
9982 /* Bit 31 :   */
9983 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
9984 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
9985 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
9986 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
9987 
9988 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
9989 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9990 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9991 
9992 /* Register: TIMER_SUBSCRIBE_CAPTURE */
9993 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
9994 
9995 /* Bit 31 :   */
9996 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
9997 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
9998 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
9999 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
10000 
10001 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
10002 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10003 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10004 
10005 /* Register: TIMER_EVENTS_COMPARE */
10006 /* Description: Description collection: Compare event on CC[n] match */
10007 
10008 /* Bit 0 : Compare event on CC[n] match */
10009 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
10010 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
10011 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
10012 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
10013 
10014 /* Register: TIMER_PUBLISH_COMPARE */
10015 /* Description: Description collection: Publish configuration for event COMPARE[n] */
10016 
10017 /* Bit 31 :   */
10018 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
10019 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
10020 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
10021 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
10022 
10023 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
10024 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10025 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10026 
10027 /* Register: TIMER_SHORTS */
10028 /* Description: Shortcuts between local events and tasks */
10029 
10030 /* Bit 23 : Shortcut between event COMPARE[7] and task STOP */
10031 #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */
10032 #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */
10033 #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0UL) /*!< Disable shortcut */
10034 #define TIMER_SHORTS_COMPARE7_STOP_Enabled (1UL) /*!< Enable shortcut */
10035 
10036 /* Bit 22 : Shortcut between event COMPARE[6] and task STOP */
10037 #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL) /*!< Position of COMPARE6_STOP field. */
10038 #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos) /*!< Bit mask of COMPARE6_STOP field. */
10039 #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0UL) /*!< Disable shortcut */
10040 #define TIMER_SHORTS_COMPARE6_STOP_Enabled (1UL) /*!< Enable shortcut */
10041 
10042 /* Bit 21 : Shortcut between event COMPARE[5] and task STOP */
10043 #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL) /*!< Position of COMPARE5_STOP field. */
10044 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
10045 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
10046 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
10047 
10048 /* Bit 20 : Shortcut between event COMPARE[4] and task STOP */
10049 #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL) /*!< Position of COMPARE4_STOP field. */
10050 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
10051 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
10052 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
10053 
10054 /* Bit 19 : Shortcut between event COMPARE[3] and task STOP */
10055 #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL) /*!< Position of COMPARE3_STOP field. */
10056 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
10057 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
10058 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
10059 
10060 /* Bit 18 : Shortcut between event COMPARE[2] and task STOP */
10061 #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL) /*!< Position of COMPARE2_STOP field. */
10062 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
10063 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
10064 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
10065 
10066 /* Bit 17 : Shortcut between event COMPARE[1] and task STOP */
10067 #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL) /*!< Position of COMPARE1_STOP field. */
10068 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
10069 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
10070 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
10071 
10072 /* Bit 16 : Shortcut between event COMPARE[0] and task STOP */
10073 #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */
10074 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
10075 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
10076 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
10077 
10078 /* Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */
10079 #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */
10080 #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */
10081 #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10082 #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10083 
10084 /* Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */
10085 #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL) /*!< Position of COMPARE6_CLEAR field. */
10086 #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field. */
10087 #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10088 #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10089 
10090 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
10091 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
10092 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
10093 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10094 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10095 
10096 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
10097 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
10098 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
10099 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10100 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10101 
10102 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
10103 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
10104 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
10105 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10106 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10107 
10108 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
10109 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
10110 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
10111 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10112 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10113 
10114 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
10115 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
10116 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
10117 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10118 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10119 
10120 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
10121 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
10122 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
10123 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10124 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10125 
10126 /* Register: TIMER_INTEN */
10127 /* Description: Enable or disable interrupt */
10128 
10129 /* Bit 23 : Enable or disable interrupt for event COMPARE[7] */
10130 #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
10131 #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
10132 #define TIMER_INTEN_COMPARE7_Disabled (0UL) /*!< Disable */
10133 #define TIMER_INTEN_COMPARE7_Enabled (1UL) /*!< Enable */
10134 
10135 /* Bit 22 : Enable or disable interrupt for event COMPARE[6] */
10136 #define TIMER_INTEN_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */
10137 #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */
10138 #define TIMER_INTEN_COMPARE6_Disabled (0UL) /*!< Disable */
10139 #define TIMER_INTEN_COMPARE6_Enabled (1UL) /*!< Enable */
10140 
10141 /* Bit 21 : Enable or disable interrupt for event COMPARE[5] */
10142 #define TIMER_INTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10143 #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10144 #define TIMER_INTEN_COMPARE5_Disabled (0UL) /*!< Disable */
10145 #define TIMER_INTEN_COMPARE5_Enabled (1UL) /*!< Enable */
10146 
10147 /* Bit 20 : Enable or disable interrupt for event COMPARE[4] */
10148 #define TIMER_INTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10149 #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10150 #define TIMER_INTEN_COMPARE4_Disabled (0UL) /*!< Disable */
10151 #define TIMER_INTEN_COMPARE4_Enabled (1UL) /*!< Enable */
10152 
10153 /* Bit 19 : Enable or disable interrupt for event COMPARE[3] */
10154 #define TIMER_INTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10155 #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10156 #define TIMER_INTEN_COMPARE3_Disabled (0UL) /*!< Disable */
10157 #define TIMER_INTEN_COMPARE3_Enabled (1UL) /*!< Enable */
10158 
10159 /* Bit 18 : Enable or disable interrupt for event COMPARE[2] */
10160 #define TIMER_INTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10161 #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10162 #define TIMER_INTEN_COMPARE2_Disabled (0UL) /*!< Disable */
10163 #define TIMER_INTEN_COMPARE2_Enabled (1UL) /*!< Enable */
10164 
10165 /* Bit 17 : Enable or disable interrupt for event COMPARE[1] */
10166 #define TIMER_INTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10167 #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10168 #define TIMER_INTEN_COMPARE1_Disabled (0UL) /*!< Disable */
10169 #define TIMER_INTEN_COMPARE1_Enabled (1UL) /*!< Enable */
10170 
10171 /* Bit 16 : Enable or disable interrupt for event COMPARE[0] */
10172 #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10173 #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10174 #define TIMER_INTEN_COMPARE0_Disabled (0UL) /*!< Disable */
10175 #define TIMER_INTEN_COMPARE0_Enabled (1UL) /*!< Enable */
10176 
10177 /* Register: TIMER_INTENSET */
10178 /* Description: Enable interrupt */
10179 
10180 /* Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */
10181 #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
10182 #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
10183 #define TIMER_INTENSET_COMPARE7_Disabled (0UL) /*!< Read: Disabled */
10184 #define TIMER_INTENSET_COMPARE7_Enabled (1UL) /*!< Read: Enabled */
10185 #define TIMER_INTENSET_COMPARE7_Set (1UL) /*!< Enable */
10186 
10187 /* Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */
10188 #define TIMER_INTENSET_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */
10189 #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */
10190 #define TIMER_INTENSET_COMPARE6_Disabled (0UL) /*!< Read: Disabled */
10191 #define TIMER_INTENSET_COMPARE6_Enabled (1UL) /*!< Read: Enabled */
10192 #define TIMER_INTENSET_COMPARE6_Set (1UL) /*!< Enable */
10193 
10194 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
10195 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10196 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10197 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10198 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10199 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
10200 
10201 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
10202 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10203 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10204 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10205 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10206 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
10207 
10208 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
10209 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10210 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10211 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10212 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10213 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10214 
10215 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
10216 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10217 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10218 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10219 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10220 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10221 
10222 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
10223 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10224 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10225 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10226 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10227 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10228 
10229 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
10230 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10231 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10232 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10233 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10234 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
10235 
10236 /* Register: TIMER_INTENCLR */
10237 /* Description: Disable interrupt */
10238 
10239 /* Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */
10240 #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
10241 #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
10242 #define TIMER_INTENCLR_COMPARE7_Disabled (0UL) /*!< Read: Disabled */
10243 #define TIMER_INTENCLR_COMPARE7_Enabled (1UL) /*!< Read: Enabled */
10244 #define TIMER_INTENCLR_COMPARE7_Clear (1UL) /*!< Disable */
10245 
10246 /* Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */
10247 #define TIMER_INTENCLR_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */
10248 #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */
10249 #define TIMER_INTENCLR_COMPARE6_Disabled (0UL) /*!< Read: Disabled */
10250 #define TIMER_INTENCLR_COMPARE6_Enabled (1UL) /*!< Read: Enabled */
10251 #define TIMER_INTENCLR_COMPARE6_Clear (1UL) /*!< Disable */
10252 
10253 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
10254 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10255 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10256 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10257 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10258 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
10259 
10260 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
10261 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10262 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10263 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10264 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10265 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
10266 
10267 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
10268 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10269 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10270 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10271 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10272 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10273 
10274 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
10275 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10276 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10277 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10278 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10279 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10280 
10281 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
10282 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10283 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10284 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10285 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10286 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10287 
10288 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
10289 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10290 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10291 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10292 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10293 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10294 
10295 /* Register: TIMER_MODE */
10296 /* Description: Timer mode selection */
10297 
10298 /* Bits 1..0 : Timer mode */
10299 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
10300 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
10301 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
10302 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
10303 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
10304 
10305 /* Register: TIMER_BITMODE */
10306 /* Description: Configure the number of bits used by the TIMER */
10307 
10308 /* Bits 1..0 : Timer bit width */
10309 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
10310 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
10311 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
10312 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
10313 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
10314 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
10315 
10316 /* Register: TIMER_PRESCALER */
10317 /* Description: Timer prescaler register */
10318 
10319 /* Bits 3..0 : Prescaler value */
10320 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10321 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10322 
10323 /* Register: TIMER_CC */
10324 /* Description: Description collection: Capture/Compare register n */
10325 
10326 /* Bits 31..0 : Capture/Compare value */
10327 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
10328 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
10329 
10330 /* Register: TIMER_ONESHOTEN */
10331 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
10332 
10333 /* Bit 0 : Enable one-shot operation */
10334 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
10335 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
10336 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
10337 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
10338 
10339 
10340 /* Peripheral: TWIM */
10341 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */
10342 
10343 /* Register: TWIM_TASKS_STARTRX */
10344 /* Description: Start TWI receive sequence */
10345 
10346 /* Bit 0 : Start TWI receive sequence */
10347 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
10348 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
10349 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
10350 
10351 /* Register: TWIM_TASKS_STARTTX */
10352 /* Description: Start TWI transmit sequence */
10353 
10354 /* Bit 0 : Start TWI transmit sequence */
10355 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
10356 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
10357 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
10358 
10359 /* Register: TWIM_TASKS_STOP */
10360 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
10361 
10362 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
10363 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10364 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10365 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10366 
10367 /* Register: TWIM_TASKS_SUSPEND */
10368 /* Description: Suspend TWI transaction */
10369 
10370 /* Bit 0 : Suspend TWI transaction */
10371 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
10372 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
10373 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
10374 
10375 /* Register: TWIM_TASKS_RESUME */
10376 /* Description: Resume TWI transaction */
10377 
10378 /* Bit 0 : Resume TWI transaction */
10379 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
10380 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
10381 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
10382 
10383 /* Register: TWIM_SUBSCRIBE_STARTRX */
10384 /* Description: Subscribe configuration for task STARTRX */
10385 
10386 /* Bit 31 :   */
10387 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
10388 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
10389 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
10390 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
10391 
10392 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
10393 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10394 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10395 
10396 /* Register: TWIM_SUBSCRIBE_STARTTX */
10397 /* Description: Subscribe configuration for task STARTTX */
10398 
10399 /* Bit 31 :   */
10400 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
10401 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
10402 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
10403 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
10404 
10405 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
10406 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10407 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10408 
10409 /* Register: TWIM_SUBSCRIBE_STOP */
10410 /* Description: Subscribe configuration for task STOP */
10411 
10412 /* Bit 31 :   */
10413 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
10414 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
10415 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
10416 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
10417 
10418 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
10419 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10420 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10421 
10422 /* Register: TWIM_SUBSCRIBE_SUSPEND */
10423 /* Description: Subscribe configuration for task SUSPEND */
10424 
10425 /* Bit 31 :   */
10426 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
10427 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
10428 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
10429 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
10430 
10431 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
10432 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10433 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10434 
10435 /* Register: TWIM_SUBSCRIBE_RESUME */
10436 /* Description: Subscribe configuration for task RESUME */
10437 
10438 /* Bit 31 :   */
10439 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
10440 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
10441 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
10442 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
10443 
10444 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
10445 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10446 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10447 
10448 /* Register: TWIM_EVENTS_STOPPED */
10449 /* Description: TWI stopped */
10450 
10451 /* Bit 0 : TWI stopped */
10452 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
10453 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
10454 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
10455 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
10456 
10457 /* Register: TWIM_EVENTS_ERROR */
10458 /* Description: TWI error */
10459 
10460 /* Bit 0 : TWI error */
10461 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
10462 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
10463 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
10464 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
10465 
10466 /* Register: TWIM_EVENTS_SUSPENDED */
10467 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
10468 
10469 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
10470 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
10471 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
10472 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
10473 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
10474 
10475 /* Register: TWIM_EVENTS_RXSTARTED */
10476 /* Description: Receive sequence started */
10477 
10478 /* Bit 0 : Receive sequence started */
10479 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
10480 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
10481 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10482 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
10483 
10484 /* Register: TWIM_EVENTS_TXSTARTED */
10485 /* Description: Transmit sequence started */
10486 
10487 /* Bit 0 : Transmit sequence started */
10488 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
10489 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
10490 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10491 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
10492 
10493 /* Register: TWIM_EVENTS_LASTRX */
10494 /* Description: Byte boundary, starting to receive the last byte */
10495 
10496 /* Bit 0 : Byte boundary, starting to receive the last byte */
10497 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
10498 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
10499 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
10500 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
10501 
10502 /* Register: TWIM_EVENTS_LASTTX */
10503 /* Description: Byte boundary, starting to transmit the last byte */
10504 
10505 /* Bit 0 : Byte boundary, starting to transmit the last byte */
10506 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
10507 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
10508 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
10509 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
10510 
10511 /* Register: TWIM_PUBLISH_STOPPED */
10512 /* Description: Publish configuration for event STOPPED */
10513 
10514 /* Bit 31 :   */
10515 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
10516 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
10517 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
10518 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
10519 
10520 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
10521 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10522 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10523 
10524 /* Register: TWIM_PUBLISH_ERROR */
10525 /* Description: Publish configuration for event ERROR */
10526 
10527 /* Bit 31 :   */
10528 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
10529 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
10530 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
10531 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
10532 
10533 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
10534 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10535 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10536 
10537 /* Register: TWIM_PUBLISH_SUSPENDED */
10538 /* Description: Publish configuration for event SUSPENDED */
10539 
10540 /* Bit 31 :   */
10541 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
10542 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
10543 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
10544 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
10545 
10546 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to. */
10547 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10548 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10549 
10550 /* Register: TWIM_PUBLISH_RXSTARTED */
10551 /* Description: Publish configuration for event RXSTARTED */
10552 
10553 /* Bit 31 :   */
10554 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10555 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10556 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10557 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10558 
10559 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
10560 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10561 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10562 
10563 /* Register: TWIM_PUBLISH_TXSTARTED */
10564 /* Description: Publish configuration for event TXSTARTED */
10565 
10566 /* Bit 31 :   */
10567 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10568 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10569 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10570 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10571 
10572 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
10573 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10574 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10575 
10576 /* Register: TWIM_PUBLISH_LASTRX */
10577 /* Description: Publish configuration for event LASTRX */
10578 
10579 /* Bit 31 :   */
10580 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
10581 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
10582 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
10583 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
10584 
10585 /* Bits 7..0 : DPPI channel that event LASTRX will publish to. */
10586 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10587 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10588 
10589 /* Register: TWIM_PUBLISH_LASTTX */
10590 /* Description: Publish configuration for event LASTTX */
10591 
10592 /* Bit 31 :   */
10593 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
10594 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
10595 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
10596 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
10597 
10598 /* Bits 7..0 : DPPI channel that event LASTTX will publish to. */
10599 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10600 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10601 
10602 /* Register: TWIM_SHORTS */
10603 /* Description: Shortcuts between local events and tasks */
10604 
10605 /* Bit 12 : Shortcut between event LASTRX and task STOP */
10606 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
10607 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
10608 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
10609 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
10610 
10611 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
10612 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
10613 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
10614 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
10615 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
10616 
10617 /* Bit 9 : Shortcut between event LASTTX and task STOP */
10618 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
10619 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
10620 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
10621 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
10622 
10623 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
10624 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
10625 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
10626 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
10627 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
10628 
10629 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
10630 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
10631 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
10632 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10633 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10634 
10635 /* Register: TWIM_INTEN */
10636 /* Description: Enable or disable interrupt */
10637 
10638 /* Bit 24 : Enable or disable interrupt for event LASTTX */
10639 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
10640 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
10641 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
10642 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
10643 
10644 /* Bit 23 : Enable or disable interrupt for event LASTRX */
10645 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
10646 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
10647 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
10648 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
10649 
10650 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10651 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10652 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10653 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10654 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10655 
10656 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10657 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10658 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10659 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10660 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10661 
10662 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
10663 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
10664 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
10665 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
10666 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
10667 
10668 /* Bit 9 : Enable or disable interrupt for event ERROR */
10669 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10670 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
10671 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10672 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10673 
10674 /* Bit 1 : Enable or disable interrupt for event STOPPED */
10675 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10676 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10677 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
10678 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
10679 
10680 /* Register: TWIM_INTENSET */
10681 /* Description: Enable interrupt */
10682 
10683 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
10684 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
10685 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
10686 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
10687 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
10688 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
10689 
10690 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
10691 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
10692 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
10693 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
10694 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
10695 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
10696 
10697 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10698 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10699 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10700 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10701 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10702 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10703 
10704 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10705 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10706 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10707 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10708 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10709 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10710 
10711 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
10712 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
10713 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
10714 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
10715 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
10716 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
10717 
10718 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10719 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10720 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10721 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10722 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10723 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
10724 
10725 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
10726 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10727 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10728 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10729 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10730 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10731 
10732 /* Register: TWIM_INTENCLR */
10733 /* Description: Disable interrupt */
10734 
10735 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
10736 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
10737 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
10738 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
10739 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
10740 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
10741 
10742 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
10743 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
10744 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
10745 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
10746 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
10747 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
10748 
10749 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10750 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10751 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10752 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10753 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10754 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10755 
10756 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10757 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10758 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10759 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10760 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10761 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10762 
10763 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
10764 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
10765 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
10766 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
10767 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
10768 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
10769 
10770 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10771 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10772 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10773 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10774 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10775 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10776 
10777 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
10778 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10779 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10780 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10781 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10782 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10783 
10784 /* Register: TWIM_ERRORSRC */
10785 /* Description: Error source */
10786 
10787 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
10788 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
10789 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
10790 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
10791 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
10792 
10793 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
10794 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
10795 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
10796 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
10797 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
10798 
10799 /* Bit 0 : Overrun error */
10800 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10801 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10802 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
10803 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
10804 
10805 /* Register: TWIM_ENABLE */
10806 /* Description: Enable TWIM */
10807 
10808 /* Bits 3..0 : Enable or disable TWIM */
10809 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10810 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10811 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
10812 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
10813 
10814 /* Register: TWIM_PSEL_SCL */
10815 /* Description: Pin select for SCL signal */
10816 
10817 /* Bit 31 : Connection */
10818 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10819 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10820 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
10821 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
10822 
10823 /* Bit 5 : Port number */
10824 #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
10825 #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
10826 
10827 /* Bits 4..0 : Pin number */
10828 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
10829 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
10830 
10831 /* Register: TWIM_PSEL_SDA */
10832 /* Description: Pin select for SDA signal */
10833 
10834 /* Bit 31 : Connection */
10835 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10836 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10837 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
10838 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
10839 
10840 /* Bit 5 : Port number */
10841 #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
10842 #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
10843 
10844 /* Bits 4..0 : Pin number */
10845 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
10846 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
10847 
10848 /* Register: TWIM_FREQUENCY */
10849 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
10850 
10851 /* Bits 31..0 : TWI master clock frequency */
10852 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10853 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10854 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
10855 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
10856 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
10857 #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */
10858 
10859 /* Register: TWIM_RXD_PTR */
10860 /* Description: Data pointer */
10861 
10862 /* Bits 31..0 : Data pointer */
10863 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10864 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10865 
10866 /* Register: TWIM_RXD_MAXCNT */
10867 /* Description: Maximum number of bytes in receive buffer */
10868 
10869 /* Bits 15..0 : Maximum number of bytes in receive buffer */
10870 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10871 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10872 
10873 /* Register: TWIM_RXD_AMOUNT */
10874 /* Description: Number of bytes transferred in the last transaction */
10875 
10876 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
10877 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10878 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10879 
10880 /* Register: TWIM_RXD_LIST */
10881 /* Description: EasyDMA list type */
10882 
10883 /* Bits 2..0 : List type */
10884 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10885 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10886 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10887 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10888 
10889 /* Register: TWIM_TXD_PTR */
10890 /* Description: Data pointer */
10891 
10892 /* Bits 31..0 : Data pointer */
10893 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10894 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10895 
10896 /* Register: TWIM_TXD_MAXCNT */
10897 /* Description: Maximum number of bytes in transmit buffer */
10898 
10899 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
10900 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10901 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10902 
10903 /* Register: TWIM_TXD_AMOUNT */
10904 /* Description: Number of bytes transferred in the last transaction */
10905 
10906 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
10907 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10908 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10909 
10910 /* Register: TWIM_TXD_LIST */
10911 /* Description: EasyDMA list type */
10912 
10913 /* Bits 2..0 : List type */
10914 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10915 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10916 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10917 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10918 
10919 /* Register: TWIM_ADDRESS */
10920 /* Description: Address used in the TWI transfer */
10921 
10922 /* Bits 6..0 : Address used in the TWI transfer */
10923 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
10924 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10925 
10926 
10927 /* Peripheral: TWIS */
10928 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */
10929 
10930 /* Register: TWIS_TASKS_STOP */
10931 /* Description: Stop TWI transaction */
10932 
10933 /* Bit 0 : Stop TWI transaction */
10934 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10935 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10936 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10937 
10938 /* Register: TWIS_TASKS_SUSPEND */
10939 /* Description: Suspend TWI transaction */
10940 
10941 /* Bit 0 : Suspend TWI transaction */
10942 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
10943 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
10944 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
10945 
10946 /* Register: TWIS_TASKS_RESUME */
10947 /* Description: Resume TWI transaction */
10948 
10949 /* Bit 0 : Resume TWI transaction */
10950 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
10951 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
10952 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
10953 
10954 /* Register: TWIS_TASKS_PREPARERX */
10955 /* Description: Prepare the TWI slave to respond to a write command */
10956 
10957 /* Bit 0 : Prepare the TWI slave to respond to a write command */
10958 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
10959 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
10960 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
10961 
10962 /* Register: TWIS_TASKS_PREPARETX */
10963 /* Description: Prepare the TWI slave to respond to a read command */
10964 
10965 /* Bit 0 : Prepare the TWI slave to respond to a read command */
10966 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
10967 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
10968 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
10969 
10970 /* Register: TWIS_SUBSCRIBE_STOP */
10971 /* Description: Subscribe configuration for task STOP */
10972 
10973 /* Bit 31 :   */
10974 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
10975 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
10976 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
10977 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
10978 
10979 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
10980 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10981 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10982 
10983 /* Register: TWIS_SUBSCRIBE_SUSPEND */
10984 /* Description: Subscribe configuration for task SUSPEND */
10985 
10986 /* Bit 31 :   */
10987 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
10988 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
10989 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
10990 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
10991 
10992 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
10993 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10994 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10995 
10996 /* Register: TWIS_SUBSCRIBE_RESUME */
10997 /* Description: Subscribe configuration for task RESUME */
10998 
10999 /* Bit 31 :   */
11000 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
11001 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
11002 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
11003 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
11004 
11005 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
11006 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11007 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11008 
11009 /* Register: TWIS_SUBSCRIBE_PREPARERX */
11010 /* Description: Subscribe configuration for task PREPARERX */
11011 
11012 /* Bit 31 :   */
11013 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
11014 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
11015 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
11016 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
11017 
11018 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
11019 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11020 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11021 
11022 /* Register: TWIS_SUBSCRIBE_PREPARETX */
11023 /* Description: Subscribe configuration for task PREPARETX */
11024 
11025 /* Bit 31 :   */
11026 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
11027 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
11028 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
11029 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
11030 
11031 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
11032 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11033 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11034 
11035 /* Register: TWIS_EVENTS_STOPPED */
11036 /* Description: TWI stopped */
11037 
11038 /* Bit 0 : TWI stopped */
11039 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11040 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11041 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
11042 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
11043 
11044 /* Register: TWIS_EVENTS_ERROR */
11045 /* Description: TWI error */
11046 
11047 /* Bit 0 : TWI error */
11048 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
11049 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
11050 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
11051 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
11052 
11053 /* Register: TWIS_EVENTS_RXSTARTED */
11054 /* Description: Receive sequence started */
11055 
11056 /* Bit 0 : Receive sequence started */
11057 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
11058 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
11059 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
11060 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
11061 
11062 /* Register: TWIS_EVENTS_TXSTARTED */
11063 /* Description: Transmit sequence started */
11064 
11065 /* Bit 0 : Transmit sequence started */
11066 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
11067 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
11068 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
11069 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
11070 
11071 /* Register: TWIS_EVENTS_WRITE */
11072 /* Description: Write command received */
11073 
11074 /* Bit 0 : Write command received */
11075 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
11076 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
11077 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
11078 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
11079 
11080 /* Register: TWIS_EVENTS_READ */
11081 /* Description: Read command received */
11082 
11083 /* Bit 0 : Read command received */
11084 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
11085 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
11086 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
11087 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
11088 
11089 /* Register: TWIS_PUBLISH_STOPPED */
11090 /* Description: Publish configuration for event STOPPED */
11091 
11092 /* Bit 31 :   */
11093 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
11094 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
11095 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
11096 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
11097 
11098 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
11099 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11100 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11101 
11102 /* Register: TWIS_PUBLISH_ERROR */
11103 /* Description: Publish configuration for event ERROR */
11104 
11105 /* Bit 31 :   */
11106 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
11107 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
11108 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
11109 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
11110 
11111 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
11112 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11113 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11114 
11115 /* Register: TWIS_PUBLISH_RXSTARTED */
11116 /* Description: Publish configuration for event RXSTARTED */
11117 
11118 /* Bit 31 :   */
11119 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
11120 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
11121 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
11122 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
11123 
11124 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
11125 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11126 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11127 
11128 /* Register: TWIS_PUBLISH_TXSTARTED */
11129 /* Description: Publish configuration for event TXSTARTED */
11130 
11131 /* Bit 31 :   */
11132 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
11133 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
11134 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
11135 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
11136 
11137 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
11138 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11139 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11140 
11141 /* Register: TWIS_PUBLISH_WRITE */
11142 /* Description: Publish configuration for event WRITE */
11143 
11144 /* Bit 31 :   */
11145 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
11146 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
11147 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
11148 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
11149 
11150 /* Bits 7..0 : DPPI channel that event WRITE will publish to. */
11151 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11152 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11153 
11154 /* Register: TWIS_PUBLISH_READ */
11155 /* Description: Publish configuration for event READ */
11156 
11157 /* Bit 31 :   */
11158 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
11159 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
11160 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
11161 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
11162 
11163 /* Bits 7..0 : DPPI channel that event READ will publish to. */
11164 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11165 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11166 
11167 /* Register: TWIS_SHORTS */
11168 /* Description: Shortcuts between local events and tasks */
11169 
11170 /* Bit 14 : Shortcut between event READ and task SUSPEND */
11171 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
11172 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
11173 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11174 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11175 
11176 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
11177 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
11178 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
11179 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11180 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11181 
11182 /* Register: TWIS_INTEN */
11183 /* Description: Enable or disable interrupt */
11184 
11185 /* Bit 26 : Enable or disable interrupt for event READ */
11186 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
11187 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
11188 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
11189 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
11190 
11191 /* Bit 25 : Enable or disable interrupt for event WRITE */
11192 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11193 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
11194 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
11195 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
11196 
11197 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
11198 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11199 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11200 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11201 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11202 
11203 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
11204 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11205 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11206 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11207 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11208 
11209 /* Bit 9 : Enable or disable interrupt for event ERROR */
11210 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11211 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11212 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11213 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11214 
11215 /* Bit 1 : Enable or disable interrupt for event STOPPED */
11216 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11217 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11218 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11219 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11220 
11221 /* Register: TWIS_INTENSET */
11222 /* Description: Enable interrupt */
11223 
11224 /* Bit 26 : Write '1' to enable interrupt for event READ */
11225 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
11226 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
11227 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
11228 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11229 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
11230 
11231 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
11232 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11233 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
11234 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
11235 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11236 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
11237 
11238 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
11239 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11240 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11241 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11242 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11243 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11244 
11245 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
11246 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11247 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11248 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11249 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11250 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11251 
11252 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
11253 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11254 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11255 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11256 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11257 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
11258 
11259 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
11260 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11261 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11262 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11263 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11264 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11265 
11266 /* Register: TWIS_INTENCLR */
11267 /* Description: Disable interrupt */
11268 
11269 /* Bit 26 : Write '1' to disable interrupt for event READ */
11270 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
11271 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
11272 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
11273 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11274 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
11275 
11276 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
11277 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11278 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
11279 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
11280 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11281 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
11282 
11283 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
11284 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11285 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11286 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11287 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11288 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11289 
11290 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
11291 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11292 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11293 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11294 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11295 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11296 
11297 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
11298 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11299 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11300 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11301 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11302 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11303 
11304 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
11305 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11306 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11307 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11308 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11309 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11310 
11311 /* Register: TWIS_ERRORSRC */
11312 /* Description: Error source */
11313 
11314 /* Bit 3 : TX buffer over-read detected, and prevented */
11315 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
11316 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
11317 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
11318 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
11319 
11320 /* Bit 2 : NACK sent after receiving a data byte */
11321 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11322 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11323 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
11324 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11325 
11326 /* Bit 0 : RX buffer overflow detected, and prevented */
11327 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
11328 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
11329 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
11330 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
11331 
11332 /* Register: TWIS_MATCH */
11333 /* Description: Status register indicating which address had a match */
11334 
11335 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
11336 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
11337 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
11338 
11339 /* Register: TWIS_ENABLE */
11340 /* Description: Enable TWIS */
11341 
11342 /* Bits 3..0 : Enable or disable TWIS */
11343 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11344 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11345 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
11346 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
11347 
11348 /* Register: TWIS_PSEL_SCL */
11349 /* Description: Pin select for SCL signal */
11350 
11351 /* Bit 31 : Connection */
11352 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11353 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11354 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
11355 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11356 
11357 /* Bit 5 : Port number */
11358 #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
11359 #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
11360 
11361 /* Bits 4..0 : Pin number */
11362 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
11363 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
11364 
11365 /* Register: TWIS_PSEL_SDA */
11366 /* Description: Pin select for SDA signal */
11367 
11368 /* Bit 31 : Connection */
11369 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11370 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11371 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
11372 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11373 
11374 /* Bit 5 : Port number */
11375 #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
11376 #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
11377 
11378 /* Bits 4..0 : Pin number */
11379 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
11380 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
11381 
11382 /* Register: TWIS_RXD_PTR */
11383 /* Description: RXD Data pointer */
11384 
11385 /* Bits 31..0 : RXD Data pointer */
11386 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11387 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11388 
11389 /* Register: TWIS_RXD_MAXCNT */
11390 /* Description: Maximum number of bytes in RXD buffer */
11391 
11392 /* Bits 15..0 : Maximum number of bytes in RXD buffer */
11393 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11394 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11395 
11396 /* Register: TWIS_RXD_AMOUNT */
11397 /* Description: Number of bytes transferred in the last RXD transaction */
11398 
11399 /* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
11400 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11401 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11402 
11403 /* Register: TWIS_RXD_LIST */
11404 /* Description: EasyDMA list type */
11405 
11406 /* Bits 1..0 : List type */
11407 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11408 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11409 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11410 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11411 
11412 /* Register: TWIS_TXD_PTR */
11413 /* Description: TXD Data pointer */
11414 
11415 /* Bits 31..0 : TXD Data pointer */
11416 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11417 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11418 
11419 /* Register: TWIS_TXD_MAXCNT */
11420 /* Description: Maximum number of bytes in TXD buffer */
11421 
11422 /* Bits 15..0 : Maximum number of bytes in TXD buffer */
11423 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11424 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11425 
11426 /* Register: TWIS_TXD_AMOUNT */
11427 /* Description: Number of bytes transferred in the last TXD transaction */
11428 
11429 /* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
11430 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11431 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11432 
11433 /* Register: TWIS_TXD_LIST */
11434 /* Description: EasyDMA list type */
11435 
11436 /* Bits 1..0 : List type */
11437 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11438 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11439 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11440 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11441 
11442 /* Register: TWIS_ADDRESS */
11443 /* Description: Description collection: TWI slave address n */
11444 
11445 /* Bits 6..0 : TWI slave address */
11446 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11447 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11448 
11449 /* Register: TWIS_CONFIG */
11450 /* Description: Configuration register for the address match mechanism */
11451 
11452 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11453 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
11454 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
11455 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
11456 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
11457 
11458 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
11459 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
11460 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
11461 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
11462 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
11463 
11464 /* Register: TWIS_ORC */
11465 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11466 
11467 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11468 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11469 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11470 
11471 
11472 /* Peripheral: UARTE */
11473 /* Description: UART with EasyDMA */
11474 
11475 /* Register: UARTE_TASKS_STARTRX */
11476 /* Description: Start UART receiver */
11477 
11478 /* Bit 0 : Start UART receiver */
11479 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
11480 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
11481 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
11482 
11483 /* Register: UARTE_TASKS_STOPRX */
11484 /* Description: Stop UART receiver */
11485 
11486 /* Bit 0 : Stop UART receiver */
11487 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
11488 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
11489 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
11490 
11491 /* Register: UARTE_TASKS_STARTTX */
11492 /* Description: Start UART transmitter */
11493 
11494 /* Bit 0 : Start UART transmitter */
11495 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
11496 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
11497 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
11498 
11499 /* Register: UARTE_TASKS_STOPTX */
11500 /* Description: Stop UART transmitter */
11501 
11502 /* Bit 0 : Stop UART transmitter */
11503 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
11504 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
11505 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
11506 
11507 /* Register: UARTE_TASKS_FLUSHRX */
11508 /* Description: Flush RX FIFO into RX buffer */
11509 
11510 /* Bit 0 : Flush RX FIFO into RX buffer */
11511 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
11512 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
11513 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
11514 
11515 /* Register: UARTE_SUBSCRIBE_STARTRX */
11516 /* Description: Subscribe configuration for task STARTRX */
11517 
11518 /* Bit 31 :   */
11519 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
11520 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
11521 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
11522 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
11523 
11524 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
11525 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11526 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11527 
11528 /* Register: UARTE_SUBSCRIBE_STOPRX */
11529 /* Description: Subscribe configuration for task STOPRX */
11530 
11531 /* Bit 31 :   */
11532 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
11533 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
11534 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
11535 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
11536 
11537 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
11538 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11539 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11540 
11541 /* Register: UARTE_SUBSCRIBE_STARTTX */
11542 /* Description: Subscribe configuration for task STARTTX */
11543 
11544 /* Bit 31 :   */
11545 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
11546 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
11547 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
11548 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
11549 
11550 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
11551 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11552 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11553 
11554 /* Register: UARTE_SUBSCRIBE_STOPTX */
11555 /* Description: Subscribe configuration for task STOPTX */
11556 
11557 /* Bit 31 :   */
11558 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
11559 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
11560 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
11561 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
11562 
11563 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
11564 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11565 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11566 
11567 /* Register: UARTE_SUBSCRIBE_FLUSHRX */
11568 /* Description: Subscribe configuration for task FLUSHRX */
11569 
11570 /* Bit 31 :   */
11571 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
11572 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
11573 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
11574 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
11575 
11576 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
11577 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11578 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11579 
11580 /* Register: UARTE_EVENTS_CTS */
11581 /* Description: CTS is activated (set low). Clear To Send. */
11582 
11583 /* Bit 0 : CTS is activated (set low). Clear To Send. */
11584 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
11585 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
11586 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
11587 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
11588 
11589 /* Register: UARTE_EVENTS_NCTS */
11590 /* Description: CTS is deactivated (set high). Not Clear To Send. */
11591 
11592 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
11593 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
11594 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
11595 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
11596 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
11597 
11598 /* Register: UARTE_EVENTS_RXDRDY */
11599 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
11600 
11601 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
11602 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
11603 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
11604 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
11605 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
11606 
11607 /* Register: UARTE_EVENTS_ENDRX */
11608 /* Description: Receive buffer is filled up */
11609 
11610 /* Bit 0 : Receive buffer is filled up */
11611 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
11612 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
11613 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
11614 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
11615 
11616 /* Register: UARTE_EVENTS_TXDRDY */
11617 /* Description: Data sent from TXD */
11618 
11619 /* Bit 0 : Data sent from TXD */
11620 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
11621 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
11622 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
11623 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
11624 
11625 /* Register: UARTE_EVENTS_ENDTX */
11626 /* Description: Last TX byte transmitted */
11627 
11628 /* Bit 0 : Last TX byte transmitted */
11629 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
11630 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
11631 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
11632 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
11633 
11634 /* Register: UARTE_EVENTS_ERROR */
11635 /* Description: Error detected */
11636 
11637 /* Bit 0 : Error detected */
11638 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
11639 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
11640 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
11641 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
11642 
11643 /* Register: UARTE_EVENTS_RXTO */
11644 /* Description: Receiver timeout */
11645 
11646 /* Bit 0 : Receiver timeout */
11647 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
11648 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
11649 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
11650 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
11651 
11652 /* Register: UARTE_EVENTS_RXSTARTED */
11653 /* Description: UART receiver has started */
11654 
11655 /* Bit 0 : UART receiver has started */
11656 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
11657 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
11658 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
11659 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
11660 
11661 /* Register: UARTE_EVENTS_TXSTARTED */
11662 /* Description: UART transmitter has started */
11663 
11664 /* Bit 0 : UART transmitter has started */
11665 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
11666 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
11667 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
11668 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
11669 
11670 /* Register: UARTE_EVENTS_TXSTOPPED */
11671 /* Description: Transmitter stopped */
11672 
11673 /* Bit 0 : Transmitter stopped */
11674 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
11675 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
11676 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
11677 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
11678 
11679 /* Register: UARTE_PUBLISH_CTS */
11680 /* Description: Publish configuration for event CTS */
11681 
11682 /* Bit 31 :   */
11683 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
11684 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
11685 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
11686 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
11687 
11688 /* Bits 7..0 : DPPI channel that event CTS will publish to. */
11689 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11690 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11691 
11692 /* Register: UARTE_PUBLISH_NCTS */
11693 /* Description: Publish configuration for event NCTS */
11694 
11695 /* Bit 31 :   */
11696 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
11697 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
11698 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
11699 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
11700 
11701 /* Bits 7..0 : DPPI channel that event NCTS will publish to. */
11702 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11703 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11704 
11705 /* Register: UARTE_PUBLISH_RXDRDY */
11706 /* Description: Publish configuration for event RXDRDY */
11707 
11708 /* Bit 31 :   */
11709 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
11710 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
11711 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
11712 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
11713 
11714 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to. */
11715 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11716 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11717 
11718 /* Register: UARTE_PUBLISH_ENDRX */
11719 /* Description: Publish configuration for event ENDRX */
11720 
11721 /* Bit 31 :   */
11722 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
11723 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
11724 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
11725 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
11726 
11727 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
11728 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11729 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11730 
11731 /* Register: UARTE_PUBLISH_TXDRDY */
11732 /* Description: Publish configuration for event TXDRDY */
11733 
11734 /* Bit 31 :   */
11735 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
11736 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
11737 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
11738 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
11739 
11740 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to. */
11741 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11742 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11743 
11744 /* Register: UARTE_PUBLISH_ENDTX */
11745 /* Description: Publish configuration for event ENDTX */
11746 
11747 /* Bit 31 :   */
11748 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
11749 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
11750 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
11751 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
11752 
11753 /* Bits 7..0 : DPPI channel that event ENDTX will publish to. */
11754 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11755 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11756 
11757 /* Register: UARTE_PUBLISH_ERROR */
11758 /* Description: Publish configuration for event ERROR */
11759 
11760 /* Bit 31 :   */
11761 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
11762 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
11763 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
11764 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
11765 
11766 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
11767 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11768 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11769 
11770 /* Register: UARTE_PUBLISH_RXTO */
11771 /* Description: Publish configuration for event RXTO */
11772 
11773 /* Bit 31 :   */
11774 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
11775 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
11776 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
11777 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
11778 
11779 /* Bits 7..0 : DPPI channel that event RXTO will publish to. */
11780 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11781 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11782 
11783 /* Register: UARTE_PUBLISH_RXSTARTED */
11784 /* Description: Publish configuration for event RXSTARTED */
11785 
11786 /* Bit 31 :   */
11787 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
11788 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
11789 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
11790 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
11791 
11792 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
11793 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11794 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11795 
11796 /* Register: UARTE_PUBLISH_TXSTARTED */
11797 /* Description: Publish configuration for event TXSTARTED */
11798 
11799 /* Bit 31 :   */
11800 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
11801 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
11802 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
11803 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
11804 
11805 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
11806 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11807 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11808 
11809 /* Register: UARTE_PUBLISH_TXSTOPPED */
11810 /* Description: Publish configuration for event TXSTOPPED */
11811 
11812 /* Bit 31 :   */
11813 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
11814 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
11815 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
11816 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
11817 
11818 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to. */
11819 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11820 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11821 
11822 /* Register: UARTE_SHORTS */
11823 /* Description: Shortcuts between local events and tasks */
11824 
11825 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
11826 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
11827 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
11828 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
11829 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
11830 
11831 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
11832 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
11833 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
11834 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11835 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11836 
11837 /* Register: UARTE_INTEN */
11838 /* Description: Enable or disable interrupt */
11839 
11840 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
11841 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
11842 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
11843 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
11844 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
11845 
11846 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
11847 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11848 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11849 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11850 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11851 
11852 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
11853 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11854 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11855 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11856 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11857 
11858 /* Bit 17 : Enable or disable interrupt for event RXTO */
11859 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11860 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
11861 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
11862 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
11863 
11864 /* Bit 9 : Enable or disable interrupt for event ERROR */
11865 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11866 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11867 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11868 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11869 
11870 /* Bit 8 : Enable or disable interrupt for event ENDTX */
11871 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11872 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11873 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
11874 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
11875 
11876 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
11877 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11878 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11879 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
11880 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
11881 
11882 /* Bit 4 : Enable or disable interrupt for event ENDRX */
11883 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11884 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11885 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
11886 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
11887 
11888 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
11889 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11890 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11891 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
11892 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
11893 
11894 /* Bit 1 : Enable or disable interrupt for event NCTS */
11895 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11896 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
11897 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
11898 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
11899 
11900 /* Bit 0 : Enable or disable interrupt for event CTS */
11901 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
11902 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
11903 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
11904 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
11905 
11906 /* Register: UARTE_INTENSET */
11907 /* Description: Enable interrupt */
11908 
11909 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
11910 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
11911 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
11912 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
11913 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
11914 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
11915 
11916 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
11917 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11918 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11919 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11920 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11921 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11922 
11923 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
11924 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11925 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11926 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11927 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11928 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11929 
11930 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
11931 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11932 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
11933 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
11934 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11935 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
11936 
11937 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
11938 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11939 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11940 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11941 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11942 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
11943 
11944 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
11945 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11946 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11947 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
11948 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
11949 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
11950 
11951 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
11952 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11953 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11954 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11955 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11956 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
11957 
11958 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
11959 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11960 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11961 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
11962 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
11963 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
11964 
11965 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
11966 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11967 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11968 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11969 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11970 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
11971 
11972 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
11973 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11974 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
11975 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
11976 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11977 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
11978 
11979 /* Bit 0 : Write '1' to enable interrupt for event CTS */
11980 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
11981 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
11982 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
11983 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11984 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
11985 
11986 /* Register: UARTE_INTENCLR */
11987 /* Description: Disable interrupt */
11988 
11989 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
11990 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
11991 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
11992 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
11993 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
11994 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
11995 
11996 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
11997 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11998 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11999 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12000 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12001 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
12002 
12003 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
12004 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12005 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12006 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12007 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12008 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
12009 
12010 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
12011 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12012 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
12013 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
12014 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12015 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
12016 
12017 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
12018 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12019 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
12020 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12021 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12022 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12023 
12024 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
12025 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12026 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12027 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12028 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12029 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12030 
12031 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
12032 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12033 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12034 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12035 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12036 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
12037 
12038 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12039 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12040 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12041 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12042 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12043 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12044 
12045 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
12046 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12047 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12048 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12049 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12050 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
12051 
12052 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
12053 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12054 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
12055 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
12056 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12057 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
12058 
12059 /* Bit 0 : Write '1' to disable interrupt for event CTS */
12060 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
12061 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
12062 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12063 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12064 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
12065 
12066 /* Register: UARTE_ERRORSRC */
12067 /* Description: Error source */
12068 
12069 /* Bit 3 : Break condition */
12070 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
12071 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
12072 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
12073 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
12074 
12075 /* Bit 2 : Framing error occurred */
12076 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
12077 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
12078 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
12079 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
12080 
12081 /* Bit 1 : Parity error */
12082 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12083 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
12084 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
12085 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
12086 
12087 /* Bit 0 : Overrun error */
12088 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
12089 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
12090 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
12091 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12092 
12093 /* Register: UARTE_ENABLE */
12094 /* Description: Enable UART */
12095 
12096 /* Bits 3..0 : Enable or disable UARTE */
12097 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12098 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12099 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
12100 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
12101 
12102 /* Register: UARTE_PSEL_RTS */
12103 /* Description: Pin select for RTS signal */
12104 
12105 /* Bit 31 : Connection */
12106 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12107 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12108 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
12109 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12110 
12111 /* Bit 5 : Port number */
12112 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
12113 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
12114 
12115 /* Bits 4..0 : Pin number */
12116 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12117 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
12118 
12119 /* Register: UARTE_PSEL_TXD */
12120 /* Description: Pin select for TXD signal */
12121 
12122 /* Bit 31 : Connection */
12123 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12124 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12125 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
12126 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12127 
12128 /* Bit 5 : Port number */
12129 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
12130 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
12131 
12132 /* Bits 4..0 : Pin number */
12133 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12134 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
12135 
12136 /* Register: UARTE_PSEL_CTS */
12137 /* Description: Pin select for CTS signal */
12138 
12139 /* Bit 31 : Connection */
12140 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12141 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12142 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
12143 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12144 
12145 /* Bit 5 : Port number */
12146 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
12147 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
12148 
12149 /* Bits 4..0 : Pin number */
12150 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12151 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
12152 
12153 /* Register: UARTE_PSEL_RXD */
12154 /* Description: Pin select for RXD signal */
12155 
12156 /* Bit 31 : Connection */
12157 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12158 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12159 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
12160 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12161 
12162 /* Bit 5 : Port number */
12163 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
12164 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
12165 
12166 /* Bits 4..0 : Pin number */
12167 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12168 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
12169 
12170 /* Register: UARTE_BAUDRATE */
12171 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
12172 
12173 /* Bits 31..0 : Baud rate */
12174 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
12175 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
12176 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
12177 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
12178 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
12179 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
12180 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
12181 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
12182 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
12183 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
12184 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
12185 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
12186 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
12187 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
12188 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
12189 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
12190 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
12191 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
12192 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
12193 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
12194 
12195 /* Register: UARTE_RXD_PTR */
12196 /* Description: Data pointer */
12197 
12198 /* Bits 31..0 : Data pointer */
12199 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12200 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12201 
12202 /* Register: UARTE_RXD_MAXCNT */
12203 /* Description: Maximum number of bytes in receive buffer */
12204 
12205 /* Bits 15..0 : Maximum number of bytes in receive buffer */
12206 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12207 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12208 
12209 /* Register: UARTE_RXD_AMOUNT */
12210 /* Description: Number of bytes transferred in the last transaction */
12211 
12212 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12213 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12214 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12215 
12216 /* Register: UARTE_TXD_PTR */
12217 /* Description: Data pointer */
12218 
12219 /* Bits 31..0 : Data pointer */
12220 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12221 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12222 
12223 /* Register: UARTE_TXD_MAXCNT */
12224 /* Description: Maximum number of bytes in transmit buffer */
12225 
12226 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
12227 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12228 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12229 
12230 /* Register: UARTE_TXD_AMOUNT */
12231 /* Description: Number of bytes transferred in the last transaction */
12232 
12233 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12234 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12235 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12236 
12237 /* Register: UARTE_CONFIG */
12238 /* Description: Configuration of parity and hardware flow control */
12239 
12240 /* Bit 8 : Even or odd parity type */
12241 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
12242 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
12243 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
12244 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
12245 
12246 /* Bit 4 : Stop bits */
12247 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
12248 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
12249 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
12250 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
12251 
12252 /* Bits 3..1 : Parity */
12253 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12254 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
12255 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
12256 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
12257 
12258 /* Bit 0 : Hardware flow control */
12259 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
12260 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
12261 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12262 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12263 
12264 
12265 /* Peripheral: UICR */
12266 /* Description: User Information Configuration Registers */
12267 
12268 /* Register: UICR_APPROTECT */
12269 /* Description: Access port protection */
12270 
12271 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and memory mapped
12272         addresses. */
12273 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
12274 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
12275 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
12276 #define UICR_APPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */
12277 
12278 /* Register: UICR_ERASEPROTECT */
12279 /* Description: Erase protection */
12280 
12281 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. */
12282 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
12283 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
12284 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
12285 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
12286 
12287 /* Register: UICR_NRFFW */
12288 /* Description: Description collection: Reserved for Nordic firmware design */
12289 
12290 /* Bits 31..0 : Reserved for Nordic firmware design */
12291 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
12292 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
12293 
12294 /* Register: UICR_CUSTOMER */
12295 /* Description: Description collection: Reserved for customer */
12296 
12297 /* Bits 31..0 : Reserved for customer */
12298 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
12299 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
12300 
12301 
12302 /* Peripheral: VMC */
12303 /* Description: Volatile Memory controller */
12304 
12305 /* Register: VMC_RAM_POWER */
12306 /* Description: Description cluster: RAM[n] power control register */
12307 
12308 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
12309 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
12310 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
12311 #define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
12312 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
12313 
12314 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
12315 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
12316 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
12317 #define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
12318 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
12319 
12320 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
12321 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
12322 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
12323 #define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
12324 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
12325 
12326 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
12327 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
12328 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
12329 #define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
12330 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
12331 
12332 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
12333 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
12334 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
12335 #define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
12336 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
12337 
12338 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
12339 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
12340 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
12341 #define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
12342 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
12343 
12344 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
12345 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
12346 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
12347 #define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
12348 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
12349 
12350 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
12351 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
12352 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
12353 #define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
12354 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
12355 
12356 /* Register: VMC_RAM_POWERSET */
12357 /* Description: Description cluster: RAM[n] power control set register */
12358 
12359 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
12360 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
12361 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
12362 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
12363 
12364 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
12365 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
12366 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
12367 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
12368 
12369 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
12370 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
12371 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
12372 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
12373 
12374 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
12375 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
12376 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
12377 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
12378 
12379 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
12380 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
12381 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
12382 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
12383 
12384 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
12385 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
12386 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
12387 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
12388 
12389 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
12390 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
12391 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
12392 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
12393 
12394 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
12395 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
12396 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
12397 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
12398 
12399 /* Register: VMC_RAM_POWERCLR */
12400 /* Description: Description cluster: RAM[n] power control clear register */
12401 
12402 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
12403 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
12404 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
12405 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
12406 
12407 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
12408 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
12409 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
12410 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
12411 
12412 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
12413 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
12414 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
12415 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
12416 
12417 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
12418 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
12419 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
12420 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
12421 
12422 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
12423 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
12424 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
12425 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
12426 
12427 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
12428 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
12429 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
12430 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
12431 
12432 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
12433 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
12434 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
12435 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
12436 
12437 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
12438 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
12439 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
12440 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
12441 
12442 
12443 /* Peripheral: VREQCTRL */
12444 /* Description: Voltage request control */
12445 
12446 /* Register: VREQCTRL_VREGRADIO_VREQH */
12447 /* Description: Request high voltage on RADIO After requesting high voltage, the user must wait until VREQHREADY is set to Ready */
12448 
12449 /* Bit 0 : Request high voltage */
12450 #define VREQCTRL_VREGRADIO_VREQH_VREQH_Pos (0UL) /*!< Position of VREQH field. */
12451 #define VREQCTRL_VREGRADIO_VREQH_VREQH_Msk (0x1UL << VREQCTRL_VREGRADIO_VREQH_VREQH_Pos) /*!< Bit mask of VREQH field. */
12452 #define VREQCTRL_VREGRADIO_VREQH_VREQH_Disabled (0UL) /*!< Disable */
12453 #define VREQCTRL_VREGRADIO_VREQH_VREQH_Enabled (1UL) /*!< Enable */
12454 
12455 /* Register: VREQCTRL_VREGRADIO_VREQHREADY */
12456 /* Description: High voltage on RADIO is ready */
12457 
12458 /* Bit 0 : RADIO is ready to operate on high voltage */
12459 #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Pos (0UL) /*!< Position of READY field. */
12460 #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Msk (0x1UL << VREQCTRL_VREGRADIO_VREQHREADY_READY_Pos) /*!< Bit mask of READY field. */
12461 #define VREQCTRL_VREGRADIO_VREQHREADY_READY_NotReady (0UL) /*!< Not ready */
12462 #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Ready (1UL) /*!< Ready */
12463 
12464 
12465 /* Peripheral: WDT */
12466 /* Description: Watchdog Timer */
12467 
12468 /* Register: WDT_TASKS_START */
12469 /* Description: Start WDT */
12470 
12471 /* Bit 0 : Start WDT */
12472 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12473 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12474 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12475 
12476 /* Register: WDT_TASKS_STOP */
12477 /* Description: Stop WDT */
12478 
12479 /* Bit 0 : Stop WDT */
12480 #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12481 #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12482 #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12483 
12484 /* Register: WDT_SUBSCRIBE_START */
12485 /* Description: Subscribe configuration for task START */
12486 
12487 /* Bit 31 :   */
12488 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
12489 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
12490 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
12491 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
12492 
12493 /* Bits 7..0 : DPPI channel that task START will subscribe to */
12494 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12495 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12496 
12497 /* Register: WDT_SUBSCRIBE_STOP */
12498 /* Description: Subscribe configuration for task STOP */
12499 
12500 /* Bit 31 :   */
12501 #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
12502 #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
12503 #define WDT_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
12504 #define WDT_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
12505 
12506 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
12507 #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12508 #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12509 
12510 /* Register: WDT_EVENTS_TIMEOUT */
12511 /* Description: Watchdog timeout */
12512 
12513 /* Bit 0 : Watchdog timeout */
12514 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
12515 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
12516 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
12517 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
12518 
12519 /* Register: WDT_EVENTS_STOPPED */
12520 /* Description: Watchdog stopped */
12521 
12522 /* Bit 0 : Watchdog stopped */
12523 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12524 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12525 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12526 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12527 
12528 /* Register: WDT_PUBLISH_TIMEOUT */
12529 /* Description: Publish configuration for event TIMEOUT */
12530 
12531 /* Bit 31 :   */
12532 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
12533 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
12534 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
12535 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
12536 
12537 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to. */
12538 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12539 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12540 
12541 /* Register: WDT_PUBLISH_STOPPED */
12542 /* Description: Publish configuration for event STOPPED */
12543 
12544 /* Bit 31 :   */
12545 #define WDT_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
12546 #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
12547 #define WDT_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
12548 #define WDT_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
12549 
12550 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
12551 #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12552 #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12553 
12554 /* Register: WDT_INTENSET */
12555 /* Description: Enable interrupt */
12556 
12557 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12558 #define WDT_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12559 #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12560 #define WDT_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12561 #define WDT_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12562 #define WDT_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12563 
12564 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
12565 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12566 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12567 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12568 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12569 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
12570 
12571 /* Register: WDT_INTENCLR */
12572 /* Description: Disable interrupt */
12573 
12574 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12575 #define WDT_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12576 #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12577 #define WDT_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12578 #define WDT_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12579 #define WDT_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12580 
12581 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
12582 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12583 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12584 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12585 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12586 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12587 
12588 /* Register: WDT_NMIENSET */
12589 /* Description: Enable interrupt */
12590 
12591 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12592 #define WDT_NMIENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12593 #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12594 #define WDT_NMIENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12595 #define WDT_NMIENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12596 #define WDT_NMIENSET_STOPPED_Set (1UL) /*!< Enable */
12597 
12598 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
12599 #define WDT_NMIENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12600 #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12601 #define WDT_NMIENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12602 #define WDT_NMIENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12603 #define WDT_NMIENSET_TIMEOUT_Set (1UL) /*!< Enable */
12604 
12605 /* Register: WDT_NMIENCLR */
12606 /* Description: Disable interrupt */
12607 
12608 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12609 #define WDT_NMIENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12610 #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12611 #define WDT_NMIENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12612 #define WDT_NMIENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12613 #define WDT_NMIENCLR_STOPPED_Clear (1UL) /*!< Disable */
12614 
12615 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
12616 #define WDT_NMIENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12617 #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12618 #define WDT_NMIENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12619 #define WDT_NMIENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12620 #define WDT_NMIENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12621 
12622 /* Register: WDT_RUNSTATUS */
12623 /* Description: Run status */
12624 
12625 /* Bit 0 : Indicates whether or not WDT is running */
12626 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
12627 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
12628 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog is not running */
12629 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
12630 
12631 /* Register: WDT_REQSTATUS */
12632 /* Description: Request status */
12633 
12634 /* Bit 7 : Request status for RR[7] register */
12635 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
12636 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
12637 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
12638 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
12639 
12640 /* Bit 6 : Request status for RR[6] register */
12641 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
12642 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
12643 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
12644 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
12645 
12646 /* Bit 5 : Request status for RR[5] register */
12647 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
12648 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
12649 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
12650 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
12651 
12652 /* Bit 4 : Request status for RR[4] register */
12653 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
12654 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
12655 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
12656 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
12657 
12658 /* Bit 3 : Request status for RR[3] register */
12659 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
12660 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
12661 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
12662 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
12663 
12664 /* Bit 2 : Request status for RR[2] register */
12665 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
12666 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
12667 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
12668 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
12669 
12670 /* Bit 1 : Request status for RR[1] register */
12671 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
12672 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
12673 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
12674 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
12675 
12676 /* Bit 0 : Request status for RR[0] register */
12677 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
12678 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
12679 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
12680 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
12681 
12682 /* Register: WDT_CRV */
12683 /* Description: Counter reload value */
12684 
12685 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
12686 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
12687 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
12688 
12689 /* Register: WDT_RREN */
12690 /* Description: Enable register for reload request registers */
12691 
12692 /* Bit 7 : Enable or disable RR[7] register */
12693 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
12694 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
12695 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
12696 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12697 
12698 /* Bit 6 : Enable or disable RR[6] register */
12699 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
12700 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
12701 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
12702 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12703 
12704 /* Bit 5 : Enable or disable RR[5] register */
12705 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
12706 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
12707 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
12708 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12709 
12710 /* Bit 4 : Enable or disable RR[4] register */
12711 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
12712 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
12713 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
12714 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12715 
12716 /* Bit 3 : Enable or disable RR[3] register */
12717 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
12718 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
12719 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
12720 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12721 
12722 /* Bit 2 : Enable or disable RR[2] register */
12723 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
12724 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
12725 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12726 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12727 
12728 /* Bit 1 : Enable or disable RR[1] register */
12729 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
12730 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
12731 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12732 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12733 
12734 /* Bit 0 : Enable or disable RR[0] register */
12735 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
12736 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
12737 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
12738 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
12739 
12740 /* Register: WDT_CONFIG */
12741 /* Description: Configuration register */
12742 
12743 /* Bit 6 : Allow stopping WDT */
12744 #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */
12745 #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */
12746 #define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping WDT */
12747 #define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping WDT */
12748 
12749 /* Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */
12750 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
12751 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
12752 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause WDT while the CPU is halted by the debugger */
12753 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep WDT running while the CPU is halted by the debugger */
12754 
12755 /* Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */
12756 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
12757 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
12758 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause WDT while the CPU is sleeping */
12759 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep WDT running while the CPU is sleeping */
12760 
12761 /* Register: WDT_TSEN */
12762 /* Description: Task stop enable */
12763 
12764 /* Bits 31..0 : Allow stopping WDT */
12765 #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */
12766 #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */
12767 #define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */
12768 
12769 /* Register: WDT_RR */
12770 /* Description: Description collection: Reload request n */
12771 
12772 /* Bits 31..0 : Reload request register */
12773 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
12774 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
12775 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
12776 
12777 
12778 /*lint --flb "Leave library region" */
12779 #endif
12780