1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52840.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:07 37 * from File 'nrf52840.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52840 49 * @{ 50 */ 51 52 53 #ifndef NRF52840_H 54 #define NRF52840_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 91 NFCT_IRQn = 5, /*!< 5 NFCT */ 92 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 93 SAADC_IRQn = 7, /*!< 7 SAADC */ 94 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 95 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 96 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 97 RTC0_IRQn = 11, /*!< 11 RTC0 */ 98 TEMP_IRQn = 12, /*!< 12 TEMP */ 99 RNG_IRQn = 13, /*!< 13 RNG */ 100 ECB_IRQn = 14, /*!< 14 ECB */ 101 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 102 WDT_IRQn = 16, /*!< 16 WDT */ 103 RTC1_IRQn = 17, /*!< 17 RTC1 */ 104 QDEC_IRQn = 18, /*!< 18 QDEC */ 105 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 106 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 107 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 108 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 109 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 110 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 111 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 112 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 113 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 114 PWM0_IRQn = 28, /*!< 28 PWM0 */ 115 PDM_IRQn = 29, /*!< 29 PDM */ 116 MWU_IRQn = 32, /*!< 32 MWU */ 117 PWM1_IRQn = 33, /*!< 33 PWM1 */ 118 PWM2_IRQn = 34, /*!< 34 PWM2 */ 119 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 120 RTC2_IRQn = 36, /*!< 36 RTC2 */ 121 I2S_IRQn = 37, /*!< 37 I2S */ 122 FPU_IRQn = 38, /*!< 38 FPU */ 123 USBD_IRQn = 39, /*!< 39 USBD */ 124 UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 125 QSPI_IRQn = 41, /*!< 41 QSPI */ 126 CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ 127 PWM3_IRQn = 45, /*!< 45 PWM3 */ 128 SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 129 } IRQn_Type; 130 131 132 133 /* =========================================================================================================================== */ 134 /* ================ Processor and Core Peripheral Section ================ */ 135 /* =========================================================================================================================== */ 136 137 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 138 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 139 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 140 #define __DSP_PRESENT 1 /*!< DSP present or not */ 141 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 142 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 143 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 144 #define __MPU_PRESENT 1 /*!< MPU present */ 145 #define __FPU_PRESENT 1 /*!< FPU present */ 146 147 148 /** @} */ /* End of group Configuration_of_CMSIS */ 149 150 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 151 #include "system_nrf52840.h" /*!< nrf52840 System */ 152 153 #ifndef __IM /*!< Fallback for older CMSIS versions */ 154 #define __IM __I 155 #endif 156 #ifndef __OM /*!< Fallback for older CMSIS versions */ 157 #define __OM __O 158 #endif 159 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 160 #define __IOM __IO 161 #endif 162 163 164 /* ======================================== Start of section using anonymous unions ======================================== */ 165 #if defined (__CC_ARM) 166 #pragma push 167 #pragma anon_unions 168 #elif defined (__ICCARM__) 169 #pragma language=extended 170 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 171 #pragma clang diagnostic push 172 #pragma clang diagnostic ignored "-Wc11-extensions" 173 #pragma clang diagnostic ignored "-Wreserved-id-macro" 174 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 175 #pragma clang diagnostic ignored "-Wnested-anon-types" 176 #elif defined (__GNUC__) 177 /* anonymous unions are enabled by default */ 178 #elif defined (__TMS470__) 179 /* anonymous unions are enabled by default */ 180 #elif defined (__TASKING__) 181 #pragma warning 586 182 #elif defined (__CSMC__) 183 /* anonymous unions are enabled by default */ 184 #else 185 #warning Not supported compiler type 186 #endif 187 188 189 /* =========================================================================================================================== */ 190 /* ================ Device Specific Cluster Section ================ */ 191 /* =========================================================================================================================== */ 192 193 194 /** @addtogroup Device_Peripheral_clusters 195 * @{ 196 */ 197 198 199 /** 200 * @brief FICR_INFO [INFO] (Device info) 201 */ 202 typedef struct { 203 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 204 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 205 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 206 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 207 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 208 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 209 210 211 /** 212 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 213 */ 214 typedef struct { 215 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 216 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 217 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 218 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 219 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 220 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 221 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 222 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 223 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 224 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 225 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 226 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 227 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 228 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 229 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 230 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 231 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 232 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 233 234 235 /** 236 * @brief FICR_NFC [NFC] (Unspecified) 237 */ 238 typedef struct { 239 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 240 these values to populate NFCID1_3RD_LAST, 241 NFCID1_2ND_LAST, and NFCID1_LAST. */ 242 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 243 these values to populate NFCID1_3RD_LAST, 244 NFCID1_2ND_LAST, and NFCID1_LAST. */ 245 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 246 these values to populate NFCID1_3RD_LAST, 247 NFCID1_2ND_LAST, and NFCID1_LAST. */ 248 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 249 these values to populate NFCID1_3RD_LAST, 250 NFCID1_2ND_LAST, and NFCID1_LAST. */ 251 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 252 253 254 /** 255 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 256 */ 257 typedef struct { 258 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 259 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 260 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 261 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 262 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 263 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 264 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 265 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 266 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 267 268 269 /** 270 * @brief POWER_RAM [RAM] (Unspecified) 271 */ 272 typedef struct { 273 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 274 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 275 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 276 register */ 277 __IM uint32_t RESERVED; 278 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 279 280 281 /** 282 * @brief UART_PSEL [PSEL] (Unspecified) 283 */ 284 typedef struct { 285 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 286 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 287 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 288 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 289 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 290 291 292 /** 293 * @brief UARTE_PSEL [PSEL] (Unspecified) 294 */ 295 typedef struct { 296 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 297 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 298 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 299 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 300 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 301 302 303 /** 304 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 305 */ 306 typedef struct { 307 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 308 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 309 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 310 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 311 312 313 /** 314 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 315 */ 316 typedef struct { 317 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 318 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 319 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 320 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 321 322 323 /** 324 * @brief SPI_PSEL [PSEL] (Unspecified) 325 */ 326 typedef struct { 327 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 328 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 329 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 330 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 331 332 333 /** 334 * @brief SPIM_PSEL [PSEL] (Unspecified) 335 */ 336 typedef struct { 337 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 338 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 339 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 340 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 341 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 342 343 344 /** 345 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 346 */ 347 typedef struct { 348 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 349 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 350 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 351 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 352 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 353 354 355 /** 356 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 357 */ 358 typedef struct { 359 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 360 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 361 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 362 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 363 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 364 365 366 /** 367 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 368 */ 369 typedef struct { 370 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 371 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 372 of SCK and minimum duration CSN must stay 373 high between transactions */ 374 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 375 376 377 /** 378 * @brief SPIS_PSEL [PSEL] (Unspecified) 379 */ 380 typedef struct { 381 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 382 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 383 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 384 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 385 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 386 387 388 /** 389 * @brief SPIS_RXD [RXD] (Unspecified) 390 */ 391 typedef struct { 392 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 393 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 394 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 395 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 396 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 397 398 399 /** 400 * @brief SPIS_TXD [TXD] (Unspecified) 401 */ 402 typedef struct { 403 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 404 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 405 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 406 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 407 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 408 409 410 /** 411 * @brief TWI_PSEL [PSEL] (Unspecified) 412 */ 413 typedef struct { 414 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 415 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 416 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 417 418 419 /** 420 * @brief TWIM_PSEL [PSEL] (Unspecified) 421 */ 422 typedef struct { 423 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 424 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 425 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 426 427 428 /** 429 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 430 */ 431 typedef struct { 432 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 433 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 434 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 435 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 436 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 437 438 439 /** 440 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 441 */ 442 typedef struct { 443 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 444 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 445 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 446 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 447 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 448 449 450 /** 451 * @brief TWIS_PSEL [PSEL] (Unspecified) 452 */ 453 typedef struct { 454 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 455 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 456 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 457 458 459 /** 460 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 461 */ 462 typedef struct { 463 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 464 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 465 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 466 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 467 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 468 469 470 /** 471 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 472 */ 473 typedef struct { 474 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 475 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 476 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 477 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 478 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 479 480 481 /** 482 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 483 */ 484 typedef struct { 485 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 486 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 487 488 489 /** 490 * @brief NFCT_TXD [TXD] (Unspecified) 491 */ 492 typedef struct { 493 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 494 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 495 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 496 497 498 /** 499 * @brief NFCT_RXD [RXD] (Unspecified) 500 */ 501 typedef struct { 502 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 503 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 504 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 505 506 507 /** 508 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 509 */ 510 typedef struct { 511 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or 512 above CH[n].LIMIT.HIGH */ 513 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or 514 below CH[n].LIMIT.LOW */ 515 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 516 517 518 /** 519 * @brief SAADC_CH [CH] (Unspecified) 520 */ 521 typedef struct { 522 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 523 for CH[n] */ 524 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 525 for CH[n] */ 526 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 527 CH[n] */ 528 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 529 monitoring of a channel */ 530 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 531 532 533 /** 534 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 535 */ 536 typedef struct { 537 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 538 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 539 to output RAM buffer */ 540 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 541 buffer since the previous START task */ 542 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 543 544 545 /** 546 * @brief QDEC_PSEL [PSEL] (Unspecified) 547 */ 548 typedef struct { 549 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 550 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 551 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 552 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 553 554 555 /** 556 * @brief PWM_SEQ [SEQ] (Unspecified) 557 */ 558 typedef struct { 559 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 560 of this sequence */ 561 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 562 in this sequence */ 563 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 564 periods between samples loaded into compare 565 register */ 566 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 567 __IM uint32_t RESERVED[4]; 568 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 569 570 571 /** 572 * @brief PWM_PSEL [PSEL] (Unspecified) 573 */ 574 typedef struct { 575 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 576 PWM channel n */ 577 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 578 579 580 /** 581 * @brief PDM_PSEL [PSEL] (Unspecified) 582 */ 583 typedef struct { 584 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 585 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 586 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 587 588 589 /** 590 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 591 */ 592 typedef struct { 593 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 594 EasyDMA */ 595 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 596 mode */ 597 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 598 599 600 /** 601 * @brief ACL_ACL [ACL] (Unspecified) 602 */ 603 typedef struct { 604 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region 605 to protect. The start address must be word-aligned. */ 606 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 607 counting from address ACL[n].ADDR. Writing 608 a '0' has no effect. */ 609 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 610 n as defined by start address ACL[n].ADDR 611 and size ACL[n].SIZE */ 612 __IM uint32_t RESERVED; 613 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 614 615 616 /** 617 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 618 */ 619 typedef struct { 620 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 621 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 622 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 623 624 625 /** 626 * @brief PPI_CH [CH] (PPI Channel) 627 */ 628 typedef struct { 629 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 630 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 631 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 632 633 634 /** 635 * @brief PPI_FORK [FORK] (Fork) 636 */ 637 typedef struct { 638 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 639 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 640 641 642 /** 643 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) 644 */ 645 typedef struct { 646 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n 647 detected */ 648 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n 649 detected */ 650 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 651 652 653 /** 654 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) 655 */ 656 typedef struct { 657 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral 658 region n detected */ 659 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral 660 region n detected */ 661 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 662 663 664 /** 665 * @brief MWU_PERREGION [PERREGION] (Unspecified) 666 */ 667 typedef struct { 668 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt 669 in region n, write access detected while 670 corresponding subregion was enabled for 671 watching */ 672 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt 673 in region n, read access detected while 674 corresponding subregion was enabled for 675 watching */ 676 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 677 678 679 /** 680 * @brief MWU_REGION [REGION] (Unspecified) 681 */ 682 typedef struct { 683 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region 684 n */ 685 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ 686 __IM uint32_t RESERVED[2]; 687 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 688 689 690 /** 691 * @brief MWU_PREGION [PREGION] (Unspecified) 692 */ 693 typedef struct { 694 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ 695 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ 696 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ 697 __IM uint32_t RESERVED; 698 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 699 700 701 /** 702 * @brief I2S_CONFIG [CONFIG] (Unspecified) 703 */ 704 typedef struct { 705 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 706 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 707 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 708 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 709 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 710 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 711 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 712 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 713 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 714 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 715 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 716 717 718 /** 719 * @brief I2S_RXD [RXD] (Unspecified) 720 */ 721 typedef struct { 722 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 723 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 724 725 726 /** 727 * @brief I2S_TXD [TXD] (Unspecified) 728 */ 729 typedef struct { 730 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 731 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 732 733 734 /** 735 * @brief I2S_RXTXD [RXTXD] (Unspecified) 736 */ 737 typedef struct { 738 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 739 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 740 741 742 /** 743 * @brief I2S_PSEL [PSEL] (Unspecified) 744 */ 745 typedef struct { 746 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 747 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 748 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 749 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 750 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 751 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 752 753 754 /** 755 * @brief USBD_HALTED [HALTED] (Unspecified) 756 */ 757 typedef struct { 758 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 759 Can be used as is as response to a GetStatus() 760 request to endpoint. */ 761 __IM uint32_t RESERVED; 762 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 763 Can be used as is as response to a GetStatus() 764 request to endpoint. */ 765 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 766 767 768 /** 769 * @brief USBD_SIZE [SIZE] (Unspecified) 770 */ 771 typedef struct { 772 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 773 last in the data stage of this OUT endpoint */ 774 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 775 data endpoint */ 776 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 777 778 779 /** 780 * @brief USBD_EPIN [EPIN] (Unspecified) 781 */ 782 typedef struct { 783 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 784 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 785 to transfer */ 786 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 787 in the last transaction */ 788 __IM uint32_t RESERVED[2]; 789 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 790 791 792 /** 793 * @brief USBD_ISOIN [ISOIN] (Unspecified) 794 */ 795 typedef struct { 796 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 797 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 798 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 799 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 800 801 802 /** 803 * @brief USBD_EPOUT [EPOUT] (Unspecified) 804 */ 805 typedef struct { 806 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 807 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 808 to transfer */ 809 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 810 in the last transaction */ 811 __IM uint32_t RESERVED[2]; 812 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 813 814 815 /** 816 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 817 */ 818 typedef struct { 819 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 820 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 821 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 822 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 823 824 825 /** 826 * @brief QSPI_READ [READ] (Unspecified) 827 */ 828 typedef struct { 829 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 830 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 831 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 832 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 833 834 835 /** 836 * @brief QSPI_WRITE [WRITE] (Unspecified) 837 */ 838 typedef struct { 839 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 840 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 841 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 842 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 843 844 845 /** 846 * @brief QSPI_ERASE [ERASE] (Unspecified) 847 */ 848 typedef struct { 849 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 850 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 851 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 852 853 854 /** 855 * @brief QSPI_PSEL [PSEL] (Unspecified) 856 */ 857 typedef struct { 858 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 859 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 860 __IM uint32_t RESERVED; 861 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 862 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 863 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ 864 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ 865 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 866 867 868 /** @} */ /* End of group Device_Peripheral_clusters */ 869 870 871 /* =========================================================================================================================== */ 872 /* ================ Device Specific Peripheral Section ================ */ 873 /* =========================================================================================================================== */ 874 875 876 /** @addtogroup Device_Peripheral_peripherals 877 * @{ 878 */ 879 880 881 882 /* =========================================================================================================================== */ 883 /* ================ FICR ================ */ 884 /* =========================================================================================================================== */ 885 886 887 /** 888 * @brief Factory information configuration registers (FICR) 889 */ 890 891 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 892 __IM uint32_t RESERVED[4]; 893 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 894 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 895 __IM uint32_t RESERVED1[18]; 896 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 897 __IM uint32_t RESERVED2[6]; 898 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 899 n */ 900 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ 901 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 902 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 903 __IM uint32_t RESERVED3[21]; 904 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 905 __IM uint32_t RESERVED4[143]; 906 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature 907 n */ 908 __IM uint32_t RESERVED5[42]; 909 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 910 coefficients */ 911 __IM uint32_t RESERVED6[2]; 912 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 913 __IM uint32_t RESERVED7[488]; 914 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 915 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 916 917 918 919 /* =========================================================================================================================== */ 920 /* ================ UICR ================ */ 921 /* =========================================================================================================================== */ 922 923 924 /** 925 * @brief User information configuration registers (UICR) 926 */ 927 928 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 929 __IM uint32_t RESERVED[5]; 930 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 931 design */ 932 __IM uint32_t RESERVED1[2]; 933 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 934 design */ 935 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 936 __IM uint32_t RESERVED2[64]; 937 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 938 function (see POWER chapter for details) */ 939 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 940 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 941 NFC antenna or GPIO */ 942 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 943 __IM uint32_t RESERVED3[60]; 944 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The 945 maximum output voltage from this stage is 946 given as VDDH - V_VDDH-VDD. */ 947 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 948 949 950 951 /* =========================================================================================================================== */ 952 /* ================ APPROTECT ================ */ 953 /* =========================================================================================================================== */ 954 955 956 /** 957 * @brief Access Port Protection (APPROTECT) 958 */ 959 960 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 961 __IM uint32_t RESERVED[340]; 962 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 963 next reset. */ 964 __IM uint32_t RESERVED1; 965 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 966 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 967 968 969 970 /* =========================================================================================================================== */ 971 /* ================ CLOCK ================ */ 972 /* =========================================================================================================================== */ 973 974 975 /** 976 * @brief Clock control (CLOCK) 977 */ 978 979 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 980 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 981 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 982 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 983 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 984 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 985 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 986 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 987 __IM uint32_t RESERVED[57]; 988 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 989 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 990 __IM uint32_t RESERVED1; 991 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 992 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 993 __IM uint32_t RESERVED2[5]; 994 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 995 to process new tasks */ 996 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 997 to process new tasks */ 998 __IM uint32_t RESERVED3[117]; 999 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1000 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1001 __IM uint32_t RESERVED4[63]; 1002 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 1003 triggered */ 1004 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 1005 __IM uint32_t RESERVED5; 1006 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 1007 triggered */ 1008 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 1009 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 1010 task was triggered */ 1011 __IM uint32_t RESERVED6[62]; 1012 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 1013 __IM uint32_t RESERVED7[3]; 1014 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 1015 the TASKS_HFCLKSTART task. */ 1016 __IM uint32_t RESERVED8[3]; 1017 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 1018 __IM uint32_t RESERVED9[8]; 1019 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 1020 __IM uint32_t RESERVED10[21]; 1021 __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ 1022 } NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ 1023 1024 1025 1026 /* =========================================================================================================================== */ 1027 /* ================ POWER ================ */ 1028 /* =========================================================================================================================== */ 1029 1030 1031 /** 1032 * @brief Power control (POWER) 1033 */ 1034 1035 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 1036 __IM uint32_t RESERVED[30]; 1037 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 1038 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 1039 __IM uint32_t RESERVED1[34]; 1040 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1041 __IM uint32_t RESERVED2[2]; 1042 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1043 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1044 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1045 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1046 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1047 __IM uint32_t RESERVED3[119]; 1048 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1049 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1050 __IM uint32_t RESERVED4[61]; 1051 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1052 __IM uint32_t RESERVED5[9]; 1053 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1054 __IM uint32_t RESERVED6[3]; 1055 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1056 __IM uint32_t RESERVED7[49]; 1057 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1058 __IM uint32_t RESERVED8[3]; 1059 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1060 __IM uint32_t RESERVED9[2]; 1061 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1062 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1063 __IM uint32_t RESERVED10[21]; 1064 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ 1065 __IM uint32_t RESERVED11; 1066 __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ 1067 __IM uint32_t RESERVED12[47]; 1068 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1069 __IM uint32_t RESERVED13[175]; 1070 __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1071 } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1072 1073 1074 1075 /* =========================================================================================================================== */ 1076 /* ================ P0 ================ */ 1077 /* =========================================================================================================================== */ 1078 1079 1080 /** 1081 * @brief GPIO Port 1 (P0) 1082 */ 1083 1084 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 1085 __IM uint32_t RESERVED[321]; 1086 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 1087 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 1088 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 1089 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 1090 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 1091 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 1092 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 1093 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 1094 have met the criteria set in the PIN_CNF[n].SENSE 1095 registers */ 1096 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 1097 and LDETECT mode */ 1098 __IM uint32_t RESERVED1[118]; 1099 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 1100 pins */ 1101 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1102 1103 1104 1105 /* =========================================================================================================================== */ 1106 /* ================ RADIO ================ */ 1107 /* =========================================================================================================================== */ 1108 1109 1110 /** 1111 * @brief 2.4 GHz radio (RADIO) 1112 */ 1113 1114 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1115 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1116 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1117 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1118 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1119 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1120 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1121 the receive signal strength */ 1122 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1123 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1124 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1125 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1126 802.15.4 mode */ 1127 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1128 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1129 802.15.4 mode */ 1130 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1131 __IM uint32_t RESERVED[51]; 1132 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1133 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1134 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1135 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1136 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1137 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1138 packet */ 1139 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1140 received packet */ 1141 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1142 __IM uint32_t RESERVED1[2]; 1143 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1144 __IM uint32_t RESERVED2; 1145 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1146 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1147 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1148 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1149 ED sample is ready for readout from the 1150 RADIO.EDSAMPLE register. */ 1151 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1152 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1153 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1154 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1155 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1156 from Ble_LR125Kbit to Ble_LR500Kbit. */ 1157 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1158 TX path */ 1159 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1160 RX path */ 1161 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1162 __IM uint32_t RESERVED3[2]; 1163 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ 1164 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and 1165 Ieee802154_250Kbit modes when last bit is 1166 sent on air. */ 1167 __IM uint32_t RESERVED4[36]; 1168 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1169 __IM uint32_t RESERVED5[64]; 1170 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1171 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1172 __IM uint32_t RESERVED6[61]; 1173 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1174 __IM uint32_t RESERVED7; 1175 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1176 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1177 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1178 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1179 __IM uint32_t RESERVED8[59]; 1180 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1181 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1182 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1183 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1184 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1185 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1186 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1187 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1188 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1189 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1190 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1191 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1192 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1193 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1194 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1195 __IM uint32_t RESERVED9; 1196 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1197 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1198 __IM uint32_t RESERVED10; 1199 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1200 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1201 __IM uint32_t RESERVED11[2]; 1202 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1203 __IM uint32_t RESERVED12[39]; 1204 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 1205 n */ 1206 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 1207 n */ 1208 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1209 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1210 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1211 __IM uint32_t RESERVED13; 1212 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1213 __IM uint32_t RESERVED14[3]; 1214 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1215 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1216 __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1217 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1218 __IM uint32_t RESERVED15[611]; 1219 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1220 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1221 1222 1223 1224 /* =========================================================================================================================== */ 1225 /* ================ UART0 ================ */ 1226 /* =========================================================================================================================== */ 1227 1228 1229 /** 1230 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1231 */ 1232 1233 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1234 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1235 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1236 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1237 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1238 __IM uint32_t RESERVED[3]; 1239 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1240 __IM uint32_t RESERVED1[56]; 1241 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1242 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1243 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1244 __IM uint32_t RESERVED2[4]; 1245 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1246 __IM uint32_t RESERVED3; 1247 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1248 __IM uint32_t RESERVED4[7]; 1249 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1250 __IM uint32_t RESERVED5[46]; 1251 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1252 __IM uint32_t RESERVED6[64]; 1253 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1254 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1255 __IM uint32_t RESERVED7[93]; 1256 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1257 __IM uint32_t RESERVED8[31]; 1258 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1259 __IM uint32_t RESERVED9; 1260 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1261 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1262 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1263 __IM uint32_t RESERVED10; 1264 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1265 selected. */ 1266 __IM uint32_t RESERVED11[17]; 1267 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1268 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1269 1270 1271 1272 /* =========================================================================================================================== */ 1273 /* ================ UARTE0 ================ */ 1274 /* =========================================================================================================================== */ 1275 1276 1277 /** 1278 * @brief UART with EasyDMA 0 (UARTE0) 1279 */ 1280 1281 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1282 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1283 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1284 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1285 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1286 __IM uint32_t RESERVED[7]; 1287 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1288 __IM uint32_t RESERVED1[52]; 1289 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1290 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1291 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1292 transferred to Data RAM) */ 1293 __IM uint32_t RESERVED2; 1294 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1295 __IM uint32_t RESERVED3[2]; 1296 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1297 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1298 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1299 __IM uint32_t RESERVED4[7]; 1300 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1301 __IM uint32_t RESERVED5; 1302 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1303 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1304 __IM uint32_t RESERVED6; 1305 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1306 __IM uint32_t RESERVED7[41]; 1307 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1308 __IM uint32_t RESERVED8[63]; 1309 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1310 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1311 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1312 __IM uint32_t RESERVED9[93]; 1313 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1314 to clear. */ 1315 __IM uint32_t RESERVED10[31]; 1316 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1317 __IM uint32_t RESERVED11; 1318 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1319 __IM uint32_t RESERVED12[3]; 1320 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1321 selected. */ 1322 __IM uint32_t RESERVED13[3]; 1323 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1324 __IM uint32_t RESERVED14; 1325 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1326 __IM uint32_t RESERVED15[7]; 1327 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1328 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1329 1330 1331 1332 /* =========================================================================================================================== */ 1333 /* ================ SPI0 ================ */ 1334 /* =========================================================================================================================== */ 1335 1336 1337 /** 1338 * @brief Serial Peripheral Interface 0 (SPI0) 1339 */ 1340 1341 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1342 __IM uint32_t RESERVED[66]; 1343 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1344 __IM uint32_t RESERVED1[126]; 1345 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1346 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1347 __IM uint32_t RESERVED2[125]; 1348 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1349 __IM uint32_t RESERVED3; 1350 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1351 __IM uint32_t RESERVED4; 1352 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1353 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1354 __IM uint32_t RESERVED5; 1355 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1356 source selected. */ 1357 __IM uint32_t RESERVED6[11]; 1358 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1359 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1360 1361 1362 1363 /* =========================================================================================================================== */ 1364 /* ================ SPIM0 ================ */ 1365 /* =========================================================================================================================== */ 1366 1367 1368 /** 1369 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1370 */ 1371 1372 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1373 __IM uint32_t RESERVED[4]; 1374 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1375 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1376 __IM uint32_t RESERVED1; 1377 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1378 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1379 __IM uint32_t RESERVED2[56]; 1380 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1381 __IM uint32_t RESERVED3[2]; 1382 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1383 __IM uint32_t RESERVED4; 1384 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1385 __IM uint32_t RESERVED5; 1386 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1387 __IM uint32_t RESERVED6[10]; 1388 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1389 __IM uint32_t RESERVED7[44]; 1390 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1391 __IM uint32_t RESERVED8[64]; 1392 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1393 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1394 __IM uint32_t RESERVED9[61]; 1395 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1396 in this register are set to STALL by hardware 1397 whenever a stall occurs and can be cleared 1398 (set to NOSTALL) by the CPU. */ 1399 __IM uint32_t RESERVED10[63]; 1400 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1401 __IM uint32_t RESERVED11; 1402 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1403 __IM uint32_t RESERVED12[3]; 1404 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1405 source selected. */ 1406 __IM uint32_t RESERVED13[3]; 1407 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1408 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1409 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1410 __IM uint32_t RESERVED14[2]; 1411 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1412 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1413 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1414 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1415 __IM uint32_t RESERVED15[19]; 1416 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1417 been transmitted in the case when RXD.MAXCNT 1418 is greater than TXD.MAXCNT */ 1419 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1420 1421 1422 1423 /* =========================================================================================================================== */ 1424 /* ================ SPIS0 ================ */ 1425 /* =========================================================================================================================== */ 1426 1427 1428 /** 1429 * @brief SPI Slave 0 (SPIS0) 1430 */ 1431 1432 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1433 __IM uint32_t RESERVED[9]; 1434 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1435 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1436 to acquire it */ 1437 __IM uint32_t RESERVED1[54]; 1438 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1439 __IM uint32_t RESERVED2[2]; 1440 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1441 __IM uint32_t RESERVED3[5]; 1442 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1443 __IM uint32_t RESERVED4[53]; 1444 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1445 __IM uint32_t RESERVED5[64]; 1446 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1447 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1448 __IM uint32_t RESERVED6[61]; 1449 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1450 __IM uint32_t RESERVED7[15]; 1451 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1452 __IM uint32_t RESERVED8[47]; 1453 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1454 __IM uint32_t RESERVED9; 1455 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1456 __IM uint32_t RESERVED10[7]; 1457 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1458 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1459 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1460 __IM uint32_t RESERVED11; 1461 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1462 of an ignored transaction. */ 1463 __IM uint32_t RESERVED12[24]; 1464 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1465 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1466 1467 1468 1469 /* =========================================================================================================================== */ 1470 /* ================ TWI0 ================ */ 1471 /* =========================================================================================================================== */ 1472 1473 1474 /** 1475 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1476 */ 1477 1478 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1479 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1480 __IM uint32_t RESERVED; 1481 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1482 __IM uint32_t RESERVED1[2]; 1483 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1484 __IM uint32_t RESERVED2; 1485 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1486 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1487 __IM uint32_t RESERVED3[56]; 1488 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1489 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1490 __IM uint32_t RESERVED4[4]; 1491 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1492 __IM uint32_t RESERVED5; 1493 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1494 __IM uint32_t RESERVED6[4]; 1495 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1496 that is sent or received */ 1497 __IM uint32_t RESERVED7[3]; 1498 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1499 __IM uint32_t RESERVED8[45]; 1500 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1501 __IM uint32_t RESERVED9[64]; 1502 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1503 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1504 __IM uint32_t RESERVED10[110]; 1505 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1506 __IM uint32_t RESERVED11[14]; 1507 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1508 __IM uint32_t RESERVED12; 1509 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1510 __IM uint32_t RESERVED13[2]; 1511 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1512 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1513 __IM uint32_t RESERVED14; 1514 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1515 source selected. */ 1516 __IM uint32_t RESERVED15[24]; 1517 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1518 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1519 1520 1521 1522 /* =========================================================================================================================== */ 1523 /* ================ TWIM0 ================ */ 1524 /* =========================================================================================================================== */ 1525 1526 1527 /** 1528 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1529 */ 1530 1531 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1532 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1533 __IM uint32_t RESERVED; 1534 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1535 __IM uint32_t RESERVED1[2]; 1536 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1537 TWI master is not suspended. */ 1538 __IM uint32_t RESERVED2; 1539 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1540 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1541 __IM uint32_t RESERVED3[56]; 1542 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1543 __IM uint32_t RESERVED4[7]; 1544 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1545 __IM uint32_t RESERVED5[8]; 1546 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1547 now suspended. */ 1548 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1549 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1550 __IM uint32_t RESERVED6[2]; 1551 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1552 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1553 byte */ 1554 __IM uint32_t RESERVED7[39]; 1555 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1556 __IM uint32_t RESERVED8[63]; 1557 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1558 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1559 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1560 __IM uint32_t RESERVED9[110]; 1561 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1562 __IM uint32_t RESERVED10[14]; 1563 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1564 __IM uint32_t RESERVED11; 1565 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1566 __IM uint32_t RESERVED12[5]; 1567 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1568 source selected. */ 1569 __IM uint32_t RESERVED13[3]; 1570 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1571 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1572 __IM uint32_t RESERVED14[13]; 1573 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1574 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1575 1576 1577 1578 /* =========================================================================================================================== */ 1579 /* ================ TWIS0 ================ */ 1580 /* =========================================================================================================================== */ 1581 1582 1583 /** 1584 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1585 */ 1586 1587 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1588 __IM uint32_t RESERVED[5]; 1589 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1590 __IM uint32_t RESERVED1; 1591 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1592 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1593 __IM uint32_t RESERVED2[3]; 1594 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1595 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1596 __IM uint32_t RESERVED3[51]; 1597 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1598 __IM uint32_t RESERVED4[7]; 1599 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1600 __IM uint32_t RESERVED5[9]; 1601 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1602 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1603 __IM uint32_t RESERVED6[4]; 1604 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1605 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1606 __IM uint32_t RESERVED7[37]; 1607 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1608 __IM uint32_t RESERVED8[63]; 1609 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1610 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1611 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1612 __IM uint32_t RESERVED9[113]; 1613 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1614 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1615 a match */ 1616 __IM uint32_t RESERVED10[10]; 1617 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1618 __IM uint32_t RESERVED11; 1619 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1620 __IM uint32_t RESERVED12[9]; 1621 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1622 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1623 __IM uint32_t RESERVED13[13]; 1624 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1625 __IM uint32_t RESERVED14; 1626 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1627 mechanism */ 1628 __IM uint32_t RESERVED15[10]; 1629 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1630 of an over-read of the transmit buffer. */ 1631 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1632 1633 1634 1635 /* =========================================================================================================================== */ 1636 /* ================ NFCT ================ */ 1637 /* =========================================================================================================================== */ 1638 1639 1640 /** 1641 * @brief NFC-A compatible radio (NFCT) 1642 */ 1643 1644 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1645 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1646 frames, change state to activated */ 1647 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1648 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1649 sense mode */ 1650 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1651 state to transmit */ 1652 __IM uint32_t RESERVED[3]; 1653 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1654 __IM uint32_t RESERVED1; 1655 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1656 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1657 __IM uint32_t RESERVED2[53]; 1658 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1659 frames */ 1660 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1661 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1662 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1663 frame */ 1664 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1665 symbol of a frame */ 1666 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1667 frame */ 1668 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1669 and transferred to RAM, and EasyDMA has 1670 ended accessing the RX buffer */ 1671 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1672 contains details on the source of the error. */ 1673 __IM uint32_t RESERVED3[2]; 1674 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1675 register contains details on the source 1676 of the error. */ 1677 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1678 in Data RAM full. */ 1679 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1680 has ended accessing the TX buffer */ 1681 __IM uint32_t RESERVED4; 1682 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1683 __IM uint32_t RESERVED5[3]; 1684 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1685 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1686 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1687 __IM uint32_t RESERVED6[43]; 1688 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1689 __IM uint32_t RESERVED7[63]; 1690 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1691 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1692 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1693 __IM uint32_t RESERVED8[62]; 1694 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1695 __IM uint32_t RESERVED9; 1696 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1697 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1698 __IM uint32_t RESERVED10[3]; 1699 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1700 __IM uint32_t RESERVED11[6]; 1701 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1702 __IM uint32_t RESERVED12[49]; 1703 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1704 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1705 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1706 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1707 Data RAM */ 1708 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1709 data storage each */ 1710 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1711 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1712 __IM uint32_t RESERVED13[26]; 1713 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1714 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1715 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1716 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1717 This setting must be done before the NFCT 1718 peripheral is activated. */ 1719 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1720 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1721 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1722 1723 1724 1725 /* =========================================================================================================================== */ 1726 /* ================ GPIOTE ================ */ 1727 /* =========================================================================================================================== */ 1728 1729 1730 /** 1731 * @brief GPIO Tasks and Events (GPIOTE) 1732 */ 1733 1734 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1735 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1736 specified in CONFIG[n].PSEL. Action on pin 1737 is configured in CONFIG[n].POLARITY. */ 1738 __IM uint32_t RESERVED[4]; 1739 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1740 specified in CONFIG[n].PSEL. Action on pin 1741 is to set it high. */ 1742 __IM uint32_t RESERVED1[4]; 1743 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1744 specified in CONFIG[n].PSEL. Action on pin 1745 is to set it low. */ 1746 __IM uint32_t RESERVED2[32]; 1747 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1748 pin specified in CONFIG[n].PSEL */ 1749 __IM uint32_t RESERVED3[23]; 1750 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1751 with SENSE mechanism enabled */ 1752 __IM uint32_t RESERVED4[97]; 1753 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1754 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1755 __IM uint32_t RESERVED5[129]; 1756 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1757 SET[n], and CLR[n] tasks and IN[n] event */ 1758 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1759 1760 1761 1762 /* =========================================================================================================================== */ 1763 /* ================ SAADC ================ */ 1764 /* =========================================================================================================================== */ 1765 1766 1767 /** 1768 * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1769 */ 1770 1771 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1772 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1773 in RAM */ 1774 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1775 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1776 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1777 __IM uint32_t RESERVED[60]; 1778 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1779 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1780 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1781 on the configuration, multiple conversions 1782 might be needed for a result to be transferred 1783 to RAM. */ 1784 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1785 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1786 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1787 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1788 __IM uint32_t RESERVED1[106]; 1789 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1790 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1791 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1792 __IM uint32_t RESERVED2[61]; 1793 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1794 __IM uint32_t RESERVED3[63]; 1795 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1796 __IM uint32_t RESERVED4[3]; 1797 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1798 __IM uint32_t RESERVED5[24]; 1799 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1800 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1801 applied before averaging, thus for high 1802 OVERSAMPLE a higher RESOLUTION should be 1803 used. */ 1804 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1805 __IM uint32_t RESERVED6[12]; 1806 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1807 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1808 1809 1810 1811 /* =========================================================================================================================== */ 1812 /* ================ TIMER0 ================ */ 1813 /* =========================================================================================================================== */ 1814 1815 1816 /** 1817 * @brief Timer/Counter 0 (TIMER0) 1818 */ 1819 1820 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1821 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1822 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1823 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1824 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1825 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1826 __IM uint32_t RESERVED[11]; 1827 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1828 CC[n] register */ 1829 __IM uint32_t RESERVED1[58]; 1830 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1831 match */ 1832 __IM uint32_t RESERVED2[42]; 1833 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1834 __IM uint32_t RESERVED3[64]; 1835 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1836 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1837 __IM uint32_t RESERVED4[126]; 1838 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1839 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1840 __IM uint32_t RESERVED5; 1841 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1842 __IM uint32_t RESERVED6[11]; 1843 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1844 n */ 1845 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1846 1847 1848 1849 /* =========================================================================================================================== */ 1850 /* ================ RTC0 ================ */ 1851 /* =========================================================================================================================== */ 1852 1853 1854 /** 1855 * @brief Real time counter 0 (RTC0) 1856 */ 1857 1858 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1859 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1860 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1861 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1862 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1863 __IM uint32_t RESERVED[60]; 1864 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1865 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1866 __IM uint32_t RESERVED1[14]; 1867 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1868 match */ 1869 __IM uint32_t RESERVED2[109]; 1870 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1871 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1872 __IM uint32_t RESERVED3[13]; 1873 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1874 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1875 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1876 __IM uint32_t RESERVED4[110]; 1877 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1878 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 1879 Must be written when RTC is stopped. */ 1880 __IM uint32_t RESERVED5[13]; 1881 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1882 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1883 1884 1885 1886 /* =========================================================================================================================== */ 1887 /* ================ TEMP ================ */ 1888 /* =========================================================================================================================== */ 1889 1890 1891 /** 1892 * @brief Temperature Sensor (TEMP) 1893 */ 1894 1895 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1896 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1897 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1898 __IM uint32_t RESERVED[62]; 1899 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1900 __IM uint32_t RESERVED1[128]; 1901 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1902 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1903 __IM uint32_t RESERVED2[127]; 1904 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1905 __IM uint32_t RESERVED3[5]; 1906 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1907 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1908 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1909 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1910 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1911 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1912 __IM uint32_t RESERVED4[2]; 1913 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1914 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1915 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1916 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1917 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1918 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1919 __IM uint32_t RESERVED5[2]; 1920 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1921 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1922 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1923 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1924 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1925 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1926 1927 1928 1929 /* =========================================================================================================================== */ 1930 /* ================ RNG ================ */ 1931 /* =========================================================================================================================== */ 1932 1933 1934 /** 1935 * @brief Random Number Generator (RNG) 1936 */ 1937 1938 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1939 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1940 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1941 __IM uint32_t RESERVED[62]; 1942 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1943 written to the VALUE register */ 1944 __IM uint32_t RESERVED1[63]; 1945 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1946 __IM uint32_t RESERVED2[64]; 1947 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1948 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1949 __IM uint32_t RESERVED3[126]; 1950 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1951 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1952 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1953 1954 1955 1956 /* =========================================================================================================================== */ 1957 /* ================ ECB ================ */ 1958 /* =========================================================================================================================== */ 1959 1960 1961 /** 1962 * @brief AES ECB Mode Encryption (ECB) 1963 */ 1964 1965 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1966 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1967 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1968 __IM uint32_t RESERVED[62]; 1969 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1970 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1971 task or due to an error */ 1972 __IM uint32_t RESERVED1[127]; 1973 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1974 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1975 __IM uint32_t RESERVED2[126]; 1976 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1977 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1978 1979 1980 1981 /* =========================================================================================================================== */ 1982 /* ================ AAR ================ */ 1983 /* =========================================================================================================================== */ 1984 1985 1986 /** 1987 * @brief Accelerated Address Resolver (AAR) 1988 */ 1989 1990 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1991 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1992 in the IRK data structure */ 1993 __IM uint32_t RESERVED; 1994 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1995 __IM uint32_t RESERVED1[61]; 1996 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1997 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1998 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1999 __IM uint32_t RESERVED2[126]; 2000 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2001 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2002 __IM uint32_t RESERVED3[61]; 2003 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 2004 __IM uint32_t RESERVED4[63]; 2005 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 2006 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 2007 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 2008 __IM uint32_t RESERVED5; 2009 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 2010 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2011 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 2012 2013 2014 2015 /* =========================================================================================================================== */ 2016 /* ================ CCM ================ */ 2017 /* =========================================================================================================================== */ 2018 2019 2020 /** 2021 * @brief AES CCM mode encryption (CCM) 2022 */ 2023 2024 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 2025 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 2026 will stop by itself when completed. */ 2027 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 2028 stop by itself when completed. */ 2029 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 2030 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 2031 the contents of the RATEOVERRIDE register 2032 for any ongoing encryption/decryption */ 2033 __IM uint32_t RESERVED[60]; 2034 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 2035 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 2036 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 2037 __IM uint32_t RESERVED1[61]; 2038 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2039 __IM uint32_t RESERVED2[64]; 2040 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2041 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2042 __IM uint32_t RESERVED3[61]; 2043 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2044 __IM uint32_t RESERVED4[63]; 2045 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2046 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2047 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 2048 and the NONCE vector */ 2049 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2050 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2051 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2052 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 2053 = Extended */ 2054 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2055 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 2056 2057 2058 2059 /* =========================================================================================================================== */ 2060 /* ================ WDT ================ */ 2061 /* =========================================================================================================================== */ 2062 2063 2064 /** 2065 * @brief Watchdog Timer (WDT) 2066 */ 2067 2068 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2069 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2070 __IM uint32_t RESERVED[63]; 2071 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2072 __IM uint32_t RESERVED1[128]; 2073 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2074 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2075 __IM uint32_t RESERVED2[61]; 2076 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2077 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2078 __IM uint32_t RESERVED3[63]; 2079 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2080 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2081 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2082 __IM uint32_t RESERVED4[60]; 2083 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2084 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2085 2086 2087 2088 /* =========================================================================================================================== */ 2089 /* ================ QDEC ================ */ 2090 /* =========================================================================================================================== */ 2091 2092 2093 /** 2094 * @brief Quadrature Decoder (QDEC) 2095 */ 2096 2097 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2098 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2099 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2100 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2101 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2102 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2103 __IM uint32_t RESERVED[59]; 2104 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2105 written to the SAMPLE register */ 2106 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2107 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2108 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2109 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2110 __IM uint32_t RESERVED1[59]; 2111 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2112 __IM uint32_t RESERVED2[64]; 2113 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2114 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2115 __IM uint32_t RESERVED3[125]; 2116 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2117 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2118 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2119 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2120 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2121 and DBLRDY events can be generated */ 2122 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2123 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2124 READCLRACC or RDCLRACC task */ 2125 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2126 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2127 __IM uint32_t RESERVED4[5]; 2128 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2129 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2130 double transitions */ 2131 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2132 or RDCLRDBL task */ 2133 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2134 2135 2136 2137 /* =========================================================================================================================== */ 2138 /* ================ COMP ================ */ 2139 /* =========================================================================================================================== */ 2140 2141 2142 /** 2143 * @brief Comparator (COMP) 2144 */ 2145 2146 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2147 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2148 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2149 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2150 __IM uint32_t RESERVED[61]; 2151 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2152 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2153 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2154 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2155 __IM uint32_t RESERVED1[60]; 2156 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2157 __IM uint32_t RESERVED2[63]; 2158 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2159 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2160 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2161 __IM uint32_t RESERVED3[61]; 2162 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2163 __IM uint32_t RESERVED4[63]; 2164 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2165 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2166 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2167 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2168 __IM uint32_t RESERVED5[8]; 2169 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2170 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2171 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2172 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2173 2174 2175 2176 /* =========================================================================================================================== */ 2177 /* ================ LPCOMP ================ */ 2178 /* =========================================================================================================================== */ 2179 2180 2181 /** 2182 * @brief Low-power comparator (LPCOMP) 2183 */ 2184 2185 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2186 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2187 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2188 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2189 __IM uint32_t RESERVED[61]; 2190 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2191 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2192 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2193 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2194 __IM uint32_t RESERVED1[60]; 2195 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2196 __IM uint32_t RESERVED2[64]; 2197 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2198 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2199 __IM uint32_t RESERVED3[61]; 2200 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2201 __IM uint32_t RESERVED4[63]; 2202 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2203 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2204 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2205 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2206 __IM uint32_t RESERVED5[4]; 2207 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2208 __IM uint32_t RESERVED6[5]; 2209 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2210 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2211 2212 2213 2214 /* =========================================================================================================================== */ 2215 /* ================ EGU0 ================ */ 2216 /* =========================================================================================================================== */ 2217 2218 2219 /** 2220 * @brief Event generator unit 0 (EGU0) 2221 */ 2222 2223 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2224 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2225 the corresponding TRIGGERED[n] event */ 2226 __IM uint32_t RESERVED[48]; 2227 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2228 by triggering the corresponding TRIGGER[n] 2229 task */ 2230 __IM uint32_t RESERVED1[112]; 2231 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2232 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2233 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2234 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2235 2236 2237 2238 /* =========================================================================================================================== */ 2239 /* ================ SWI0 ================ */ 2240 /* =========================================================================================================================== */ 2241 2242 2243 /** 2244 * @brief Software interrupt 0 (SWI0) 2245 */ 2246 2247 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2248 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2249 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2250 2251 2252 2253 /* =========================================================================================================================== */ 2254 /* ================ PWM0 ================ */ 2255 /* =========================================================================================================================== */ 2256 2257 2258 /** 2259 * @brief Pulse width modulation unit 0 (PWM0) 2260 */ 2261 2262 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2263 __IM uint32_t RESERVED; 2264 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2265 the end of current PWM period, and stops 2266 sequence playback */ 2267 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2268 on all enabled channels from sequence n, 2269 and starts playing that sequence at the 2270 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2271 Causes PWM generation to start if not running. */ 2272 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2273 all enabled channels if DECODER.MODE=NextStep. 2274 Does not cause PWM generation to start if 2275 not running. */ 2276 __IM uint32_t RESERVED1[60]; 2277 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2278 are no longer generated */ 2279 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2280 on sequence n */ 2281 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2282 sequence n, when last value from RAM has 2283 been applied to wave counter */ 2284 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2285 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2286 of times defined in LOOP.CNT */ 2287 __IM uint32_t RESERVED2[56]; 2288 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2289 __IM uint32_t RESERVED3[63]; 2290 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2291 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2292 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2293 __IM uint32_t RESERVED4[125]; 2294 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2295 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2296 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2297 counts */ 2298 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2299 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2300 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2301 __IM uint32_t RESERVED5[2]; 2302 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2303 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2304 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2305 2306 2307 2308 /* =========================================================================================================================== */ 2309 /* ================ PDM ================ */ 2310 /* =========================================================================================================================== */ 2311 2312 2313 /** 2314 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2315 */ 2316 2317 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2318 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2319 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2320 __IM uint32_t RESERVED[62]; 2321 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2322 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2323 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2324 by SAMPLE.MAXCNT (or the last sample after 2325 a STOP task has been received) to Data RAM */ 2326 __IM uint32_t RESERVED1[125]; 2327 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2328 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2329 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2330 __IM uint32_t RESERVED2[125]; 2331 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2332 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2333 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2334 signals */ 2335 __IM uint32_t RESERVED3[3]; 2336 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2337 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2338 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2339 sample rate. Change PDMCLKCTRL accordingly. */ 2340 __IM uint32_t RESERVED4[7]; 2341 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2342 __IM uint32_t RESERVED5[6]; 2343 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2344 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2345 2346 2347 2348 /* =========================================================================================================================== */ 2349 /* ================ ACL ================ */ 2350 /* =========================================================================================================================== */ 2351 2352 2353 /** 2354 * @brief Access control lists (ACL) 2355 */ 2356 2357 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2358 __IM uint32_t RESERVED[512]; 2359 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2360 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2361 2362 2363 2364 /* =========================================================================================================================== */ 2365 /* ================ NVMC ================ */ 2366 /* =========================================================================================================================== */ 2367 2368 2369 /** 2370 * @brief Non Volatile Memory Controller (NVMC) 2371 */ 2372 2373 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2374 __IM uint32_t RESERVED[256]; 2375 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2376 __IM uint32_t RESERVED1; 2377 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2378 __IM uint32_t RESERVED2[62]; 2379 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2380 2381 union { 2382 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2383 __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2384 page in code area, equivalent to ERASEPAGE */ 2385 }; 2386 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2387 __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2388 page in code area, equivalent to ERASEPAGE */ 2389 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2390 registers */ 2391 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2392 area */ 2393 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2394 __IM uint32_t RESERVED3[8]; 2395 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 2396 __IM uint32_t RESERVED4; 2397 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 2398 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2399 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2400 2401 2402 2403 /* =========================================================================================================================== */ 2404 /* ================ PPI ================ */ 2405 /* =========================================================================================================================== */ 2406 2407 2408 /** 2409 * @brief Programmable Peripheral Interconnect (PPI) 2410 */ 2411 2412 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2413 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2414 __IM uint32_t RESERVED[308]; 2415 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2416 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2417 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2418 __IM uint32_t RESERVED1; 2419 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2420 __IM uint32_t RESERVED2[148]; 2421 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 2422 __IM uint32_t RESERVED3[62]; 2423 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2424 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2425 2426 2427 2428 /* =========================================================================================================================== */ 2429 /* ================ MWU ================ */ 2430 /* =========================================================================================================================== */ 2431 2432 2433 /** 2434 * @brief Memory Watch Unit (MWU) 2435 */ 2436 2437 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2438 __IM uint32_t RESERVED[64]; 2439 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ 2440 __IM uint32_t RESERVED1[16]; 2441 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ 2442 __IM uint32_t RESERVED2[100]; 2443 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2444 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2445 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2446 __IM uint32_t RESERVED3[5]; 2447 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ 2448 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2449 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2450 __IM uint32_t RESERVED4[53]; 2451 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2452 __IM uint32_t RESERVED5[64]; 2453 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2454 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2455 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2456 __IM uint32_t RESERVED6[57]; 2457 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2458 __IM uint32_t RESERVED7[32]; 2459 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2460 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2461 2462 2463 2464 /* =========================================================================================================================== */ 2465 /* ================ I2S ================ */ 2466 /* =========================================================================================================================== */ 2467 2468 2469 /** 2470 * @brief Inter-IC Sound (I2S) 2471 */ 2472 2473 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2474 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2475 generator when this is enabled. */ 2476 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2477 Triggering this task will cause the STOPPED 2478 event to be generated. */ 2479 __IM uint32_t RESERVED[63]; 2480 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2481 double-buffers. When the I2S module is started 2482 and RX is enabled, this event will be generated 2483 for every RXTXD.MAXCNT words that are received 2484 on the SDIN pin. */ 2485 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2486 __IM uint32_t RESERVED1[2]; 2487 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2488 double-buffers. When the I2S module is started 2489 and TX is enabled, this event will be generated 2490 for every RXTXD.MAXCNT words that are sent 2491 on the SDOUT pin. */ 2492 __IM uint32_t RESERVED2[122]; 2493 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2494 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2495 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2496 __IM uint32_t RESERVED3[125]; 2497 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2498 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2499 __IM uint32_t RESERVED4[3]; 2500 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2501 __IM uint32_t RESERVED5; 2502 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2503 __IM uint32_t RESERVED6[3]; 2504 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2505 __IM uint32_t RESERVED7[3]; 2506 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2507 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2508 2509 2510 2511 /* =========================================================================================================================== */ 2512 /* ================ FPU ================ */ 2513 /* =========================================================================================================================== */ 2514 2515 2516 /** 2517 * @brief FPU (FPU) 2518 */ 2519 2520 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2521 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2522 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2523 2524 2525 2526 /* =========================================================================================================================== */ 2527 /* ================ USBD ================ */ 2528 /* =========================================================================================================================== */ 2529 2530 2531 /** 2532 * @brief Universal serial bus device (USBD) 2533 */ 2534 2535 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2536 __IM uint32_t RESERVED; 2537 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 2538 and EPIN[n].MAXCNT registers values, and 2539 enables endpoint IN n to respond to traffic 2540 from host */ 2541 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2542 values, and enables sending data on ISO 2543 endpoint */ 2544 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 2545 and EPOUT[n].MAXCNT registers values, and 2546 enables endpoint n to respond to traffic 2547 from host */ 2548 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2549 values, and enables receiving of data on 2550 ISO endpoint */ 2551 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2552 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2553 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2554 0 */ 2555 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2556 in the DPDMVALUE register */ 2557 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2558 (USB engine takes control) */ 2559 __IM uint32_t RESERVED1[40]; 2560 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2561 on USB lines */ 2562 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2563 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2564 have been captured on all endpoints reported 2565 in the EPSTATUS register */ 2566 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 2567 has been consumed. The buffer can be accessed 2568 safely by software. */ 2569 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2570 on the control endpoint */ 2571 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2572 buffer can be accessed safely by software. */ 2573 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 2574 has been consumed. The buffer can be accessed 2575 safely by software. */ 2576 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2577 buffer can be accessed safely by software. */ 2578 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2579 has been detected on USB lines */ 2580 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2581 events has occurred. Check EVENTCAUSE register 2582 to find the cause. */ 2583 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2584 on the control endpoint */ 2585 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2586 indicated by the EPDATASTATUS register */ 2587 __IM uint32_t RESERVED2[39]; 2588 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2589 __IM uint32_t RESERVED3[63]; 2590 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2591 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2592 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2593 __IM uint32_t RESERVED4[61]; 2594 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2595 __IM uint32_t RESERVED5[7]; 2596 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2597 __IM uint32_t RESERVED6; 2598 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2599 registers have been captured */ 2600 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2601 acknowledged data transfer has occurred 2602 (EPDATA event) */ 2603 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2604 __IM uint32_t RESERVED7[3]; 2605 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2606 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2607 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2608 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2609 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2610 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2611 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2612 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2613 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2614 __IM uint32_t RESERVED8[15]; 2615 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2616 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2617 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2618 the DPDMDRIVE task. The DPDMNODRIVE task 2619 reverts the control of the lines to MAC 2620 IP (no forcing). */ 2621 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2622 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2623 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2624 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2625 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2626 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2627 counter */ 2628 __IM uint32_t RESERVED9[2]; 2629 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2630 USB suspend */ 2631 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2632 to an IN token when no data is ready to 2633 be sent */ 2634 __IM uint32_t RESERVED10[51]; 2635 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2636 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2637 __IM uint32_t RESERVED11[21]; 2638 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2639 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2640 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2641 2642 2643 2644 /* =========================================================================================================================== */ 2645 /* ================ QSPI ================ */ 2646 /* =========================================================================================================================== */ 2647 2648 2649 /** 2650 * @brief External flash interface (QSPI) 2651 */ 2652 2653 typedef struct { /*!< (@ 0x40029000) QSPI Structure */ 2654 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2655 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2656 internal RAM */ 2657 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2658 flash memory */ 2659 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2660 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2661 __IM uint32_t RESERVED[59]; 2662 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2663 generated as a response to any QSPI task. */ 2664 __IM uint32_t RESERVED1[127]; 2665 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2666 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2667 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2668 __IM uint32_t RESERVED2[125]; 2669 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2670 in PSELn registers */ 2671 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2672 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2673 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2674 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2675 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2676 in Place operation. */ 2677 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2678 __IM uint32_t RESERVED3[46]; 2679 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2680 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2681 __IM uint32_t RESERVED4[3]; 2682 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2683 power-down mode (DPM). */ 2684 __IM uint32_t RESERVED5[3]; 2685 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2686 __IM uint32_t RESERVED6[3]; 2687 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2688 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2689 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2690 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2691 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2692 2693 2694 2695 /* =========================================================================================================================== */ 2696 /* ================ CC_HOST_RGF ================ */ 2697 /* =========================================================================================================================== */ 2698 2699 2700 /** 2701 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) 2702 */ 2703 2704 typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ 2705 __IM uint32_t RESERVED[1678]; 2706 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 2707 __IM uint32_t RESERVED1[4]; 2708 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 2709 When this register is set, K_PRTL cannot 2710 be used and a zeroed key will be used instead. 2711 The value of this register is saved in the 2712 CRYPTOCELL AO power domain. */ 2713 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 2714 of this register is saved in the CRYPTOCELL 2715 AO power domain. Reading from this address 2716 returns the K_DR valid status indicating 2717 if K_DR is successfully retained. */ 2718 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 2719 of this register is saved in the CRYPTOCELL 2720 AO power domain. */ 2721 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 2722 of this register is saved in the CRYPTOCELL 2723 AO power domain. */ 2724 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 2725 value of this register is saved in the CRYPTOCELL 2726 AO power domain. */ 2727 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 2728 subsystem */ 2729 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 2730 2731 2732 2733 /* =========================================================================================================================== */ 2734 /* ================ CRYPTOCELL ================ */ 2735 /* =========================================================================================================================== */ 2736 2737 2738 /** 2739 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) 2740 */ 2741 2742 typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ 2743 __IM uint32_t RESERVED[320]; 2744 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2745 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2746 2747 2748 /** @} */ /* End of group Device_Peripheral_peripherals */ 2749 2750 2751 /* =========================================================================================================================== */ 2752 /* ================ Device Specific Peripheral Address Map ================ */ 2753 /* =========================================================================================================================== */ 2754 2755 2756 /** @addtogroup Device_Peripheral_peripheralAddr 2757 * @{ 2758 */ 2759 2760 #define NRF_FICR_BASE 0x10000000UL 2761 #define NRF_UICR_BASE 0x10001000UL 2762 #define NRF_APPROTECT_BASE 0x40000000UL 2763 #define NRF_CLOCK_BASE 0x40000000UL 2764 #define NRF_POWER_BASE 0x40000000UL 2765 #define NRF_P0_BASE 0x50000000UL 2766 #define NRF_P1_BASE 0x50000300UL 2767 #define NRF_RADIO_BASE 0x40001000UL 2768 #define NRF_UART0_BASE 0x40002000UL 2769 #define NRF_UARTE0_BASE 0x40002000UL 2770 #define NRF_SPI0_BASE 0x40003000UL 2771 #define NRF_SPIM0_BASE 0x40003000UL 2772 #define NRF_SPIS0_BASE 0x40003000UL 2773 #define NRF_TWI0_BASE 0x40003000UL 2774 #define NRF_TWIM0_BASE 0x40003000UL 2775 #define NRF_TWIS0_BASE 0x40003000UL 2776 #define NRF_SPI1_BASE 0x40004000UL 2777 #define NRF_SPIM1_BASE 0x40004000UL 2778 #define NRF_SPIS1_BASE 0x40004000UL 2779 #define NRF_TWI1_BASE 0x40004000UL 2780 #define NRF_TWIM1_BASE 0x40004000UL 2781 #define NRF_TWIS1_BASE 0x40004000UL 2782 #define NRF_NFCT_BASE 0x40005000UL 2783 #define NRF_GPIOTE_BASE 0x40006000UL 2784 #define NRF_SAADC_BASE 0x40007000UL 2785 #define NRF_TIMER0_BASE 0x40008000UL 2786 #define NRF_TIMER1_BASE 0x40009000UL 2787 #define NRF_TIMER2_BASE 0x4000A000UL 2788 #define NRF_RTC0_BASE 0x4000B000UL 2789 #define NRF_TEMP_BASE 0x4000C000UL 2790 #define NRF_RNG_BASE 0x4000D000UL 2791 #define NRF_ECB_BASE 0x4000E000UL 2792 #define NRF_AAR_BASE 0x4000F000UL 2793 #define NRF_CCM_BASE 0x4000F000UL 2794 #define NRF_WDT_BASE 0x40010000UL 2795 #define NRF_RTC1_BASE 0x40011000UL 2796 #define NRF_QDEC_BASE 0x40012000UL 2797 #define NRF_COMP_BASE 0x40013000UL 2798 #define NRF_LPCOMP_BASE 0x40013000UL 2799 #define NRF_EGU0_BASE 0x40014000UL 2800 #define NRF_SWI0_BASE 0x40014000UL 2801 #define NRF_EGU1_BASE 0x40015000UL 2802 #define NRF_SWI1_BASE 0x40015000UL 2803 #define NRF_EGU2_BASE 0x40016000UL 2804 #define NRF_SWI2_BASE 0x40016000UL 2805 #define NRF_EGU3_BASE 0x40017000UL 2806 #define NRF_SWI3_BASE 0x40017000UL 2807 #define NRF_EGU4_BASE 0x40018000UL 2808 #define NRF_SWI4_BASE 0x40018000UL 2809 #define NRF_EGU5_BASE 0x40019000UL 2810 #define NRF_SWI5_BASE 0x40019000UL 2811 #define NRF_TIMER3_BASE 0x4001A000UL 2812 #define NRF_TIMER4_BASE 0x4001B000UL 2813 #define NRF_PWM0_BASE 0x4001C000UL 2814 #define NRF_PDM_BASE 0x4001D000UL 2815 #define NRF_ACL_BASE 0x4001E000UL 2816 #define NRF_NVMC_BASE 0x4001E000UL 2817 #define NRF_PPI_BASE 0x4001F000UL 2818 #define NRF_MWU_BASE 0x40020000UL 2819 #define NRF_PWM1_BASE 0x40021000UL 2820 #define NRF_PWM2_BASE 0x40022000UL 2821 #define NRF_SPI2_BASE 0x40023000UL 2822 #define NRF_SPIM2_BASE 0x40023000UL 2823 #define NRF_SPIS2_BASE 0x40023000UL 2824 #define NRF_RTC2_BASE 0x40024000UL 2825 #define NRF_I2S_BASE 0x40025000UL 2826 #define NRF_FPU_BASE 0x40026000UL 2827 #define NRF_USBD_BASE 0x40027000UL 2828 #define NRF_UARTE1_BASE 0x40028000UL 2829 #define NRF_QSPI_BASE 0x40029000UL 2830 #define NRF_CC_HOST_RGF_BASE 0x5002A000UL 2831 #define NRF_CRYPTOCELL_BASE 0x5002A000UL 2832 #define NRF_PWM3_BASE 0x4002D000UL 2833 #define NRF_SPIM3_BASE 0x4002F000UL 2834 2835 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2836 2837 2838 /* =========================================================================================================================== */ 2839 /* ================ Peripheral declaration ================ */ 2840 /* =========================================================================================================================== */ 2841 2842 2843 /** @addtogroup Device_Peripheral_declaration 2844 * @{ 2845 */ 2846 2847 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2848 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2849 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 2850 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2851 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2852 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2853 #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 2854 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2855 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2856 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2857 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2858 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2859 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2860 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2861 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2862 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2863 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2864 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2865 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2866 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2867 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2868 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2869 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2870 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2871 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2872 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2873 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2874 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2875 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2876 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2877 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2878 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2879 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2880 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2881 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2882 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2883 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2884 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2885 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2886 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2887 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2888 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2889 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2890 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2891 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2892 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2893 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2894 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2895 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2896 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2897 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2898 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2899 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2900 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2901 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2902 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2903 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2904 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2905 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2906 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2907 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2908 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2909 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2910 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2911 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2912 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2913 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2914 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2915 #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 2916 #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) 2917 #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) 2918 #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) 2919 #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 2920 #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 2921 2922 /** @} */ /* End of group Device_Peripheral_declaration */ 2923 2924 2925 /* ========================================= End of section using anonymous unions ========================================= */ 2926 #if defined (__CC_ARM) 2927 #pragma pop 2928 #elif defined (__ICCARM__) 2929 /* leave anonymous unions enabled */ 2930 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2931 #pragma clang diagnostic pop 2932 #elif defined (__GNUC__) 2933 /* anonymous unions are enabled by default */ 2934 #elif defined (__TMS470__) 2935 /* anonymous unions are enabled by default */ 2936 #elif defined (__TASKING__) 2937 #pragma warning restore 2938 #elif defined (__CSMC__) 2939 /* anonymous unions are enabled by default */ 2940 #endif 2941 2942 2943 #ifdef __cplusplus 2944 } 2945 #endif 2946 2947 #endif /* NRF52840_H */ 2948 2949 2950 /** @} */ /* End of group nrf52840 */ 2951 2952 /** @} */ /* End of group Nordic Semiconductor */ 2953
