1 /*
2 
3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52833_BITS_H
36 #define __NRF52833_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: ACL */
180 /* Description: Access control lists */
181 
182 /* Register: ACL_ACL_ADDR */
183 /* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */
184 
185 /* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */
186 #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
187 #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
188 
189 /* Register: ACL_ACL_SIZE */
190 /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
191 
192 /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
193 #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
194 #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
195 
196 /* Register: ACL_ACL_PERM */
197 /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
198 
199 /* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
200 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
201 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
202 #define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
203 #define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
204 
205 /* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
206 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
207 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
208 #define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
209 #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
210 
211 
212 /* Peripheral: APPROTECT */
213 /* Description: Access Port Protection */
214 
215 /* Register: APPROTECT_FORCEPROTECT */
216 /* Description: Software force enable APPROTECT mechanism until next reset. */
217 
218 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
219 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
220 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
221 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */
222 
223 /* Register: APPROTECT_DISABLE */
224 /* Description: Software disable APPROTECT mechanism */
225 
226 /* Bits 7..0 : Software disable APPROTECT mechanism */
227 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
228 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
229 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
230 
231 
232 /* Peripheral: CCM */
233 /* Description: AES CCM mode encryption */
234 
235 /* Register: CCM_TASKS_KSGEN */
236 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
237 
238 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
239 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
240 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
241 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
242 
243 /* Register: CCM_TASKS_CRYPT */
244 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
245 
246 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
247 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
248 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
249 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
250 
251 /* Register: CCM_TASKS_STOP */
252 /* Description: Stop encryption/decryption */
253 
254 /* Bit 0 : Stop encryption/decryption */
255 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
256 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
257 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
258 
259 /* Register: CCM_TASKS_RATEOVERRIDE */
260 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
261 
262 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
263 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
264 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
265 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
266 
267 /* Register: CCM_EVENTS_ENDKSGEN */
268 /* Description: Keystream generation complete */
269 
270 /* Bit 0 : Keystream generation complete */
271 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
272 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
273 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
274 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
275 
276 /* Register: CCM_EVENTS_ENDCRYPT */
277 /* Description: Encrypt/decrypt complete */
278 
279 /* Bit 0 : Encrypt/decrypt complete */
280 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
281 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
282 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
283 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
284 
285 /* Register: CCM_EVENTS_ERROR */
286 /* Description: Deprecated register - CCM error event */
287 
288 /* Bit 0 : Deprecated field -  CCM error event */
289 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
290 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
291 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
292 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
293 
294 /* Register: CCM_SHORTS */
295 /* Description: Shortcuts between local events and tasks */
296 
297 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
298 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
299 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
300 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
301 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
302 
303 /* Register: CCM_INTENSET */
304 /* Description: Enable interrupt */
305 
306 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
307 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
308 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
309 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
310 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
311 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
312 
313 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
314 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
315 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
316 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
317 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
318 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
319 
320 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
321 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
322 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
323 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
324 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
325 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
326 
327 /* Register: CCM_INTENCLR */
328 /* Description: Disable interrupt */
329 
330 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
331 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
332 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
333 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
334 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
335 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
336 
337 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
338 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
339 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
340 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
341 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
342 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
343 
344 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
345 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
346 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
347 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
348 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
349 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
350 
351 /* Register: CCM_MICSTATUS */
352 /* Description: MIC check result */
353 
354 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
355 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
356 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
357 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
358 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
359 
360 /* Register: CCM_ENABLE */
361 /* Description: Enable */
362 
363 /* Bits 1..0 : Enable or disable CCM */
364 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
365 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
366 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
367 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
368 
369 /* Register: CCM_MODE */
370 /* Description: Operation mode */
371 
372 /* Bit 24 : Packet length configuration */
373 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
374 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
375 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
376 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
377 
378 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
379 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
380 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
381 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
382 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
383 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
384 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
385 
386 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
387 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
388 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
389 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
390 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
391 
392 /* Register: CCM_CNFPTR */
393 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
394 
395 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
396 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
397 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
398 
399 /* Register: CCM_INPTR */
400 /* Description: Input pointer */
401 
402 /* Bits 31..0 : Input pointer */
403 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
404 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
405 
406 /* Register: CCM_OUTPTR */
407 /* Description: Output pointer */
408 
409 /* Bits 31..0 : Output pointer */
410 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
411 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
412 
413 /* Register: CCM_SCRATCHPTR */
414 /* Description: Pointer to data area used for temporary storage */
415 
416 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
417         MIC generation and encryption/decryption. */
418 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
419 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
420 
421 /* Register: CCM_MAXPACKETSIZE */
422 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
423 
424 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
425 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
426 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
427 
428 /* Register: CCM_RATEOVERRIDE */
429 /* Description: Data rate override setting. */
430 
431 /* Bits 1..0 : Data rate override setting */
432 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
433 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
434 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
435 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
436 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
437 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
438 
439 /* Register: CCM_HEADERMASK */
440 /* Description: Header (S0) mask. */
441 
442 /* Bits 7..0 : Header (S0) mask */
443 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
444 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
445 
446 
447 /* Peripheral: CLOCK */
448 /* Description: Clock control */
449 
450 /* Register: CLOCK_TASKS_HFCLKSTART */
451 /* Description: Start HFXO crystal oscillator */
452 
453 /* Bit 0 : Start HFXO crystal oscillator */
454 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
455 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
456 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
457 
458 /* Register: CLOCK_TASKS_HFCLKSTOP */
459 /* Description: Stop HFXO crystal oscillator */
460 
461 /* Bit 0 : Stop HFXO crystal oscillator */
462 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
463 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
464 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
465 
466 /* Register: CLOCK_TASKS_LFCLKSTART */
467 /* Description: Start LFCLK */
468 
469 /* Bit 0 : Start LFCLK */
470 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
471 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
472 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
473 
474 /* Register: CLOCK_TASKS_LFCLKSTOP */
475 /* Description: Stop LFCLK */
476 
477 /* Bit 0 : Stop LFCLK */
478 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
479 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
480 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
481 
482 /* Register: CLOCK_TASKS_CAL */
483 /* Description: Start calibration of LFRC */
484 
485 /* Bit 0 : Start calibration of LFRC */
486 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
487 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
488 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
489 
490 /* Register: CLOCK_TASKS_CTSTART */
491 /* Description: Start calibration timer */
492 
493 /* Bit 0 : Start calibration timer */
494 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
495 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
496 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
497 
498 /* Register: CLOCK_TASKS_CTSTOP */
499 /* Description: Stop calibration timer */
500 
501 /* Bit 0 : Stop calibration timer */
502 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
503 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
504 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
505 
506 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
507 /* Description: HFXO crystal oscillator started */
508 
509 /* Bit 0 : HFXO crystal oscillator started */
510 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
511 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
512 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
513 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
514 
515 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
516 /* Description: LFCLK started */
517 
518 /* Bit 0 : LFCLK started */
519 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
520 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
521 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
522 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
523 
524 /* Register: CLOCK_EVENTS_DONE */
525 /* Description: Calibration of LFRC completed */
526 
527 /* Bit 0 : Calibration of LFRC completed */
528 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
529 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
530 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
531 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
532 
533 /* Register: CLOCK_EVENTS_CTTO */
534 /* Description: Calibration timer timeout */
535 
536 /* Bit 0 : Calibration timer timeout */
537 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
538 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
539 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
540 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
541 
542 /* Register: CLOCK_EVENTS_CTSTARTED */
543 /* Description: Calibration timer has been started and is ready to process new tasks */
544 
545 /* Bit 0 : Calibration timer has been started and is ready to process new tasks */
546 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */
547 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */
548 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */
549 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */
550 
551 /* Register: CLOCK_EVENTS_CTSTOPPED */
552 /* Description: Calibration timer has been stopped and is ready to process new tasks */
553 
554 /* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */
555 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */
556 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */
557 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */
558 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */
559 
560 /* Register: CLOCK_INTENSET */
561 /* Description: Enable interrupt */
562 
563 /* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */
564 #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
565 #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
566 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
567 #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
568 #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
569 
570 /* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */
571 #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
572 #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
573 #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
574 #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
575 #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
576 
577 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
578 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
579 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
580 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
581 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
582 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
583 
584 /* Bit 3 : Write '1' to enable interrupt for event DONE */
585 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
586 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
587 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
588 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
589 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
590 
591 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
592 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
593 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
594 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
595 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
596 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
597 
598 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
599 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
600 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
601 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
602 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
603 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
604 
605 /* Register: CLOCK_INTENCLR */
606 /* Description: Disable interrupt */
607 
608 /* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */
609 #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
610 #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
611 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
612 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
613 #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
614 
615 /* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */
616 #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
617 #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
618 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
619 #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
620 #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
621 
622 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
623 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
624 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
625 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
626 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
627 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
628 
629 /* Bit 3 : Write '1' to disable interrupt for event DONE */
630 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
631 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
632 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
633 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
634 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
635 
636 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
637 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
638 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
639 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
640 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
641 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
642 
643 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
644 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
645 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
646 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
647 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
648 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
649 
650 /* Register: CLOCK_HFCLKRUN */
651 /* Description: Status indicating that HFCLKSTART task has been triggered */
652 
653 /* Bit 0 : HFCLKSTART task triggered or not */
654 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
655 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
656 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
657 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
658 
659 /* Register: CLOCK_HFCLKSTAT */
660 /* Description: HFCLK status */
661 
662 /* Bit 16 : HFCLK state */
663 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
664 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
665 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
666 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
667 
668 /* Bit 0 : Source of HFCLK */
669 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
670 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
671 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
672 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
673 
674 /* Register: CLOCK_LFCLKRUN */
675 /* Description: Status indicating that LFCLKSTART task has been triggered */
676 
677 /* Bit 0 : LFCLKSTART task triggered or not */
678 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
679 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
680 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
681 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
682 
683 /* Register: CLOCK_LFCLKSTAT */
684 /* Description: LFCLK status */
685 
686 /* Bit 16 : LFCLK state */
687 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
688 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
689 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
690 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
691 
692 /* Bits 1..0 : Source of LFCLK */
693 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
694 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
695 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
696 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
697 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
698 
699 /* Register: CLOCK_LFCLKSRCCOPY */
700 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
701 
702 /* Bits 1..0 : Clock source */
703 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
704 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
705 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
706 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
707 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
708 
709 /* Register: CLOCK_LFCLKSRC */
710 /* Description: Clock source for the LFCLK */
711 
712 /* Bit 17 : Enable or disable external source for LFCLK */
713 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
714 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
715 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
716 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
717 
718 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
719 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
720 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
721 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
722 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
723 
724 /* Bits 1..0 : Clock source */
725 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
726 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
727 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
728 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
729 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
730 
731 /* Register: CLOCK_HFXODEBOUNCE */
732 /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
733 
734 /* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */
735 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */
736 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */
737 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for 1.6 mm x 2.0 mm crystals and larger. */
738 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. */
739 
740 /* Register: CLOCK_LFXODEBOUNCE */
741 /* Description: LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. */
742 
743 /* Bit 0 : LFXO debounce time. */
744 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos (0UL) /*!< Position of LFXODEBOUNCE field. */
745 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Msk (0x1UL << CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos) /*!< Bit mask of LFXODEBOUNCE field. */
746 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Normal (0UL) /*!< 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. */
747 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Extended (1UL) /*!< 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. */
748 
749 /* Register: CLOCK_CTIV */
750 /* Description: Calibration timer interval */
751 
752 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
753 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
754 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
755 
756 /* Register: CLOCK_TRACECONFIG */
757 /* Description: Clocking options for the trace port debug interface */
758 
759 /* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */
760 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
761 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
762 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */
763 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */
764 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */
765 
766 /* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */
767 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
768 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
769 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */
770 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */
771 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */
772 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */
773 
774 
775 /* Peripheral: COMP */
776 /* Description: Comparator */
777 
778 /* Register: COMP_TASKS_START */
779 /* Description: Start comparator */
780 
781 /* Bit 0 : Start comparator */
782 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
783 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
784 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
785 
786 /* Register: COMP_TASKS_STOP */
787 /* Description: Stop comparator */
788 
789 /* Bit 0 : Stop comparator */
790 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
791 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
792 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
793 
794 /* Register: COMP_TASKS_SAMPLE */
795 /* Description: Sample comparator value */
796 
797 /* Bit 0 : Sample comparator value */
798 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
799 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
800 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
801 
802 /* Register: COMP_EVENTS_READY */
803 /* Description: COMP is ready and output is valid */
804 
805 /* Bit 0 : COMP is ready and output is valid */
806 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
807 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
808 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
809 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
810 
811 /* Register: COMP_EVENTS_DOWN */
812 /* Description: Downward crossing */
813 
814 /* Bit 0 : Downward crossing */
815 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
816 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
817 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
818 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
819 
820 /* Register: COMP_EVENTS_UP */
821 /* Description: Upward crossing */
822 
823 /* Bit 0 : Upward crossing */
824 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
825 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
826 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
827 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
828 
829 /* Register: COMP_EVENTS_CROSS */
830 /* Description: Downward or upward crossing */
831 
832 /* Bit 0 : Downward or upward crossing */
833 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
834 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
835 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
836 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
837 
838 /* Register: COMP_SHORTS */
839 /* Description: Shortcuts between local events and tasks */
840 
841 /* Bit 4 : Shortcut between event CROSS and task STOP */
842 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
843 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
844 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
845 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
846 
847 /* Bit 3 : Shortcut between event UP and task STOP */
848 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
849 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
850 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
851 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
852 
853 /* Bit 2 : Shortcut between event DOWN and task STOP */
854 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
855 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
856 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
857 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
858 
859 /* Bit 1 : Shortcut between event READY and task STOP */
860 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
861 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
862 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
863 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
864 
865 /* Bit 0 : Shortcut between event READY and task SAMPLE */
866 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
867 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
868 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
869 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
870 
871 /* Register: COMP_INTEN */
872 /* Description: Enable or disable interrupt */
873 
874 /* Bit 3 : Enable or disable interrupt for event CROSS */
875 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
876 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
877 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
878 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
879 
880 /* Bit 2 : Enable or disable interrupt for event UP */
881 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
882 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
883 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
884 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
885 
886 /* Bit 1 : Enable or disable interrupt for event DOWN */
887 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
888 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
889 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
890 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
891 
892 /* Bit 0 : Enable or disable interrupt for event READY */
893 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
894 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
895 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
896 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
897 
898 /* Register: COMP_INTENSET */
899 /* Description: Enable interrupt */
900 
901 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
902 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
903 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
904 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
905 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
906 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
907 
908 /* Bit 2 : Write '1' to enable interrupt for event UP */
909 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
910 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
911 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
912 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
913 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
914 
915 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
916 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
917 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
918 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
919 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
920 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
921 
922 /* Bit 0 : Write '1' to enable interrupt for event READY */
923 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
924 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
925 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
926 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
927 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
928 
929 /* Register: COMP_INTENCLR */
930 /* Description: Disable interrupt */
931 
932 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
933 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
934 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
935 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
936 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
937 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
938 
939 /* Bit 2 : Write '1' to disable interrupt for event UP */
940 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
941 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
942 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
943 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
944 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
945 
946 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
947 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
948 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
949 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
950 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
951 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
952 
953 /* Bit 0 : Write '1' to disable interrupt for event READY */
954 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
955 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
956 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
957 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
958 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
959 
960 /* Register: COMP_RESULT */
961 /* Description: Compare result */
962 
963 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
964 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
965 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
966 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
967 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
968 
969 /* Register: COMP_ENABLE */
970 /* Description: COMP enable */
971 
972 /* Bits 1..0 : Enable or disable COMP */
973 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
974 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
975 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
976 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
977 
978 /* Register: COMP_PSEL */
979 /* Description: Pin select */
980 
981 /* Bits 2..0 : Analog pin select */
982 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
983 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
984 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
985 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
986 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
987 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
988 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
989 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
990 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
991 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
992 
993 /* Register: COMP_REFSEL */
994 /* Description: Reference source select for single-ended mode */
995 
996 /* Bits 2..0 : Reference select */
997 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
998 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
999 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1000 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1001 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1002 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1003 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */
1004 
1005 /* Register: COMP_EXTREFSEL */
1006 /* Description: External reference select */
1007 
1008 /* Bits 2..0 : External analog reference select */
1009 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1010 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1011 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1012 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1013 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1014 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1015 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1016 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1017 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1018 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1019 
1020 /* Register: COMP_TH */
1021 /* Description: Threshold configuration for hysteresis unit */
1022 
1023 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1024 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1025 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1026 
1027 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1028 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1029 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1030 
1031 /* Register: COMP_MODE */
1032 /* Description: Mode configuration */
1033 
1034 /* Bit 8 : Main operation modes */
1035 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1036 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1037 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1038 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1039 
1040 /* Bits 1..0 : Speed and power modes */
1041 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1042 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1043 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1044 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1045 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1046 
1047 /* Register: COMP_HYST */
1048 /* Description: Comparator hysteresis enable */
1049 
1050 /* Bit 0 : Comparator hysteresis */
1051 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1052 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1053 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1054 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1055 
1056 
1057 /* Peripheral: ECB */
1058 /* Description: AES ECB Mode Encryption */
1059 
1060 /* Register: ECB_TASKS_STARTECB */
1061 /* Description: Start ECB block encrypt */
1062 
1063 /* Bit 0 : Start ECB block encrypt */
1064 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1065 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1066 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1067 
1068 /* Register: ECB_TASKS_STOPECB */
1069 /* Description: Abort a possible executing ECB operation */
1070 
1071 /* Bit 0 : Abort a possible executing ECB operation */
1072 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1073 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1074 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1075 
1076 /* Register: ECB_EVENTS_ENDECB */
1077 /* Description: ECB block encrypt complete */
1078 
1079 /* Bit 0 : ECB block encrypt complete */
1080 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1081 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1082 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1083 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1084 
1085 /* Register: ECB_EVENTS_ERRORECB */
1086 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1087 
1088 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1089 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1090 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1091 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1092 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1093 
1094 /* Register: ECB_INTENSET */
1095 /* Description: Enable interrupt */
1096 
1097 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1098 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1099 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1100 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1101 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1102 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1103 
1104 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1105 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1106 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1107 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1108 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1109 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1110 
1111 /* Register: ECB_INTENCLR */
1112 /* Description: Disable interrupt */
1113 
1114 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1115 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1116 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1117 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1118 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1119 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1120 
1121 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1122 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1123 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1124 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1125 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1126 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1127 
1128 /* Register: ECB_ECBDATAPTR */
1129 /* Description: ECB block encrypt memory pointers */
1130 
1131 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1132 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1133 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1134 
1135 
1136 /* Peripheral: EGU */
1137 /* Description: Event generator unit 0 */
1138 
1139 /* Register: EGU_TASKS_TRIGGER */
1140 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1141 
1142 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1143 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1144 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1145 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1146 
1147 /* Register: EGU_EVENTS_TRIGGERED */
1148 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1149 
1150 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1151 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1152 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1153 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1154 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1155 
1156 /* Register: EGU_INTEN */
1157 /* Description: Enable or disable interrupt */
1158 
1159 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1160 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1161 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1162 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1163 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1164 
1165 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1166 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1167 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1168 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1169 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1170 
1171 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1172 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1173 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1174 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1175 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1176 
1177 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1178 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1179 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1180 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1181 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1182 
1183 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1184 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1185 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1186 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1187 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1188 
1189 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1190 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1191 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1192 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1193 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1194 
1195 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1196 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1197 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1198 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1199 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1200 
1201 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1202 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1203 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1204 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1205 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1206 
1207 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1208 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1209 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1210 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1211 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1212 
1213 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1214 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1215 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1216 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1217 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1218 
1219 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1220 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1221 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1222 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1223 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1224 
1225 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1226 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1227 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1228 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1229 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1230 
1231 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1232 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1233 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1234 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1235 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1236 
1237 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1238 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1239 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1240 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1241 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1242 
1243 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1244 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1245 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1246 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1247 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1248 
1249 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1250 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1251 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1252 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1253 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1254 
1255 /* Register: EGU_INTENSET */
1256 /* Description: Enable interrupt */
1257 
1258 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1259 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1260 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1261 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1262 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1263 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1264 
1265 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1266 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1267 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1268 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1269 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1270 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1271 
1272 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1273 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1274 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1275 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1276 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1277 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1278 
1279 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1280 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1281 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1282 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1283 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1284 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1285 
1286 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1287 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1288 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1289 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1290 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1291 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1292 
1293 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1294 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1295 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1296 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1297 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1298 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1299 
1300 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1301 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1302 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1303 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1304 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1305 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1306 
1307 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1308 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1309 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1310 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1311 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1312 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1313 
1314 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1315 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1316 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1317 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1318 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1319 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1320 
1321 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1322 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1323 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1324 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1325 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1326 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1327 
1328 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1329 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1330 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1331 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1332 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1333 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1334 
1335 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1336 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1337 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1338 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1339 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1340 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1341 
1342 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1343 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1344 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1345 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1346 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1347 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1348 
1349 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1350 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1351 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1352 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1353 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1354 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1355 
1356 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1357 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1358 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1359 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1360 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1361 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1362 
1363 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1364 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1365 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1366 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1367 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1368 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1369 
1370 /* Register: EGU_INTENCLR */
1371 /* Description: Disable interrupt */
1372 
1373 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1374 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1375 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1376 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1377 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1378 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1379 
1380 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1381 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1382 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1383 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1384 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1385 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1386 
1387 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1388 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1389 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1390 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1391 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1392 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1393 
1394 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1395 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1396 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1397 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1398 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1399 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1400 
1401 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1402 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1403 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1404 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1405 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1406 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1407 
1408 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1409 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1410 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1411 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1412 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1413 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1414 
1415 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1416 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1417 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1418 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1419 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1420 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1421 
1422 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1423 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1424 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1425 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1426 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1427 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1428 
1429 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1430 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1431 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1432 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1433 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1434 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1435 
1436 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1437 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1438 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1439 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1440 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1441 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1442 
1443 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1444 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1445 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1446 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1447 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1448 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1449 
1450 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1451 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1452 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1453 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1454 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1455 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1456 
1457 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1458 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1459 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1460 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1461 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1462 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1463 
1464 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1465 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1466 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1467 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1468 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1469 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1470 
1471 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1472 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1473 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1474 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1475 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1476 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1477 
1478 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1479 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1480 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1481 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1482 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1483 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1484 
1485 
1486 /* Peripheral: FICR */
1487 /* Description: Factory information configuration registers */
1488 
1489 /* Register: FICR_CODEPAGESIZE */
1490 /* Description: Code memory page size */
1491 
1492 /* Bits 31..0 : Code memory page size */
1493 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1494 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1495 
1496 /* Register: FICR_CODESIZE */
1497 /* Description: Code memory size */
1498 
1499 /* Bits 31..0 : Code memory size in number of pages */
1500 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1501 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1502 
1503 /* Register: FICR_DEVICEID */
1504 /* Description: Description collection: Device identifier */
1505 
1506 /* Bits 31..0 : 64 bit unique device identifier */
1507 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1508 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1509 
1510 /* Register: FICR_ER */
1511 /* Description: Description collection: Encryption root, word n */
1512 
1513 /* Bits 31..0 : Encryption root, word n */
1514 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1515 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1516 
1517 /* Register: FICR_IR */
1518 /* Description: Description collection: Identity Root, word n */
1519 
1520 /* Bits 31..0 : Identity Root, word n */
1521 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1522 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1523 
1524 /* Register: FICR_DEVICEADDRTYPE */
1525 /* Description: Device address type */
1526 
1527 /* Bit 0 : Device address type */
1528 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1529 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1530 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1531 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1532 
1533 /* Register: FICR_DEVICEADDR */
1534 /* Description: Description collection: Device address n */
1535 
1536 /* Bits 31..0 : 48 bit device address */
1537 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1538 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1539 
1540 /* Register: FICR_INFO_PART */
1541 /* Description: Part code */
1542 
1543 /* Bits 31..0 : Part code */
1544 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1545 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1546 #define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */
1547 #define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */
1548 #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
1549 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1550 
1551 /* Register: FICR_INFO_VARIANT */
1552 /* Description: Build code (hardware version and production configuration) */
1553 
1554 /* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */
1555 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1556 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1557 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
1558 #define FICR_INFO_VARIANT_VARIANT_AAA1 (0x41414131UL) /*!< AAA1 */
1559 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1560 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
1561 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1562 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1563 
1564 /* Register: FICR_INFO_PACKAGE */
1565 /* Description: Package option */
1566 
1567 /* Bits 31..0 : Package option */
1568 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1569 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1570 #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */
1571 #define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 5x5 40-pin QFN */
1572 #define FICR_INFO_PACKAGE_PACKAGE_CJ (0x2008UL) /*!< CJxx - 3.175 x 3.175 WLCSP */
1573 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1574 
1575 /* Register: FICR_INFO_RAM */
1576 /* Description: RAM variant */
1577 
1578 /* Bits 31..0 : RAM variant */
1579 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1580 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1581 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
1582 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
1583 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
1584 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
1585 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
1586 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1587 
1588 /* Register: FICR_INFO_FLASH */
1589 /* Description: Flash variant */
1590 
1591 /* Bits 31..0 : Flash variant */
1592 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1593 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1594 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
1595 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
1596 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
1597 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
1598 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
1599 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1600 
1601 /* Register: FICR_PRODTEST */
1602 /* Description: Description collection: Production test signature n */
1603 
1604 /* Bits 31..0 : Production test signature n */
1605 #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */
1606 #define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */
1607 #define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */
1608 #define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */
1609 
1610 /* Register: FICR_TEMP_A0 */
1611 /* Description: Slope definition A0 */
1612 
1613 /* Bits 11..0 : A (slope definition) register. */
1614 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1615 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1616 
1617 /* Register: FICR_TEMP_A1 */
1618 /* Description: Slope definition A1 */
1619 
1620 /* Bits 11..0 : A (slope definition) register. */
1621 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1622 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1623 
1624 /* Register: FICR_TEMP_A2 */
1625 /* Description: Slope definition A2 */
1626 
1627 /* Bits 11..0 : A (slope definition) register. */
1628 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1629 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1630 
1631 /* Register: FICR_TEMP_A3 */
1632 /* Description: Slope definition A3 */
1633 
1634 /* Bits 11..0 : A (slope definition) register. */
1635 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1636 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1637 
1638 /* Register: FICR_TEMP_A4 */
1639 /* Description: Slope definition A4 */
1640 
1641 /* Bits 11..0 : A (slope definition) register. */
1642 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1643 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1644 
1645 /* Register: FICR_TEMP_A5 */
1646 /* Description: Slope definition A5 */
1647 
1648 /* Bits 11..0 : A (slope definition) register. */
1649 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1650 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1651 
1652 /* Register: FICR_TEMP_B0 */
1653 /* Description: Y-intercept B0 */
1654 
1655 /* Bits 13..0 : B (y-intercept) */
1656 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1657 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1658 
1659 /* Register: FICR_TEMP_B1 */
1660 /* Description: Y-intercept B1 */
1661 
1662 /* Bits 13..0 : B (y-intercept) */
1663 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
1664 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
1665 
1666 /* Register: FICR_TEMP_B2 */
1667 /* Description: Y-intercept B2 */
1668 
1669 /* Bits 13..0 : B (y-intercept) */
1670 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
1671 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
1672 
1673 /* Register: FICR_TEMP_B3 */
1674 /* Description: Y-intercept B3 */
1675 
1676 /* Bits 13..0 : B (y-intercept) */
1677 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
1678 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
1679 
1680 /* Register: FICR_TEMP_B4 */
1681 /* Description: Y-intercept B4 */
1682 
1683 /* Bits 13..0 : B (y-intercept) */
1684 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
1685 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
1686 
1687 /* Register: FICR_TEMP_B5 */
1688 /* Description: Y-intercept B5 */
1689 
1690 /* Bits 13..0 : B (y-intercept) */
1691 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
1692 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1693 
1694 /* Register: FICR_TEMP_T0 */
1695 /* Description: Segment end T0 */
1696 
1697 /* Bits 7..0 : T (segment end) register */
1698 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
1699 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
1700 
1701 /* Register: FICR_TEMP_T1 */
1702 /* Description: Segment end T1 */
1703 
1704 /* Bits 7..0 : T (segment end) register */
1705 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
1706 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
1707 
1708 /* Register: FICR_TEMP_T2 */
1709 /* Description: Segment end T2 */
1710 
1711 /* Bits 7..0 : T (segment end) register */
1712 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
1713 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
1714 
1715 /* Register: FICR_TEMP_T3 */
1716 /* Description: Segment end T3 */
1717 
1718 /* Bits 7..0 : T (segment end) register */
1719 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
1720 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
1721 
1722 /* Register: FICR_TEMP_T4 */
1723 /* Description: Segment end T4 */
1724 
1725 /* Bits 7..0 : T (segment end) register */
1726 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
1727 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
1728 
1729 /* Register: FICR_NFC_TAGHEADER0 */
1730 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1731 
1732 /* Bits 31..24 : Unique identifier byte 3 */
1733 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
1734 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
1735 
1736 /* Bits 23..16 : Unique identifier byte 2 */
1737 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
1738 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
1739 
1740 /* Bits 15..8 : Unique identifier byte 1 */
1741 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
1742 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
1743 
1744 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
1745 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
1746 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
1747 
1748 /* Register: FICR_NFC_TAGHEADER1 */
1749 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1750 
1751 /* Bits 31..24 : Unique identifier byte 7 */
1752 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
1753 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
1754 
1755 /* Bits 23..16 : Unique identifier byte 6 */
1756 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
1757 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
1758 
1759 /* Bits 15..8 : Unique identifier byte 5 */
1760 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
1761 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
1762 
1763 /* Bits 7..0 : Unique identifier byte 4 */
1764 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
1765 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
1766 
1767 /* Register: FICR_NFC_TAGHEADER2 */
1768 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1769 
1770 /* Bits 31..24 : Unique identifier byte 11 */
1771 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
1772 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
1773 
1774 /* Bits 23..16 : Unique identifier byte 10 */
1775 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
1776 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
1777 
1778 /* Bits 15..8 : Unique identifier byte 9 */
1779 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
1780 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
1781 
1782 /* Bits 7..0 : Unique identifier byte 8 */
1783 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
1784 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
1785 
1786 /* Register: FICR_NFC_TAGHEADER3 */
1787 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1788 
1789 /* Bits 31..24 : Unique identifier byte 15 */
1790 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
1791 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
1792 
1793 /* Bits 23..16 : Unique identifier byte 14 */
1794 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
1795 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
1796 
1797 /* Bits 15..8 : Unique identifier byte 13 */
1798 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
1799 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
1800 
1801 /* Bits 7..0 : Unique identifier byte 12 */
1802 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
1803 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
1804 
1805 
1806 /* Peripheral: GPIOTE */
1807 /* Description: GPIO Tasks and Events */
1808 
1809 /* Register: GPIOTE_TASKS_OUT */
1810 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1811 
1812 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1813 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1814 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1815 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1816 
1817 /* Register: GPIOTE_TASKS_SET */
1818 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1819 
1820 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1821 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1822 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1823 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1824 
1825 /* Register: GPIOTE_TASKS_CLR */
1826 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1827 
1828 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1829 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1830 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1831 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1832 
1833 /* Register: GPIOTE_EVENTS_IN */
1834 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1835 
1836 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1837 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1838 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1839 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1840 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1841 
1842 /* Register: GPIOTE_EVENTS_PORT */
1843 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1844 
1845 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1846 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1847 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1848 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1849 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1850 
1851 /* Register: GPIOTE_INTENSET */
1852 /* Description: Enable interrupt */
1853 
1854 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1855 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1856 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
1857 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1858 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1859 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1860 
1861 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1862 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
1863 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
1864 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1865 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1866 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1867 
1868 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1869 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
1870 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
1871 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1872 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1873 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1874 
1875 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1876 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
1877 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
1878 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1879 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1880 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1881 
1882 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1883 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
1884 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
1885 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1886 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1887 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1888 
1889 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1890 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
1891 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
1892 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1893 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1894 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1895 
1896 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1897 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1898 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
1899 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1900 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1901 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1902 
1903 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1904 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
1905 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
1906 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1907 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1908 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1909 
1910 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1911 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
1912 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
1913 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1914 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1915 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1916 
1917 /* Register: GPIOTE_INTENCLR */
1918 /* Description: Disable interrupt */
1919 
1920 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1921 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
1922 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
1923 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1924 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1925 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1926 
1927 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1928 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
1929 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
1930 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1931 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1932 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1933 
1934 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1935 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
1936 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
1937 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1938 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1939 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1940 
1941 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1942 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
1943 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
1944 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1945 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1946 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1947 
1948 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1949 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
1950 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
1951 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1952 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1953 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1954 
1955 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1956 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
1957 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
1958 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1959 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1960 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1961 
1962 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1963 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
1964 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
1965 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1966 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1967 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1968 
1969 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1970 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
1971 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
1972 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1973 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1974 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1975 
1976 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1977 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
1978 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
1979 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1980 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1981 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1982 
1983 /* Register: GPIOTE_CONFIG */
1984 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
1985 
1986 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
1987 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
1988 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
1989 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
1990 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
1991 
1992 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
1993 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
1994 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
1995 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
1996 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
1997 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
1998 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
1999 
2000 /* Bit 13 : Port number */
2001 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
2002 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
2003 
2004 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
2005 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2006 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2007 
2008 /* Bits 1..0 : Mode */
2009 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2010 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2011 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2012 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2013 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2014 
2015 
2016 /* Peripheral: I2S */
2017 /* Description: Inter-IC Sound */
2018 
2019 /* Register: I2S_TASKS_START */
2020 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2021 
2022 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2023 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2024 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2025 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2026 
2027 /* Register: I2S_TASKS_STOP */
2028 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
2029 
2030 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
2031 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2032 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2033 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2034 
2035 /* Register: I2S_EVENTS_RXPTRUPD */
2036 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2037       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2038 
2039 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
2040       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2041 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
2042 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
2043 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2044 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
2045 
2046 /* Register: I2S_EVENTS_STOPPED */
2047 /* Description: I2S transfer stopped. */
2048 
2049 /* Bit 0 : I2S transfer stopped. */
2050 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
2051 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
2052 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
2053 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
2054 
2055 /* Register: I2S_EVENTS_TXPTRUPD */
2056 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2057       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2058 
2059 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
2060       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2061 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
2062 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
2063 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2064 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
2065 
2066 /* Register: I2S_INTEN */
2067 /* Description: Enable or disable interrupt */
2068 
2069 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
2070 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2071 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2072 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2073 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2074 
2075 /* Bit 2 : Enable or disable interrupt for event STOPPED */
2076 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2077 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2078 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2079 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2080 
2081 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
2082 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2083 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2084 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2085 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2086 
2087 /* Register: I2S_INTENSET */
2088 /* Description: Enable interrupt */
2089 
2090 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
2091 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2092 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2093 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2094 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2095 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2096 
2097 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
2098 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2099 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2100 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2101 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2102 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2103 
2104 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
2105 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2106 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2107 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2108 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2109 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2110 
2111 /* Register: I2S_INTENCLR */
2112 /* Description: Disable interrupt */
2113 
2114 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
2115 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2116 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2117 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2118 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2119 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2120 
2121 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
2122 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2123 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2124 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2125 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2126 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2127 
2128 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
2129 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2130 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2131 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2132 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2133 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2134 
2135 /* Register: I2S_ENABLE */
2136 /* Description: Enable I2S module. */
2137 
2138 /* Bit 0 : Enable I2S module. */
2139 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2140 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2141 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2142 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2143 
2144 /* Register: I2S_CONFIG_MODE */
2145 /* Description: I2S mode. */
2146 
2147 /* Bit 0 : I2S mode. */
2148 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2149 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2150 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2151 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2152 
2153 /* Register: I2S_CONFIG_RXEN */
2154 /* Description: Reception (RX) enable. */
2155 
2156 /* Bit 0 : Reception (RX) enable. */
2157 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2158 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2159 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2160 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2161 
2162 /* Register: I2S_CONFIG_TXEN */
2163 /* Description: Transmission (TX) enable. */
2164 
2165 /* Bit 0 : Transmission (TX) enable. */
2166 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2167 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2168 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2169 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2170 
2171 /* Register: I2S_CONFIG_MCKEN */
2172 /* Description: Master clock generator enable. */
2173 
2174 /* Bit 0 : Master clock generator enable. */
2175 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2176 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2177 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2178 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2179 
2180 /* Register: I2S_CONFIG_MCKFREQ */
2181 /* Description: Master clock generator frequency. */
2182 
2183 /* Bits 31..0 : Master clock generator frequency. */
2184 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2185 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2186 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2187 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2188 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2189 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2190 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2191 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2192 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2193 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2194 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2195 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2196 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2197 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2198 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2199 
2200 /* Register: I2S_CONFIG_RATIO */
2201 /* Description: MCK / LRCK ratio. */
2202 
2203 /* Bits 3..0 : MCK / LRCK ratio. */
2204 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2205 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2206 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2207 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2208 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2209 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2210 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2211 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2212 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2213 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2214 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2215 
2216 /* Register: I2S_CONFIG_SWIDTH */
2217 /* Description: Sample width. */
2218 
2219 /* Bits 1..0 : Sample width. */
2220 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2221 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2222 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2223 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2224 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2225 
2226 /* Register: I2S_CONFIG_ALIGN */
2227 /* Description: Alignment of sample within a frame. */
2228 
2229 /* Bit 0 : Alignment of sample within a frame. */
2230 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2231 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2232 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2233 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2234 
2235 /* Register: I2S_CONFIG_FORMAT */
2236 /* Description: Frame format. */
2237 
2238 /* Bit 0 : Frame format. */
2239 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2240 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2241 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2242 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2243 
2244 /* Register: I2S_CONFIG_CHANNELS */
2245 /* Description: Enable channels. */
2246 
2247 /* Bits 1..0 : Enable channels. */
2248 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2249 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2250 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2251 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2252 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2253 
2254 /* Register: I2S_RXD_PTR */
2255 /* Description: Receive buffer RAM start address. */
2256 
2257 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2258 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2259 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2260 
2261 /* Register: I2S_TXD_PTR */
2262 /* Description: Transmit buffer RAM start address. */
2263 
2264 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2265 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2266 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2267 
2268 /* Register: I2S_RXTXD_MAXCNT */
2269 /* Description: Size of RXD and TXD buffers. */
2270 
2271 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2272 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2273 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2274 
2275 /* Register: I2S_PSEL_MCK */
2276 /* Description: Pin select for MCK signal. */
2277 
2278 /* Bit 31 : Connection */
2279 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2280 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2281 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2282 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2283 
2284 /* Bit 5 : Port number */
2285 #define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2286 #define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
2287 
2288 /* Bits 4..0 : Pin number */
2289 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2290 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2291 
2292 /* Register: I2S_PSEL_SCK */
2293 /* Description: Pin select for SCK signal. */
2294 
2295 /* Bit 31 : Connection */
2296 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2297 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2298 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2299 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2300 
2301 /* Bit 5 : Port number */
2302 #define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2303 #define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
2304 
2305 /* Bits 4..0 : Pin number */
2306 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2307 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2308 
2309 /* Register: I2S_PSEL_LRCK */
2310 /* Description: Pin select for LRCK signal. */
2311 
2312 /* Bit 31 : Connection */
2313 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2314 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2315 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2316 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2317 
2318 /* Bit 5 : Port number */
2319 #define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2320 #define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
2321 
2322 /* Bits 4..0 : Pin number */
2323 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2324 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2325 
2326 /* Register: I2S_PSEL_SDIN */
2327 /* Description: Pin select for SDIN signal. */
2328 
2329 /* Bit 31 : Connection */
2330 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2331 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2332 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2333 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2334 
2335 /* Bit 5 : Port number */
2336 #define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
2337 #define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
2338 
2339 /* Bits 4..0 : Pin number */
2340 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2341 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2342 
2343 /* Register: I2S_PSEL_SDOUT */
2344 /* Description: Pin select for SDOUT signal. */
2345 
2346 /* Bit 31 : Connection */
2347 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2348 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2349 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2350 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2351 
2352 /* Bit 5 : Port number */
2353 #define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
2354 #define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
2355 
2356 /* Bits 4..0 : Pin number */
2357 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2358 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2359 
2360 
2361 /* Peripheral: LPCOMP */
2362 /* Description: Low-power comparator */
2363 
2364 /* Register: LPCOMP_TASKS_START */
2365 /* Description: Start comparator */
2366 
2367 /* Bit 0 : Start comparator */
2368 #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2369 #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2370 #define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2371 
2372 /* Register: LPCOMP_TASKS_STOP */
2373 /* Description: Stop comparator */
2374 
2375 /* Bit 0 : Stop comparator */
2376 #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2377 #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2378 #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2379 
2380 /* Register: LPCOMP_TASKS_SAMPLE */
2381 /* Description: Sample comparator value */
2382 
2383 /* Bit 0 : Sample comparator value */
2384 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
2385 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
2386 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
2387 
2388 /* Register: LPCOMP_EVENTS_READY */
2389 /* Description: LPCOMP is ready and output is valid */
2390 
2391 /* Bit 0 : LPCOMP is ready and output is valid */
2392 #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
2393 #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
2394 #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
2395 #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
2396 
2397 /* Register: LPCOMP_EVENTS_DOWN */
2398 /* Description: Downward crossing */
2399 
2400 /* Bit 0 : Downward crossing */
2401 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
2402 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
2403 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
2404 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
2405 
2406 /* Register: LPCOMP_EVENTS_UP */
2407 /* Description: Upward crossing */
2408 
2409 /* Bit 0 : Upward crossing */
2410 #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
2411 #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
2412 #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
2413 #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
2414 
2415 /* Register: LPCOMP_EVENTS_CROSS */
2416 /* Description: Downward or upward crossing */
2417 
2418 /* Bit 0 : Downward or upward crossing */
2419 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
2420 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
2421 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
2422 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
2423 
2424 /* Register: LPCOMP_SHORTS */
2425 /* Description: Shortcuts between local events and tasks */
2426 
2427 /* Bit 4 : Shortcut between event CROSS and task STOP */
2428 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2429 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2430 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2431 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2432 
2433 /* Bit 3 : Shortcut between event UP and task STOP */
2434 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2435 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2436 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2437 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2438 
2439 /* Bit 2 : Shortcut between event DOWN and task STOP */
2440 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2441 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2442 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2443 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2444 
2445 /* Bit 1 : Shortcut between event READY and task STOP */
2446 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2447 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2448 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2449 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2450 
2451 /* Bit 0 : Shortcut between event READY and task SAMPLE */
2452 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2453 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2454 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2455 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2456 
2457 /* Register: LPCOMP_INTENSET */
2458 /* Description: Enable interrupt */
2459 
2460 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
2461 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2462 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2463 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2464 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2465 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2466 
2467 /* Bit 2 : Write '1' to enable interrupt for event UP */
2468 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2469 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2470 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2471 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2472 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2473 
2474 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
2475 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2476 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2477 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2478 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2479 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2480 
2481 /* Bit 0 : Write '1' to enable interrupt for event READY */
2482 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2483 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2484 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2485 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2486 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2487 
2488 /* Register: LPCOMP_INTENCLR */
2489 /* Description: Disable interrupt */
2490 
2491 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
2492 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2493 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2494 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2495 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2496 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2497 
2498 /* Bit 2 : Write '1' to disable interrupt for event UP */
2499 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2500 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2501 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2502 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2503 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2504 
2505 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
2506 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2507 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2508 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2509 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2510 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2511 
2512 /* Bit 0 : Write '1' to disable interrupt for event READY */
2513 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2514 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2515 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2516 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2517 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2518 
2519 /* Register: LPCOMP_RESULT */
2520 /* Description: Compare result */
2521 
2522 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2523 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2524 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2525 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-) */
2526 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-) */
2527 
2528 /* Register: LPCOMP_ENABLE */
2529 /* Description: Enable LPCOMP */
2530 
2531 /* Bits 1..0 : Enable or disable LPCOMP */
2532 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2533 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2534 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2535 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2536 
2537 /* Register: LPCOMP_PSEL */
2538 /* Description: Input pin select */
2539 
2540 /* Bits 2..0 : Analog pin select */
2541 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2542 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2543 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
2544 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2545 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2546 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
2547 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
2548 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
2549 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
2550 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
2551 
2552 /* Register: LPCOMP_REFSEL */
2553 /* Description: Reference select */
2554 
2555 /* Bits 3..0 : Reference select */
2556 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2557 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2558 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2559 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2560 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2561 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
2562 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
2563 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
2564 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
2565 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
2566 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2567 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
2568 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
2569 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
2570 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
2571 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
2572 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
2573 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
2574 
2575 /* Register: LPCOMP_EXTREFSEL */
2576 /* Description: External reference select */
2577 
2578 /* Bit 0 : External analog reference select */
2579 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2580 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2581 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
2582 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
2583 
2584 /* Register: LPCOMP_ANADETECT */
2585 /* Description: Analog detect configuration */
2586 
2587 /* Bits 1..0 : Analog detect configuration */
2588 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
2589 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
2590 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
2591 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2592 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2593 
2594 /* Register: LPCOMP_HYST */
2595 /* Description: Comparator hysteresis enable */
2596 
2597 /* Bit 0 : Comparator hysteresis enable */
2598 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2599 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2600 #define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
2601 #define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
2602 
2603 
2604 /* Peripheral: MWU */
2605 /* Description: Memory Watch Unit */
2606 
2607 /* Register: MWU_EVENTS_REGION_WA */
2608 /* Description: Description cluster: Write access to region n detected */
2609 
2610 /* Bit 0 : Write access to region n detected */
2611 #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
2612 #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
2613 #define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
2614 #define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */
2615 
2616 /* Register: MWU_EVENTS_REGION_RA */
2617 /* Description: Description cluster: Read access to region n detected */
2618 
2619 /* Bit 0 : Read access to region n detected */
2620 #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
2621 #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
2622 #define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
2623 #define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */
2624 
2625 /* Register: MWU_EVENTS_PREGION_WA */
2626 /* Description: Description cluster: Write access to peripheral region n detected */
2627 
2628 /* Bit 0 : Write access to peripheral region n detected */
2629 #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
2630 #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
2631 #define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
2632 #define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */
2633 
2634 /* Register: MWU_EVENTS_PREGION_RA */
2635 /* Description: Description cluster: Read access to peripheral region n detected */
2636 
2637 /* Bit 0 : Read access to peripheral region n detected */
2638 #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
2639 #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
2640 #define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
2641 #define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */
2642 
2643 /* Register: MWU_INTEN */
2644 /* Description: Enable or disable interrupt */
2645 
2646 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
2647 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2648 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2649 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2650 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2651 
2652 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
2653 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2654 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2655 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2656 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2657 
2658 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
2659 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2660 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2661 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2662 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2663 
2664 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
2665 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2666 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2667 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2668 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2669 
2670 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
2671 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2672 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2673 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2674 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2675 
2676 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
2677 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2678 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2679 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2680 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2681 
2682 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
2683 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2684 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2685 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2686 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2687 
2688 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
2689 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2690 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2691 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2692 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2693 
2694 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
2695 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2696 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2697 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2698 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2699 
2700 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
2701 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2702 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2703 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2704 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2705 
2706 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
2707 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2708 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2709 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2710 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2711 
2712 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
2713 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2714 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2715 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2716 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2717 
2718 /* Register: MWU_INTENSET */
2719 /* Description: Enable interrupt */
2720 
2721 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
2722 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2723 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2724 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2725 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2726 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2727 
2728 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
2729 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2730 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2731 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2732 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2733 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2734 
2735 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
2736 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2737 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2738 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2739 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2740 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2741 
2742 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
2743 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2744 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2745 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2746 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2747 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2748 
2749 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
2750 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2751 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2752 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2753 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2754 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2755 
2756 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
2757 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2758 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2759 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2760 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2761 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2762 
2763 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
2764 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2765 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2766 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2767 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2768 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2769 
2770 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
2771 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2772 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2773 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2774 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2775 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2776 
2777 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
2778 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2779 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2780 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2781 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2782 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2783 
2784 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
2785 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2786 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2787 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2788 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2789 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2790 
2791 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
2792 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2793 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2794 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2795 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2796 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2797 
2798 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
2799 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2800 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2801 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2802 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2803 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2804 
2805 /* Register: MWU_INTENCLR */
2806 /* Description: Disable interrupt */
2807 
2808 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
2809 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2810 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2811 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2812 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2813 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2814 
2815 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
2816 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2817 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2818 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2819 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2820 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2821 
2822 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
2823 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2824 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2825 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2826 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2827 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2828 
2829 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
2830 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2831 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2832 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2833 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2834 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2835 
2836 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
2837 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2838 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2839 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2840 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2841 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2842 
2843 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
2844 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2845 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2846 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2847 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2848 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2849 
2850 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
2851 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2852 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2853 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2854 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2855 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2856 
2857 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
2858 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2859 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2860 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2861 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2862 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2863 
2864 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
2865 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2866 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2867 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2868 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2869 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
2870 
2871 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
2872 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2873 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2874 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2875 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2876 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
2877 
2878 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
2879 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2880 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2881 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2882 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2883 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
2884 
2885 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
2886 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2887 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2888 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2889 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2890 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
2891 
2892 /* Register: MWU_NMIEN */
2893 /* Description: Enable or disable interrupt */
2894 
2895 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
2896 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2897 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2898 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2899 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2900 
2901 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
2902 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2903 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2904 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2905 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2906 
2907 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
2908 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2909 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2910 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2911 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2912 
2913 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
2914 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2915 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2916 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2917 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2918 
2919 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
2920 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2921 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2922 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
2923 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
2924 
2925 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
2926 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2927 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2928 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
2929 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
2930 
2931 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
2932 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2933 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2934 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
2935 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
2936 
2937 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
2938 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2939 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2940 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
2941 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
2942 
2943 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
2944 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2945 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2946 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
2947 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
2948 
2949 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
2950 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2951 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2952 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
2953 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
2954 
2955 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
2956 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2957 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2958 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
2959 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
2960 
2961 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
2962 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2963 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2964 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
2965 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
2966 
2967 /* Register: MWU_NMIENSET */
2968 /* Description: Enable interrupt */
2969 
2970 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
2971 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2972 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2973 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2974 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2975 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
2976 
2977 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
2978 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2979 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2980 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2981 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2982 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
2983 
2984 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
2985 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2986 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2987 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2988 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2989 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
2990 
2991 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
2992 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2993 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2994 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2995 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2996 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
2997 
2998 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
2999 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3000 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3001 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3002 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3003 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3004 
3005 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
3006 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3007 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3008 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3009 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3010 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3011 
3012 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
3013 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3014 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3015 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3016 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3017 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3018 
3019 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
3020 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3021 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3022 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3023 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3024 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3025 
3026 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
3027 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3028 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3029 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3030 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3031 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3032 
3033 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
3034 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3035 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3036 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3037 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3038 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3039 
3040 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
3041 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3042 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3043 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3044 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3045 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3046 
3047 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
3048 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3049 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3050 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3051 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3052 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3053 
3054 /* Register: MWU_NMIENCLR */
3055 /* Description: Disable interrupt */
3056 
3057 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
3058 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3059 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3060 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3061 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3062 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3063 
3064 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
3065 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3066 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3067 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3068 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3069 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3070 
3071 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
3072 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3073 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3074 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3075 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3076 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3077 
3078 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
3079 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3080 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3081 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3082 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3083 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3084 
3085 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
3086 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3087 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3088 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3089 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3090 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3091 
3092 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
3093 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3094 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3095 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3096 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3097 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3098 
3099 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
3100 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3101 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3102 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3103 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3104 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3105 
3106 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
3107 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3108 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3109 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3110 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3111 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3112 
3113 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
3114 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3115 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3116 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3117 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3118 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3119 
3120 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
3121 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3122 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3123 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3124 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3125 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3126 
3127 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
3128 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3129 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3130 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3131 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3132 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3133 
3134 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
3135 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3136 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3137 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3138 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3139 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3140 
3141 /* Register: MWU_PERREGION_SUBSTATWA */
3142 /* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
3143 
3144 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3145 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3146 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3147 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3148 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3149 
3150 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3151 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3152 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3153 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3154 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3155 
3156 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3157 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3158 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3159 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3160 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3161 
3162 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3163 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3164 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3165 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3166 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3167 
3168 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3169 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3170 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3171 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3172 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3173 
3174 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3175 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3176 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3177 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3178 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3179 
3180 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3181 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3182 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3183 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3184 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3185 
3186 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3187 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3188 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3189 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3190 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3191 
3192 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3193 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3194 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3195 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3196 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3197 
3198 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3199 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3200 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3201 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3202 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3203 
3204 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3205 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3206 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3207 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3208 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3209 
3210 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3211 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3212 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3213 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3214 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3215 
3216 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3217 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3218 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3219 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3220 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3221 
3222 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3223 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3224 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3225 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3226 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3227 
3228 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3229 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3230 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3231 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3232 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3233 
3234 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3235 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3236 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3237 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3238 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3239 
3240 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3241 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3242 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3243 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3244 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3245 
3246 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3247 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3248 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3249 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3250 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3251 
3252 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3253 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3254 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3255 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3256 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3257 
3258 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3259 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3260 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3261 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3262 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3263 
3264 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3265 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3266 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3267 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3268 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3269 
3270 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3271 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3272 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3273 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3274 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3275 
3276 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3277 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3278 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3279 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3280 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3281 
3282 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3283 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3284 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3285 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3286 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3287 
3288 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3289 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3290 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3291 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3292 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3293 
3294 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3295 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3296 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3297 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3298 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3299 
3300 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3301 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3302 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3303 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3304 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3305 
3306 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3307 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3308 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3309 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3310 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3311 
3312 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3313 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3314 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3315 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3316 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3317 
3318 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3319 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3320 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3321 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3322 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3323 
3324 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3325 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3326 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3327 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3328 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3329 
3330 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3331 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3332 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3333 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3334 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3335 
3336 /* Register: MWU_PERREGION_SUBSTATRA */
3337 /* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
3338 
3339 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3340 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3341 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3342 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3343 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3344 
3345 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3346 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3347 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3348 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3349 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3350 
3351 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3352 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3353 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
3354 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
3355 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3356 
3357 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3358 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3359 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
3360 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
3361 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3362 
3363 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3364 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3365 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
3366 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
3367 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3368 
3369 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3370 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3371 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
3372 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
3373 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3374 
3375 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3376 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3377 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
3378 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
3379 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3380 
3381 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3382 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3383 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
3384 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
3385 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3386 
3387 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3388 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3389 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
3390 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
3391 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3392 
3393 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3394 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3395 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
3396 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
3397 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3398 
3399 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3400 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3401 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
3402 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
3403 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3404 
3405 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3406 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3407 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
3408 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
3409 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3410 
3411 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3412 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3413 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
3414 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
3415 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3416 
3417 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3418 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3419 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
3420 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
3421 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3422 
3423 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3424 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3425 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
3426 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
3427 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3428 
3429 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3430 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3431 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
3432 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
3433 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3434 
3435 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3436 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3437 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
3438 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
3439 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3440 
3441 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3442 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3443 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
3444 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
3445 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3446 
3447 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3448 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3449 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
3450 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
3451 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3452 
3453 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3454 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3455 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
3456 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
3457 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3458 
3459 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3460 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3461 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
3462 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
3463 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3464 
3465 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3466 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3467 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
3468 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
3469 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3470 
3471 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3472 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3473 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
3474 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3475 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3476 
3477 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3478 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3479 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
3480 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3481 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3482 
3483 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3484 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3485 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
3486 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3487 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3488 
3489 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3490 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3491 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
3492 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3493 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3494 
3495 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3496 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3497 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
3498 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3499 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3500 
3501 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3502 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3503 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
3504 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3505 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3506 
3507 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3508 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3509 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
3510 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3511 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3512 
3513 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3514 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3515 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
3516 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3517 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3518 
3519 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3520 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3521 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
3522 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3523 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3524 
3525 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3526 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3527 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
3528 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3529 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3530 
3531 /* Register: MWU_REGIONEN */
3532 /* Description: Enable/disable regions watch */
3533 
3534 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3535 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3536 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3537 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3538 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3539 
3540 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3541 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3542 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3543 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3544 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3545 
3546 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3547 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3548 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3549 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3550 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3551 
3552 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3553 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3554 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3555 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3556 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3557 
3558 /* Bit 7 : Enable/disable read access watch in region[3] */
3559 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3560 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3561 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3562 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3563 
3564 /* Bit 6 : Enable/disable write access watch in region[3] */
3565 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3566 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3567 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3568 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3569 
3570 /* Bit 5 : Enable/disable read access watch in region[2] */
3571 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3572 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3573 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3574 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3575 
3576 /* Bit 4 : Enable/disable write access watch in region[2] */
3577 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3578 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3579 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3580 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3581 
3582 /* Bit 3 : Enable/disable read access watch in region[1] */
3583 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3584 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3585 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3586 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3587 
3588 /* Bit 2 : Enable/disable write access watch in region[1] */
3589 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3590 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3591 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3592 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3593 
3594 /* Bit 1 : Enable/disable read access watch in region[0] */
3595 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3596 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3597 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3598 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3599 
3600 /* Bit 0 : Enable/disable write access watch in region[0] */
3601 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3602 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3603 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3604 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3605 
3606 /* Register: MWU_REGIONENSET */
3607 /* Description: Enable regions watch */
3608 
3609 /* Bit 27 : Enable read access watch in PREGION[1] */
3610 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3611 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3612 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3613 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3614 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3615 
3616 /* Bit 26 : Enable write access watch in PREGION[1] */
3617 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3618 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3619 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3620 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3621 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3622 
3623 /* Bit 25 : Enable read access watch in PREGION[0] */
3624 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3625 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3626 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3627 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3628 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3629 
3630 /* Bit 24 : Enable write access watch in PREGION[0] */
3631 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3632 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3633 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3634 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3635 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3636 
3637 /* Bit 7 : Enable read access watch in region[3] */
3638 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3639 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3640 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3641 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3642 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3643 
3644 /* Bit 6 : Enable write access watch in region[3] */
3645 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3646 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3647 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3648 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3649 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3650 
3651 /* Bit 5 : Enable read access watch in region[2] */
3652 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3653 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3654 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3655 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3656 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3657 
3658 /* Bit 4 : Enable write access watch in region[2] */
3659 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3660 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3661 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3662 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3663 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3664 
3665 /* Bit 3 : Enable read access watch in region[1] */
3666 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3667 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3668 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3669 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3670 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3671 
3672 /* Bit 2 : Enable write access watch in region[1] */
3673 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3674 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3675 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3676 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3677 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3678 
3679 /* Bit 1 : Enable read access watch in region[0] */
3680 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3681 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3682 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3683 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3684 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3685 
3686 /* Bit 0 : Enable write access watch in region[0] */
3687 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3688 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3689 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3690 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3691 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3692 
3693 /* Register: MWU_REGIONENCLR */
3694 /* Description: Disable regions watch */
3695 
3696 /* Bit 27 : Disable read access watch in PREGION[1] */
3697 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3698 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3699 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3700 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3701 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3702 
3703 /* Bit 26 : Disable write access watch in PREGION[1] */
3704 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3705 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3706 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3707 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3708 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3709 
3710 /* Bit 25 : Disable read access watch in PREGION[0] */
3711 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3712 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3713 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3714 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3715 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3716 
3717 /* Bit 24 : Disable write access watch in PREGION[0] */
3718 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3719 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3720 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3721 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3722 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3723 
3724 /* Bit 7 : Disable read access watch in region[3] */
3725 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3726 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3727 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3728 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3729 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3730 
3731 /* Bit 6 : Disable write access watch in region[3] */
3732 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3733 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3734 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3735 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3736 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3737 
3738 /* Bit 5 : Disable read access watch in region[2] */
3739 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3740 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3741 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3742 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3743 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3744 
3745 /* Bit 4 : Disable write access watch in region[2] */
3746 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3747 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3748 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3749 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3750 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3751 
3752 /* Bit 3 : Disable read access watch in region[1] */
3753 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3754 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3755 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3756 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3757 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3758 
3759 /* Bit 2 : Disable write access watch in region[1] */
3760 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3761 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3762 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3763 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3764 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3765 
3766 /* Bit 1 : Disable read access watch in region[0] */
3767 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3768 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3769 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3770 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3771 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3772 
3773 /* Bit 0 : Disable write access watch in region[0] */
3774 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3775 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3776 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3777 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3778 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3779 
3780 /* Register: MWU_REGION_START */
3781 /* Description: Description cluster: Start address for region n */
3782 
3783 /* Bits 31..0 : Start address for region */
3784 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
3785 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
3786 
3787 /* Register: MWU_REGION_END */
3788 /* Description: Description cluster: End address of region n */
3789 
3790 /* Bits 31..0 : End address of region. */
3791 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
3792 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
3793 
3794 /* Register: MWU_PREGION_START */
3795 /* Description: Description cluster: Reserved for future use */
3796 
3797 /* Bits 31..0 : Reserved for future use */
3798 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
3799 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
3800 
3801 /* Register: MWU_PREGION_END */
3802 /* Description: Description cluster: Reserved for future use */
3803 
3804 /* Bits 31..0 : Reserved for future use */
3805 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
3806 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
3807 
3808 /* Register: MWU_PREGION_SUBS */
3809 /* Description: Description cluster: Subregions of region n */
3810 
3811 /* Bit 31 : Include or exclude subregion 31 in region */
3812 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
3813 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
3814 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
3815 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3816 
3817 /* Bit 30 : Include or exclude subregion 30 in region */
3818 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
3819 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
3820 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
3821 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3822 
3823 /* Bit 29 : Include or exclude subregion 29 in region */
3824 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
3825 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
3826 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
3827 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3828 
3829 /* Bit 28 : Include or exclude subregion 28 in region */
3830 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
3831 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
3832 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
3833 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3834 
3835 /* Bit 27 : Include or exclude subregion 27 in region */
3836 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
3837 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
3838 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
3839 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3840 
3841 /* Bit 26 : Include or exclude subregion 26 in region */
3842 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
3843 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
3844 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
3845 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3846 
3847 /* Bit 25 : Include or exclude subregion 25 in region */
3848 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
3849 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
3850 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
3851 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
3852 
3853 /* Bit 24 : Include or exclude subregion 24 in region */
3854 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
3855 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
3856 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
3857 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
3858 
3859 /* Bit 23 : Include or exclude subregion 23 in region */
3860 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
3861 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
3862 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
3863 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
3864 
3865 /* Bit 22 : Include or exclude subregion 22 in region */
3866 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
3867 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
3868 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
3869 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
3870 
3871 /* Bit 21 : Include or exclude subregion 21 in region */
3872 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
3873 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
3874 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
3875 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
3876 
3877 /* Bit 20 : Include or exclude subregion 20 in region */
3878 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
3879 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
3880 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
3881 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
3882 
3883 /* Bit 19 : Include or exclude subregion 19 in region */
3884 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
3885 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
3886 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
3887 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
3888 
3889 /* Bit 18 : Include or exclude subregion 18 in region */
3890 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
3891 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
3892 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
3893 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
3894 
3895 /* Bit 17 : Include or exclude subregion 17 in region */
3896 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
3897 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
3898 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
3899 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
3900 
3901 /* Bit 16 : Include or exclude subregion 16 in region */
3902 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
3903 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
3904 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
3905 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
3906 
3907 /* Bit 15 : Include or exclude subregion 15 in region */
3908 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
3909 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
3910 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
3911 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
3912 
3913 /* Bit 14 : Include or exclude subregion 14 in region */
3914 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
3915 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
3916 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
3917 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
3918 
3919 /* Bit 13 : Include or exclude subregion 13 in region */
3920 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
3921 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
3922 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
3923 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
3924 
3925 /* Bit 12 : Include or exclude subregion 12 in region */
3926 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
3927 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
3928 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
3929 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
3930 
3931 /* Bit 11 : Include or exclude subregion 11 in region */
3932 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
3933 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
3934 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
3935 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
3936 
3937 /* Bit 10 : Include or exclude subregion 10 in region */
3938 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
3939 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
3940 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
3941 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
3942 
3943 /* Bit 9 : Include or exclude subregion 9 in region */
3944 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
3945 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
3946 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
3947 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
3948 
3949 /* Bit 8 : Include or exclude subregion 8 in region */
3950 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
3951 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
3952 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
3953 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
3954 
3955 /* Bit 7 : Include or exclude subregion 7 in region */
3956 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
3957 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
3958 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
3959 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
3960 
3961 /* Bit 6 : Include or exclude subregion 6 in region */
3962 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
3963 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
3964 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
3965 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
3966 
3967 /* Bit 5 : Include or exclude subregion 5 in region */
3968 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
3969 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
3970 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
3971 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
3972 
3973 /* Bit 4 : Include or exclude subregion 4 in region */
3974 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
3975 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
3976 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
3977 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
3978 
3979 /* Bit 3 : Include or exclude subregion 3 in region */
3980 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
3981 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
3982 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
3983 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
3984 
3985 /* Bit 2 : Include or exclude subregion 2 in region */
3986 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
3987 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
3988 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
3989 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
3990 
3991 /* Bit 1 : Include or exclude subregion 1 in region */
3992 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
3993 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
3994 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
3995 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
3996 
3997 /* Bit 0 : Include or exclude subregion 0 in region */
3998 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
3999 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4000 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4001 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4002 
4003 
4004 /* Peripheral: NFCT */
4005 /* Description: NFC-A compatible radio */
4006 
4007 /* Register: NFCT_TASKS_ACTIVATE */
4008 /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
4009 
4010 /* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
4011 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
4012 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
4013 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
4014 
4015 /* Register: NFCT_TASKS_DISABLE */
4016 /* Description: Disable NFCT peripheral */
4017 
4018 /* Bit 0 : Disable NFCT peripheral */
4019 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
4020 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
4021 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
4022 
4023 /* Register: NFCT_TASKS_SENSE */
4024 /* Description: Enable NFC sense field mode, change state to sense mode */
4025 
4026 /* Bit 0 : Enable NFC sense field mode, change state to sense mode */
4027 #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
4028 #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
4029 #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
4030 
4031 /* Register: NFCT_TASKS_STARTTX */
4032 /* Description: Start transmission of an outgoing frame, change state to transmit */
4033 
4034 /* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
4035 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
4036 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
4037 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
4038 
4039 /* Register: NFCT_TASKS_ENABLERXDATA */
4040 /* Description: Initializes the EasyDMA for receive. */
4041 
4042 /* Bit 0 : Initializes the EasyDMA for receive. */
4043 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
4044 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
4045 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
4046 
4047 /* Register: NFCT_TASKS_GOIDLE */
4048 /* Description: Force state machine to IDLE state */
4049 
4050 /* Bit 0 : Force state machine to IDLE state */
4051 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
4052 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
4053 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
4054 
4055 /* Register: NFCT_TASKS_GOSLEEP */
4056 /* Description: Force state machine to SLEEP_A state */
4057 
4058 /* Bit 0 : Force state machine to SLEEP_A state */
4059 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
4060 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
4061 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
4062 
4063 /* Register: NFCT_EVENTS_READY */
4064 /* Description: The NFCT peripheral is ready to receive and send frames */
4065 
4066 /* Bit 0 : The NFCT peripheral is ready to receive and send frames */
4067 #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
4068 #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
4069 #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
4070 #define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
4071 
4072 /* Register: NFCT_EVENTS_FIELDDETECTED */
4073 /* Description: Remote NFC field detected */
4074 
4075 /* Bit 0 : Remote NFC field detected */
4076 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
4077 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
4078 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
4079 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
4080 
4081 /* Register: NFCT_EVENTS_FIELDLOST */
4082 /* Description: Remote NFC field lost */
4083 
4084 /* Bit 0 : Remote NFC field lost */
4085 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
4086 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
4087 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
4088 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
4089 
4090 /* Register: NFCT_EVENTS_TXFRAMESTART */
4091 /* Description: Marks the start of the first symbol of a transmitted frame */
4092 
4093 /* Bit 0 : Marks the start of the first symbol of a transmitted frame */
4094 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
4095 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
4096 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4097 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
4098 
4099 /* Register: NFCT_EVENTS_TXFRAMEEND */
4100 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4101 
4102 /* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
4103 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
4104 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
4105 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4106 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
4107 
4108 /* Register: NFCT_EVENTS_RXFRAMESTART */
4109 /* Description: Marks the end of the first symbol of a received frame */
4110 
4111 /* Bit 0 : Marks the end of the first symbol of a received frame */
4112 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
4113 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
4114 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4115 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
4116 
4117 /* Register: NFCT_EVENTS_RXFRAMEEND */
4118 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4119 
4120 /* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4121 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
4122 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
4123 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4124 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
4125 
4126 /* Register: NFCT_EVENTS_ERROR */
4127 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4128 
4129 /* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4130 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
4131 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
4132 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
4133 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
4134 
4135 /* Register: NFCT_EVENTS_RXERROR */
4136 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4137 
4138 /* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4139 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
4140 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
4141 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
4142 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
4143 
4144 /* Register: NFCT_EVENTS_ENDRX */
4145 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4146 
4147 /* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4148 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
4149 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
4150 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
4151 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
4152 
4153 /* Register: NFCT_EVENTS_ENDTX */
4154 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4155 
4156 /* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4157 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
4158 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
4159 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
4160 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
4161 
4162 /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
4163 /* Description: Auto collision resolution process has started */
4164 
4165 /* Bit 0 : Auto collision resolution process has started */
4166 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
4167 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
4168 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
4169 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
4170 
4171 /* Register: NFCT_EVENTS_COLLISION */
4172 /* Description: NFC auto collision resolution error reported. */
4173 
4174 /* Bit 0 : NFC auto collision resolution error reported. */
4175 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
4176 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
4177 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
4178 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
4179 
4180 /* Register: NFCT_EVENTS_SELECTED */
4181 /* Description: NFC auto collision resolution successfully completed */
4182 
4183 /* Bit 0 : NFC auto collision resolution successfully completed */
4184 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
4185 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
4186 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
4187 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
4188 
4189 /* Register: NFCT_EVENTS_STARTED */
4190 /* Description: EasyDMA is ready to receive or send frames. */
4191 
4192 /* Bit 0 : EasyDMA is ready to receive or send frames. */
4193 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
4194 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
4195 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
4196 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4197 
4198 /* Register: NFCT_SHORTS */
4199 /* Description: Shortcuts between local events and tasks */
4200 
4201 /* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
4202 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
4203 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
4204 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
4205 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
4206 
4207 /* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
4208 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4209 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4210 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4211 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4212 
4213 /* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
4214 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4215 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4216 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4217 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4218 
4219 /* Register: NFCT_INTEN */
4220 /* Description: Enable or disable interrupt */
4221 
4222 /* Bit 20 : Enable or disable interrupt for event STARTED */
4223 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4224 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4225 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4226 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4227 
4228 /* Bit 19 : Enable or disable interrupt for event SELECTED */
4229 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4230 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4231 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4232 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4233 
4234 /* Bit 18 : Enable or disable interrupt for event COLLISION */
4235 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4236 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4237 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4238 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4239 
4240 /* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
4241 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4242 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4243 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4244 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4245 
4246 /* Bit 12 : Enable or disable interrupt for event ENDTX */
4247 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4248 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4249 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4250 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4251 
4252 /* Bit 11 : Enable or disable interrupt for event ENDRX */
4253 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4254 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4255 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4256 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4257 
4258 /* Bit 10 : Enable or disable interrupt for event RXERROR */
4259 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4260 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4261 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4262 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4263 
4264 /* Bit 7 : Enable or disable interrupt for event ERROR */
4265 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4266 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4267 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4268 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4269 
4270 /* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
4271 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4272 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4273 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4274 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4275 
4276 /* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
4277 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4278 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4279 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4280 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4281 
4282 /* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
4283 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4284 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4285 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4286 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4287 
4288 /* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
4289 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4290 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4291 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4292 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4293 
4294 /* Bit 2 : Enable or disable interrupt for event FIELDLOST */
4295 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4296 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4297 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4298 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4299 
4300 /* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
4301 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4302 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4303 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4304 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4305 
4306 /* Bit 0 : Enable or disable interrupt for event READY */
4307 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4308 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4309 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4310 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4311 
4312 /* Register: NFCT_INTENSET */
4313 /* Description: Enable interrupt */
4314 
4315 /* Bit 20 : Write '1' to enable interrupt for event STARTED */
4316 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4317 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4318 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4319 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4320 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4321 
4322 /* Bit 19 : Write '1' to enable interrupt for event SELECTED */
4323 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4324 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4325 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4326 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4327 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4328 
4329 /* Bit 18 : Write '1' to enable interrupt for event COLLISION */
4330 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4331 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4332 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4333 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4334 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4335 
4336 /* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
4337 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4338 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4339 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4340 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4341 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4342 
4343 /* Bit 12 : Write '1' to enable interrupt for event ENDTX */
4344 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4345 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4346 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4347 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4348 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4349 
4350 /* Bit 11 : Write '1' to enable interrupt for event ENDRX */
4351 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4352 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4353 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4354 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4355 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4356 
4357 /* Bit 10 : Write '1' to enable interrupt for event RXERROR */
4358 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4359 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4360 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4361 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4362 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4363 
4364 /* Bit 7 : Write '1' to enable interrupt for event ERROR */
4365 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4366 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
4367 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4368 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4369 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4370 
4371 /* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
4372 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4373 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4374 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4375 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4376 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4377 
4378 /* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
4379 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4380 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4381 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4382 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4383 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4384 
4385 /* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
4386 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4387 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4388 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4389 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4390 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4391 
4392 /* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
4393 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4394 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4395 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4396 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4397 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4398 
4399 /* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
4400 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4401 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4402 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4403 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4404 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4405 
4406 /* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
4407 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4408 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4409 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4410 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4411 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4412 
4413 /* Bit 0 : Write '1' to enable interrupt for event READY */
4414 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4415 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4416 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4417 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4418 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4419 
4420 /* Register: NFCT_INTENCLR */
4421 /* Description: Disable interrupt */
4422 
4423 /* Bit 20 : Write '1' to disable interrupt for event STARTED */
4424 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4425 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4426 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4427 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4428 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4429 
4430 /* Bit 19 : Write '1' to disable interrupt for event SELECTED */
4431 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4432 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4433 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4434 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4435 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4436 
4437 /* Bit 18 : Write '1' to disable interrupt for event COLLISION */
4438 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4439 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4440 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4441 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4442 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4443 
4444 /* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
4445 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4446 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4447 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4448 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4449 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4450 
4451 /* Bit 12 : Write '1' to disable interrupt for event ENDTX */
4452 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4453 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4454 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4455 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4456 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4457 
4458 /* Bit 11 : Write '1' to disable interrupt for event ENDRX */
4459 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4460 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4461 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4462 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4463 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4464 
4465 /* Bit 10 : Write '1' to disable interrupt for event RXERROR */
4466 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4467 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4468 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4469 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4470 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4471 
4472 /* Bit 7 : Write '1' to disable interrupt for event ERROR */
4473 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4474 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
4475 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4476 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4477 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4478 
4479 /* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
4480 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4481 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4482 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4483 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4484 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4485 
4486 /* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
4487 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4488 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4489 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4490 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4491 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4492 
4493 /* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
4494 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4495 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4496 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4497 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4498 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4499 
4500 /* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
4501 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4502 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4503 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4504 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4505 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4506 
4507 /* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
4508 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4509 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4510 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4511 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4512 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4513 
4514 /* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
4515 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4516 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4517 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4518 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4519 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4520 
4521 /* Bit 0 : Write '1' to disable interrupt for event READY */
4522 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4523 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4524 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4525 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4526 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4527 
4528 /* Register: NFCT_ERRORSTATUS */
4529 /* Description: NFC Error Status register */
4530 
4531 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
4532 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
4533 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
4534 
4535 /* Register: NFCT_FRAMESTATUS_RX */
4536 /* Description: Result of last incoming frame */
4537 
4538 /* Bit 3 : Overrun detected */
4539 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
4540 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
4541 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
4542 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4543 
4544 /* Bit 2 : Parity status of received frame */
4545 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4546 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
4547 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
4548 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4549 
4550 /* Bit 0 : No valid end of frame (EoF) detected */
4551 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
4552 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
4553 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
4554 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4555 
4556 /* Register: NFCT_NFCTAGSTATE */
4557 /* Description: NfcTag state register */
4558 
4559 /* Bits 2..0 : NfcTag state */
4560 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
4561 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
4562 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
4563 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
4564 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
4565 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
4566 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
4567 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
4568 
4569 /* Register: NFCT_SLEEPSTATE */
4570 /* Description: Sleep state during automatic collision resolution */
4571 
4572 /* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
4573         by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
4574         GOSLEEP task. */
4575 #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
4576 #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
4577 #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */
4578 #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */
4579 
4580 /* Register: NFCT_FIELDPRESENT */
4581 /* Description: Indicates the presence or not of a valid field */
4582 
4583 /* Bit 1 : Indicates if the low level has locked to the field */
4584 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4585 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
4586 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
4587 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4588 
4589 /* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
4590 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
4591 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
4592 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
4593 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4594 
4595 /* Register: NFCT_FRAMEDELAYMIN */
4596 /* Description: Minimum frame delay */
4597 
4598 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
4599 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
4600 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
4601 
4602 /* Register: NFCT_FRAMEDELAYMAX */
4603 /* Description: Maximum frame delay */
4604 
4605 /* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */
4606 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
4607 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
4608 
4609 /* Register: NFCT_FRAMEDELAYMODE */
4610 /* Description: Configuration register for the Frame Delay Timer */
4611 
4612 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
4613 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
4614 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
4615 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
4616 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
4617 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
4618 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
4619 
4620 /* Register: NFCT_PACKETPTR */
4621 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4622 
4623 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
4624 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4625 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
4626 
4627 /* Register: NFCT_MAXLEN */
4628 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
4629 
4630 /* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
4631 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4632 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4633 
4634 /* Register: NFCT_TXD_FRAMECONFIG */
4635 /* Description: Configuration of outgoing frames */
4636 
4637 /* Bit 4 : CRC mode for outgoing frames */
4638 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
4639 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
4640 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
4641 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
4642 
4643 /* Bit 2 : Adding SoF or not in TX frames */
4644 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4645 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4646 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
4647 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
4648 
4649 /* Bit 1 : Discarding unused bits at start or end of a frame */
4650 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4651 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
4652 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
4653 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
4654 
4655 /* Bit 0 : Indicates if parity is added to the frame */
4656 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4657 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4658 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
4659 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
4660 
4661 /* Register: NFCT_TXD_AMOUNT */
4662 /* Description: Size of outgoing frame */
4663 
4664 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
4665 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
4666 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
4667 
4668 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
4669 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
4670 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
4671 
4672 /* Register: NFCT_RXD_FRAMECONFIG */
4673 /* Description: Configuration of incoming frames */
4674 
4675 /* Bit 4 : CRC mode for incoming frames */
4676 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
4677 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
4678 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
4679 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
4680 
4681 /* Bit 2 : SoF expected or not in RX frames */
4682 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4683 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4684 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
4685 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
4686 
4687 /* Bit 0 : Indicates if parity expected in RX frame */
4688 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4689 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4690 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
4691 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4692 
4693 /* Register: NFCT_RXD_AMOUNT */
4694 /* Description: Size of last incoming frame */
4695 
4696 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
4697 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
4698 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
4699 
4700 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
4701 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
4702 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
4703 
4704 /* Register: NFCT_MODULATIONCTRL */
4705 /* Description: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */
4706 
4707 /* Bits 1..0 : Configuration of modulation control. */
4708 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field. */
4709 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of MODULATIONCTRL field. */
4710 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal */
4711 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only */
4712 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin. */
4713 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital modulation signal to a GPIO pin. */
4714 
4715 /* Register: NFCT_MODULATIONPSEL */
4716 /* Description: Pin select for Modulation control. */
4717 
4718 /* Bit 31 : Connection */
4719 #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4720 #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4721 #define NFCT_MODULATIONPSEL_CONNECT_Connected (0UL) /*!< Connect */
4722 #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (1UL) /*!< Disconnect */
4723 
4724 /* Bit 5 : Port number */
4725 #define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */
4726 #define NFCT_MODULATIONPSEL_PORT_Msk (0x1UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */
4727 
4728 /* Bits 4..0 : Pin number */
4729 #define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */
4730 #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field. */
4731 
4732 /* Register: NFCT_NFCID1_LAST */
4733 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4734 
4735 /* Bits 31..24 : NFCID1 byte W */
4736 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
4737 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
4738 
4739 /* Bits 23..16 : NFCID1 byte X */
4740 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
4741 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
4742 
4743 /* Bits 15..8 : NFCID1 byte Y */
4744 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
4745 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
4746 
4747 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
4748 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
4749 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
4750 
4751 /* Register: NFCT_NFCID1_2ND_LAST */
4752 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4753 
4754 /* Bits 23..16 : NFCID1 byte T */
4755 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
4756 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
4757 
4758 /* Bits 15..8 : NFCID1 byte U */
4759 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
4760 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
4761 
4762 /* Bits 7..0 : NFCID1 byte V */
4763 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
4764 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
4765 
4766 /* Register: NFCT_NFCID1_3RD_LAST */
4767 /* Description: Third last NFCID1 part (10 bytes ID) */
4768 
4769 /* Bits 23..16 : NFCID1 byte Q */
4770 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
4771 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
4772 
4773 /* Bits 15..8 : NFCID1 byte R */
4774 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
4775 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
4776 
4777 /* Bits 7..0 : NFCID1 byte S */
4778 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
4779 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
4780 
4781 /* Register: NFCT_AUTOCOLRESCONFIG */
4782 /* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */
4783 
4784 /* Bit 0 : Enables/disables auto collision resolution */
4785 #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
4786 #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
4787 #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
4788 #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
4789 
4790 /* Register: NFCT_SENSRES */
4791 /* Description: NFC-A SENS_RES auto-response settings */
4792 
4793 /* Bits 15..12 : Reserved for future use. Shall be 0. */
4794 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
4795 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
4796 
4797 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4798 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
4799 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
4800 
4801 /* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
4802 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
4803 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
4804 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
4805 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4806 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4807 
4808 /* Bit 5 : Reserved for future use. Shall be 0. */
4809 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
4810 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
4811 
4812 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4813 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
4814 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
4815 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
4816 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4817 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4818 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
4819 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
4820 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
4821 
4822 /* Register: NFCT_SELRES */
4823 /* Description: NFC-A SEL_RES auto-response settings */
4824 
4825 /* Bit 7 : Reserved for future use. Shall be 0. */
4826 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
4827 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
4828 
4829 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4830 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
4831 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
4832 
4833 /* Bits 4..3 : Reserved for future use. Shall be 0. */
4834 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
4835 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
4836 
4837 /* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
4838 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4839 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
4840 
4841 /* Bits 1..0 : Reserved for future use. Shall be 0. */
4842 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
4843 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
4844 
4845 
4846 /* Peripheral: NVMC */
4847 /* Description: Non Volatile Memory Controller */
4848 
4849 /* Register: NVMC_READY */
4850 /* Description: Ready flag */
4851 
4852 /* Bit 0 : NVMC is ready or busy */
4853 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4854 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4855 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4856 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4857 
4858 /* Register: NVMC_READYNEXT */
4859 /* Description: Ready flag */
4860 
4861 /* Bit 0 : NVMC can accept a new write operation */
4862 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
4863 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
4864 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
4865 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
4866 
4867 /* Register: NVMC_CONFIG */
4868 /* Description: Configuration register */
4869 
4870 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4871 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4872 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4873 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4874 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
4875 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4876 
4877 /* Register: NVMC_ERASEPAGE */
4878 /* Description: Register for erasing a page in code area */
4879 
4880 /* Bits 31..0 : Register for starting erase of a page in code area */
4881 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
4882 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
4883 
4884 /* Register: NVMC_ERASEPCR1 */
4885 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
4886 
4887 /* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */
4888 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
4889 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
4890 
4891 /* Register: NVMC_ERASEALL */
4892 /* Description: Register for erasing all non-volatile user memory */
4893 
4894 /* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
4895 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
4896 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
4897 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
4898 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4899 
4900 /* Register: NVMC_ERASEPCR0 */
4901 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
4902 
4903 /* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */
4904 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
4905 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
4906 
4907 /* Register: NVMC_ERASEUICR */
4908 /* Description: Register for erasing user information configuration registers */
4909 
4910 /* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */
4911 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
4912 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
4913 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
4914 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
4915 
4916 /* Register: NVMC_ERASEPAGEPARTIAL */
4917 /* Description: Register for partial erase of a page in code area */
4918 
4919 /* Bits 31..0 : Register for starting partial erase of a page in code area */
4920 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
4921 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
4922 
4923 /* Register: NVMC_ERASEPAGEPARTIALCFG */
4924 /* Description: Register for partial erase configuration */
4925 
4926 /* Bits 6..0 : Duration of the partial erase in milliseconds */
4927 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
4928 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
4929 
4930 /* Register: NVMC_ICACHECNF */
4931 /* Description: I-code cache configuration register */
4932 
4933 /* Bit 8 : Cache profiling enable */
4934 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
4935 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
4936 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4937 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4938 
4939 /* Bit 0 : Cache enable */
4940 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
4941 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
4942 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4943 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4944 
4945 /* Register: NVMC_IHIT */
4946 /* Description: I-code cache hit counter */
4947 
4948 /* Bits 31..0 : Number of cache hits. Register is writable, but only to '0'. */
4949 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
4950 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
4951 
4952 /* Register: NVMC_IMISS */
4953 /* Description: I-code cache miss counter */
4954 
4955 /* Bits 31..0 : Number of cache misses. Register is writable, but only to '0'. */
4956 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
4957 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
4958 
4959 
4960 /* Peripheral: GPIO */
4961 /* Description: GPIO Port 1 */
4962 
4963 /* Register: GPIO_OUT */
4964 /* Description: Write GPIO port */
4965 
4966 /* Bit 31 : Pin 31 */
4967 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4968 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4969 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
4970 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4971 
4972 /* Bit 30 : Pin 30 */
4973 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4974 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4975 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
4976 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4977 
4978 /* Bit 29 : Pin 29 */
4979 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4980 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4981 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
4982 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4983 
4984 /* Bit 28 : Pin 28 */
4985 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4986 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4987 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
4988 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4989 
4990 /* Bit 27 : Pin 27 */
4991 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4992 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4993 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
4994 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4995 
4996 /* Bit 26 : Pin 26 */
4997 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4998 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4999 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
5000 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
5001 
5002 /* Bit 25 : Pin 25 */
5003 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5004 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5005 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
5006 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
5007 
5008 /* Bit 24 : Pin 24 */
5009 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5010 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5011 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
5012 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
5013 
5014 /* Bit 23 : Pin 23 */
5015 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5016 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5017 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
5018 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
5019 
5020 /* Bit 22 : Pin 22 */
5021 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5022 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5023 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
5024 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
5025 
5026 /* Bit 21 : Pin 21 */
5027 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5028 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5029 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
5030 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
5031 
5032 /* Bit 20 : Pin 20 */
5033 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5034 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5035 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
5036 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
5037 
5038 /* Bit 19 : Pin 19 */
5039 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5040 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5041 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
5042 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
5043 
5044 /* Bit 18 : Pin 18 */
5045 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5046 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5047 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
5048 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
5049 
5050 /* Bit 17 : Pin 17 */
5051 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5052 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5053 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
5054 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
5055 
5056 /* Bit 16 : Pin 16 */
5057 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5058 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5059 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
5060 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
5061 
5062 /* Bit 15 : Pin 15 */
5063 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5064 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5065 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
5066 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
5067 
5068 /* Bit 14 : Pin 14 */
5069 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5070 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5071 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
5072 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
5073 
5074 /* Bit 13 : Pin 13 */
5075 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5076 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5077 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
5078 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
5079 
5080 /* Bit 12 : Pin 12 */
5081 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5082 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5083 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
5084 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
5085 
5086 /* Bit 11 : Pin 11 */
5087 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5088 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5089 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
5090 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
5091 
5092 /* Bit 10 : Pin 10 */
5093 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5094 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5095 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
5096 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
5097 
5098 /* Bit 9 : Pin 9 */
5099 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5100 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5101 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
5102 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
5103 
5104 /* Bit 8 : Pin 8 */
5105 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5106 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5107 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
5108 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
5109 
5110 /* Bit 7 : Pin 7 */
5111 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5112 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5113 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
5114 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
5115 
5116 /* Bit 6 : Pin 6 */
5117 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5118 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5119 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
5120 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
5121 
5122 /* Bit 5 : Pin 5 */
5123 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5124 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5125 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
5126 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5127 
5128 /* Bit 4 : Pin 4 */
5129 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5130 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5131 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5132 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5133 
5134 /* Bit 3 : Pin 3 */
5135 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5136 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5137 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5138 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5139 
5140 /* Bit 2 : Pin 2 */
5141 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5142 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5143 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5144 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5145 
5146 /* Bit 1 : Pin 1 */
5147 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5148 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5149 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5150 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5151 
5152 /* Bit 0 : Pin 0 */
5153 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5154 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5155 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5156 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5157 
5158 /* Register: GPIO_OUTSET */
5159 /* Description: Set individual bits in GPIO port */
5160 
5161 /* Bit 31 : Pin 31 */
5162 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5163 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5164 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5165 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5166 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5167 
5168 /* Bit 30 : Pin 30 */
5169 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5170 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5171 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5172 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5173 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5174 
5175 /* Bit 29 : Pin 29 */
5176 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5177 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5178 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5179 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5180 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5181 
5182 /* Bit 28 : Pin 28 */
5183 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5184 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5185 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5186 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5187 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5188 
5189 /* Bit 27 : Pin 27 */
5190 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5191 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5192 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5193 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5194 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5195 
5196 /* Bit 26 : Pin 26 */
5197 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5198 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5199 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5200 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5201 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5202 
5203 /* Bit 25 : Pin 25 */
5204 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5205 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5206 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5207 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5208 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5209 
5210 /* Bit 24 : Pin 24 */
5211 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5212 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5213 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5214 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5215 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5216 
5217 /* Bit 23 : Pin 23 */
5218 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5219 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5220 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5221 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5222 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5223 
5224 /* Bit 22 : Pin 22 */
5225 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5226 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5227 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5228 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5229 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5230 
5231 /* Bit 21 : Pin 21 */
5232 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5233 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5234 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5235 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5236 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5237 
5238 /* Bit 20 : Pin 20 */
5239 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5240 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5241 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5242 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5243 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5244 
5245 /* Bit 19 : Pin 19 */
5246 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5247 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5248 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5249 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5250 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5251 
5252 /* Bit 18 : Pin 18 */
5253 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5254 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5255 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5256 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5257 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5258 
5259 /* Bit 17 : Pin 17 */
5260 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5261 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5262 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5263 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5264 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5265 
5266 /* Bit 16 : Pin 16 */
5267 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5268 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5269 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5270 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5271 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5272 
5273 /* Bit 15 : Pin 15 */
5274 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5275 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5276 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5277 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5278 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5279 
5280 /* Bit 14 : Pin 14 */
5281 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5282 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5283 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5284 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5285 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5286 
5287 /* Bit 13 : Pin 13 */
5288 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5289 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5290 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5291 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5292 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5293 
5294 /* Bit 12 : Pin 12 */
5295 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5296 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5297 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5298 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5299 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5300 
5301 /* Bit 11 : Pin 11 */
5302 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5303 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5304 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5305 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5306 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5307 
5308 /* Bit 10 : Pin 10 */
5309 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5310 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5311 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5312 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5313 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5314 
5315 /* Bit 9 : Pin 9 */
5316 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5317 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5318 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5319 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5320 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5321 
5322 /* Bit 8 : Pin 8 */
5323 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5324 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5325 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5326 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5327 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5328 
5329 /* Bit 7 : Pin 7 */
5330 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5331 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5332 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5333 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5334 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5335 
5336 /* Bit 6 : Pin 6 */
5337 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5338 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5339 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5340 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5341 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5342 
5343 /* Bit 5 : Pin 5 */
5344 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5345 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5346 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5347 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5348 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5349 
5350 /* Bit 4 : Pin 4 */
5351 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5352 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5353 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5354 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5355 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5356 
5357 /* Bit 3 : Pin 3 */
5358 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5359 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5360 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5361 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5362 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5363 
5364 /* Bit 2 : Pin 2 */
5365 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5366 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5367 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5368 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5369 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5370 
5371 /* Bit 1 : Pin 1 */
5372 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5373 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5374 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5375 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5376 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5377 
5378 /* Bit 0 : Pin 0 */
5379 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5380 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5381 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5382 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5383 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5384 
5385 /* Register: GPIO_OUTCLR */
5386 /* Description: Clear individual bits in GPIO port */
5387 
5388 /* Bit 31 : Pin 31 */
5389 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5390 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5391 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5392 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5393 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5394 
5395 /* Bit 30 : Pin 30 */
5396 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5397 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5398 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5399 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5400 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5401 
5402 /* Bit 29 : Pin 29 */
5403 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5404 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5405 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5406 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5407 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5408 
5409 /* Bit 28 : Pin 28 */
5410 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5411 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5412 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5413 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5414 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5415 
5416 /* Bit 27 : Pin 27 */
5417 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5418 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5419 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5420 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5421 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5422 
5423 /* Bit 26 : Pin 26 */
5424 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5425 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5426 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5427 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5428 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5429 
5430 /* Bit 25 : Pin 25 */
5431 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5432 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5433 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5434 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5435 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5436 
5437 /* Bit 24 : Pin 24 */
5438 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5439 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5440 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5441 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5442 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5443 
5444 /* Bit 23 : Pin 23 */
5445 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5446 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5447 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5448 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5449 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5450 
5451 /* Bit 22 : Pin 22 */
5452 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5453 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5454 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5455 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5456 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5457 
5458 /* Bit 21 : Pin 21 */
5459 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5460 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5461 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5462 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5463 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5464 
5465 /* Bit 20 : Pin 20 */
5466 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5467 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5468 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5469 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5470 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5471 
5472 /* Bit 19 : Pin 19 */
5473 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5474 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5475 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5476 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5477 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5478 
5479 /* Bit 18 : Pin 18 */
5480 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5481 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5482 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5483 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5484 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5485 
5486 /* Bit 17 : Pin 17 */
5487 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5488 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5489 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5490 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5491 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5492 
5493 /* Bit 16 : Pin 16 */
5494 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5495 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5496 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5497 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5498 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5499 
5500 /* Bit 15 : Pin 15 */
5501 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5502 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5503 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5504 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5505 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5506 
5507 /* Bit 14 : Pin 14 */
5508 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5509 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5510 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5511 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5512 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5513 
5514 /* Bit 13 : Pin 13 */
5515 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5516 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5517 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5518 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5519 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5520 
5521 /* Bit 12 : Pin 12 */
5522 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5523 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5524 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5525 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5526 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5527 
5528 /* Bit 11 : Pin 11 */
5529 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5530 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5531 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5532 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5533 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5534 
5535 /* Bit 10 : Pin 10 */
5536 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5537 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5538 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5539 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5540 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5541 
5542 /* Bit 9 : Pin 9 */
5543 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5544 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5545 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5546 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5547 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5548 
5549 /* Bit 8 : Pin 8 */
5550 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5551 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5552 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5553 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5554 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5555 
5556 /* Bit 7 : Pin 7 */
5557 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5558 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5559 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5560 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5561 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5562 
5563 /* Bit 6 : Pin 6 */
5564 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5565 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5566 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5567 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5568 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5569 
5570 /* Bit 5 : Pin 5 */
5571 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5572 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5573 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5574 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5575 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5576 
5577 /* Bit 4 : Pin 4 */
5578 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5579 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5580 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5581 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5582 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5583 
5584 /* Bit 3 : Pin 3 */
5585 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5586 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5587 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5588 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5589 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5590 
5591 /* Bit 2 : Pin 2 */
5592 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5593 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5594 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5595 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5596 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5597 
5598 /* Bit 1 : Pin 1 */
5599 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5600 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5601 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5602 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5603 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5604 
5605 /* Bit 0 : Pin 0 */
5606 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5607 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5608 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5609 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5610 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5611 
5612 /* Register: GPIO_IN */
5613 /* Description: Read GPIO port */
5614 
5615 /* Bit 31 : Pin 31 */
5616 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5617 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5618 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
5619 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5620 
5621 /* Bit 30 : Pin 30 */
5622 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5623 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5624 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
5625 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5626 
5627 /* Bit 29 : Pin 29 */
5628 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5629 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5630 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
5631 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5632 
5633 /* Bit 28 : Pin 28 */
5634 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5635 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5636 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
5637 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5638 
5639 /* Bit 27 : Pin 27 */
5640 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5641 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5642 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
5643 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5644 
5645 /* Bit 26 : Pin 26 */
5646 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5647 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5648 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
5649 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5650 
5651 /* Bit 25 : Pin 25 */
5652 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5653 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5654 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
5655 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5656 
5657 /* Bit 24 : Pin 24 */
5658 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5659 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5660 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
5661 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5662 
5663 /* Bit 23 : Pin 23 */
5664 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5665 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5666 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
5667 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5668 
5669 /* Bit 22 : Pin 22 */
5670 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5671 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5672 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
5673 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5674 
5675 /* Bit 21 : Pin 21 */
5676 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5677 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5678 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
5679 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5680 
5681 /* Bit 20 : Pin 20 */
5682 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5683 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5684 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
5685 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5686 
5687 /* Bit 19 : Pin 19 */
5688 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5689 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5690 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
5691 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5692 
5693 /* Bit 18 : Pin 18 */
5694 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5695 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5696 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
5697 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5698 
5699 /* Bit 17 : Pin 17 */
5700 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5701 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5702 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
5703 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5704 
5705 /* Bit 16 : Pin 16 */
5706 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5707 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5708 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
5709 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5710 
5711 /* Bit 15 : Pin 15 */
5712 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5713 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5714 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
5715 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5716 
5717 /* Bit 14 : Pin 14 */
5718 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5719 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5720 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
5721 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5722 
5723 /* Bit 13 : Pin 13 */
5724 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5725 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5726 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
5727 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5728 
5729 /* Bit 12 : Pin 12 */
5730 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5731 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5732 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
5733 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5734 
5735 /* Bit 11 : Pin 11 */
5736 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5737 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5738 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
5739 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5740 
5741 /* Bit 10 : Pin 10 */
5742 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5743 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5744 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
5745 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5746 
5747 /* Bit 9 : Pin 9 */
5748 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5749 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5750 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
5751 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5752 
5753 /* Bit 8 : Pin 8 */
5754 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5755 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5756 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
5757 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5758 
5759 /* Bit 7 : Pin 7 */
5760 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5761 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5762 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
5763 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5764 
5765 /* Bit 6 : Pin 6 */
5766 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5767 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5768 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
5769 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5770 
5771 /* Bit 5 : Pin 5 */
5772 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5773 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5774 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
5775 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5776 
5777 /* Bit 4 : Pin 4 */
5778 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5779 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5780 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
5781 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5782 
5783 /* Bit 3 : Pin 3 */
5784 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5785 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5786 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
5787 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5788 
5789 /* Bit 2 : Pin 2 */
5790 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5791 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5792 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
5793 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5794 
5795 /* Bit 1 : Pin 1 */
5796 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5797 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5798 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
5799 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5800 
5801 /* Bit 0 : Pin 0 */
5802 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5803 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5804 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
5805 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5806 
5807 /* Register: GPIO_DIR */
5808 /* Description: Direction of GPIO pins */
5809 
5810 /* Bit 31 : Pin 31 */
5811 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5812 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5813 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
5814 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5815 
5816 /* Bit 30 : Pin 30 */
5817 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5818 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5819 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5820 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5821 
5822 /* Bit 29 : Pin 29 */
5823 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5824 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5825 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5826 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5827 
5828 /* Bit 28 : Pin 28 */
5829 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5830 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5831 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5832 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5833 
5834 /* Bit 27 : Pin 27 */
5835 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5836 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5837 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5838 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5839 
5840 /* Bit 26 : Pin 26 */
5841 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5842 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5843 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5844 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5845 
5846 /* Bit 25 : Pin 25 */
5847 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5848 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5849 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5850 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5851 
5852 /* Bit 24 : Pin 24 */
5853 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5854 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5855 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5856 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5857 
5858 /* Bit 23 : Pin 23 */
5859 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5860 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5861 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5862 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5863 
5864 /* Bit 22 : Pin 22 */
5865 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5866 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5867 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5868 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5869 
5870 /* Bit 21 : Pin 21 */
5871 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5872 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5873 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5874 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5875 
5876 /* Bit 20 : Pin 20 */
5877 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5878 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5879 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5880 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5881 
5882 /* Bit 19 : Pin 19 */
5883 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5884 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5885 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
5886 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5887 
5888 /* Bit 18 : Pin 18 */
5889 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5890 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5891 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
5892 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5893 
5894 /* Bit 17 : Pin 17 */
5895 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5896 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5897 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
5898 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5899 
5900 /* Bit 16 : Pin 16 */
5901 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5902 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5903 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
5904 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5905 
5906 /* Bit 15 : Pin 15 */
5907 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5908 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5909 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
5910 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5911 
5912 /* Bit 14 : Pin 14 */
5913 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5914 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5915 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
5916 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5917 
5918 /* Bit 13 : Pin 13 */
5919 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5920 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5921 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
5922 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5923 
5924 /* Bit 12 : Pin 12 */
5925 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5926 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5927 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
5928 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5929 
5930 /* Bit 11 : Pin 11 */
5931 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5932 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5933 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
5934 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5935 
5936 /* Bit 10 : Pin 10 */
5937 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5938 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5939 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
5940 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5941 
5942 /* Bit 9 : Pin 9 */
5943 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5944 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5945 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
5946 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5947 
5948 /* Bit 8 : Pin 8 */
5949 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5950 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5951 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
5952 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5953 
5954 /* Bit 7 : Pin 7 */
5955 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5956 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5957 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
5958 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5959 
5960 /* Bit 6 : Pin 6 */
5961 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5962 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5963 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
5964 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5965 
5966 /* Bit 5 : Pin 5 */
5967 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5968 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5969 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
5970 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5971 
5972 /* Bit 4 : Pin 4 */
5973 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5974 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5975 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
5976 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5977 
5978 /* Bit 3 : Pin 3 */
5979 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5980 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5981 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
5982 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5983 
5984 /* Bit 2 : Pin 2 */
5985 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5986 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5987 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
5988 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5989 
5990 /* Bit 1 : Pin 1 */
5991 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5992 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5993 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
5994 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5995 
5996 /* Bit 0 : Pin 0 */
5997 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5998 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5999 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
6000 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
6001 
6002 /* Register: GPIO_DIRSET */
6003 /* Description: DIR set register */
6004 
6005 /* Bit 31 : Set as output pin 31 */
6006 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6007 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6008 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
6009 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
6010 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6011 
6012 /* Bit 30 : Set as output pin 30 */
6013 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6014 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6015 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
6016 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
6017 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6018 
6019 /* Bit 29 : Set as output pin 29 */
6020 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6021 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6022 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
6023 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
6024 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6025 
6026 /* Bit 28 : Set as output pin 28 */
6027 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6028 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6029 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
6030 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
6031 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6032 
6033 /* Bit 27 : Set as output pin 27 */
6034 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6035 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6036 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
6037 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
6038 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6039 
6040 /* Bit 26 : Set as output pin 26 */
6041 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6042 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6043 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
6044 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
6045 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6046 
6047 /* Bit 25 : Set as output pin 25 */
6048 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6049 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6050 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
6051 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
6052 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6053 
6054 /* Bit 24 : Set as output pin 24 */
6055 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6056 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6057 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
6058 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
6059 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6060 
6061 /* Bit 23 : Set as output pin 23 */
6062 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6063 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6064 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
6065 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
6066 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6067 
6068 /* Bit 22 : Set as output pin 22 */
6069 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6070 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6071 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
6072 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
6073 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6074 
6075 /* Bit 21 : Set as output pin 21 */
6076 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6077 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6078 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
6079 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
6080 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6081 
6082 /* Bit 20 : Set as output pin 20 */
6083 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6084 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6085 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
6086 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
6087 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6088 
6089 /* Bit 19 : Set as output pin 19 */
6090 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6091 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6092 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
6093 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
6094 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6095 
6096 /* Bit 18 : Set as output pin 18 */
6097 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6098 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6099 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
6100 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
6101 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6102 
6103 /* Bit 17 : Set as output pin 17 */
6104 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6105 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6106 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
6107 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
6108 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6109 
6110 /* Bit 16 : Set as output pin 16 */
6111 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6112 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6113 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
6114 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
6115 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6116 
6117 /* Bit 15 : Set as output pin 15 */
6118 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6119 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6120 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
6121 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
6122 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6123 
6124 /* Bit 14 : Set as output pin 14 */
6125 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6126 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6127 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
6128 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6129 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6130 
6131 /* Bit 13 : Set as output pin 13 */
6132 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6133 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6134 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6135 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6136 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6137 
6138 /* Bit 12 : Set as output pin 12 */
6139 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6140 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6141 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6142 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6143 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6144 
6145 /* Bit 11 : Set as output pin 11 */
6146 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6147 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6148 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6149 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6150 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6151 
6152 /* Bit 10 : Set as output pin 10 */
6153 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6154 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6155 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6156 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6157 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6158 
6159 /* Bit 9 : Set as output pin 9 */
6160 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6161 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6162 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6163 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6164 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6165 
6166 /* Bit 8 : Set as output pin 8 */
6167 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6168 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6169 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6170 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6171 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6172 
6173 /* Bit 7 : Set as output pin 7 */
6174 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6175 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6176 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6177 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6178 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6179 
6180 /* Bit 6 : Set as output pin 6 */
6181 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6182 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6183 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6184 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6185 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6186 
6187 /* Bit 5 : Set as output pin 5 */
6188 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6189 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6190 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6191 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6192 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6193 
6194 /* Bit 4 : Set as output pin 4 */
6195 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6196 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6197 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6198 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6199 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6200 
6201 /* Bit 3 : Set as output pin 3 */
6202 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6203 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6204 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6205 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6206 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6207 
6208 /* Bit 2 : Set as output pin 2 */
6209 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6210 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6211 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6212 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6213 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6214 
6215 /* Bit 1 : Set as output pin 1 */
6216 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6217 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6218 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6219 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6220 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6221 
6222 /* Bit 0 : Set as output pin 0 */
6223 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6224 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6225 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6226 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6227 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6228 
6229 /* Register: GPIO_DIRCLR */
6230 /* Description: DIR clear register */
6231 
6232 /* Bit 31 : Set as input pin 31 */
6233 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6234 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6235 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6236 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6237 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6238 
6239 /* Bit 30 : Set as input pin 30 */
6240 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6241 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6242 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6243 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6244 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6245 
6246 /* Bit 29 : Set as input pin 29 */
6247 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6248 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6249 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6250 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6251 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6252 
6253 /* Bit 28 : Set as input pin 28 */
6254 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6255 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6256 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6257 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6258 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6259 
6260 /* Bit 27 : Set as input pin 27 */
6261 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6262 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6263 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6264 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6265 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6266 
6267 /* Bit 26 : Set as input pin 26 */
6268 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6269 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6270 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6271 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6272 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6273 
6274 /* Bit 25 : Set as input pin 25 */
6275 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6276 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6277 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6278 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6279 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6280 
6281 /* Bit 24 : Set as input pin 24 */
6282 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6283 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6284 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6285 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6286 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6287 
6288 /* Bit 23 : Set as input pin 23 */
6289 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6290 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6291 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6292 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6293 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6294 
6295 /* Bit 22 : Set as input pin 22 */
6296 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6297 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6298 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6299 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6300 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6301 
6302 /* Bit 21 : Set as input pin 21 */
6303 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6304 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6305 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6306 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6307 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6308 
6309 /* Bit 20 : Set as input pin 20 */
6310 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6311 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6312 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6313 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6314 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6315 
6316 /* Bit 19 : Set as input pin 19 */
6317 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6318 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6319 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6320 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6321 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6322 
6323 /* Bit 18 : Set as input pin 18 */
6324 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6325 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6326 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6327 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6328 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6329 
6330 /* Bit 17 : Set as input pin 17 */
6331 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6332 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6333 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6334 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6335 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6336 
6337 /* Bit 16 : Set as input pin 16 */
6338 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6339 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6340 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6341 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6342 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6343 
6344 /* Bit 15 : Set as input pin 15 */
6345 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6346 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6347 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6348 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6349 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6350 
6351 /* Bit 14 : Set as input pin 14 */
6352 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6353 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6354 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6355 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6356 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6357 
6358 /* Bit 13 : Set as input pin 13 */
6359 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6360 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6361 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6362 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6363 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6364 
6365 /* Bit 12 : Set as input pin 12 */
6366 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6367 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6368 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6369 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6370 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6371 
6372 /* Bit 11 : Set as input pin 11 */
6373 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6374 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6375 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6376 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6377 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6378 
6379 /* Bit 10 : Set as input pin 10 */
6380 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6381 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6382 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6383 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6384 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6385 
6386 /* Bit 9 : Set as input pin 9 */
6387 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6388 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6389 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6390 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6391 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6392 
6393 /* Bit 8 : Set as input pin 8 */
6394 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6395 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6396 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6397 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6398 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6399 
6400 /* Bit 7 : Set as input pin 7 */
6401 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6402 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6403 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6404 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6405 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6406 
6407 /* Bit 6 : Set as input pin 6 */
6408 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6409 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6410 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6411 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6412 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6413 
6414 /* Bit 5 : Set as input pin 5 */
6415 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6416 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6417 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6418 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6419 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6420 
6421 /* Bit 4 : Set as input pin 4 */
6422 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6423 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6424 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6425 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6426 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6427 
6428 /* Bit 3 : Set as input pin 3 */
6429 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6430 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6431 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6432 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6433 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6434 
6435 /* Bit 2 : Set as input pin 2 */
6436 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6437 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6438 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6439 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6440 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6441 
6442 /* Bit 1 : Set as input pin 1 */
6443 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6444 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6445 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6446 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6447 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6448 
6449 /* Bit 0 : Set as input pin 0 */
6450 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6451 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6452 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6453 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6454 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6455 
6456 /* Register: GPIO_LATCH */
6457 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
6458 
6459 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
6460 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6461 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6462 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
6463 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6464 
6465 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
6466 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6467 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6468 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
6469 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6470 
6471 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
6472 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6473 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6474 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
6475 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6476 
6477 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
6478 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6479 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6480 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
6481 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6482 
6483 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
6484 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6485 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6486 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
6487 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6488 
6489 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
6490 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6491 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6492 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
6493 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6494 
6495 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
6496 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6497 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6498 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
6499 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6500 
6501 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
6502 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6503 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6504 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
6505 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6506 
6507 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
6508 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6509 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6510 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
6511 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6512 
6513 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
6514 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6515 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6516 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
6517 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6518 
6519 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
6520 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6521 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6522 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
6523 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6524 
6525 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
6526 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6527 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6528 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
6529 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6530 
6531 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
6532 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6533 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6534 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
6535 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6536 
6537 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
6538 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6539 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6540 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
6541 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6542 
6543 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
6544 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6545 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6546 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
6547 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6548 
6549 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
6550 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6551 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6552 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
6553 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6554 
6555 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
6556 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6557 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6558 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
6559 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6560 
6561 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
6562 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6563 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6564 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
6565 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6566 
6567 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
6568 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6569 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6570 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
6571 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6572 
6573 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
6574 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6575 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6576 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
6577 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6578 
6579 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
6580 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6581 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6582 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
6583 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6584 
6585 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
6586 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6587 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6588 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
6589 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6590 
6591 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
6592 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6593 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6594 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
6595 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6596 
6597 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
6598 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6599 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6600 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
6601 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6602 
6603 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
6604 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6605 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6606 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
6607 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6608 
6609 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
6610 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6611 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6612 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
6613 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6614 
6615 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
6616 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6617 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6618 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
6619 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6620 
6621 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
6622 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6623 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6624 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
6625 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6626 
6627 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
6628 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6629 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6630 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
6631 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6632 
6633 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
6634 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6635 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6636 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
6637 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6638 
6639 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
6640 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6641 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6642 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
6643 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6644 
6645 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
6646 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6647 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6648 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
6649 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6650 
6651 /* Register: GPIO_DETECTMODE */
6652 /* Description: Select between default DETECT signal behavior and LDETECT mode */
6653 
6654 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
6655 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
6656 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
6657 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
6658 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
6659 
6660 /* Register: GPIO_PIN_CNF */
6661 /* Description: Description collection: Configuration of GPIO pins */
6662 
6663 /* Bits 17..16 : Pin sensing mechanism */
6664 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
6665 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
6666 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6667 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6668 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
6669 
6670 /* Bits 10..8 : Drive configuration */
6671 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
6672 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
6673 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6674 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6675 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6676 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6677 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
6678 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
6679 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
6680 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
6681 
6682 /* Bits 3..2 : Pull configuration */
6683 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6684 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
6685 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
6686 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6687 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6688 
6689 /* Bit 1 : Connect or disconnect input buffer */
6690 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6691 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
6692 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
6693 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6694 
6695 /* Bit 0 : Pin direction. Same physical register as DIR register */
6696 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
6697 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
6698 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
6699 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6700 
6701 
6702 /* Peripheral: PDM */
6703 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
6704 
6705 /* Register: PDM_TASKS_START */
6706 /* Description: Starts continuous PDM transfer */
6707 
6708 /* Bit 0 : Starts continuous PDM transfer */
6709 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6710 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6711 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6712 
6713 /* Register: PDM_TASKS_STOP */
6714 /* Description: Stops PDM transfer */
6715 
6716 /* Bit 0 : Stops PDM transfer */
6717 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6718 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6719 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6720 
6721 /* Register: PDM_EVENTS_STARTED */
6722 /* Description: PDM transfer has started */
6723 
6724 /* Bit 0 : PDM transfer has started */
6725 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
6726 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
6727 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
6728 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6729 
6730 /* Register: PDM_EVENTS_STOPPED */
6731 /* Description: PDM transfer has finished */
6732 
6733 /* Bit 0 : PDM transfer has finished */
6734 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6735 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6736 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6737 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6738 
6739 /* Register: PDM_EVENTS_END */
6740 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
6741 
6742 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
6743 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6744 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6745 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6746 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6747 
6748 /* Register: PDM_INTEN */
6749 /* Description: Enable or disable interrupt */
6750 
6751 /* Bit 2 : Enable or disable interrupt for event END */
6752 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6753 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
6754 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6755 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6756 
6757 /* Bit 1 : Enable or disable interrupt for event STOPPED */
6758 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6759 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6760 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6761 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6762 
6763 /* Bit 0 : Enable or disable interrupt for event STARTED */
6764 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6765 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6766 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6767 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6768 
6769 /* Register: PDM_INTENSET */
6770 /* Description: Enable interrupt */
6771 
6772 /* Bit 2 : Write '1' to enable interrupt for event END */
6773 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6774 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6775 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6776 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6777 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6778 
6779 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
6780 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6781 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6782 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6783 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6784 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6785 
6786 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6787 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6788 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6789 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6790 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6791 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6792 
6793 /* Register: PDM_INTENCLR */
6794 /* Description: Disable interrupt */
6795 
6796 /* Bit 2 : Write '1' to disable interrupt for event END */
6797 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6798 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6799 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6800 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6801 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6802 
6803 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
6804 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6805 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6806 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6807 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6808 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6809 
6810 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6811 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6812 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6813 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6814 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6815 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6816 
6817 /* Register: PDM_ENABLE */
6818 /* Description: PDM module enable register */
6819 
6820 /* Bit 0 : Enable or disable PDM module */
6821 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6822 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6823 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6824 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6825 
6826 /* Register: PDM_PDMCLKCTRL */
6827 /* Description: PDM clock generator control */
6828 
6829 /* Bits 31..0 : PDM_CLK frequency configuration */
6830 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
6831 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
6832 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
6833 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
6834 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
6835 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
6836 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
6837 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
6838 
6839 /* Register: PDM_MODE */
6840 /* Description: Defines the routing of the connected PDM microphones' signals */
6841 
6842 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
6843 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6844 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
6845 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
6846 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6847 
6848 /* Bit 0 : Mono or stereo operation */
6849 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
6850 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
6851 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
6852 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
6853 
6854 /* Register: PDM_GAINL */
6855 /* Description: Left output gain adjustment */
6856 
6857 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
6858 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
6859 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
6860 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
6861 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
6862 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
6863 
6864 /* Register: PDM_GAINR */
6865 /* Description: Right output gain adjustment */
6866 
6867 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
6868 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
6869 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
6870 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
6871 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
6872 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
6873 
6874 /* Register: PDM_RATIO */
6875 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
6876 
6877 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
6878 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
6879 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
6880 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
6881 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
6882 
6883 /* Register: PDM_PSEL_CLK */
6884 /* Description: Pin number configuration for PDM CLK signal */
6885 
6886 /* Bit 31 : Connection */
6887 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6888 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6889 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
6890 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
6891 
6892 /* Bit 5 : Port number */
6893 #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
6894 #define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
6895 
6896 /* Bits 4..0 : Pin number */
6897 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
6898 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
6899 
6900 /* Register: PDM_PSEL_DIN */
6901 /* Description: Pin number configuration for PDM DIN signal */
6902 
6903 /* Bit 31 : Connection */
6904 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6905 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6906 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
6907 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
6908 
6909 /* Bit 5 : Port number */
6910 #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
6911 #define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
6912 
6913 /* Bits 4..0 : Pin number */
6914 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
6915 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
6916 
6917 /* Register: PDM_SAMPLE_PTR */
6918 /* Description: RAM address pointer to write samples to with EasyDMA */
6919 
6920 /* Bits 31..0 : Address to write PDM samples to over DMA */
6921 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
6922 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
6923 
6924 /* Register: PDM_SAMPLE_MAXCNT */
6925 /* Description: Number of samples to allocate memory for in EasyDMA mode */
6926 
6927 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
6928 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
6929 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
6930 
6931 
6932 /* Peripheral: POWER */
6933 /* Description: Power control */
6934 
6935 /* Register: POWER_TASKS_CONSTLAT */
6936 /* Description: Enable Constant Latency mode */
6937 
6938 /* Bit 0 : Enable Constant Latency mode */
6939 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
6940 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
6941 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
6942 
6943 /* Register: POWER_TASKS_LOWPWR */
6944 /* Description: Enable Low-power mode (variable latency) */
6945 
6946 /* Bit 0 : Enable Low-power mode (variable latency) */
6947 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
6948 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
6949 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
6950 
6951 /* Register: POWER_EVENTS_POFWARN */
6952 /* Description: Power failure warning */
6953 
6954 /* Bit 0 : Power failure warning */
6955 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
6956 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
6957 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
6958 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
6959 
6960 /* Register: POWER_EVENTS_SLEEPENTER */
6961 /* Description: CPU entered WFI/WFE sleep */
6962 
6963 /* Bit 0 : CPU entered WFI/WFE sleep */
6964 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
6965 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
6966 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
6967 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
6968 
6969 /* Register: POWER_EVENTS_SLEEPEXIT */
6970 /* Description: CPU exited WFI/WFE sleep */
6971 
6972 /* Bit 0 : CPU exited WFI/WFE sleep */
6973 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
6974 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
6975 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
6976 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
6977 
6978 /* Register: POWER_EVENTS_USBDETECTED */
6979 /* Description: Voltage supply detected on VBUS */
6980 
6981 /* Bit 0 : Voltage supply detected on VBUS */
6982 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
6983 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
6984 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */
6985 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */
6986 
6987 /* Register: POWER_EVENTS_USBREMOVED */
6988 /* Description: Voltage supply removed from VBUS */
6989 
6990 /* Bit 0 : Voltage supply removed from VBUS */
6991 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
6992 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
6993 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */
6994 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */
6995 
6996 /* Register: POWER_EVENTS_USBPWRRDY */
6997 /* Description: USB 3.3 V supply ready */
6998 
6999 /* Bit 0 : USB 3.3 V supply ready */
7000 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
7001 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
7002 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */
7003 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */
7004 
7005 /* Register: POWER_INTENSET */
7006 /* Description: Enable interrupt */
7007 
7008 /* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */
7009 #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
7010 #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
7011 #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
7012 #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
7013 #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
7014 
7015 /* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */
7016 #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
7017 #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
7018 #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
7019 #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7020 #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
7021 
7022 /* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */
7023 #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
7024 #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
7025 #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7026 #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7027 #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
7028 
7029 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
7030 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7031 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7032 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7033 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7034 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
7035 
7036 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
7037 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7038 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7039 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7040 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7041 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
7042 
7043 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
7044 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7045 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7046 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7047 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7048 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
7049 
7050 /* Register: POWER_INTENCLR */
7051 /* Description: Disable interrupt */
7052 
7053 /* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */
7054 #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
7055 #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
7056 #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
7057 #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
7058 #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
7059 
7060 /* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */
7061 #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
7062 #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
7063 #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
7064 #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7065 #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
7066 
7067 /* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */
7068 #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
7069 #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
7070 #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7071 #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7072 #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
7073 
7074 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
7075 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7076 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7077 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7078 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7079 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
7080 
7081 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
7082 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7083 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7084 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7085 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7086 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
7087 
7088 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
7089 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7090 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7091 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7092 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7093 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
7094 
7095 /* Register: POWER_RESETREAS */
7096 /* Description: Reset reason */
7097 
7098 /* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
7099 #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
7100 #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
7101 #define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
7102 #define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
7103 
7104 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
7105 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
7106 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
7107 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
7108 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
7109 
7110 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
7111 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
7112 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
7113 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
7114 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
7115 
7116 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
7117 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
7118 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
7119 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
7120 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
7121 
7122 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
7123 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
7124 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
7125 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
7126 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
7127 
7128 /* Bit 3 : Reset from CPU lock-up detected */
7129 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
7130 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
7131 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
7132 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
7133 
7134 /* Bit 2 : Reset from soft reset detected */
7135 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
7136 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
7137 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
7138 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
7139 
7140 /* Bit 1 : Reset from watchdog detected */
7141 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
7142 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
7143 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
7144 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
7145 
7146 /* Bit 0 : Reset from pin-reset detected */
7147 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
7148 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
7149 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
7150 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
7151 
7152 /* Register: POWER_RAMSTATUS */
7153 /* Description: Deprecated register - RAM status register */
7154 
7155 /* Bit 3 : RAM block 3 is on or off/powering up */
7156 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
7157 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
7158 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
7159 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
7160 
7161 /* Bit 2 : RAM block 2 is on or off/powering up */
7162 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
7163 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
7164 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
7165 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
7166 
7167 /* Bit 1 : RAM block 1 is on or off/powering up */
7168 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
7169 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
7170 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
7171 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
7172 
7173 /* Bit 0 : RAM block 0 is on or off/powering up */
7174 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
7175 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
7176 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
7177 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
7178 
7179 /* Register: POWER_USBREGSTATUS */
7180 /* Description: USB supply status */
7181 
7182 /* Bit 1 : USB supply output settling time elapsed */
7183 #define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
7184 #define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
7185 #define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
7186 #define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
7187 
7188 /* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
7189 #define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
7190 #define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
7191 #define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
7192 #define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
7193 
7194 /* Register: POWER_SYSTEMOFF */
7195 /* Description: System OFF register */
7196 
7197 /* Bit 0 : Enable System OFF mode */
7198 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
7199 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
7200 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
7201 
7202 /* Register: POWER_POFCON */
7203 /* Description: Power-fail comparator configuration */
7204 
7205 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */
7206 #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
7207 #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
7208 #define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
7209 #define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
7210 #define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
7211 #define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
7212 #define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
7213 #define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
7214 #define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
7215 #define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
7216 #define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
7217 #define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
7218 #define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
7219 #define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
7220 #define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
7221 #define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
7222 #define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
7223 #define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
7224 
7225 /* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */
7226 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
7227 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
7228 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
7229 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
7230 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
7231 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
7232 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
7233 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
7234 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
7235 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
7236 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
7237 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
7238 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
7239 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
7240 
7241 /* Bit 0 : Enable or disable power failure warning */
7242 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
7243 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
7244 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
7245 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
7246 
7247 /* Register: POWER_GPREGRET */
7248 /* Description: General purpose retention register */
7249 
7250 /* Bits 7..0 : General purpose retention register */
7251 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7252 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7253 
7254 /* Register: POWER_GPREGRET2 */
7255 /* Description: General purpose retention register */
7256 
7257 /* Bits 7..0 : General purpose retention register */
7258 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7259 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7260 
7261 /* Register: POWER_DCDCEN */
7262 /* Description: Enable DC/DC converter for REG1 stage */
7263 
7264 /* Bit 0 : Enable DC/DC converter for REG1 stage. */
7265 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
7266 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
7267 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
7268 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
7269 
7270 /* Register: POWER_MAINREGSTATUS */
7271 /* Description: Main supply status */
7272 
7273 /* Bit 0 : Main supply status */
7274 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
7275 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
7276 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
7277 #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
7278 
7279 /* Register: POWER_RAM_POWER */
7280 /* Description: Description cluster: RAMn power control register */
7281 
7282 /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */
7283 #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7284 #define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7285 #define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
7286 #define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
7287 
7288 /* Bit 30 : Keep retention on RAM section S14 when RAM section is off */
7289 #define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7290 #define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7291 #define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
7292 #define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
7293 
7294 /* Bit 29 : Keep retention on RAM section S13 when RAM section is off */
7295 #define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7296 #define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7297 #define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
7298 #define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
7299 
7300 /* Bit 28 : Keep retention on RAM section S12 when RAM section is off */
7301 #define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7302 #define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7303 #define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
7304 #define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
7305 
7306 /* Bit 27 : Keep retention on RAM section S11 when RAM section is off */
7307 #define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7308 #define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7309 #define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
7310 #define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
7311 
7312 /* Bit 26 : Keep retention on RAM section S10 when RAM section is off */
7313 #define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7314 #define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7315 #define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
7316 #define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
7317 
7318 /* Bit 25 : Keep retention on RAM section S9 when RAM section is off */
7319 #define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7320 #define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7321 #define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
7322 #define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
7323 
7324 /* Bit 24 : Keep retention on RAM section S8 when RAM section is off */
7325 #define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7326 #define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7327 #define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
7328 #define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
7329 
7330 /* Bit 23 : Keep retention on RAM section S7 when RAM section is off */
7331 #define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7332 #define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7333 #define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
7334 #define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
7335 
7336 /* Bit 22 : Keep retention on RAM section S6 when RAM section is off */
7337 #define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7338 #define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7339 #define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
7340 #define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
7341 
7342 /* Bit 21 : Keep retention on RAM section S5 when RAM section is off */
7343 #define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7344 #define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7345 #define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
7346 #define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
7347 
7348 /* Bit 20 : Keep retention on RAM section S4 when RAM section is off */
7349 #define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7350 #define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7351 #define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
7352 #define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
7353 
7354 /* Bit 19 : Keep retention on RAM section S3 when RAM section is off */
7355 #define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7356 #define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7357 #define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
7358 #define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
7359 
7360 /* Bit 18 : Keep retention on RAM section S2 when RAM section is off */
7361 #define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7362 #define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7363 #define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
7364 #define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
7365 
7366 /* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
7367 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7368 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7369 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
7370 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
7371 
7372 /* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
7373 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7374 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7375 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
7376 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
7377 
7378 /* Bit 15 : Keep RAM section S15 on or off in System ON mode. */
7379 #define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7380 #define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7381 #define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
7382 #define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */
7383 
7384 /* Bit 14 : Keep RAM section S14 on or off in System ON mode. */
7385 #define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7386 #define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7387 #define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
7388 #define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */
7389 
7390 /* Bit 13 : Keep RAM section S13 on or off in System ON mode. */
7391 #define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7392 #define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7393 #define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
7394 #define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */
7395 
7396 /* Bit 12 : Keep RAM section S12 on or off in System ON mode. */
7397 #define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7398 #define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7399 #define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
7400 #define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */
7401 
7402 /* Bit 11 : Keep RAM section S11 on or off in System ON mode. */
7403 #define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7404 #define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7405 #define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
7406 #define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */
7407 
7408 /* Bit 10 : Keep RAM section S10 on or off in System ON mode. */
7409 #define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7410 #define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7411 #define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
7412 #define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */
7413 
7414 /* Bit 9 : Keep RAM section S9 on or off in System ON mode. */
7415 #define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7416 #define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7417 #define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
7418 #define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */
7419 
7420 /* Bit 8 : Keep RAM section S8 on or off in System ON mode. */
7421 #define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7422 #define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7423 #define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
7424 #define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */
7425 
7426 /* Bit 7 : Keep RAM section S7 on or off in System ON mode. */
7427 #define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7428 #define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7429 #define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
7430 #define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */
7431 
7432 /* Bit 6 : Keep RAM section S6 on or off in System ON mode. */
7433 #define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7434 #define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7435 #define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
7436 #define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */
7437 
7438 /* Bit 5 : Keep RAM section S5 on or off in System ON mode. */
7439 #define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7440 #define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7441 #define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
7442 #define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */
7443 
7444 /* Bit 4 : Keep RAM section S4 on or off in System ON mode. */
7445 #define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7446 #define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7447 #define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
7448 #define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */
7449 
7450 /* Bit 3 : Keep RAM section S3 on or off in System ON mode. */
7451 #define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7452 #define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7453 #define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
7454 #define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */
7455 
7456 /* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
7457 #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7458 #define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7459 #define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
7460 #define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */
7461 
7462 /* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
7463 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7464 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7465 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
7466 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
7467 
7468 /* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
7469 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7470 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7471 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7472 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7473 
7474 /* Register: POWER_RAM_POWERSET */
7475 /* Description: Description cluster: RAMn power control set register */
7476 
7477 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7478 #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7479 #define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7480 #define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
7481 
7482 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7483 #define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7484 #define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7485 #define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
7486 
7487 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7488 #define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7489 #define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7490 #define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
7491 
7492 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7493 #define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7494 #define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7495 #define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
7496 
7497 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7498 #define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7499 #define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7500 #define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
7501 
7502 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7503 #define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7504 #define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7505 #define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
7506 
7507 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7508 #define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7509 #define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7510 #define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
7511 
7512 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7513 #define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7514 #define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7515 #define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
7516 
7517 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7518 #define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7519 #define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7520 #define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
7521 
7522 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7523 #define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7524 #define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7525 #define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
7526 
7527 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7528 #define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7529 #define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7530 #define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
7531 
7532 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7533 #define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7534 #define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7535 #define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
7536 
7537 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7538 #define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7539 #define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7540 #define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
7541 
7542 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7543 #define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7544 #define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7545 #define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
7546 
7547 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7548 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7549 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7550 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7551 
7552 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7553 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7554 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7555 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7556 
7557 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7558 #define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7559 #define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7560 #define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
7561 
7562 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7563 #define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7564 #define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7565 #define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
7566 
7567 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7568 #define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7569 #define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7570 #define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
7571 
7572 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7573 #define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7574 #define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7575 #define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
7576 
7577 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7578 #define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7579 #define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7580 #define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
7581 
7582 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7583 #define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7584 #define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7585 #define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
7586 
7587 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7588 #define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7589 #define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7590 #define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
7591 
7592 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7593 #define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7594 #define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7595 #define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
7596 
7597 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7598 #define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7599 #define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7600 #define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
7601 
7602 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7603 #define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7604 #define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7605 #define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
7606 
7607 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7608 #define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7609 #define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7610 #define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
7611 
7612 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7613 #define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7614 #define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7615 #define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
7616 
7617 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7618 #define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7619 #define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7620 #define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
7621 
7622 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7623 #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7624 #define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7625 #define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
7626 
7627 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7628 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7629 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7630 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7631 
7632 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7633 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7634 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7635 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7636 
7637 /* Register: POWER_RAM_POWERCLR */
7638 /* Description: Description cluster: RAMn power control clear register */
7639 
7640 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7641 #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7642 #define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7643 #define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
7644 
7645 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7646 #define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7647 #define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7648 #define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
7649 
7650 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7651 #define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7652 #define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7653 #define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
7654 
7655 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7656 #define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7657 #define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7658 #define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
7659 
7660 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7661 #define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7662 #define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7663 #define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
7664 
7665 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7666 #define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7667 #define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7668 #define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
7669 
7670 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7671 #define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7672 #define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7673 #define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
7674 
7675 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7676 #define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7677 #define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7678 #define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
7679 
7680 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7681 #define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7682 #define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7683 #define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
7684 
7685 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7686 #define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7687 #define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7688 #define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
7689 
7690 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7691 #define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7692 #define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7693 #define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
7694 
7695 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7696 #define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7697 #define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7698 #define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
7699 
7700 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7701 #define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7702 #define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7703 #define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
7704 
7705 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7706 #define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7707 #define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7708 #define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
7709 
7710 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7711 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7712 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7713 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7714 
7715 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7716 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7717 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7718 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7719 
7720 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7721 #define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7722 #define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7723 #define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
7724 
7725 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7726 #define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7727 #define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7728 #define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
7729 
7730 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7731 #define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7732 #define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7733 #define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
7734 
7735 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7736 #define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7737 #define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7738 #define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
7739 
7740 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7741 #define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7742 #define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7743 #define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
7744 
7745 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7746 #define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7747 #define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7748 #define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
7749 
7750 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7751 #define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7752 #define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7753 #define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
7754 
7755 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7756 #define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7757 #define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7758 #define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
7759 
7760 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7761 #define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7762 #define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7763 #define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
7764 
7765 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7766 #define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7767 #define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7768 #define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
7769 
7770 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7771 #define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7772 #define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7773 #define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
7774 
7775 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7776 #define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7777 #define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7778 #define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
7779 
7780 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7781 #define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7782 #define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7783 #define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
7784 
7785 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7786 #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7787 #define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7788 #define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
7789 
7790 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7791 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7792 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7793 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7794 
7795 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7796 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7797 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7798 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7799 
7800 
7801 /* Peripheral: PPI */
7802 /* Description: Programmable Peripheral Interconnect */
7803 
7804 /* Register: PPI_TASKS_CHG_EN */
7805 /* Description: Description cluster: Enable channel group n */
7806 
7807 /* Bit 0 : Enable channel group n */
7808 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
7809 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
7810 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
7811 
7812 /* Register: PPI_TASKS_CHG_DIS */
7813 /* Description: Description cluster: Disable channel group n */
7814 
7815 /* Bit 0 : Disable channel group n */
7816 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
7817 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
7818 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
7819 
7820 /* Register: PPI_CHEN */
7821 /* Description: Channel enable register */
7822 
7823 /* Bit 31 : Enable or disable channel 31 */
7824 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7825 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7826 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7827 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7828 
7829 /* Bit 30 : Enable or disable channel 30 */
7830 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7831 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7832 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7833 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7834 
7835 /* Bit 29 : Enable or disable channel 29 */
7836 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7837 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7838 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7839 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7840 
7841 /* Bit 28 : Enable or disable channel 28 */
7842 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7843 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7844 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7845 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7846 
7847 /* Bit 27 : Enable or disable channel 27 */
7848 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7849 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7850 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7851 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7852 
7853 /* Bit 26 : Enable or disable channel 26 */
7854 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7855 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7856 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7857 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7858 
7859 /* Bit 25 : Enable or disable channel 25 */
7860 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7861 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7862 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7863 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7864 
7865 /* Bit 24 : Enable or disable channel 24 */
7866 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7867 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7868 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7869 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7870 
7871 /* Bit 23 : Enable or disable channel 23 */
7872 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7873 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7874 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7875 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7876 
7877 /* Bit 22 : Enable or disable channel 22 */
7878 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
7879 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
7880 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7881 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7882 
7883 /* Bit 21 : Enable or disable channel 21 */
7884 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
7885 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
7886 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7887 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7888 
7889 /* Bit 20 : Enable or disable channel 20 */
7890 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
7891 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
7892 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7893 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7894 
7895 /* Bit 19 : Enable or disable channel 19 */
7896 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
7897 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
7898 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7899 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7900 
7901 /* Bit 18 : Enable or disable channel 18 */
7902 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
7903 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
7904 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7905 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7906 
7907 /* Bit 17 : Enable or disable channel 17 */
7908 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
7909 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
7910 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7911 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7912 
7913 /* Bit 16 : Enable or disable channel 16 */
7914 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
7915 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
7916 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7917 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7918 
7919 /* Bit 15 : Enable or disable channel 15 */
7920 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
7921 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
7922 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7923 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7924 
7925 /* Bit 14 : Enable or disable channel 14 */
7926 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
7927 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
7928 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7929 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7930 
7931 /* Bit 13 : Enable or disable channel 13 */
7932 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
7933 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
7934 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7935 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7936 
7937 /* Bit 12 : Enable or disable channel 12 */
7938 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
7939 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
7940 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7941 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7942 
7943 /* Bit 11 : Enable or disable channel 11 */
7944 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
7945 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
7946 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7947 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7948 
7949 /* Bit 10 : Enable or disable channel 10 */
7950 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
7951 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
7952 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7953 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7954 
7955 /* Bit 9 : Enable or disable channel 9 */
7956 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
7957 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
7958 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7959 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7960 
7961 /* Bit 8 : Enable or disable channel 8 */
7962 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
7963 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
7964 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7965 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7966 
7967 /* Bit 7 : Enable or disable channel 7 */
7968 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
7969 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
7970 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7971 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7972 
7973 /* Bit 6 : Enable or disable channel 6 */
7974 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
7975 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
7976 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7977 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7978 
7979 /* Bit 5 : Enable or disable channel 5 */
7980 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
7981 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
7982 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7983 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7984 
7985 /* Bit 4 : Enable or disable channel 4 */
7986 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
7987 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
7988 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7989 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7990 
7991 /* Bit 3 : Enable or disable channel 3 */
7992 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
7993 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
7994 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7995 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7996 
7997 /* Bit 2 : Enable or disable channel 2 */
7998 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
7999 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
8000 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
8001 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
8002 
8003 /* Bit 1 : Enable or disable channel 1 */
8004 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
8005 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
8006 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
8007 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
8008 
8009 /* Bit 0 : Enable or disable channel 0 */
8010 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
8011 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
8012 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
8013 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
8014 
8015 /* Register: PPI_CHENSET */
8016 /* Description: Channel enable set register */
8017 
8018 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect. */
8019 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
8020 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
8021 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
8022 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
8023 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
8024 
8025 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect. */
8026 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
8027 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
8028 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
8029 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
8030 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
8031 
8032 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect. */
8033 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
8034 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
8035 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
8036 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
8037 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
8038 
8039 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect. */
8040 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
8041 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
8042 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
8043 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
8044 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
8045 
8046 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect. */
8047 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
8048 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
8049 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
8050 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
8051 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
8052 
8053 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect. */
8054 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
8055 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
8056 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
8057 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
8058 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
8059 
8060 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect. */
8061 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
8062 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
8063 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
8064 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
8065 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
8066 
8067 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect. */
8068 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
8069 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
8070 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
8071 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
8072 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
8073 
8074 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect. */
8075 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
8076 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
8077 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
8078 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
8079 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
8080 
8081 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect. */
8082 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
8083 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
8084 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
8085 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
8086 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
8087 
8088 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect. */
8089 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
8090 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
8091 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
8092 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
8093 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
8094 
8095 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect. */
8096 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
8097 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
8098 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
8099 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
8100 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
8101 
8102 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect. */
8103 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
8104 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
8105 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
8106 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
8107 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
8108 
8109 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect. */
8110 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
8111 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
8112 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
8113 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
8114 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
8115 
8116 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect. */
8117 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
8118 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
8119 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
8120 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
8121 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
8122 
8123 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect. */
8124 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
8125 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
8126 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
8127 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
8128 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
8129 
8130 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect. */
8131 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
8132 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
8133 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
8134 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
8135 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
8136 
8137 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect. */
8138 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
8139 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
8140 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
8141 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
8142 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
8143 
8144 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect. */
8145 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
8146 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
8147 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
8148 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
8149 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
8150 
8151 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect. */
8152 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
8153 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
8154 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
8155 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
8156 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
8157 
8158 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect. */
8159 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
8160 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
8161 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
8162 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
8163 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
8164 
8165 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect. */
8166 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
8167 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
8168 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
8169 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
8170 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
8171 
8172 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect. */
8173 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
8174 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
8175 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
8176 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
8177 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
8178 
8179 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect. */
8180 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
8181 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
8182 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
8183 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
8184 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
8185 
8186 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect. */
8187 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
8188 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
8189 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
8190 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
8191 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
8192 
8193 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect. */
8194 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
8195 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
8196 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
8197 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
8198 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
8199 
8200 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect. */
8201 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
8202 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
8203 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
8204 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
8205 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
8206 
8207 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect. */
8208 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
8209 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
8210 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
8211 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
8212 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
8213 
8214 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect. */
8215 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
8216 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
8217 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
8218 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
8219 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
8220 
8221 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect. */
8222 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
8223 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
8224 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
8225 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
8226 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
8227 
8228 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect. */
8229 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
8230 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
8231 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
8232 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
8233 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
8234 
8235 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect. */
8236 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
8237 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
8238 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
8239 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
8240 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
8241 
8242 /* Register: PPI_CHENCLR */
8243 /* Description: Channel enable clear register */
8244 
8245 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect. */
8246 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
8247 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
8248 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
8249 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
8250 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
8251 
8252 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect. */
8253 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
8254 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
8255 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
8256 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
8257 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
8258 
8259 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect. */
8260 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
8261 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
8262 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
8263 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
8264 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
8265 
8266 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect. */
8267 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
8268 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
8269 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
8270 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
8271 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
8272 
8273 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect. */
8274 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
8275 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
8276 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
8277 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
8278 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
8279 
8280 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect. */
8281 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
8282 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
8283 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
8284 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
8285 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
8286 
8287 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect. */
8288 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
8289 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
8290 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
8291 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
8292 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
8293 
8294 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect. */
8295 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
8296 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
8297 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
8298 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
8299 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
8300 
8301 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect. */
8302 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
8303 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
8304 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
8305 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
8306 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
8307 
8308 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect. */
8309 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
8310 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
8311 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
8312 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
8313 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
8314 
8315 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect. */
8316 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
8317 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
8318 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
8319 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
8320 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
8321 
8322 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect. */
8323 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
8324 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
8325 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
8326 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
8327 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
8328 
8329 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect. */
8330 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
8331 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
8332 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
8333 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
8334 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
8335 
8336 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect. */
8337 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
8338 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
8339 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
8340 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
8341 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
8342 
8343 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect. */
8344 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
8345 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
8346 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
8347 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
8348 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
8349 
8350 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect. */
8351 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
8352 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
8353 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
8354 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
8355 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
8356 
8357 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect. */
8358 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
8359 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
8360 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
8361 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
8362 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
8363 
8364 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect. */
8365 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
8366 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
8367 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
8368 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
8369 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
8370 
8371 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect. */
8372 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
8373 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
8374 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
8375 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
8376 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
8377 
8378 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect. */
8379 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
8380 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
8381 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
8382 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
8383 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
8384 
8385 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect. */
8386 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
8387 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
8388 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
8389 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
8390 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
8391 
8392 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect. */
8393 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
8394 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
8395 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
8396 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
8397 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
8398 
8399 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect. */
8400 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
8401 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
8402 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
8403 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
8404 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
8405 
8406 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect. */
8407 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
8408 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
8409 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
8410 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
8411 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
8412 
8413 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect. */
8414 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
8415 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
8416 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
8417 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
8418 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
8419 
8420 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect. */
8421 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
8422 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
8423 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
8424 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
8425 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
8426 
8427 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect. */
8428 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
8429 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
8430 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
8431 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
8432 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
8433 
8434 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect. */
8435 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
8436 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
8437 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
8438 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
8439 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
8440 
8441 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect. */
8442 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
8443 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
8444 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
8445 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
8446 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
8447 
8448 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect. */
8449 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
8450 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
8451 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
8452 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
8453 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
8454 
8455 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect. */
8456 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
8457 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
8458 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
8459 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
8460 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
8461 
8462 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect. */
8463 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
8464 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
8465 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8466 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8467 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8468 
8469 /* Register: PPI_CH_EEP */
8470 /* Description: Description cluster: Channel n event endpoint */
8471 
8472 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
8473 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
8474 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
8475 
8476 /* Register: PPI_CH_TEP */
8477 /* Description: Description cluster: Channel n task endpoint */
8478 
8479 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
8480 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8481 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8482 
8483 /* Register: PPI_CHG */
8484 /* Description: Description collection: Channel group n */
8485 
8486 /* Bit 31 : Include or exclude channel 31 */
8487 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
8488 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
8489 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
8490 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
8491 
8492 /* Bit 30 : Include or exclude channel 30 */
8493 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
8494 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
8495 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
8496 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
8497 
8498 /* Bit 29 : Include or exclude channel 29 */
8499 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
8500 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
8501 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
8502 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
8503 
8504 /* Bit 28 : Include or exclude channel 28 */
8505 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
8506 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
8507 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
8508 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
8509 
8510 /* Bit 27 : Include or exclude channel 27 */
8511 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
8512 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
8513 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
8514 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
8515 
8516 /* Bit 26 : Include or exclude channel 26 */
8517 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
8518 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
8519 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
8520 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
8521 
8522 /* Bit 25 : Include or exclude channel 25 */
8523 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
8524 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
8525 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
8526 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
8527 
8528 /* Bit 24 : Include or exclude channel 24 */
8529 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
8530 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
8531 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
8532 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
8533 
8534 /* Bit 23 : Include or exclude channel 23 */
8535 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
8536 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
8537 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
8538 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
8539 
8540 /* Bit 22 : Include or exclude channel 22 */
8541 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
8542 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
8543 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
8544 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
8545 
8546 /* Bit 21 : Include or exclude channel 21 */
8547 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
8548 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
8549 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
8550 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
8551 
8552 /* Bit 20 : Include or exclude channel 20 */
8553 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
8554 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
8555 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
8556 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
8557 
8558 /* Bit 19 : Include or exclude channel 19 */
8559 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
8560 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
8561 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
8562 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
8563 
8564 /* Bit 18 : Include or exclude channel 18 */
8565 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
8566 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
8567 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
8568 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
8569 
8570 /* Bit 17 : Include or exclude channel 17 */
8571 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
8572 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
8573 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
8574 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
8575 
8576 /* Bit 16 : Include or exclude channel 16 */
8577 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
8578 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
8579 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
8580 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
8581 
8582 /* Bit 15 : Include or exclude channel 15 */
8583 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
8584 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
8585 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
8586 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
8587 
8588 /* Bit 14 : Include or exclude channel 14 */
8589 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
8590 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
8591 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
8592 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
8593 
8594 /* Bit 13 : Include or exclude channel 13 */
8595 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
8596 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
8597 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
8598 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
8599 
8600 /* Bit 12 : Include or exclude channel 12 */
8601 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
8602 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
8603 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
8604 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
8605 
8606 /* Bit 11 : Include or exclude channel 11 */
8607 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
8608 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
8609 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
8610 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
8611 
8612 /* Bit 10 : Include or exclude channel 10 */
8613 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
8614 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
8615 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
8616 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
8617 
8618 /* Bit 9 : Include or exclude channel 9 */
8619 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
8620 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
8621 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
8622 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
8623 
8624 /* Bit 8 : Include or exclude channel 8 */
8625 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
8626 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
8627 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
8628 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
8629 
8630 /* Bit 7 : Include or exclude channel 7 */
8631 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
8632 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
8633 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
8634 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
8635 
8636 /* Bit 6 : Include or exclude channel 6 */
8637 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
8638 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
8639 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
8640 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
8641 
8642 /* Bit 5 : Include or exclude channel 5 */
8643 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
8644 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
8645 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
8646 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
8647 
8648 /* Bit 4 : Include or exclude channel 4 */
8649 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
8650 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
8651 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
8652 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
8653 
8654 /* Bit 3 : Include or exclude channel 3 */
8655 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
8656 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
8657 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
8658 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
8659 
8660 /* Bit 2 : Include or exclude channel 2 */
8661 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
8662 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
8663 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
8664 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
8665 
8666 /* Bit 1 : Include or exclude channel 1 */
8667 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
8668 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
8669 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
8670 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
8671 
8672 /* Bit 0 : Include or exclude channel 0 */
8673 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
8674 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
8675 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
8676 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
8677 
8678 /* Register: PPI_FORK_TEP */
8679 /* Description: Description cluster: Channel n task endpoint */
8680 
8681 /* Bits 31..0 : Pointer to task register */
8682 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8683 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8684 
8685 
8686 /* Peripheral: PWM */
8687 /* Description: Pulse width modulation unit 0 */
8688 
8689 /* Register: PWM_TASKS_STOP */
8690 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8691 
8692 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8693 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8694 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8695 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8696 
8697 /* Register: PWM_TASKS_SEQSTART */
8698 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
8699 
8700 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
8701 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
8702 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
8703 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
8704 
8705 /* Register: PWM_TASKS_NEXTSTEP */
8706 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
8707 
8708 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
8709 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
8710 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
8711 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
8712 
8713 /* Register: PWM_EVENTS_STOPPED */
8714 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
8715 
8716 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
8717 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8718 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8719 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8720 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8721 
8722 /* Register: PWM_EVENTS_SEQSTARTED */
8723 /* Description: Description collection: First PWM period started on sequence n */
8724 
8725 /* Bit 0 : First PWM period started on sequence n */
8726 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
8727 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
8728 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
8729 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
8730 
8731 /* Register: PWM_EVENTS_SEQEND */
8732 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8733 
8734 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8735 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
8736 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
8737 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
8738 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
8739 
8740 /* Register: PWM_EVENTS_PWMPERIODEND */
8741 /* Description: Emitted at the end of each PWM period */
8742 
8743 /* Bit 0 : Emitted at the end of each PWM period */
8744 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
8745 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
8746 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
8747 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
8748 
8749 /* Register: PWM_EVENTS_LOOPSDONE */
8750 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8751 
8752 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8753 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
8754 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
8755 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
8756 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
8757 
8758 /* Register: PWM_SHORTS */
8759 /* Description: Shortcuts between local events and tasks */
8760 
8761 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
8762 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
8763 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
8764 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
8765 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
8766 
8767 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
8768 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
8769 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
8770 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
8771 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
8772 
8773 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
8774 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
8775 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
8776 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
8777 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
8778 
8779 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
8780 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
8781 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
8782 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
8783 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
8784 
8785 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
8786 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
8787 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
8788 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
8789 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
8790 
8791 /* Register: PWM_INTEN */
8792 /* Description: Enable or disable interrupt */
8793 
8794 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
8795 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8796 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8797 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
8798 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
8799 
8800 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
8801 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8802 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8803 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
8804 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
8805 
8806 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
8807 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8808 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8809 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
8810 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
8811 
8812 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
8813 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8814 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8815 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
8816 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
8817 
8818 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
8819 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8820 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8821 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
8822 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
8823 
8824 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
8825 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8826 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8827 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
8828 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
8829 
8830 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8831 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8832 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8833 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8834 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8835 
8836 /* Register: PWM_INTENSET */
8837 /* Description: Enable interrupt */
8838 
8839 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
8840 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8841 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8842 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8843 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8844 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8845 
8846 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
8847 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8848 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8849 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8850 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8851 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8852 
8853 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
8854 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8855 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8856 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8857 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8858 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8859 
8860 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
8861 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8862 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8863 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8864 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8865 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8866 
8867 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
8868 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8869 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8870 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8871 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8872 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8873 
8874 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
8875 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8876 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8877 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8878 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8879 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8880 
8881 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8882 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8883 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8884 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8885 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8886 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8887 
8888 /* Register: PWM_INTENCLR */
8889 /* Description: Disable interrupt */
8890 
8891 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
8892 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8893 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8894 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8895 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8896 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8897 
8898 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
8899 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8900 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8901 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8902 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8903 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8904 
8905 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
8906 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8907 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8908 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8909 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8910 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8911 
8912 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
8913 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8914 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8915 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8916 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8917 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8918 
8919 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
8920 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8921 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8922 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8923 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8924 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8925 
8926 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
8927 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8928 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8929 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8930 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8931 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8932 
8933 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8934 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8935 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8936 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8937 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8938 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8939 
8940 /* Register: PWM_ENABLE */
8941 /* Description: PWM module enable register */
8942 
8943 /* Bit 0 : Enable or disable PWM module */
8944 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8945 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8946 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8947 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8948 
8949 /* Register: PWM_MODE */
8950 /* Description: Selects operating mode of the wave counter */
8951 
8952 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
8953 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
8954 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
8955 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
8956 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
8957 
8958 /* Register: PWM_COUNTERTOP */
8959 /* Description: Value up to which the pulse generator counter counts */
8960 
8961 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
8962 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
8963 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
8964 
8965 /* Register: PWM_PRESCALER */
8966 /* Description: Configuration for PWM_CLK */
8967 
8968 /* Bits 2..0 : Prescaler of PWM_CLK */
8969 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8970 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8971 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
8972 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
8973 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
8974 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
8975 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
8976 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
8977 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
8978 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
8979 
8980 /* Register: PWM_DECODER */
8981 /* Description: Configuration of the decoder */
8982 
8983 /* Bit 8 : Selects source for advancing the active sequence */
8984 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
8985 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
8986 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
8987 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
8988 
8989 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
8990 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
8991 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
8992 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8993 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
8994 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
8995 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
8996 
8997 /* Register: PWM_LOOP */
8998 /* Description: Number of playbacks of a loop */
8999 
9000 /* Bits 15..0 : Number of playbacks of pattern cycles */
9001 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
9002 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
9003 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
9004 
9005 /* Register: PWM_SEQ_PTR */
9006 /* Description: Description cluster: Beginning address in RAM of this sequence */
9007 
9008 /* Bits 31..0 : Beginning address in RAM of this sequence */
9009 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9010 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9011 
9012 /* Register: PWM_SEQ_CNT */
9013 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
9014 
9015 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
9016 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9017 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9018 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
9019 
9020 /* Register: PWM_SEQ_REFRESH */
9021 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
9022 
9023 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
9024 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
9025 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
9026 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
9027 
9028 /* Register: PWM_SEQ_ENDDELAY */
9029 /* Description: Description cluster: Time added after the sequence */
9030 
9031 /* Bits 23..0 : Time added after the sequence in PWM periods */
9032 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
9033 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
9034 
9035 /* Register: PWM_PSEL_OUT */
9036 /* Description: Description collection: Output pin select for PWM channel n */
9037 
9038 /* Bit 31 : Connection */
9039 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9040 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9041 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
9042 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
9043 
9044 /* Bit 5 : Port number */
9045 #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
9046 #define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
9047 
9048 /* Bits 4..0 : Pin number */
9049 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
9050 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
9051 
9052 
9053 /* Peripheral: QDEC */
9054 /* Description: Quadrature Decoder */
9055 
9056 /* Register: QDEC_TASKS_START */
9057 /* Description: Task starting the quadrature decoder */
9058 
9059 /* Bit 0 : Task starting the quadrature decoder */
9060 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9061 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9062 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9063 
9064 /* Register: QDEC_TASKS_STOP */
9065 /* Description: Task stopping the quadrature decoder */
9066 
9067 /* Bit 0 : Task stopping the quadrature decoder */
9068 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9069 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9070 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9071 
9072 /* Register: QDEC_TASKS_READCLRACC */
9073 /* Description: Read and clear ACC and ACCDBL */
9074 
9075 /* Bit 0 : Read and clear ACC and ACCDBL */
9076 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
9077 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
9078 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
9079 
9080 /* Register: QDEC_TASKS_RDCLRACC */
9081 /* Description: Read and clear ACC */
9082 
9083 /* Bit 0 : Read and clear ACC */
9084 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
9085 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
9086 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
9087 
9088 /* Register: QDEC_TASKS_RDCLRDBL */
9089 /* Description: Read and clear ACCDBL */
9090 
9091 /* Bit 0 : Read and clear ACCDBL */
9092 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
9093 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
9094 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
9095 
9096 /* Register: QDEC_EVENTS_SAMPLERDY */
9097 /* Description: Event being generated for every new sample value written to the SAMPLE register */
9098 
9099 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
9100 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
9101 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
9102 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
9103 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
9104 
9105 /* Register: QDEC_EVENTS_REPORTRDY */
9106 /* Description: Non-null report ready */
9107 
9108 /* Bit 0 : Non-null report ready */
9109 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
9110 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
9111 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
9112 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
9113 
9114 /* Register: QDEC_EVENTS_ACCOF */
9115 /* Description: ACC or ACCDBL register overflow */
9116 
9117 /* Bit 0 : ACC or ACCDBL register overflow */
9118 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
9119 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
9120 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
9121 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
9122 
9123 /* Register: QDEC_EVENTS_DBLRDY */
9124 /* Description: Double displacement(s) detected */
9125 
9126 /* Bit 0 : Double displacement(s) detected */
9127 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
9128 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
9129 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
9130 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
9131 
9132 /* Register: QDEC_EVENTS_STOPPED */
9133 /* Description: QDEC has been stopped */
9134 
9135 /* Bit 0 : QDEC has been stopped */
9136 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9137 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9138 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9139 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9140 
9141 /* Register: QDEC_SHORTS */
9142 /* Description: Shortcuts between local events and tasks */
9143 
9144 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
9145 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
9146 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
9147 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9148 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9149 
9150 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
9151 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
9152 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
9153 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9154 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9155 
9156 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
9157 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
9158 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
9159 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
9160 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
9161 
9162 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
9163 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
9164 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
9165 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9166 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9167 
9168 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
9169 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
9170 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
9171 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
9172 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
9173 
9174 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
9175 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
9176 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
9177 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9178 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9179 
9180 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
9181 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
9182 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
9183 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9184 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9185 
9186 /* Register: QDEC_INTENSET */
9187 /* Description: Enable interrupt */
9188 
9189 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
9190 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9191 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9192 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9193 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9194 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9195 
9196 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
9197 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9198 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9199 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9200 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9201 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
9202 
9203 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
9204 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9205 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9206 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9207 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9208 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
9209 
9210 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
9211 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9212 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9213 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9214 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9215 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
9216 
9217 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
9218 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9219 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9220 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9221 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9222 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
9223 
9224 /* Register: QDEC_INTENCLR */
9225 /* Description: Disable interrupt */
9226 
9227 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
9228 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9229 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9230 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9231 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9232 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9233 
9234 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
9235 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9236 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9237 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9238 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9239 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
9240 
9241 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
9242 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9243 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9244 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9245 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9246 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
9247 
9248 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
9249 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9250 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9251 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9252 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9253 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
9254 
9255 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
9256 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9257 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9258 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9259 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9260 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
9261 
9262 /* Register: QDEC_ENABLE */
9263 /* Description: Enable the quadrature decoder */
9264 
9265 /* Bit 0 : Enable or disable the quadrature decoder */
9266 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9267 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9268 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
9269 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9270 
9271 /* Register: QDEC_LEDPOL */
9272 /* Description: LED output pin polarity */
9273 
9274 /* Bit 0 : LED output pin polarity */
9275 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
9276 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
9277 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
9278 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
9279 
9280 /* Register: QDEC_SAMPLEPER */
9281 /* Description: Sample period */
9282 
9283 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
9284 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
9285 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
9286 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
9287 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
9288 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
9289 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
9290 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
9291 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
9292 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
9293 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
9294 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
9295 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
9296 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
9297 
9298 /* Register: QDEC_SAMPLE */
9299 /* Description: Motion sample value */
9300 
9301 /* Bits 31..0 : Last motion sample */
9302 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
9303 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
9304 
9305 /* Register: QDEC_REPORTPER */
9306 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
9307 
9308 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
9309 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
9310 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
9311 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */
9312 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */
9313 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */
9314 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */
9315 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */
9316 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */
9317 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */
9318 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */
9319 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */
9320 
9321 /* Register: QDEC_ACC */
9322 /* Description: Register accumulating the valid transitions */
9323 
9324 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
9325 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
9326 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
9327 
9328 /* Register: QDEC_ACCREAD */
9329 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
9330 
9331 /* Bits 31..0 : Snapshot of the ACC register. */
9332 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
9333 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
9334 
9335 /* Register: QDEC_PSEL_LED */
9336 /* Description: Pin select for LED signal */
9337 
9338 /* Bit 31 : Connection */
9339 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9340 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9341 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
9342 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
9343 
9344 /* Bit 5 : Port number */
9345 #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
9346 #define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
9347 
9348 /* Bits 4..0 : Pin number */
9349 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
9350 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
9351 
9352 /* Register: QDEC_PSEL_A */
9353 /* Description: Pin select for A signal */
9354 
9355 /* Bit 31 : Connection */
9356 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9357 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9358 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
9359 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
9360 
9361 /* Bit 5 : Port number */
9362 #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
9363 #define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
9364 
9365 /* Bits 4..0 : Pin number */
9366 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
9367 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
9368 
9369 /* Register: QDEC_PSEL_B */
9370 /* Description: Pin select for B signal */
9371 
9372 /* Bit 31 : Connection */
9373 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9374 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9375 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
9376 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
9377 
9378 /* Bit 5 : Port number */
9379 #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
9380 #define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
9381 
9382 /* Bits 4..0 : Pin number */
9383 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
9384 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
9385 
9386 /* Register: QDEC_DBFEN */
9387 /* Description: Enable input debounce filters */
9388 
9389 /* Bit 0 : Enable input debounce filters */
9390 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
9391 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
9392 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
9393 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
9394 
9395 /* Register: QDEC_LEDPRE */
9396 /* Description: Time period the LED is switched ON prior to sampling */
9397 
9398 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
9399 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
9400 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
9401 
9402 /* Register: QDEC_ACCDBL */
9403 /* Description: Register accumulating the number of detected double transitions */
9404 
9405 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
9406 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
9407 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
9408 
9409 /* Register: QDEC_ACCDBLREAD */
9410 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
9411 
9412 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
9413 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
9414 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
9415 
9416 
9417 /* Peripheral: RADIO */
9418 /* Description: 2.4 GHz radio */
9419 
9420 /* Register: RADIO_TASKS_TXEN */
9421 /* Description: Enable RADIO in TX mode */
9422 
9423 /* Bit 0 : Enable RADIO in TX mode */
9424 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
9425 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
9426 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
9427 
9428 /* Register: RADIO_TASKS_RXEN */
9429 /* Description: Enable RADIO in RX mode */
9430 
9431 /* Bit 0 : Enable RADIO in RX mode */
9432 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
9433 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
9434 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
9435 
9436 /* Register: RADIO_TASKS_START */
9437 /* Description: Start RADIO */
9438 
9439 /* Bit 0 : Start RADIO */
9440 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9441 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9442 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9443 
9444 /* Register: RADIO_TASKS_STOP */
9445 /* Description: Stop RADIO */
9446 
9447 /* Bit 0 : Stop RADIO */
9448 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9449 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9450 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9451 
9452 /* Register: RADIO_TASKS_DISABLE */
9453 /* Description: Disable RADIO */
9454 
9455 /* Bit 0 : Disable RADIO */
9456 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
9457 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
9458 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
9459 
9460 /* Register: RADIO_TASKS_RSSISTART */
9461 /* Description: Start the RSSI and take one single sample of the receive signal strength */
9462 
9463 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
9464 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
9465 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
9466 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
9467 
9468 /* Register: RADIO_TASKS_RSSISTOP */
9469 /* Description: Stop the RSSI measurement */
9470 
9471 /* Bit 0 : Stop the RSSI measurement */
9472 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
9473 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
9474 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
9475 
9476 /* Register: RADIO_TASKS_BCSTART */
9477 /* Description: Start the bit counter */
9478 
9479 /* Bit 0 : Start the bit counter */
9480 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
9481 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
9482 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
9483 
9484 /* Register: RADIO_TASKS_BCSTOP */
9485 /* Description: Stop the bit counter */
9486 
9487 /* Bit 0 : Stop the bit counter */
9488 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
9489 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
9490 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
9491 
9492 /* Register: RADIO_TASKS_EDSTART */
9493 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
9494 
9495 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
9496 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
9497 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
9498 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
9499 
9500 /* Register: RADIO_TASKS_EDSTOP */
9501 /* Description: Stop the energy detect measurement */
9502 
9503 /* Bit 0 : Stop the energy detect measurement */
9504 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
9505 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
9506 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
9507 
9508 /* Register: RADIO_TASKS_CCASTART */
9509 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
9510 
9511 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
9512 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
9513 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
9514 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
9515 
9516 /* Register: RADIO_TASKS_CCASTOP */
9517 /* Description: Stop the clear channel assessment */
9518 
9519 /* Bit 0 : Stop the clear channel assessment */
9520 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
9521 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
9522 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
9523 
9524 /* Register: RADIO_EVENTS_READY */
9525 /* Description: RADIO has ramped up and is ready to be started */
9526 
9527 /* Bit 0 : RADIO has ramped up and is ready to be started */
9528 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
9529 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
9530 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
9531 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
9532 
9533 /* Register: RADIO_EVENTS_ADDRESS */
9534 /* Description: Address sent or received */
9535 
9536 /* Bit 0 : Address sent or received */
9537 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
9538 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
9539 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
9540 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
9541 
9542 /* Register: RADIO_EVENTS_PAYLOAD */
9543 /* Description: Packet payload sent or received */
9544 
9545 /* Bit 0 : Packet payload sent or received */
9546 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
9547 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
9548 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
9549 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
9550 
9551 /* Register: RADIO_EVENTS_END */
9552 /* Description: Packet sent or received */
9553 
9554 /* Bit 0 : Packet sent or received */
9555 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
9556 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
9557 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
9558 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
9559 
9560 /* Register: RADIO_EVENTS_DISABLED */
9561 /* Description: RADIO has been disabled */
9562 
9563 /* Bit 0 : RADIO has been disabled */
9564 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
9565 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
9566 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
9567 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
9568 
9569 /* Register: RADIO_EVENTS_DEVMATCH */
9570 /* Description: A device address match occurred on the last received packet */
9571 
9572 /* Bit 0 : A device address match occurred on the last received packet */
9573 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
9574 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
9575 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
9576 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
9577 
9578 /* Register: RADIO_EVENTS_DEVMISS */
9579 /* Description: No device address match occurred on the last received packet */
9580 
9581 /* Bit 0 : No device address match occurred on the last received packet */
9582 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
9583 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
9584 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
9585 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
9586 
9587 /* Register: RADIO_EVENTS_RSSIEND */
9588 /* Description: Sampling of receive signal strength complete */
9589 
9590 /* Bit 0 : Sampling of receive signal strength complete */
9591 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
9592 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
9593 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
9594 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
9595 
9596 /* Register: RADIO_EVENTS_BCMATCH */
9597 /* Description: Bit counter reached bit count value */
9598 
9599 /* Bit 0 : Bit counter reached bit count value */
9600 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
9601 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
9602 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
9603 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
9604 
9605 /* Register: RADIO_EVENTS_CRCOK */
9606 /* Description: Packet received with CRC ok */
9607 
9608 /* Bit 0 : Packet received with CRC ok */
9609 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
9610 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
9611 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
9612 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
9613 
9614 /* Register: RADIO_EVENTS_CRCERROR */
9615 /* Description: Packet received with CRC error */
9616 
9617 /* Bit 0 : Packet received with CRC error */
9618 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
9619 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
9620 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
9621 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
9622 
9623 /* Register: RADIO_EVENTS_FRAMESTART */
9624 /* Description: IEEE 802.15.4 length field received */
9625 
9626 /* Bit 0 : IEEE 802.15.4 length field received */
9627 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
9628 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
9629 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
9630 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
9631 
9632 /* Register: RADIO_EVENTS_EDEND */
9633 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
9634 
9635 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
9636 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
9637 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
9638 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
9639 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
9640 
9641 /* Register: RADIO_EVENTS_EDSTOPPED */
9642 /* Description: The sampling of energy detection has stopped */
9643 
9644 /* Bit 0 : The sampling of energy detection has stopped */
9645 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
9646 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
9647 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
9648 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
9649 
9650 /* Register: RADIO_EVENTS_CCAIDLE */
9651 /* Description: Wireless medium in idle - clear to send */
9652 
9653 /* Bit 0 : Wireless medium in idle - clear to send */
9654 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
9655 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
9656 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
9657 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
9658 
9659 /* Register: RADIO_EVENTS_CCABUSY */
9660 /* Description: Wireless medium busy - do not send */
9661 
9662 /* Bit 0 : Wireless medium busy - do not send */
9663 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
9664 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
9665 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
9666 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
9667 
9668 /* Register: RADIO_EVENTS_CCASTOPPED */
9669 /* Description: The CCA has stopped */
9670 
9671 /* Bit 0 : The CCA has stopped */
9672 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
9673 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
9674 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
9675 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
9676 
9677 /* Register: RADIO_EVENTS_RATEBOOST */
9678 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
9679 
9680 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
9681 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
9682 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
9683 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
9684 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
9685 
9686 /* Register: RADIO_EVENTS_TXREADY */
9687 /* Description: RADIO has ramped up and is ready to be started TX path */
9688 
9689 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
9690 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
9691 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
9692 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
9693 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
9694 
9695 /* Register: RADIO_EVENTS_RXREADY */
9696 /* Description: RADIO has ramped up and is ready to be started RX path */
9697 
9698 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
9699 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
9700 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
9701 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
9702 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
9703 
9704 /* Register: RADIO_EVENTS_MHRMATCH */
9705 /* Description: MAC header match found */
9706 
9707 /* Bit 0 : MAC header match found */
9708 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
9709 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
9710 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
9711 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
9712 
9713 /* Register: RADIO_EVENTS_SYNC */
9714 /* Description: Preamble indicator */
9715 
9716 /* Bit 0 : Preamble indicator */
9717 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
9718 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
9719 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */
9720 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */
9721 
9722 /* Register: RADIO_EVENTS_PHYEND */
9723 /* Description: Generated when last bit is sent on air, or received from air */
9724 
9725 /* Bit 0 : Generated when last bit is sent on air, or received from air */
9726 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
9727 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
9728 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
9729 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
9730 
9731 /* Register: RADIO_EVENTS_CTEPRESENT */
9732 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */
9733 
9734 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
9735 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
9736 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
9737 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
9738 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
9739 
9740 /* Register: RADIO_SHORTS */
9741 /* Description: Shortcuts between local events and tasks */
9742 
9743 /* Bit 21 : Shortcut between event PHYEND and task START */
9744 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
9745 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
9746 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
9747 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
9748 
9749 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
9750 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
9751 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
9752 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
9753 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
9754 
9755 /* Bit 19 : Shortcut between event RXREADY and task START */
9756 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
9757 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
9758 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
9759 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
9760 
9761 /* Bit 18 : Shortcut between event TXREADY and task START */
9762 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
9763 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
9764 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
9765 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
9766 
9767 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
9768 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
9769 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
9770 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
9771 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
9772 
9773 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
9774 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
9775 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
9776 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
9777 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
9778 
9779 /* Bit 15 : Shortcut between event READY and task EDSTART */
9780 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
9781 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
9782 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
9783 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
9784 
9785 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
9786 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
9787 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
9788 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
9789 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
9790 
9791 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
9792 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
9793 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
9794 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
9795 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
9796 
9797 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
9798 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
9799 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
9800 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
9801 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
9802 
9803 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
9804 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
9805 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
9806 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
9807 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
9808 
9809 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
9810 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
9811 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
9812 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
9813 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
9814 
9815 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
9816 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
9817 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
9818 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
9819 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
9820 
9821 /* Bit 5 : Shortcut between event END and task START */
9822 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
9823 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
9824 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
9825 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
9826 
9827 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
9828 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
9829 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
9830 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
9831 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
9832 
9833 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
9834 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
9835 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
9836 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
9837 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
9838 
9839 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
9840 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
9841 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
9842 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
9843 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
9844 
9845 /* Bit 1 : Shortcut between event END and task DISABLE */
9846 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
9847 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
9848 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
9849 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
9850 
9851 /* Bit 0 : Shortcut between event READY and task START */
9852 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
9853 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
9854 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
9855 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
9856 
9857 /* Register: RADIO_INTENSET */
9858 /* Description: Enable interrupt */
9859 
9860 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
9861 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
9862 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
9863 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
9864 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
9865 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
9866 
9867 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
9868 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
9869 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
9870 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
9871 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
9872 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
9873 
9874 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
9875 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
9876 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
9877 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */
9878 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */
9879 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */
9880 
9881 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
9882 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
9883 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
9884 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
9885 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
9886 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
9887 
9888 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
9889 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
9890 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
9891 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
9892 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
9893 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
9894 
9895 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
9896 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
9897 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
9898 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
9899 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
9900 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
9901 
9902 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
9903 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
9904 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
9905 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
9906 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
9907 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
9908 
9909 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
9910 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
9911 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
9912 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
9913 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
9914 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
9915 
9916 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
9917 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
9918 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
9919 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
9920 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
9921 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
9922 
9923 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
9924 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
9925 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
9926 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
9927 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
9928 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
9929 
9930 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
9931 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
9932 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
9933 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
9934 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
9935 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
9936 
9937 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
9938 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
9939 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
9940 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
9941 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
9942 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
9943 
9944 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
9945 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
9946 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
9947 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
9948 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
9949 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
9950 
9951 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
9952 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
9953 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
9954 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
9955 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
9956 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
9957 
9958 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
9959 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
9960 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
9961 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
9962 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
9963 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
9964 
9965 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
9966 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
9967 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
9968 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
9969 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
9970 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
9971 
9972 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
9973 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
9974 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
9975 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
9976 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
9977 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
9978 
9979 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
9980 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
9981 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
9982 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
9983 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
9984 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
9985 
9986 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
9987 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
9988 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
9989 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
9990 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
9991 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
9992 
9993 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
9994 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
9995 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
9996 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
9997 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
9998 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
9999 
10000 /* Bit 3 : Write '1' to enable interrupt for event END */
10001 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
10002 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
10003 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10004 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10005 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
10006 
10007 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
10008 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10009 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
10010 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10011 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10012 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
10013 
10014 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
10015 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
10016 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10017 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10018 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10019 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
10020 
10021 /* Bit 0 : Write '1' to enable interrupt for event READY */
10022 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
10023 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
10024 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10025 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10026 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
10027 
10028 /* Register: RADIO_INTENCLR */
10029 /* Description: Disable interrupt */
10030 
10031 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
10032 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
10033 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
10034 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
10035 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
10036 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
10037 
10038 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
10039 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
10040 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
10041 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10042 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10043 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
10044 
10045 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
10046 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
10047 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
10048 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */
10049 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */
10050 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */
10051 
10052 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
10053 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
10054 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
10055 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10056 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10057 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
10058 
10059 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
10060 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
10061 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
10062 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10063 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10064 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
10065 
10066 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
10067 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
10068 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
10069 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10070 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10071 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
10072 
10073 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
10074 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
10075 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
10076 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10077 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10078 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
10079 
10080 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
10081 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
10082 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
10083 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10084 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10085 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
10086 
10087 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
10088 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
10089 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
10090 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10091 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10092 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
10093 
10094 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
10095 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
10096 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
10097 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10098 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10099 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
10100 
10101 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
10102 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
10103 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
10104 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10105 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10106 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
10107 
10108 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
10109 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
10110 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
10111 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
10112 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
10113 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
10114 
10115 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
10116 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
10117 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
10118 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10119 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10120 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
10121 
10122 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
10123 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
10124 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
10125 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10126 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10127 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
10128 
10129 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
10130 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
10131 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
10132 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10133 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10134 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
10135 
10136 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
10137 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
10138 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
10139 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10140 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10141 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
10142 
10143 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
10144 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
10145 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
10146 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10147 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10148 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
10149 
10150 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
10151 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
10152 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
10153 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10154 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10155 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
10156 
10157 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
10158 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
10159 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
10160 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10161 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10162 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
10163 
10164 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
10165 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
10166 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
10167 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10168 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10169 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
10170 
10171 /* Bit 3 : Write '1' to disable interrupt for event END */
10172 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
10173 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10174 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10175 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10176 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
10177 
10178 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
10179 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10180 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
10181 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10182 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10183 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
10184 
10185 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
10186 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
10187 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10188 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10189 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10190 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
10191 
10192 /* Bit 0 : Write '1' to disable interrupt for event READY */
10193 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
10194 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
10195 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10196 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10197 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
10198 
10199 /* Register: RADIO_CRCSTATUS */
10200 /* Description: CRC status */
10201 
10202 /* Bit 0 : CRC status of packet received */
10203 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
10204 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
10205 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
10206 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
10207 
10208 /* Register: RADIO_RXMATCH */
10209 /* Description: Received address */
10210 
10211 /* Bits 2..0 : Received address */
10212 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
10213 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
10214 
10215 /* Register: RADIO_RXCRC */
10216 /* Description: CRC field of previously received packet */
10217 
10218 /* Bits 23..0 : CRC field of previously received packet */
10219 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
10220 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
10221 
10222 /* Register: RADIO_DAI */
10223 /* Description: Device address match index */
10224 
10225 /* Bits 2..0 : Device address match index */
10226 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
10227 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
10228 
10229 /* Register: RADIO_PDUSTAT */
10230 /* Description: Payload status */
10231 
10232 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
10233 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
10234 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
10235 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */
10236 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */
10237 
10238 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
10239 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
10240 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
10241 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
10242 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
10243 
10244 /* Register: RADIO_CTESTATUS */
10245 /* Description: CTEInfo parsed from received packet */
10246 
10247 /* Bits 7..6 : CTEType parsed from packet */
10248 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
10249 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
10250 
10251 /* Bit 5 : RFU parsed from packet */
10252 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
10253 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
10254 
10255 /* Bits 4..0 : CTETime parsed from packet */
10256 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
10257 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
10258 
10259 /* Register: RADIO_DFESTATUS */
10260 /* Description: DFE status information */
10261 
10262 /* Bit 4 : Internal state of sampling state machine */
10263 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
10264 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
10265 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
10266 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
10267 
10268 /* Bits 2..0 : Internal state of switching state machine */
10269 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
10270 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
10271 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
10272 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
10273 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
10274 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
10275 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
10276 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
10277 
10278 /* Register: RADIO_PACKETPTR */
10279 /* Description: Packet pointer */
10280 
10281 /* Bits 31..0 : Packet pointer */
10282 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
10283 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
10284 
10285 /* Register: RADIO_FREQUENCY */
10286 /* Description: Frequency */
10287 
10288 /* Bit 8 : Channel map selection */
10289 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
10290 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
10291 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
10292 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
10293 
10294 /* Bits 6..0 : Radio channel frequency */
10295 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10296 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10297 
10298 /* Register: RADIO_TXPOWER */
10299 /* Description: Output power */
10300 
10301 /* Bits 7..0 : RADIO output power */
10302 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
10303 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
10304 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
10305 #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
10306 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
10307 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
10308 #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
10309 #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
10310 #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
10311 #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
10312 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
10313 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
10314 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
10315 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
10316 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
10317 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
10318 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
10319 
10320 /* Register: RADIO_MODE */
10321 /* Description: Data rate and modulation */
10322 
10323 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
10324 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
10325 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
10326 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
10327 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
10328 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
10329 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
10330 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */
10331 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */
10332 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
10333 
10334 /* Register: RADIO_PCNF0 */
10335 /* Description: Packet configuration register 0 */
10336 
10337 /* Bits 30..29 : Length of TERM field in Long Range operation */
10338 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
10339 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
10340 
10341 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
10342 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
10343 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
10344 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
10345 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
10346 
10347 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
10348 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
10349 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
10350 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
10351 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
10352 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
10353 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */
10354 
10355 /* Bits 23..22 : Length of code indicator - long range */
10356 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
10357 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
10358 
10359 /* Bit 20 : Include or exclude S1 field in RAM */
10360 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
10361 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
10362 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
10363 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
10364 
10365 /* Bits 19..16 : Length on air of S1 field in number of bits */
10366 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
10367 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
10368 
10369 /* Bit 8 : Length on air of S0 field in number of bytes */
10370 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
10371 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
10372 
10373 /* Bits 3..0 : Length on air of LENGTH field in number of bits */
10374 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
10375 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
10376 
10377 /* Register: RADIO_PCNF1 */
10378 /* Description: Packet configuration register 1 */
10379 
10380 /* Bit 25 : Enable or disable packet whitening */
10381 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
10382 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
10383 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
10384 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
10385 
10386 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
10387 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
10388 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
10389 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
10390 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
10391 
10392 /* Bits 18..16 : Base address length in number of bytes */
10393 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
10394 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
10395 
10396 /* Bits 15..8 : Static length in number of bytes */
10397 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
10398 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
10399 
10400 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
10401 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
10402 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
10403 
10404 /* Register: RADIO_BASE0 */
10405 /* Description: Base address 0 */
10406 
10407 /* Bits 31..0 : Base address 0 */
10408 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
10409 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
10410 
10411 /* Register: RADIO_BASE1 */
10412 /* Description: Base address 1 */
10413 
10414 /* Bits 31..0 : Base address 1 */
10415 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
10416 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
10417 
10418 /* Register: RADIO_PREFIX0 */
10419 /* Description: Prefixes bytes for logical addresses 0-3 */
10420 
10421 /* Bits 31..24 : Address prefix 3. */
10422 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
10423 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
10424 
10425 /* Bits 23..16 : Address prefix 2. */
10426 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
10427 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
10428 
10429 /* Bits 15..8 : Address prefix 1. */
10430 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
10431 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
10432 
10433 /* Bits 7..0 : Address prefix 0. */
10434 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
10435 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
10436 
10437 /* Register: RADIO_PREFIX1 */
10438 /* Description: Prefixes bytes for logical addresses 4-7 */
10439 
10440 /* Bits 31..24 : Address prefix 7. */
10441 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
10442 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
10443 
10444 /* Bits 23..16 : Address prefix 6. */
10445 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
10446 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
10447 
10448 /* Bits 15..8 : Address prefix 5. */
10449 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
10450 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
10451 
10452 /* Bits 7..0 : Address prefix 4. */
10453 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
10454 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
10455 
10456 /* Register: RADIO_TXADDRESS */
10457 /* Description: Transmit address select */
10458 
10459 /* Bits 2..0 : Transmit address select */
10460 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
10461 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
10462 
10463 /* Register: RADIO_RXADDRESSES */
10464 /* Description: Receive address select */
10465 
10466 /* Bit 7 : Enable or disable reception on logical address 7. */
10467 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
10468 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
10469 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
10470 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
10471 
10472 /* Bit 6 : Enable or disable reception on logical address 6. */
10473 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
10474 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
10475 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
10476 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
10477 
10478 /* Bit 5 : Enable or disable reception on logical address 5. */
10479 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
10480 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
10481 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
10482 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
10483 
10484 /* Bit 4 : Enable or disable reception on logical address 4. */
10485 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
10486 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
10487 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
10488 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
10489 
10490 /* Bit 3 : Enable or disable reception on logical address 3. */
10491 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
10492 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
10493 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
10494 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
10495 
10496 /* Bit 2 : Enable or disable reception on logical address 2. */
10497 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
10498 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
10499 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
10500 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
10501 
10502 /* Bit 1 : Enable or disable reception on logical address 1. */
10503 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
10504 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
10505 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
10506 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
10507 
10508 /* Bit 0 : Enable or disable reception on logical address 0. */
10509 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
10510 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
10511 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
10512 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
10513 
10514 /* Register: RADIO_CRCCNF */
10515 /* Description: CRC configuration */
10516 
10517 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
10518 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
10519 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
10520 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
10521 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
10522 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
10523 
10524 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */
10525 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
10526 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
10527 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
10528 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
10529 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
10530 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
10531 
10532 /* Register: RADIO_CRCPOLY */
10533 /* Description: CRC polynomial */
10534 
10535 /* Bits 23..0 : CRC polynomial */
10536 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
10537 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
10538 
10539 /* Register: RADIO_CRCINIT */
10540 /* Description: CRC initial value */
10541 
10542 /* Bits 23..0 : CRC initial value */
10543 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
10544 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
10545 
10546 /* Register: RADIO_TIFS */
10547 /* Description: Interframe spacing in us */
10548 
10549 /* Bits 9..0 : Interframe spacing in us. */
10550 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
10551 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
10552 
10553 /* Register: RADIO_RSSISAMPLE */
10554 /* Description: RSSI sample */
10555 
10556 /* Bits 6..0 : RSSI sample. */
10557 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
10558 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
10559 
10560 /* Register: RADIO_STATE */
10561 /* Description: Current radio state */
10562 
10563 /* Bits 3..0 : Current radio state */
10564 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
10565 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
10566 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
10567 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
10568 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
10569 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
10570 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
10571 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
10572 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
10573 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
10574 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
10575 
10576 /* Register: RADIO_DATAWHITEIV */
10577 /* Description: Data whitening initial value */
10578 
10579 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
10580 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
10581 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
10582 
10583 /* Register: RADIO_BCC */
10584 /* Description: Bit counter compare */
10585 
10586 /* Bits 31..0 : Bit counter compare */
10587 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
10588 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
10589 
10590 /* Register: RADIO_DAB */
10591 /* Description: Description collection: Device address base segment n */
10592 
10593 /* Bits 31..0 : Device address base segment n */
10594 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
10595 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
10596 
10597 /* Register: RADIO_DAP */
10598 /* Description: Description collection: Device address prefix n */
10599 
10600 /* Bits 15..0 : Device address prefix n */
10601 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
10602 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
10603 
10604 /* Register: RADIO_DACNF */
10605 /* Description: Device address match configuration */
10606 
10607 /* Bit 15 : TxAdd for device address 7 */
10608 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
10609 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
10610 
10611 /* Bit 14 : TxAdd for device address 6 */
10612 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
10613 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
10614 
10615 /* Bit 13 : TxAdd for device address 5 */
10616 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
10617 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
10618 
10619 /* Bit 12 : TxAdd for device address 4 */
10620 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
10621 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
10622 
10623 /* Bit 11 : TxAdd for device address 3 */
10624 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
10625 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
10626 
10627 /* Bit 10 : TxAdd for device address 2 */
10628 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
10629 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
10630 
10631 /* Bit 9 : TxAdd for device address 1 */
10632 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
10633 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
10634 
10635 /* Bit 8 : TxAdd for device address 0 */
10636 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
10637 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
10638 
10639 /* Bit 7 : Enable or disable device address matching using device address 7 */
10640 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
10641 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
10642 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
10643 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
10644 
10645 /* Bit 6 : Enable or disable device address matching using device address 6 */
10646 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
10647 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
10648 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
10649 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
10650 
10651 /* Bit 5 : Enable or disable device address matching using device address 5 */
10652 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
10653 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
10654 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
10655 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
10656 
10657 /* Bit 4 : Enable or disable device address matching using device address 4 */
10658 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
10659 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
10660 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
10661 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
10662 
10663 /* Bit 3 : Enable or disable device address matching using device address 3 */
10664 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
10665 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
10666 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
10667 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
10668 
10669 /* Bit 2 : Enable or disable device address matching using device address 2 */
10670 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
10671 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
10672 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
10673 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
10674 
10675 /* Bit 1 : Enable or disable device address matching using device address 1 */
10676 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
10677 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
10678 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
10679 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
10680 
10681 /* Bit 0 : Enable or disable device address matching using device address 0 */
10682 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
10683 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
10684 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
10685 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
10686 
10687 /* Register: RADIO_MHRMATCHCONF */
10688 /* Description: Search pattern configuration */
10689 
10690 /* Bits 31..0 : Search pattern configuration */
10691 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
10692 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
10693 
10694 /* Register: RADIO_MHRMATCHMAS */
10695 /* Description: Pattern mask */
10696 
10697 /* Bits 31..0 : Pattern mask */
10698 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
10699 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
10700 
10701 /* Register: RADIO_MODECNF0 */
10702 /* Description: Radio mode configuration register 0 */
10703 
10704 /* Bits 9..8 : Default TX value */
10705 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
10706 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
10707 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
10708 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
10709 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
10710 
10711 /* Bit 0 : Radio ramp-up time */
10712 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
10713 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
10714 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
10715 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */
10716 
10717 /* Register: RADIO_SFD */
10718 /* Description: IEEE 802.15.4 start of frame delimiter */
10719 
10720 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
10721 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
10722 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
10723 
10724 /* Register: RADIO_EDCNT */
10725 /* Description: IEEE 802.15.4 energy detect loop count */
10726 
10727 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
10728 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
10729 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
10730 
10731 /* Register: RADIO_EDSAMPLE */
10732 /* Description: IEEE 802.15.4 energy detect level */
10733 
10734 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
10735 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
10736 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
10737 
10738 /* Register: RADIO_CCACTRL */
10739 /* Description: IEEE 802.15.4 clear channel assessment control */
10740 
10741 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
10742 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
10743 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
10744 
10745 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
10746 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
10747 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
10748 
10749 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
10750 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
10751 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
10752 
10753 /* Bits 2..0 : CCA mode of operation */
10754 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
10755 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
10756 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
10757 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
10758 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
10759 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
10760 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
10761 
10762 /* Register: RADIO_DFEMODE */
10763 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
10764 
10765 /* Bits 1..0 : Direction finding operation mode */
10766 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
10767 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
10768 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
10769 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
10770 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
10771 
10772 /* Register: RADIO_CTEINLINECONF */
10773 /* Description: Configuration for CTE inline mode */
10774 
10775 /* Bits 31..24 : S0 bit mask to set which bit to match */
10776 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
10777 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
10778 
10779 /* Bits 23..16 : S0 bit pattern to match */
10780 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
10781 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
10782 
10783 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
10784 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
10785 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
10786 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */
10787 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */
10788 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */
10789 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */
10790 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */
10791 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */
10792 
10793 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
10794 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
10795 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
10796 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */
10797 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */
10798 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */
10799 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */
10800 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */
10801 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */
10802 
10803 /* Bits 7..6 : Max range of CTETime */
10804 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
10805 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
10806 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */
10807 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */
10808 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */
10809 
10810 /* Bit 4 : Sampling/switching if CRC is not OK */
10811 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
10812 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
10813 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
10814 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
10815 
10816 /* Bit 3 : CTEInfo is S1 byte or not */
10817 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
10818 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
10819 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
10820 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
10821 
10822 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
10823 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
10824 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
10825 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
10826 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
10827 
10828 /* Register: RADIO_DFECTRL1 */
10829 /* Description: Various configuration for Direction finding */
10830 
10831 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
10832 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
10833 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
10834 
10835 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */
10836 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */
10837 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */
10838 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */
10839 
10840 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
10841 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
10842 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
10843 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */
10844 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */
10845 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */
10846 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */
10847 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */
10848 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */
10849 
10850 /* Bit 15 : Whether to sample I/Q or magnitude/phase */
10851 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
10852 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
10853 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
10854 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
10855 
10856 /* Bits 14..12 : Interval between samples in the REFERENCE period */
10857 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
10858 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
10859 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */
10860 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */
10861 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */
10862 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */
10863 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */
10864 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */
10865 
10866 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
10867 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
10868 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
10869 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */
10870 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */
10871 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */
10872 
10873 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
10874 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
10875 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
10876 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
10877 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
10878 
10879 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
10880 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
10881 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
10882 
10883 /* Register: RADIO_DFECTRL2 */
10884 /* Description: Start offset for Direction finding */
10885 
10886 /* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */
10887 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
10888 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
10889 
10890 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */
10891 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
10892 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
10893 
10894 /* Register: RADIO_SWITCHPATTERN */
10895 /* Description: GPIO patterns to be used for each antenna */
10896 
10897 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */
10898 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
10899 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
10900 
10901 /* Register: RADIO_CLEARPATTERN */
10902 /* Description: Clear the GPIO pattern array for antenna control */
10903 
10904 /* Bit 0 : Clears GPIO pattern array for antenna control */
10905 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
10906 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
10907 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
10908 
10909 /* Register: RADIO_PSEL_DFEGPIO */
10910 /* Description: Description collection: Pin select for DFE pin n */
10911 
10912 /* Bit 31 : Connection */
10913 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10914 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10915 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
10916 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10917 
10918 /* Bit 5 : Port number */
10919 #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */
10920 #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */
10921 
10922 /* Bits 4..0 : Pin number */
10923 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
10924 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
10925 
10926 /* Register: RADIO_DFEPACKET_PTR */
10927 /* Description: Data pointer */
10928 
10929 /* Bits 31..0 : Data pointer */
10930 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10931 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10932 
10933 /* Register: RADIO_DFEPACKET_MAXCNT */
10934 /* Description: Maximum number of buffer words to transfer */
10935 
10936 /* Bits 13..0 : Maximum number of buffer words to transfer */
10937 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10938 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10939 
10940 /* Register: RADIO_DFEPACKET_AMOUNT */
10941 /* Description: Number of samples transferred in the last transaction */
10942 
10943 /* Bits 15..0 : Number of samples transferred in the last transaction */
10944 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10945 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10946 
10947 /* Register: RADIO_POWER */
10948 /* Description: Peripheral power control */
10949 
10950 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
10951 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
10952 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
10953 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
10954 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
10955 
10956 
10957 /* Peripheral: RNG */
10958 /* Description: Random Number Generator */
10959 
10960 /* Register: RNG_TASKS_START */
10961 /* Description: Task starting the random number generator */
10962 
10963 /* Bit 0 : Task starting the random number generator */
10964 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10965 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10966 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10967 
10968 /* Register: RNG_TASKS_STOP */
10969 /* Description: Task stopping the random number generator */
10970 
10971 /* Bit 0 : Task stopping the random number generator */
10972 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10973 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10974 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10975 
10976 /* Register: RNG_EVENTS_VALRDY */
10977 /* Description: Event being generated for every new random number written to the VALUE register */
10978 
10979 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
10980 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
10981 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
10982 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
10983 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
10984 
10985 /* Register: RNG_SHORTS */
10986 /* Description: Shortcuts between local events and tasks */
10987 
10988 /* Bit 0 : Shortcut between event VALRDY and task STOP */
10989 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
10990 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
10991 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
10992 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
10993 
10994 /* Register: RNG_INTENSET */
10995 /* Description: Enable interrupt */
10996 
10997 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
10998 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
10999 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
11000 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11001 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11002 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
11003 
11004 /* Register: RNG_INTENCLR */
11005 /* Description: Disable interrupt */
11006 
11007 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
11008 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
11009 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
11010 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11011 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11012 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
11013 
11014 /* Register: RNG_CONFIG */
11015 /* Description: Configuration register */
11016 
11017 /* Bit 0 : Bias correction */
11018 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
11019 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
11020 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
11021 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
11022 
11023 /* Register: RNG_VALUE */
11024 /* Description: Output random number */
11025 
11026 /* Bits 7..0 : Generated random number */
11027 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
11028 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
11029 
11030 
11031 /* Peripheral: RTC */
11032 /* Description: Real time counter 0 */
11033 
11034 /* Register: RTC_TASKS_START */
11035 /* Description: Start RTC COUNTER */
11036 
11037 /* Bit 0 : Start RTC COUNTER */
11038 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11039 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11040 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11041 
11042 /* Register: RTC_TASKS_STOP */
11043 /* Description: Stop RTC COUNTER */
11044 
11045 /* Bit 0 : Stop RTC COUNTER */
11046 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11047 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11048 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11049 
11050 /* Register: RTC_TASKS_CLEAR */
11051 /* Description: Clear RTC COUNTER */
11052 
11053 /* Bit 0 : Clear RTC COUNTER */
11054 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
11055 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
11056 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
11057 
11058 /* Register: RTC_TASKS_TRIGOVRFLW */
11059 /* Description: Set COUNTER to 0xFFFFF0 */
11060 
11061 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
11062 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
11063 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
11064 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
11065 
11066 /* Register: RTC_EVENTS_TICK */
11067 /* Description: Event on COUNTER increment */
11068 
11069 /* Bit 0 : Event on COUNTER increment */
11070 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
11071 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
11072 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
11073 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
11074 
11075 /* Register: RTC_EVENTS_OVRFLW */
11076 /* Description: Event on COUNTER overflow */
11077 
11078 /* Bit 0 : Event on COUNTER overflow */
11079 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
11080 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
11081 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
11082 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
11083 
11084 /* Register: RTC_EVENTS_COMPARE */
11085 /* Description: Description collection: Compare event on CC[n] match */
11086 
11087 /* Bit 0 : Compare event on CC[n] match */
11088 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
11089 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
11090 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
11091 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
11092 
11093 /* Register: RTC_INTENSET */
11094 /* Description: Enable interrupt */
11095 
11096 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
11097 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11098 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11099 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11100 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11101 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
11102 
11103 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
11104 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11105 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11106 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11107 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11108 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
11109 
11110 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
11111 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11112 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11113 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11114 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11115 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
11116 
11117 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
11118 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11119 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11120 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11121 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11122 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
11123 
11124 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
11125 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11126 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11127 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11128 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11129 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
11130 
11131 /* Bit 0 : Write '1' to enable interrupt for event TICK */
11132 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11133 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11134 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11135 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11136 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
11137 
11138 /* Register: RTC_INTENCLR */
11139 /* Description: Disable interrupt */
11140 
11141 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
11142 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11143 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11144 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11145 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11146 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11147 
11148 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
11149 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11150 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11151 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11152 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11153 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11154 
11155 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
11156 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11157 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11158 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11159 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11160 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11161 
11162 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
11163 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11164 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11165 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11166 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11167 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11168 
11169 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
11170 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11171 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11172 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11173 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11174 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11175 
11176 /* Bit 0 : Write '1' to disable interrupt for event TICK */
11177 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11178 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11179 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11180 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11181 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
11182 
11183 /* Register: RTC_EVTEN */
11184 /* Description: Enable or disable event routing */
11185 
11186 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
11187 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11188 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11189 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
11190 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
11191 
11192 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
11193 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11194 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11195 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
11196 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
11197 
11198 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
11199 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11200 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11201 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
11202 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
11203 
11204 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
11205 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11206 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11207 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
11208 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
11209 
11210 /* Bit 1 : Enable or disable event routing for event OVRFLW */
11211 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11212 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11213 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
11214 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
11215 
11216 /* Bit 0 : Enable or disable event routing for event TICK */
11217 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
11218 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
11219 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
11220 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
11221 
11222 /* Register: RTC_EVTENSET */
11223 /* Description: Enable event routing */
11224 
11225 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
11226 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11227 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11228 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11229 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11230 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
11231 
11232 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
11233 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11234 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11235 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11236 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11237 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
11238 
11239 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
11240 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11241 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11242 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11243 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11244 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
11245 
11246 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
11247 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11248 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11249 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11250 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11251 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
11252 
11253 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
11254 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11255 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11256 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11257 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11258 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
11259 
11260 /* Bit 0 : Write '1' to enable event routing for event TICK */
11261 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11262 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11263 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11264 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11265 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
11266 
11267 /* Register: RTC_EVTENCLR */
11268 /* Description: Disable event routing */
11269 
11270 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
11271 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11272 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11273 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11274 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11275 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11276 
11277 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
11278 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11279 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11280 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11281 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11282 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11283 
11284 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
11285 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11286 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11287 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11288 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11289 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11290 
11291 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
11292 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11293 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11294 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11295 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11296 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11297 
11298 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
11299 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11300 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11301 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11302 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11303 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11304 
11305 /* Bit 0 : Write '1' to disable event routing for event TICK */
11306 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11307 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11308 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11309 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11310 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
11311 
11312 /* Register: RTC_COUNTER */
11313 /* Description: Current COUNTER value */
11314 
11315 /* Bits 23..0 : Counter value */
11316 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
11317 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
11318 
11319 /* Register: RTC_PRESCALER */
11320 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
11321 
11322 /* Bits 11..0 : Prescaler value */
11323 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
11324 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
11325 
11326 /* Register: RTC_CC */
11327 /* Description: Description collection: Compare register n */
11328 
11329 /* Bits 23..0 : Compare value */
11330 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
11331 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
11332 
11333 
11334 /* Peripheral: SAADC */
11335 /* Description: Successive approximation register (SAR) analog-to-digital converter */
11336 
11337 /* Register: SAADC_TASKS_START */
11338 /* Description: Starts the SAADC and prepares the result buffer in RAM */
11339 
11340 /* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */
11341 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11342 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11343 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11344 
11345 /* Register: SAADC_TASKS_SAMPLE */
11346 /* Description: Takes one SAADC sample */
11347 
11348 /* Bit 0 : Takes one SAADC sample */
11349 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
11350 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
11351 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
11352 
11353 /* Register: SAADC_TASKS_STOP */
11354 /* Description: Stops the SAADC and terminates all on-going conversions */
11355 
11356 /* Bit 0 : Stops the SAADC and terminates all on-going conversions */
11357 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11358 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11359 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11360 
11361 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
11362 /* Description: Starts offset auto-calibration */
11363 
11364 /* Bit 0 : Starts offset auto-calibration */
11365 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
11366 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
11367 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
11368 
11369 /* Register: SAADC_EVENTS_STARTED */
11370 /* Description: The SAADC has started */
11371 
11372 /* Bit 0 : The SAADC has started */
11373 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
11374 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
11375 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
11376 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
11377 
11378 /* Register: SAADC_EVENTS_END */
11379 /* Description: The SAADC has filled up the result buffer */
11380 
11381 /* Bit 0 : The SAADC has filled up the result buffer */
11382 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11383 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11384 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
11385 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
11386 
11387 /* Register: SAADC_EVENTS_DONE */
11388 /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
11389 
11390 /* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
11391 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
11392 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
11393 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
11394 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
11395 
11396 /* Register: SAADC_EVENTS_RESULTDONE */
11397 /* Description: Result ready for transfer to RAM */
11398 
11399 /* Bit 0 : Result ready for transfer to RAM */
11400 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
11401 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
11402 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
11403 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
11404 
11405 /* Register: SAADC_EVENTS_CALIBRATEDONE */
11406 /* Description: Calibration is complete */
11407 
11408 /* Bit 0 : Calibration is complete */
11409 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
11410 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
11411 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
11412 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
11413 
11414 /* Register: SAADC_EVENTS_STOPPED */
11415 /* Description: The SAADC has stopped */
11416 
11417 /* Bit 0 : The SAADC has stopped */
11418 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11419 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11420 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
11421 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
11422 
11423 /* Register: SAADC_EVENTS_CH_LIMITH */
11424 /* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */
11425 
11426 /* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */
11427 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
11428 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
11429 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
11430 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
11431 
11432 /* Register: SAADC_EVENTS_CH_LIMITL */
11433 /* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */
11434 
11435 /* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */
11436 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
11437 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
11438 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
11439 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
11440 
11441 /* Register: SAADC_INTEN */
11442 /* Description: Enable or disable interrupt */
11443 
11444 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
11445 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11446 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11447 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
11448 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
11449 
11450 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
11451 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11452 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11453 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
11454 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
11455 
11456 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
11457 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11458 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11459 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
11460 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
11461 
11462 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
11463 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11464 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11465 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
11466 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
11467 
11468 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
11469 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11470 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11471 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
11472 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
11473 
11474 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
11475 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11476 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11477 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
11478 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
11479 
11480 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
11481 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11482 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11483 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
11484 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
11485 
11486 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
11487 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11488 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11489 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
11490 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
11491 
11492 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
11493 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11494 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11495 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
11496 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
11497 
11498 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
11499 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11500 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11501 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
11502 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
11503 
11504 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
11505 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11506 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11507 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
11508 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
11509 
11510 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
11511 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11512 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11513 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
11514 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
11515 
11516 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
11517 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11518 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11519 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
11520 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
11521 
11522 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
11523 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11524 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11525 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
11526 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
11527 
11528 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
11529 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11530 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11531 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
11532 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
11533 
11534 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
11535 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11536 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11537 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
11538 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
11539 
11540 /* Bit 5 : Enable or disable interrupt for event STOPPED */
11541 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11542 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11543 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11544 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11545 
11546 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
11547 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11548 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11549 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
11550 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
11551 
11552 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
11553 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11554 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11555 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
11556 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
11557 
11558 /* Bit 2 : Enable or disable interrupt for event DONE */
11559 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
11560 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
11561 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
11562 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
11563 
11564 /* Bit 1 : Enable or disable interrupt for event END */
11565 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
11566 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
11567 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
11568 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
11569 
11570 /* Bit 0 : Enable or disable interrupt for event STARTED */
11571 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11572 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
11573 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
11574 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
11575 
11576 /* Register: SAADC_INTENSET */
11577 /* Description: Enable interrupt */
11578 
11579 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
11580 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11581 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11582 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11583 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11584 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
11585 
11586 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
11587 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11588 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11589 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11590 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11591 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
11592 
11593 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
11594 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11595 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11596 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11597 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11598 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
11599 
11600 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
11601 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11602 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11603 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11604 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11605 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
11606 
11607 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
11608 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11609 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11610 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11611 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11612 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
11613 
11614 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
11615 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11616 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11617 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11618 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11619 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
11620 
11621 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
11622 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11623 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11624 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11625 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11626 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
11627 
11628 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
11629 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11630 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11631 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11632 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11633 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
11634 
11635 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
11636 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11637 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11638 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11639 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11640 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
11641 
11642 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
11643 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11644 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11645 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11646 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11647 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
11648 
11649 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
11650 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11651 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11652 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11653 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11654 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
11655 
11656 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
11657 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11658 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11659 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11660 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11661 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
11662 
11663 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
11664 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11665 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11666 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11667 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11668 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
11669 
11670 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
11671 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11672 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11673 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11674 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11675 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
11676 
11677 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
11678 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11679 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11680 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11681 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11682 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
11683 
11684 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
11685 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11686 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11687 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11688 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11689 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
11690 
11691 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
11692 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11693 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11694 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11695 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11696 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11697 
11698 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
11699 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11700 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11701 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11702 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11703 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
11704 
11705 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
11706 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11707 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11708 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11709 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11710 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
11711 
11712 /* Bit 2 : Write '1' to enable interrupt for event DONE */
11713 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
11714 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
11715 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
11716 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
11717 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
11718 
11719 /* Bit 1 : Write '1' to enable interrupt for event END */
11720 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
11721 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
11722 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11723 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11724 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
11725 
11726 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
11727 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11728 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11729 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11730 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11731 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
11732 
11733 /* Register: SAADC_INTENCLR */
11734 /* Description: Disable interrupt */
11735 
11736 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
11737 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11738 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11739 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11740 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11741 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
11742 
11743 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
11744 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11745 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11746 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11747 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11748 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
11749 
11750 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
11751 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11752 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11753 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11754 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11755 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
11756 
11757 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
11758 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11759 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11760 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11761 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11762 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
11763 
11764 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
11765 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11766 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11767 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11768 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11769 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
11770 
11771 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
11772 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11773 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11774 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11775 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11776 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
11777 
11778 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
11779 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11780 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11781 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11782 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11783 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
11784 
11785 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
11786 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11787 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11788 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11789 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11790 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
11791 
11792 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
11793 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11794 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11795 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11796 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11797 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
11798 
11799 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
11800 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11801 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11802 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11803 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11804 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
11805 
11806 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
11807 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11808 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11809 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11810 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11811 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
11812 
11813 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
11814 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11815 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11816 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11817 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11818 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
11819 
11820 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
11821 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11822 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11823 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11824 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11825 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
11826 
11827 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
11828 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11829 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11830 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11831 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11832 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
11833 
11834 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
11835 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11836 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11837 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11838 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11839 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
11840 
11841 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
11842 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11843 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11844 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11845 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11846 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
11847 
11848 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
11849 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11850 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11851 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11852 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11853 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11854 
11855 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
11856 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11857 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11858 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11859 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11860 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
11861 
11862 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
11863 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11864 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11865 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11866 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11867 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
11868 
11869 /* Bit 2 : Write '1' to disable interrupt for event DONE */
11870 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
11871 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
11872 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
11873 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
11874 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
11875 
11876 /* Bit 1 : Write '1' to disable interrupt for event END */
11877 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
11878 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11879 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11880 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11881 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
11882 
11883 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
11884 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11885 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
11886 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11887 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
11888 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
11889 
11890 /* Register: SAADC_STATUS */
11891 /* Description: Status */
11892 
11893 /* Bit 0 : Status */
11894 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
11895 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
11896 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */
11897 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */
11898 
11899 /* Register: SAADC_ENABLE */
11900 /* Description: Enable or disable SAADC */
11901 
11902 /* Bit 0 : Enable or disable SAADC */
11903 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11904 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11905 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */
11906 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */
11907 
11908 /* Register: SAADC_CH_PSELP */
11909 /* Description: Description cluster: Input positive pin selection for CH[n] */
11910 
11911 /* Bits 4..0 : Analog positive input channel */
11912 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
11913 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
11914 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
11915 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
11916 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
11917 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
11918 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
11919 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
11920 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
11921 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
11922 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
11923 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
11924 #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
11925 
11926 /* Register: SAADC_CH_PSELN */
11927 /* Description: Description cluster: Input negative pin selection for CH[n] */
11928 
11929 /* Bits 4..0 : Analog negative input, enables differential channel */
11930 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
11931 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
11932 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
11933 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
11934 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
11935 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
11936 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
11937 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
11938 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
11939 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
11940 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
11941 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
11942 #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
11943 
11944 /* Register: SAADC_CH_CONFIG */
11945 /* Description: Description cluster: Input configuration for CH[n] */
11946 
11947 /* Bit 24 : Enable burst mode */
11948 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
11949 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
11950 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
11951 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
11952 
11953 /* Bit 20 : Enable differential mode */
11954 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
11955 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
11956 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */
11957 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
11958 
11959 /* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */
11960 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
11961 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
11962 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
11963 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
11964 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
11965 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
11966 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
11967 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
11968 
11969 /* Bit 12 : Reference control */
11970 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
11971 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
11972 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
11973 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
11974 
11975 /* Bits 10..8 : Gain control */
11976 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
11977 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
11978 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
11979 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
11980 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
11981 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
11982 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
11983 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
11984 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
11985 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
11986 
11987 /* Bits 5..4 : Negative channel resistor control */
11988 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
11989 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
11990 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
11991 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
11992 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
11993 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
11994 
11995 /* Bits 1..0 : Positive channel resistor control */
11996 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
11997 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
11998 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
11999 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
12000 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12001 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12002 
12003 /* Register: SAADC_CH_LIMIT */
12004 /* Description: Description cluster: High/low limits for event monitoring of a channel */
12005 
12006 /* Bits 31..16 : High level limit */
12007 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
12008 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
12009 
12010 /* Bits 15..0 : Low level limit */
12011 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
12012 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
12013 
12014 /* Register: SAADC_RESOLUTION */
12015 /* Description: Resolution configuration */
12016 
12017 /* Bits 2..0 : Set the resolution */
12018 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
12019 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
12020 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */
12021 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */
12022 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */
12023 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */
12024 
12025 /* Register: SAADC_OVERSAMPLE */
12026 /* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
12027 
12028 /* Bits 3..0 : Oversample control */
12029 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
12030 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
12031 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
12032 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
12033 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
12034 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
12035 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
12036 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
12037 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
12038 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
12039 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
12040 
12041 /* Register: SAADC_SAMPLERATE */
12042 /* Description: Controls normal or continuous sample rate */
12043 
12044 /* Bit 12 : Select mode for sample rate control */
12045 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
12046 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
12047 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
12048 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
12049 
12050 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
12051 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
12052 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
12053 
12054 /* Register: SAADC_RESULT_PTR */
12055 /* Description: Data pointer */
12056 
12057 /* Bits 31..0 : Data pointer */
12058 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12059 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12060 
12061 /* Register: SAADC_RESULT_MAXCNT */
12062 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
12063 
12064 /* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
12065 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12066 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12067 
12068 /* Register: SAADC_RESULT_AMOUNT */
12069 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */
12070 
12071 /* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */
12072 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12073 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12074 
12075 
12076 /* Peripheral: SPI */
12077 /* Description: Serial Peripheral Interface 0 */
12078 
12079 /* Register: SPI_EVENTS_READY */
12080 /* Description: TXD byte sent and RXD byte received */
12081 
12082 /* Bit 0 : TXD byte sent and RXD byte received */
12083 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
12084 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
12085 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
12086 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
12087 
12088 /* Register: SPI_INTENSET */
12089 /* Description: Enable interrupt */
12090 
12091 /* Bit 2 : Write '1' to enable interrupt for event READY */
12092 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
12093 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
12094 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
12095 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
12096 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
12097 
12098 /* Register: SPI_INTENCLR */
12099 /* Description: Disable interrupt */
12100 
12101 /* Bit 2 : Write '1' to disable interrupt for event READY */
12102 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
12103 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
12104 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
12105 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
12106 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
12107 
12108 /* Register: SPI_ENABLE */
12109 /* Description: Enable SPI */
12110 
12111 /* Bits 3..0 : Enable or disable SPI */
12112 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12113 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12114 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
12115 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
12116 
12117 /* Register: SPI_PSEL_SCK */
12118 /* Description: Pin select for SCK */
12119 
12120 /* Bit 31 : Connection */
12121 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12122 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12123 #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12124 #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12125 
12126 /* Bit 5 : Port number */
12127 #define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12128 #define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12129 
12130 /* Bits 4..0 : Pin number */
12131 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12132 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12133 
12134 /* Register: SPI_PSEL_MOSI */
12135 /* Description: Pin select for MOSI signal */
12136 
12137 /* Bit 31 : Connection */
12138 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12139 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12140 #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12141 #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12142 
12143 /* Bit 5 : Port number */
12144 #define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12145 #define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12146 
12147 /* Bits 4..0 : Pin number */
12148 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12149 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12150 
12151 /* Register: SPI_PSEL_MISO */
12152 /* Description: Pin select for MISO signal */
12153 
12154 /* Bit 31 : Connection */
12155 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12156 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12157 #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12158 #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12159 
12160 /* Bit 5 : Port number */
12161 #define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12162 #define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12163 
12164 /* Bits 4..0 : Pin number */
12165 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12166 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12167 
12168 /* Register: SPI_RXD */
12169 /* Description: RXD register */
12170 
12171 /* Bits 7..0 : RX data received. Double buffered */
12172 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
12173 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
12174 
12175 /* Register: SPI_TXD */
12176 /* Description: TXD register */
12177 
12178 /* Bits 7..0 : TX data to send. Double buffered. */
12179 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
12180 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
12181 
12182 /* Register: SPI_FREQUENCY */
12183 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12184 
12185 /* Bits 31..0 : SPI master data rate */
12186 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12187 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12188 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
12189 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12190 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
12191 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12192 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12193 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12194 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12195 
12196 /* Register: SPI_CONFIG */
12197 /* Description: Configuration register */
12198 
12199 /* Bit 2 : Serial clock (SCK) polarity */
12200 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12201 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12202 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12203 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12204 
12205 /* Bit 1 : Serial clock (SCK) phase */
12206 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12207 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12208 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12209 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12210 
12211 /* Bit 0 : Bit order */
12212 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12213 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12214 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12215 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12216 
12217 
12218 /* Peripheral: SPIM */
12219 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
12220 
12221 /* Register: SPIM_TASKS_START */
12222 /* Description: Start SPI transaction */
12223 
12224 /* Bit 0 : Start SPI transaction */
12225 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12226 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12227 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12228 
12229 /* Register: SPIM_TASKS_STOP */
12230 /* Description: Stop SPI transaction */
12231 
12232 /* Bit 0 : Stop SPI transaction */
12233 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12234 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12235 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12236 
12237 /* Register: SPIM_TASKS_SUSPEND */
12238 /* Description: Suspend SPI transaction */
12239 
12240 /* Bit 0 : Suspend SPI transaction */
12241 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
12242 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
12243 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
12244 
12245 /* Register: SPIM_TASKS_RESUME */
12246 /* Description: Resume SPI transaction */
12247 
12248 /* Bit 0 : Resume SPI transaction */
12249 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
12250 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
12251 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
12252 
12253 /* Register: SPIM_EVENTS_STOPPED */
12254 /* Description: SPI transaction has stopped */
12255 
12256 /* Bit 0 : SPI transaction has stopped */
12257 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12258 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12259 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12260 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12261 
12262 /* Register: SPIM_EVENTS_ENDRX */
12263 /* Description: End of RXD buffer reached */
12264 
12265 /* Bit 0 : End of RXD buffer reached */
12266 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
12267 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
12268 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
12269 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
12270 
12271 /* Register: SPIM_EVENTS_END */
12272 /* Description: End of RXD buffer and TXD buffer reached */
12273 
12274 /* Bit 0 : End of RXD buffer and TXD buffer reached */
12275 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
12276 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
12277 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
12278 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
12279 
12280 /* Register: SPIM_EVENTS_ENDTX */
12281 /* Description: End of TXD buffer reached */
12282 
12283 /* Bit 0 : End of TXD buffer reached */
12284 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
12285 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
12286 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
12287 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
12288 
12289 /* Register: SPIM_EVENTS_STARTED */
12290 /* Description: Transaction started */
12291 
12292 /* Bit 0 : Transaction started */
12293 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
12294 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
12295 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
12296 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
12297 
12298 /* Register: SPIM_SHORTS */
12299 /* Description: Shortcuts between local events and tasks */
12300 
12301 /* Bit 17 : Shortcut between event END and task START */
12302 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
12303 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
12304 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
12305 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
12306 
12307 /* Register: SPIM_INTENSET */
12308 /* Description: Enable interrupt */
12309 
12310 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
12311 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12312 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
12313 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12314 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12315 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
12316 
12317 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
12318 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12319 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12320 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12321 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12322 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12323 
12324 /* Bit 6 : Write '1' to enable interrupt for event END */
12325 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
12326 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
12327 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12328 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12329 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
12330 
12331 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
12332 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12333 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12334 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12335 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12336 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12337 
12338 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12339 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12340 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12341 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12342 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12343 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12344 
12345 /* Register: SPIM_INTENCLR */
12346 /* Description: Disable interrupt */
12347 
12348 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
12349 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12350 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
12351 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12352 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12353 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12354 
12355 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
12356 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12357 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12358 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12359 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12360 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12361 
12362 /* Bit 6 : Write '1' to disable interrupt for event END */
12363 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
12364 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12365 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12366 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12367 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
12368 
12369 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12370 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12371 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12372 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12373 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12374 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12375 
12376 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12377 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12378 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12379 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12380 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12381 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12382 
12383 /* Register: SPIM_STALLSTAT */
12384 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */
12385 
12386 /* Bit 1 : Stall status for EasyDMA RAM writes */
12387 #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
12388 #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
12389 #define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
12390 #define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
12391 
12392 /* Bit 0 : Stall status for EasyDMA RAM reads */
12393 #define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
12394 #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
12395 #define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
12396 #define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
12397 
12398 /* Register: SPIM_ENABLE */
12399 /* Description: Enable SPIM */
12400 
12401 /* Bits 3..0 : Enable or disable SPIM */
12402 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12403 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12404 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
12405 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
12406 
12407 /* Register: SPIM_PSEL_SCK */
12408 /* Description: Pin select for SCK */
12409 
12410 /* Bit 31 : Connection */
12411 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12412 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12413 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12414 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12415 
12416 /* Bit 5 : Port number */
12417 #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12418 #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12419 
12420 /* Bits 4..0 : Pin number */
12421 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12422 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12423 
12424 /* Register: SPIM_PSEL_MOSI */
12425 /* Description: Pin select for MOSI signal */
12426 
12427 /* Bit 31 : Connection */
12428 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12429 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12430 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12431 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12432 
12433 /* Bit 5 : Port number */
12434 #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12435 #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12436 
12437 /* Bits 4..0 : Pin number */
12438 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12439 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12440 
12441 /* Register: SPIM_PSEL_MISO */
12442 /* Description: Pin select for MISO signal */
12443 
12444 /* Bit 31 : Connection */
12445 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12446 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12447 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12448 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12449 
12450 /* Bit 5 : Port number */
12451 #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12452 #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12453 
12454 /* Bits 4..0 : Pin number */
12455 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12456 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12457 
12458 /* Register: SPIM_PSEL_CSN */
12459 /* Description: Pin select for CSN */
12460 
12461 /* Bit 31 : Connection */
12462 #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12463 #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12464 #define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
12465 #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
12466 
12467 /* Bit 5 : Port number */
12468 #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
12469 #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
12470 
12471 /* Bits 4..0 : Pin number */
12472 #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
12473 #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
12474 
12475 /* Register: SPIM_FREQUENCY */
12476 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12477 
12478 /* Bits 31..0 : SPI master data rate */
12479 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12480 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12481 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
12482 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12483 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
12484 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
12485 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12486 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
12487 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12488 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12489 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12490 
12491 /* Register: SPIM_RXD_PTR */
12492 /* Description: Data pointer */
12493 
12494 /* Bits 31..0 : Data pointer */
12495 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12496 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12497 
12498 /* Register: SPIM_RXD_MAXCNT */
12499 /* Description: Maximum number of bytes in receive buffer */
12500 
12501 /* Bits 15..0 : Maximum number of bytes in receive buffer */
12502 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12503 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12504 
12505 /* Register: SPIM_RXD_AMOUNT */
12506 /* Description: Number of bytes transferred in the last transaction */
12507 
12508 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12509 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12510 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12511 
12512 /* Register: SPIM_RXD_LIST */
12513 /* Description: EasyDMA list type */
12514 
12515 /* Bits 1..0 : List type */
12516 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12517 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12518 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12519 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12520 
12521 /* Register: SPIM_TXD_PTR */
12522 /* Description: Data pointer */
12523 
12524 /* Bits 31..0 : Data pointer */
12525 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12526 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12527 
12528 /* Register: SPIM_TXD_MAXCNT */
12529 /* Description: Number of bytes in transmit buffer */
12530 
12531 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
12532 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12533 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12534 
12535 /* Register: SPIM_TXD_AMOUNT */
12536 /* Description: Number of bytes transferred in the last transaction */
12537 
12538 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12539 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12540 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12541 
12542 /* Register: SPIM_TXD_LIST */
12543 /* Description: EasyDMA list type */
12544 
12545 /* Bits 1..0 : List type */
12546 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12547 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12548 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12549 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12550 
12551 /* Register: SPIM_CONFIG */
12552 /* Description: Configuration register */
12553 
12554 /* Bit 2 : Serial clock (SCK) polarity */
12555 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12556 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12557 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12558 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12559 
12560 /* Bit 1 : Serial clock (SCK) phase */
12561 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12562 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12563 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12564 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12565 
12566 /* Bit 0 : Bit order */
12567 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12568 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12569 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12570 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12571 
12572 /* Register: SPIM_IFTIMING_RXDELAY */
12573 /* Description: Sample delay for input serial data on MISO */
12574 
12575 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
12576 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
12577 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
12578 
12579 /* Register: SPIM_IFTIMING_CSNDUR */
12580 /* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */
12581 
12582 /* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
12583 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
12584 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
12585 
12586 /* Register: SPIM_CSNPOL */
12587 /* Description: Polarity of CSN output */
12588 
12589 /* Bit 0 : Polarity of CSN output */
12590 #define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
12591 #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
12592 #define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
12593 #define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
12594 
12595 /* Register: SPIM_PSELDCX */
12596 /* Description: Pin select for DCX signal */
12597 
12598 /* Bit 31 : Connection */
12599 #define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12600 #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12601 #define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
12602 #define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
12603 
12604 /* Bit 5 : Port number */
12605 #define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
12606 #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
12607 
12608 /* Bits 4..0 : Pin number */
12609 #define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
12610 #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
12611 
12612 /* Register: SPIM_DCXCNT */
12613 /* Description: DCX configuration */
12614 
12615 /* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
12616 #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
12617 #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
12618 
12619 /* Register: SPIM_ORC */
12620 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
12621 
12622 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
12623 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
12624 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
12625 
12626 
12627 /* Peripheral: SPIS */
12628 /* Description: SPI Slave 0 */
12629 
12630 /* Register: SPIS_TASKS_ACQUIRE */
12631 /* Description: Acquire SPI semaphore */
12632 
12633 /* Bit 0 : Acquire SPI semaphore */
12634 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
12635 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
12636 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
12637 
12638 /* Register: SPIS_TASKS_RELEASE */
12639 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
12640 
12641 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
12642 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
12643 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
12644 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
12645 
12646 /* Register: SPIS_EVENTS_END */
12647 /* Description: Granted transaction completed */
12648 
12649 /* Bit 0 : Granted transaction completed */
12650 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
12651 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
12652 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
12653 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
12654 
12655 /* Register: SPIS_EVENTS_ENDRX */
12656 /* Description: End of RXD buffer reached */
12657 
12658 /* Bit 0 : End of RXD buffer reached */
12659 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
12660 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
12661 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
12662 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
12663 
12664 /* Register: SPIS_EVENTS_ACQUIRED */
12665 /* Description: Semaphore acquired */
12666 
12667 /* Bit 0 : Semaphore acquired */
12668 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
12669 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
12670 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
12671 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
12672 
12673 /* Register: SPIS_SHORTS */
12674 /* Description: Shortcuts between local events and tasks */
12675 
12676 /* Bit 2 : Shortcut between event END and task ACQUIRE */
12677 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
12678 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
12679 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
12680 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
12681 
12682 /* Register: SPIS_INTENSET */
12683 /* Description: Enable interrupt */
12684 
12685 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
12686 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
12687 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
12688 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12689 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12690 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
12691 
12692 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
12693 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12694 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12695 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12696 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12697 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12698 
12699 /* Bit 1 : Write '1' to enable interrupt for event END */
12700 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
12701 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
12702 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12703 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12704 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
12705 
12706 /* Register: SPIS_INTENCLR */
12707 /* Description: Disable interrupt */
12708 
12709 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
12710 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
12711 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
12712 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12713 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12714 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
12715 
12716 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12717 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12718 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12719 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12720 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12721 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12722 
12723 /* Bit 1 : Write '1' to disable interrupt for event END */
12724 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
12725 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12726 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12727 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12728 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
12729 
12730 /* Register: SPIS_SEMSTAT */
12731 /* Description: Semaphore status register */
12732 
12733 /* Bits 1..0 : Semaphore status */
12734 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
12735 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
12736 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
12737 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
12738 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
12739 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
12740 
12741 /* Register: SPIS_STATUS */
12742 /* Description: Status from last transaction */
12743 
12744 /* Bit 1 : RX buffer overflow detected, and prevented */
12745 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
12746 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
12747 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
12748 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
12749 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
12750 
12751 /* Bit 0 : TX buffer over-read detected, and prevented */
12752 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
12753 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
12754 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
12755 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
12756 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
12757 
12758 /* Register: SPIS_ENABLE */
12759 /* Description: Enable SPI slave */
12760 
12761 /* Bits 3..0 : Enable or disable SPI slave */
12762 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12763 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12764 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
12765 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
12766 
12767 /* Register: SPIS_PSEL_SCK */
12768 /* Description: Pin select for SCK */
12769 
12770 /* Bit 31 : Connection */
12771 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12772 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12773 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12774 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12775 
12776 /* Bit 5 : Port number */
12777 #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12778 #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12779 
12780 /* Bits 4..0 : Pin number */
12781 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12782 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12783 
12784 /* Register: SPIS_PSEL_MISO */
12785 /* Description: Pin select for MISO signal */
12786 
12787 /* Bit 31 : Connection */
12788 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12789 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12790 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12791 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12792 
12793 /* Bit 5 : Port number */
12794 #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12795 #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12796 
12797 /* Bits 4..0 : Pin number */
12798 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12799 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12800 
12801 /* Register: SPIS_PSEL_MOSI */
12802 /* Description: Pin select for MOSI signal */
12803 
12804 /* Bit 31 : Connection */
12805 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12806 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12807 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12808 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12809 
12810 /* Bit 5 : Port number */
12811 #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12812 #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12813 
12814 /* Bits 4..0 : Pin number */
12815 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12816 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12817 
12818 /* Register: SPIS_PSEL_CSN */
12819 /* Description: Pin select for CSN signal */
12820 
12821 /* Bit 31 : Connection */
12822 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12823 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12824 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
12825 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
12826 
12827 /* Bit 5 : Port number */
12828 #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
12829 #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
12830 
12831 /* Bits 4..0 : Pin number */
12832 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
12833 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
12834 
12835 /* Register: SPIS_RXD_PTR */
12836 /* Description: RXD data pointer */
12837 
12838 /* Bits 31..0 : RXD data pointer */
12839 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12840 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12841 
12842 /* Register: SPIS_RXD_MAXCNT */
12843 /* Description: Maximum number of bytes in receive buffer */
12844 
12845 /* Bits 15..0 : Maximum number of bytes in receive buffer */
12846 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12847 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12848 
12849 /* Register: SPIS_RXD_AMOUNT */
12850 /* Description: Number of bytes received in last granted transaction */
12851 
12852 /* Bits 15..0 : Number of bytes received in the last granted transaction */
12853 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12854 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12855 
12856 /* Register: SPIS_RXD_LIST */
12857 /* Description: EasyDMA list type */
12858 
12859 /* Bits 1..0 : List type */
12860 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12861 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12862 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12863 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12864 
12865 /* Register: SPIS_TXD_PTR */
12866 /* Description: TXD data pointer */
12867 
12868 /* Bits 31..0 : TXD data pointer */
12869 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12870 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12871 
12872 /* Register: SPIS_TXD_MAXCNT */
12873 /* Description: Maximum number of bytes in transmit buffer */
12874 
12875 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
12876 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12877 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12878 
12879 /* Register: SPIS_TXD_AMOUNT */
12880 /* Description: Number of bytes transmitted in last granted transaction */
12881 
12882 /* Bits 15..0 : Number of bytes transmitted in last granted transaction */
12883 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12884 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12885 
12886 /* Register: SPIS_TXD_LIST */
12887 /* Description: EasyDMA list type */
12888 
12889 /* Bits 1..0 : List type */
12890 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12891 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12892 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12893 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12894 
12895 /* Register: SPIS_CONFIG */
12896 /* Description: Configuration register */
12897 
12898 /* Bit 2 : Serial clock (SCK) polarity */
12899 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12900 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12901 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12902 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12903 
12904 /* Bit 1 : Serial clock (SCK) phase */
12905 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12906 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12907 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12908 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12909 
12910 /* Bit 0 : Bit order */
12911 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12912 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12913 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12914 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12915 
12916 /* Register: SPIS_DEF */
12917 /* Description: Default character. Character clocked out in case of an ignored transaction. */
12918 
12919 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
12920 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
12921 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
12922 
12923 /* Register: SPIS_ORC */
12924 /* Description: Over-read character */
12925 
12926 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
12927 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
12928 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
12929 
12930 
12931 /* Peripheral: TEMP */
12932 /* Description: Temperature Sensor */
12933 
12934 /* Register: TEMP_TASKS_START */
12935 /* Description: Start temperature measurement */
12936 
12937 /* Bit 0 : Start temperature measurement */
12938 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12939 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12940 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12941 
12942 /* Register: TEMP_TASKS_STOP */
12943 /* Description: Stop temperature measurement */
12944 
12945 /* Bit 0 : Stop temperature measurement */
12946 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12947 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12948 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12949 
12950 /* Register: TEMP_EVENTS_DATARDY */
12951 /* Description: Temperature measurement complete, data ready */
12952 
12953 /* Bit 0 : Temperature measurement complete, data ready */
12954 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
12955 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
12956 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
12957 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
12958 
12959 /* Register: TEMP_INTENSET */
12960 /* Description: Enable interrupt */
12961 
12962 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
12963 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
12964 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
12965 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12966 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12967 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
12968 
12969 /* Register: TEMP_INTENCLR */
12970 /* Description: Disable interrupt */
12971 
12972 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
12973 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
12974 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
12975 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12976 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12977 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
12978 
12979 /* Register: TEMP_TEMP */
12980 /* Description: Temperature in degC (0.25deg steps) */
12981 
12982 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
12983 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
12984 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
12985 
12986 /* Register: TEMP_A0 */
12987 /* Description: Slope of first piecewise linear function */
12988 
12989 /* Bits 11..0 : Slope of first piecewise linear function */
12990 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
12991 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
12992 
12993 /* Register: TEMP_A1 */
12994 /* Description: Slope of second piecewise linear function */
12995 
12996 /* Bits 11..0 : Slope of second piecewise linear function */
12997 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
12998 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
12999 
13000 /* Register: TEMP_A2 */
13001 /* Description: Slope of third piecewise linear function */
13002 
13003 /* Bits 11..0 : Slope of third piecewise linear function */
13004 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
13005 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
13006 
13007 /* Register: TEMP_A3 */
13008 /* Description: Slope of fourth piecewise linear function */
13009 
13010 /* Bits 11..0 : Slope of fourth piecewise linear function */
13011 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
13012 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
13013 
13014 /* Register: TEMP_A4 */
13015 /* Description: Slope of fifth piecewise linear function */
13016 
13017 /* Bits 11..0 : Slope of fifth piecewise linear function */
13018 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
13019 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
13020 
13021 /* Register: TEMP_A5 */
13022 /* Description: Slope of sixth piecewise linear function */
13023 
13024 /* Bits 11..0 : Slope of sixth piecewise linear function */
13025 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
13026 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
13027 
13028 /* Register: TEMP_B0 */
13029 /* Description: y-intercept of first piecewise linear function */
13030 
13031 /* Bits 13..0 : y-intercept of first piecewise linear function */
13032 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
13033 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
13034 
13035 /* Register: TEMP_B1 */
13036 /* Description: y-intercept of second piecewise linear function */
13037 
13038 /* Bits 13..0 : y-intercept of second piecewise linear function */
13039 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
13040 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
13041 
13042 /* Register: TEMP_B2 */
13043 /* Description: y-intercept of third piecewise linear function */
13044 
13045 /* Bits 13..0 : y-intercept of third piecewise linear function */
13046 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
13047 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
13048 
13049 /* Register: TEMP_B3 */
13050 /* Description: y-intercept of fourth piecewise linear function */
13051 
13052 /* Bits 13..0 : y-intercept of fourth piecewise linear function */
13053 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
13054 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
13055 
13056 /* Register: TEMP_B4 */
13057 /* Description: y-intercept of fifth piecewise linear function */
13058 
13059 /* Bits 13..0 : y-intercept of fifth piecewise linear function */
13060 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
13061 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
13062 
13063 /* Register: TEMP_B5 */
13064 /* Description: y-intercept of sixth piecewise linear function */
13065 
13066 /* Bits 13..0 : y-intercept of sixth piecewise linear function */
13067 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
13068 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
13069 
13070 /* Register: TEMP_T0 */
13071 /* Description: End point of first piecewise linear function */
13072 
13073 /* Bits 7..0 : End point of first piecewise linear function */
13074 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
13075 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
13076 
13077 /* Register: TEMP_T1 */
13078 /* Description: End point of second piecewise linear function */
13079 
13080 /* Bits 7..0 : End point of second piecewise linear function */
13081 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
13082 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
13083 
13084 /* Register: TEMP_T2 */
13085 /* Description: End point of third piecewise linear function */
13086 
13087 /* Bits 7..0 : End point of third piecewise linear function */
13088 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
13089 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
13090 
13091 /* Register: TEMP_T3 */
13092 /* Description: End point of fourth piecewise linear function */
13093 
13094 /* Bits 7..0 : End point of fourth piecewise linear function */
13095 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
13096 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
13097 
13098 /* Register: TEMP_T4 */
13099 /* Description: End point of fifth piecewise linear function */
13100 
13101 /* Bits 7..0 : End point of fifth piecewise linear function */
13102 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
13103 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
13104 
13105 
13106 /* Peripheral: TIMER */
13107 /* Description: Timer/Counter 0 */
13108 
13109 /* Register: TIMER_TASKS_START */
13110 /* Description: Start Timer */
13111 
13112 /* Bit 0 : Start Timer */
13113 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
13114 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
13115 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
13116 
13117 /* Register: TIMER_TASKS_STOP */
13118 /* Description: Stop Timer */
13119 
13120 /* Bit 0 : Stop Timer */
13121 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13122 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13123 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13124 
13125 /* Register: TIMER_TASKS_COUNT */
13126 /* Description: Increment Timer (Counter mode only) */
13127 
13128 /* Bit 0 : Increment Timer (Counter mode only) */
13129 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
13130 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
13131 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
13132 
13133 /* Register: TIMER_TASKS_CLEAR */
13134 /* Description: Clear time */
13135 
13136 /* Bit 0 : Clear time */
13137 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
13138 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
13139 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
13140 
13141 /* Register: TIMER_TASKS_SHUTDOWN */
13142 /* Description: Deprecated register - Shut down timer */
13143 
13144 /* Bit 0 : Deprecated field -  Shut down timer */
13145 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
13146 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
13147 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
13148 
13149 /* Register: TIMER_TASKS_CAPTURE */
13150 /* Description: Description collection: Capture Timer value to CC[n] register */
13151 
13152 /* Bit 0 : Capture Timer value to CC[n] register */
13153 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
13154 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
13155 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
13156 
13157 /* Register: TIMER_EVENTS_COMPARE */
13158 /* Description: Description collection: Compare event on CC[n] match */
13159 
13160 /* Bit 0 : Compare event on CC[n] match */
13161 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
13162 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
13163 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
13164 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
13165 
13166 /* Register: TIMER_SHORTS */
13167 /* Description: Shortcuts between local events and tasks */
13168 
13169 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
13170 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
13171 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
13172 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
13173 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
13174 
13175 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
13176 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
13177 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
13178 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
13179 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
13180 
13181 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
13182 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
13183 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
13184 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
13185 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
13186 
13187 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
13188 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
13189 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
13190 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
13191 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
13192 
13193 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
13194 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
13195 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
13196 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
13197 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
13198 
13199 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
13200 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
13201 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
13202 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
13203 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
13204 
13205 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
13206 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
13207 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
13208 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13209 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13210 
13211 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
13212 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
13213 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
13214 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13215 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13216 
13217 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
13218 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
13219 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
13220 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13221 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13222 
13223 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
13224 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
13225 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
13226 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13227 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13228 
13229 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
13230 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
13231 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
13232 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13233 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13234 
13235 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
13236 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
13237 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
13238 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13239 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13240 
13241 /* Register: TIMER_INTENSET */
13242 /* Description: Enable interrupt */
13243 
13244 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
13245 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
13246 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
13247 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13248 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13249 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
13250 
13251 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
13252 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
13253 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
13254 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13255 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13256 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
13257 
13258 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
13259 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13260 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13261 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13262 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13263 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
13264 
13265 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
13266 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13267 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13268 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13269 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13270 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
13271 
13272 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
13273 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13274 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13275 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13276 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13277 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
13278 
13279 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
13280 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13281 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13282 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13283 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13284 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
13285 
13286 /* Register: TIMER_INTENCLR */
13287 /* Description: Disable interrupt */
13288 
13289 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
13290 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
13291 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
13292 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13293 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13294 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
13295 
13296 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
13297 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
13298 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
13299 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13300 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13301 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
13302 
13303 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
13304 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13305 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13306 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13307 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13308 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
13309 
13310 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
13311 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13312 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13313 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13314 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13315 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
13316 
13317 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
13318 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13319 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13320 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13321 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13322 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
13323 
13324 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
13325 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13326 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13327 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13328 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13329 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
13330 
13331 /* Register: TIMER_MODE */
13332 /* Description: Timer mode selection */
13333 
13334 /* Bits 1..0 : Timer mode */
13335 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
13336 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
13337 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
13338 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
13339 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
13340 
13341 /* Register: TIMER_BITMODE */
13342 /* Description: Configure the number of bits used by the TIMER */
13343 
13344 /* Bits 1..0 : Timer bit width */
13345 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
13346 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
13347 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
13348 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
13349 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
13350 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
13351 
13352 /* Register: TIMER_PRESCALER */
13353 /* Description: Timer prescaler register */
13354 
13355 /* Bits 3..0 : Prescaler value */
13356 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
13357 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
13358 
13359 /* Register: TIMER_CC */
13360 /* Description: Description collection: Capture/Compare register n */
13361 
13362 /* Bits 31..0 : Capture/Compare value */
13363 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
13364 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
13365 
13366 
13367 /* Peripheral: TWI */
13368 /* Description: I2C compatible Two-Wire Interface 0 */
13369 
13370 /* Register: TWI_TASKS_STARTRX */
13371 /* Description: Start TWI receive sequence */
13372 
13373 /* Bit 0 : Start TWI receive sequence */
13374 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
13375 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
13376 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
13377 
13378 /* Register: TWI_TASKS_STARTTX */
13379 /* Description: Start TWI transmit sequence */
13380 
13381 /* Bit 0 : Start TWI transmit sequence */
13382 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
13383 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
13384 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
13385 
13386 /* Register: TWI_TASKS_STOP */
13387 /* Description: Stop TWI transaction */
13388 
13389 /* Bit 0 : Stop TWI transaction */
13390 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13391 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13392 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13393 
13394 /* Register: TWI_TASKS_SUSPEND */
13395 /* Description: Suspend TWI transaction */
13396 
13397 /* Bit 0 : Suspend TWI transaction */
13398 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
13399 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
13400 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
13401 
13402 /* Register: TWI_TASKS_RESUME */
13403 /* Description: Resume TWI transaction */
13404 
13405 /* Bit 0 : Resume TWI transaction */
13406 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
13407 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
13408 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
13409 
13410 /* Register: TWI_EVENTS_STOPPED */
13411 /* Description: TWI stopped */
13412 
13413 /* Bit 0 : TWI stopped */
13414 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
13415 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
13416 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
13417 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
13418 
13419 /* Register: TWI_EVENTS_RXDREADY */
13420 /* Description: TWI RXD byte received */
13421 
13422 /* Bit 0 : TWI RXD byte received */
13423 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
13424 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
13425 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
13426 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
13427 
13428 /* Register: TWI_EVENTS_TXDSENT */
13429 /* Description: TWI TXD byte sent */
13430 
13431 /* Bit 0 : TWI TXD byte sent */
13432 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
13433 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
13434 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
13435 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
13436 
13437 /* Register: TWI_EVENTS_ERROR */
13438 /* Description: TWI error */
13439 
13440 /* Bit 0 : TWI error */
13441 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
13442 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
13443 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
13444 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
13445 
13446 /* Register: TWI_EVENTS_BB */
13447 /* Description: TWI byte boundary, generated before each byte that is sent or received */
13448 
13449 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
13450 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
13451 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
13452 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
13453 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
13454 
13455 /* Register: TWI_EVENTS_SUSPENDED */
13456 /* Description: TWI entered the suspended state */
13457 
13458 /* Bit 0 : TWI entered the suspended state */
13459 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
13460 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
13461 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
13462 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
13463 
13464 /* Register: TWI_SHORTS */
13465 /* Description: Shortcuts between local events and tasks */
13466 
13467 /* Bit 1 : Shortcut between event BB and task STOP */
13468 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
13469 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
13470 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
13471 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
13472 
13473 /* Bit 0 : Shortcut between event BB and task SUSPEND */
13474 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
13475 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
13476 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13477 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13478 
13479 /* Register: TWI_INTENSET */
13480 /* Description: Enable interrupt */
13481 
13482 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
13483 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13484 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13485 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13486 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13487 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13488 
13489 /* Bit 14 : Write '1' to enable interrupt for event BB */
13490 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
13491 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
13492 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
13493 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
13494 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
13495 
13496 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13497 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13498 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13499 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13500 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13501 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
13502 
13503 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
13504 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
13505 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
13506 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13507 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13508 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
13509 
13510 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
13511 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13512 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
13513 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13514 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13515 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
13516 
13517 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
13518 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13519 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13520 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13521 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13522 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13523 
13524 /* Register: TWI_INTENCLR */
13525 /* Description: Disable interrupt */
13526 
13527 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
13528 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13529 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13530 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13531 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13532 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13533 
13534 /* Bit 14 : Write '1' to disable interrupt for event BB */
13535 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
13536 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
13537 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
13538 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
13539 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
13540 
13541 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13542 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13543 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13544 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13545 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13546 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13547 
13548 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
13549 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
13550 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
13551 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13552 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13553 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
13554 
13555 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
13556 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13557 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
13558 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13559 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13560 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
13561 
13562 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
13563 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13564 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13565 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13566 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13567 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13568 
13569 /* Register: TWI_ERRORSRC */
13570 /* Description: Error source */
13571 
13572 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13573 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13574 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
13575 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
13576 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
13577 
13578 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
13579 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
13580 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
13581 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
13582 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
13583 
13584 /* Bit 0 : Overrun error */
13585 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
13586 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
13587 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
13588 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
13589 
13590 /* Register: TWI_ENABLE */
13591 /* Description: Enable TWI */
13592 
13593 /* Bits 3..0 : Enable or disable TWI */
13594 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13595 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13596 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
13597 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
13598 
13599 /* Register: TWI_PSEL_SCL */
13600 /* Description: Pin select for SCL */
13601 
13602 /* Bit 31 : Connection */
13603 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13604 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13605 #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
13606 #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
13607 
13608 /* Bit 5 : Port number */
13609 #define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
13610 #define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
13611 
13612 /* Bits 4..0 : Pin number */
13613 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
13614 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
13615 
13616 /* Register: TWI_PSEL_SDA */
13617 /* Description: Pin select for SDA */
13618 
13619 /* Bit 31 : Connection */
13620 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13621 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13622 #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
13623 #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
13624 
13625 /* Bit 5 : Port number */
13626 #define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
13627 #define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
13628 
13629 /* Bits 4..0 : Pin number */
13630 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
13631 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
13632 
13633 /* Register: TWI_RXD */
13634 /* Description: RXD register */
13635 
13636 /* Bits 7..0 : RXD register */
13637 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
13638 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
13639 
13640 /* Register: TWI_TXD */
13641 /* Description: TXD register */
13642 
13643 /* Bits 7..0 : TXD register */
13644 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
13645 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
13646 
13647 /* Register: TWI_FREQUENCY */
13648 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
13649 
13650 /* Bits 31..0 : TWI master clock frequency */
13651 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
13652 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
13653 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
13654 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
13655 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
13656 
13657 /* Register: TWI_ADDRESS */
13658 /* Description: Address used in the TWI transfer */
13659 
13660 /* Bits 6..0 : Address used in the TWI transfer */
13661 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
13662 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
13663 
13664 
13665 /* Peripheral: TWIM */
13666 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
13667 
13668 /* Register: TWIM_TASKS_STARTRX */
13669 /* Description: Start TWI receive sequence */
13670 
13671 /* Bit 0 : Start TWI receive sequence */
13672 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
13673 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
13674 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
13675 
13676 /* Register: TWIM_TASKS_STARTTX */
13677 /* Description: Start TWI transmit sequence */
13678 
13679 /* Bit 0 : Start TWI transmit sequence */
13680 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
13681 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
13682 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
13683 
13684 /* Register: TWIM_TASKS_STOP */
13685 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
13686 
13687 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
13688 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13689 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13690 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13691 
13692 /* Register: TWIM_TASKS_SUSPEND */
13693 /* Description: Suspend TWI transaction */
13694 
13695 /* Bit 0 : Suspend TWI transaction */
13696 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
13697 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
13698 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
13699 
13700 /* Register: TWIM_TASKS_RESUME */
13701 /* Description: Resume TWI transaction */
13702 
13703 /* Bit 0 : Resume TWI transaction */
13704 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
13705 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
13706 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
13707 
13708 /* Register: TWIM_EVENTS_STOPPED */
13709 /* Description: TWI stopped */
13710 
13711 /* Bit 0 : TWI stopped */
13712 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
13713 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
13714 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
13715 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
13716 
13717 /* Register: TWIM_EVENTS_ERROR */
13718 /* Description: TWI error */
13719 
13720 /* Bit 0 : TWI error */
13721 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
13722 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
13723 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
13724 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
13725 
13726 /* Register: TWIM_EVENTS_SUSPENDED */
13727 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
13728 
13729 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
13730 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
13731 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
13732 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
13733 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
13734 
13735 /* Register: TWIM_EVENTS_RXSTARTED */
13736 /* Description: Receive sequence started */
13737 
13738 /* Bit 0 : Receive sequence started */
13739 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
13740 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
13741 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
13742 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
13743 
13744 /* Register: TWIM_EVENTS_TXSTARTED */
13745 /* Description: Transmit sequence started */
13746 
13747 /* Bit 0 : Transmit sequence started */
13748 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
13749 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
13750 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
13751 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
13752 
13753 /* Register: TWIM_EVENTS_LASTRX */
13754 /* Description: Byte boundary, starting to receive the last byte */
13755 
13756 /* Bit 0 : Byte boundary, starting to receive the last byte */
13757 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
13758 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
13759 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
13760 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
13761 
13762 /* Register: TWIM_EVENTS_LASTTX */
13763 /* Description: Byte boundary, starting to transmit the last byte */
13764 
13765 /* Bit 0 : Byte boundary, starting to transmit the last byte */
13766 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
13767 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
13768 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
13769 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
13770 
13771 /* Register: TWIM_SHORTS */
13772 /* Description: Shortcuts between local events and tasks */
13773 
13774 /* Bit 12 : Shortcut between event LASTRX and task STOP */
13775 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
13776 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
13777 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
13778 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
13779 
13780 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
13781 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
13782 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
13783 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13784 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13785 
13786 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
13787 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
13788 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
13789 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
13790 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
13791 
13792 /* Bit 9 : Shortcut between event LASTTX and task STOP */
13793 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
13794 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
13795 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
13796 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
13797 
13798 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
13799 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
13800 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
13801 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13802 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13803 
13804 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
13805 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
13806 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
13807 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
13808 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
13809 
13810 /* Register: TWIM_INTEN */
13811 /* Description: Enable or disable interrupt */
13812 
13813 /* Bit 24 : Enable or disable interrupt for event LASTTX */
13814 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
13815 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
13816 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
13817 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
13818 
13819 /* Bit 23 : Enable or disable interrupt for event LASTRX */
13820 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
13821 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
13822 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
13823 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
13824 
13825 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
13826 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13827 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13828 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
13829 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
13830 
13831 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
13832 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13833 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13834 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
13835 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
13836 
13837 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
13838 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13839 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13840 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
13841 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
13842 
13843 /* Bit 9 : Enable or disable interrupt for event ERROR */
13844 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13845 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
13846 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
13847 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
13848 
13849 /* Bit 1 : Enable or disable interrupt for event STOPPED */
13850 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13851 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13852 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
13853 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
13854 
13855 /* Register: TWIM_INTENSET */
13856 /* Description: Enable interrupt */
13857 
13858 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
13859 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
13860 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
13861 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13862 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13863 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
13864 
13865 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
13866 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
13867 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
13868 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13869 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13870 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
13871 
13872 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
13873 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13874 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13875 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13876 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13877 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
13878 
13879 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
13880 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13881 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13882 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13883 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13884 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
13885 
13886 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
13887 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13888 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13889 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13890 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13891 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13892 
13893 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13894 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13895 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13896 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13897 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13898 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
13899 
13900 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
13901 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13902 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13903 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13904 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13905 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13906 
13907 /* Register: TWIM_INTENCLR */
13908 /* Description: Disable interrupt */
13909 
13910 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
13911 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
13912 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
13913 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13914 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13915 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
13916 
13917 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
13918 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
13919 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
13920 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13921 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13922 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
13923 
13924 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
13925 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13926 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13927 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13928 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13929 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
13930 
13931 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
13932 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13933 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13934 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13935 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13936 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
13937 
13938 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
13939 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13940 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13941 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13942 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13943 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13944 
13945 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13946 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13947 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13948 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13949 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13950 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13951 
13952 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
13953 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13954 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13955 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13956 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13957 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13958 
13959 /* Register: TWIM_ERRORSRC */
13960 /* Description: Error source */
13961 
13962 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13963 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13964 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
13965 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
13966 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
13967 
13968 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
13969 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
13970 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
13971 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
13972 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
13973 
13974 /* Bit 0 : Overrun error */
13975 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
13976 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
13977 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
13978 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
13979 
13980 /* Register: TWIM_ENABLE */
13981 /* Description: Enable TWIM */
13982 
13983 /* Bits 3..0 : Enable or disable TWIM */
13984 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13985 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13986 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
13987 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
13988 
13989 /* Register: TWIM_PSEL_SCL */
13990 /* Description: Pin select for SCL signal */
13991 
13992 /* Bit 31 : Connection */
13993 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13994 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13995 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
13996 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
13997 
13998 /* Bit 5 : Port number */
13999 #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
14000 #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
14001 
14002 /* Bits 4..0 : Pin number */
14003 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14004 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14005 
14006 /* Register: TWIM_PSEL_SDA */
14007 /* Description: Pin select for SDA signal */
14008 
14009 /* Bit 31 : Connection */
14010 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14011 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14012 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
14013 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
14014 
14015 /* Bit 5 : Port number */
14016 #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
14017 #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
14018 
14019 /* Bits 4..0 : Pin number */
14020 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14021 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14022 
14023 /* Register: TWIM_FREQUENCY */
14024 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
14025 
14026 /* Bits 31..0 : TWI master clock frequency */
14027 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14028 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14029 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
14030 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14031 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
14032 
14033 /* Register: TWIM_RXD_PTR */
14034 /* Description: Data pointer */
14035 
14036 /* Bits 31..0 : Data pointer */
14037 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14038 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14039 
14040 /* Register: TWIM_RXD_MAXCNT */
14041 /* Description: Maximum number of bytes in receive buffer */
14042 
14043 /* Bits 15..0 : Maximum number of bytes in receive buffer */
14044 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14045 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14046 
14047 /* Register: TWIM_RXD_AMOUNT */
14048 /* Description: Number of bytes transferred in the last transaction */
14049 
14050 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14051 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14052 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14053 
14054 /* Register: TWIM_RXD_LIST */
14055 /* Description: EasyDMA list type */
14056 
14057 /* Bits 2..0 : List type */
14058 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14059 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14060 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14061 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14062 
14063 /* Register: TWIM_TXD_PTR */
14064 /* Description: Data pointer */
14065 
14066 /* Bits 31..0 : Data pointer */
14067 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14068 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14069 
14070 /* Register: TWIM_TXD_MAXCNT */
14071 /* Description: Maximum number of bytes in transmit buffer */
14072 
14073 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
14074 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14075 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14076 
14077 /* Register: TWIM_TXD_AMOUNT */
14078 /* Description: Number of bytes transferred in the last transaction */
14079 
14080 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14081 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14082 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14083 
14084 /* Register: TWIM_TXD_LIST */
14085 /* Description: EasyDMA list type */
14086 
14087 /* Bits 2..0 : List type */
14088 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14089 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14090 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14091 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14092 
14093 /* Register: TWIM_ADDRESS */
14094 /* Description: Address used in the TWI transfer */
14095 
14096 /* Bits 6..0 : Address used in the TWI transfer */
14097 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14098 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14099 
14100 
14101 /* Peripheral: TWIS */
14102 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14103 
14104 /* Register: TWIS_TASKS_STOP */
14105 /* Description: Stop TWI transaction */
14106 
14107 /* Bit 0 : Stop TWI transaction */
14108 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14109 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14110 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
14111 
14112 /* Register: TWIS_TASKS_SUSPEND */
14113 /* Description: Suspend TWI transaction */
14114 
14115 /* Bit 0 : Suspend TWI transaction */
14116 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14117 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14118 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14119 
14120 /* Register: TWIS_TASKS_RESUME */
14121 /* Description: Resume TWI transaction */
14122 
14123 /* Bit 0 : Resume TWI transaction */
14124 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14125 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14126 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
14127 
14128 /* Register: TWIS_TASKS_PREPARERX */
14129 /* Description: Prepare the TWI slave to respond to a write command */
14130 
14131 /* Bit 0 : Prepare the TWI slave to respond to a write command */
14132 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
14133 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
14134 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
14135 
14136 /* Register: TWIS_TASKS_PREPARETX */
14137 /* Description: Prepare the TWI slave to respond to a read command */
14138 
14139 /* Bit 0 : Prepare the TWI slave to respond to a read command */
14140 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
14141 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
14142 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
14143 
14144 /* Register: TWIS_EVENTS_STOPPED */
14145 /* Description: TWI stopped */
14146 
14147 /* Bit 0 : TWI stopped */
14148 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14149 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14150 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
14151 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
14152 
14153 /* Register: TWIS_EVENTS_ERROR */
14154 /* Description: TWI error */
14155 
14156 /* Bit 0 : TWI error */
14157 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14158 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14159 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14160 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14161 
14162 /* Register: TWIS_EVENTS_RXSTARTED */
14163 /* Description: Receive sequence started */
14164 
14165 /* Bit 0 : Receive sequence started */
14166 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14167 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14168 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14169 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14170 
14171 /* Register: TWIS_EVENTS_TXSTARTED */
14172 /* Description: Transmit sequence started */
14173 
14174 /* Bit 0 : Transmit sequence started */
14175 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14176 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14177 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14178 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
14179 
14180 /* Register: TWIS_EVENTS_WRITE */
14181 /* Description: Write command received */
14182 
14183 /* Bit 0 : Write command received */
14184 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
14185 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
14186 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
14187 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
14188 
14189 /* Register: TWIS_EVENTS_READ */
14190 /* Description: Read command received */
14191 
14192 /* Bit 0 : Read command received */
14193 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
14194 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
14195 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
14196 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
14197 
14198 /* Register: TWIS_SHORTS */
14199 /* Description: Shortcuts between local events and tasks */
14200 
14201 /* Bit 14 : Shortcut between event READ and task SUSPEND */
14202 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
14203 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
14204 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14205 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14206 
14207 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
14208 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
14209 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
14210 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14211 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14212 
14213 /* Register: TWIS_INTEN */
14214 /* Description: Enable or disable interrupt */
14215 
14216 /* Bit 26 : Enable or disable interrupt for event READ */
14217 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
14218 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
14219 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
14220 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
14221 
14222 /* Bit 25 : Enable or disable interrupt for event WRITE */
14223 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14224 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
14225 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
14226 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
14227 
14228 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14229 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14230 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14231 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14232 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14233 
14234 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14235 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14236 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14237 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14238 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14239 
14240 /* Bit 9 : Enable or disable interrupt for event ERROR */
14241 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14242 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14243 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14244 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14245 
14246 /* Bit 1 : Enable or disable interrupt for event STOPPED */
14247 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14248 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14249 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
14250 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
14251 
14252 /* Register: TWIS_INTENSET */
14253 /* Description: Enable interrupt */
14254 
14255 /* Bit 26 : Write '1' to enable interrupt for event READ */
14256 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
14257 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
14258 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
14259 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
14260 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
14261 
14262 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
14263 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14264 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
14265 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
14266 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
14267 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
14268 
14269 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14270 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14271 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14272 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14273 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14274 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14275 
14276 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14277 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14278 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14279 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14280 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14281 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14282 
14283 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14284 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14285 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14286 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14287 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14288 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
14289 
14290 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14291 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14292 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14293 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14294 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14295 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
14296 
14297 /* Register: TWIS_INTENCLR */
14298 /* Description: Disable interrupt */
14299 
14300 /* Bit 26 : Write '1' to disable interrupt for event READ */
14301 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
14302 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
14303 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
14304 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
14305 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
14306 
14307 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
14308 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14309 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
14310 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
14311 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
14312 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
14313 
14314 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14315 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14316 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14317 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14318 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14319 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14320 
14321 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14322 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14323 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14324 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14325 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14326 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14327 
14328 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14329 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14330 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14331 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14332 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14333 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14334 
14335 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14336 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14337 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14338 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14339 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14340 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
14341 
14342 /* Register: TWIS_ERRORSRC */
14343 /* Description: Error source */
14344 
14345 /* Bit 3 : TX buffer over-read detected, and prevented */
14346 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
14347 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
14348 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
14349 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
14350 
14351 /* Bit 2 : NACK sent after receiving a data byte */
14352 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14353 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
14354 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
14355 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
14356 
14357 /* Bit 0 : RX buffer overflow detected, and prevented */
14358 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
14359 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
14360 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
14361 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
14362 
14363 /* Register: TWIS_MATCH */
14364 /* Description: Status register indicating which address had a match */
14365 
14366 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
14367 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
14368 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
14369 
14370 /* Register: TWIS_ENABLE */
14371 /* Description: Enable TWIS */
14372 
14373 /* Bits 3..0 : Enable or disable TWIS */
14374 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14375 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14376 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
14377 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
14378 
14379 /* Register: TWIS_PSEL_SCL */
14380 /* Description: Pin select for SCL signal */
14381 
14382 /* Bit 31 : Connection */
14383 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14384 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14385 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
14386 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
14387 
14388 /* Bit 5 : Port number */
14389 #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
14390 #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
14391 
14392 /* Bits 4..0 : Pin number */
14393 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14394 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14395 
14396 /* Register: TWIS_PSEL_SDA */
14397 /* Description: Pin select for SDA signal */
14398 
14399 /* Bit 31 : Connection */
14400 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14401 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14402 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
14403 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
14404 
14405 /* Bit 5 : Port number */
14406 #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
14407 #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
14408 
14409 /* Bits 4..0 : Pin number */
14410 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14411 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14412 
14413 /* Register: TWIS_RXD_PTR */
14414 /* Description: RXD Data pointer */
14415 
14416 /* Bits 31..0 : RXD Data pointer */
14417 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14418 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14419 
14420 /* Register: TWIS_RXD_MAXCNT */
14421 /* Description: Maximum number of bytes in RXD buffer */
14422 
14423 /* Bits 15..0 : Maximum number of bytes in RXD buffer */
14424 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14425 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14426 
14427 /* Register: TWIS_RXD_AMOUNT */
14428 /* Description: Number of bytes transferred in the last RXD transaction */
14429 
14430 /* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
14431 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14432 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14433 
14434 /* Register: TWIS_RXD_LIST */
14435 /* Description: EasyDMA list type */
14436 
14437 /* Bits 1..0 : List type */
14438 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14439 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14440 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14441 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14442 
14443 /* Register: TWIS_TXD_PTR */
14444 /* Description: TXD Data pointer */
14445 
14446 /* Bits 31..0 : TXD Data pointer */
14447 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14448 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14449 
14450 /* Register: TWIS_TXD_MAXCNT */
14451 /* Description: Maximum number of bytes in TXD buffer */
14452 
14453 /* Bits 15..0 : Maximum number of bytes in TXD buffer */
14454 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14455 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14456 
14457 /* Register: TWIS_TXD_AMOUNT */
14458 /* Description: Number of bytes transferred in the last TXD transaction */
14459 
14460 /* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
14461 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14462 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14463 
14464 /* Register: TWIS_TXD_LIST */
14465 /* Description: EasyDMA list type */
14466 
14467 /* Bits 1..0 : List type */
14468 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14469 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14470 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14471 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14472 
14473 /* Register: TWIS_ADDRESS */
14474 /* Description: Description collection: TWI slave address n */
14475 
14476 /* Bits 6..0 : TWI slave address */
14477 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14478 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14479 
14480 /* Register: TWIS_CONFIG */
14481 /* Description: Configuration register for the address match mechanism */
14482 
14483 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
14484 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
14485 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
14486 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
14487 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
14488 
14489 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
14490 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
14491 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
14492 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
14493 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
14494 
14495 /* Register: TWIS_ORC */
14496 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
14497 
14498 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
14499 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
14500 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
14501 
14502 
14503 /* Peripheral: UART */
14504 /* Description: Universal Asynchronous Receiver/Transmitter */
14505 
14506 /* Register: UART_TASKS_STARTRX */
14507 /* Description: Start UART receiver */
14508 
14509 /* Bit 0 : Start UART receiver */
14510 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14511 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14512 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
14513 
14514 /* Register: UART_TASKS_STOPRX */
14515 /* Description: Stop UART receiver */
14516 
14517 /* Bit 0 : Stop UART receiver */
14518 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
14519 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
14520 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
14521 
14522 /* Register: UART_TASKS_STARTTX */
14523 /* Description: Start UART transmitter */
14524 
14525 /* Bit 0 : Start UART transmitter */
14526 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14527 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14528 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
14529 
14530 /* Register: UART_TASKS_STOPTX */
14531 /* Description: Stop UART transmitter */
14532 
14533 /* Bit 0 : Stop UART transmitter */
14534 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
14535 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
14536 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
14537 
14538 /* Register: UART_TASKS_SUSPEND */
14539 /* Description: Suspend UART */
14540 
14541 /* Bit 0 : Suspend UART */
14542 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14543 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14544 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14545 
14546 /* Register: UART_EVENTS_CTS */
14547 /* Description: CTS is activated (set low). Clear To Send. */
14548 
14549 /* Bit 0 : CTS is activated (set low). Clear To Send. */
14550 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
14551 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
14552 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
14553 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
14554 
14555 /* Register: UART_EVENTS_NCTS */
14556 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14557 
14558 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
14559 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
14560 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
14561 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
14562 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
14563 
14564 /* Register: UART_EVENTS_RXDRDY */
14565 /* Description: Data received in RXD */
14566 
14567 /* Bit 0 : Data received in RXD */
14568 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
14569 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
14570 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
14571 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
14572 
14573 /* Register: UART_EVENTS_TXDRDY */
14574 /* Description: Data sent from TXD */
14575 
14576 /* Bit 0 : Data sent from TXD */
14577 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
14578 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
14579 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
14580 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
14581 
14582 /* Register: UART_EVENTS_ERROR */
14583 /* Description: Error detected */
14584 
14585 /* Bit 0 : Error detected */
14586 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14587 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14588 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14589 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14590 
14591 /* Register: UART_EVENTS_RXTO */
14592 /* Description: Receiver timeout */
14593 
14594 /* Bit 0 : Receiver timeout */
14595 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
14596 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
14597 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
14598 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
14599 
14600 /* Register: UART_SHORTS */
14601 /* Description: Shortcuts between local events and tasks */
14602 
14603 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
14604 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
14605 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
14606 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
14607 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
14608 
14609 /* Bit 3 : Shortcut between event CTS and task STARTRX */
14610 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
14611 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
14612 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14613 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14614 
14615 /* Register: UART_INTENSET */
14616 /* Description: Enable interrupt */
14617 
14618 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
14619 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14620 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
14621 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14622 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14623 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
14624 
14625 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14626 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14627 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14628 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14629 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14630 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
14631 
14632 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
14633 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14634 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14635 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14636 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14637 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
14638 
14639 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
14640 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14641 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
14642 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14643 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14644 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
14645 
14646 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
14647 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
14648 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
14649 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
14650 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
14651 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
14652 
14653 /* Bit 0 : Write '1' to enable interrupt for event CTS */
14654 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
14655 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
14656 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
14657 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
14658 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
14659 
14660 /* Register: UART_INTENCLR */
14661 /* Description: Disable interrupt */
14662 
14663 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
14664 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14665 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
14666 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
14667 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
14668 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
14669 
14670 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14671 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14672 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14673 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14674 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14675 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14676 
14677 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
14678 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14679 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14680 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14681 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14682 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
14683 
14684 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
14685 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14686 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
14687 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14688 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14689 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
14690 
14691 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
14692 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
14693 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
14694 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
14695 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
14696 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
14697 
14698 /* Bit 0 : Write '1' to disable interrupt for event CTS */
14699 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
14700 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
14701 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
14702 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
14703 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
14704 
14705 /* Register: UART_ERRORSRC */
14706 /* Description: Error source */
14707 
14708 /* Bit 3 : Break condition */
14709 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
14710 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
14711 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
14712 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
14713 
14714 /* Bit 2 : Framing error occurred */
14715 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
14716 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
14717 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
14718 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
14719 
14720 /* Bit 1 : Parity error */
14721 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
14722 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
14723 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
14724 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
14725 
14726 /* Bit 0 : Overrun error */
14727 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
14728 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
14729 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
14730 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
14731 
14732 /* Register: UART_ENABLE */
14733 /* Description: Enable UART */
14734 
14735 /* Bits 3..0 : Enable or disable UART */
14736 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14737 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14738 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
14739 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
14740 
14741 /* Register: UART_PSEL_RTS */
14742 /* Description: Pin select for RTS */
14743 
14744 /* Bit 31 : Connection */
14745 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14746 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14747 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
14748 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
14749 
14750 /* Bit 5 : Port number */
14751 #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
14752 #define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
14753 
14754 /* Bits 4..0 : Pin number */
14755 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
14756 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
14757 
14758 /* Register: UART_PSEL_TXD */
14759 /* Description: Pin select for TXD */
14760 
14761 /* Bit 31 : Connection */
14762 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14763 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14764 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
14765 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
14766 
14767 /* Bit 5 : Port number */
14768 #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
14769 #define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
14770 
14771 /* Bits 4..0 : Pin number */
14772 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
14773 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
14774 
14775 /* Register: UART_PSEL_CTS */
14776 /* Description: Pin select for CTS */
14777 
14778 /* Bit 31 : Connection */
14779 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14780 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14781 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
14782 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
14783 
14784 /* Bit 5 : Port number */
14785 #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
14786 #define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
14787 
14788 /* Bits 4..0 : Pin number */
14789 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
14790 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
14791 
14792 /* Register: UART_PSEL_RXD */
14793 /* Description: Pin select for RXD */
14794 
14795 /* Bit 31 : Connection */
14796 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14797 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14798 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
14799 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
14800 
14801 /* Bit 5 : Port number */
14802 #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
14803 #define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
14804 
14805 /* Bits 4..0 : Pin number */
14806 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
14807 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
14808 
14809 /* Register: UART_RXD */
14810 /* Description: RXD register */
14811 
14812 /* Bits 7..0 : RX data received in previous transfers, double buffered */
14813 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
14814 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
14815 
14816 /* Register: UART_TXD */
14817 /* Description: TXD register */
14818 
14819 /* Bits 7..0 : TX data to be transferred */
14820 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
14821 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
14822 
14823 /* Register: UART_BAUDRATE */
14824 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
14825 
14826 /* Bits 31..0 : Baud rate */
14827 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
14828 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
14829 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
14830 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
14831 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
14832 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
14833 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
14834 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
14835 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
14836 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
14837 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
14838 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
14839 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
14840 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
14841 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
14842 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
14843 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
14844 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
14845 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
14846 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
14847 
14848 /* Register: UART_CONFIG */
14849 /* Description: Configuration of parity and hardware flow control */
14850 
14851 /* Bit 8 : Even or odd parity type */
14852 #define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
14853 #define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
14854 #define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
14855 #define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
14856 
14857 /* Bit 4 : Stop bits */
14858 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
14859 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
14860 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
14861 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
14862 
14863 /* Bits 3..1 : Parity */
14864 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
14865 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
14866 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
14867 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
14868 
14869 /* Bit 0 : Hardware flow control */
14870 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
14871 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
14872 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
14873 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
14874 
14875 
14876 /* Peripheral: UARTE */
14877 /* Description: UART with EasyDMA 0 */
14878 
14879 /* Register: UARTE_TASKS_STARTRX */
14880 /* Description: Start UART receiver */
14881 
14882 /* Bit 0 : Start UART receiver */
14883 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14884 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14885 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
14886 
14887 /* Register: UARTE_TASKS_STOPRX */
14888 /* Description: Stop UART receiver */
14889 
14890 /* Bit 0 : Stop UART receiver */
14891 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
14892 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
14893 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
14894 
14895 /* Register: UARTE_TASKS_STARTTX */
14896 /* Description: Start UART transmitter */
14897 
14898 /* Bit 0 : Start UART transmitter */
14899 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14900 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14901 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
14902 
14903 /* Register: UARTE_TASKS_STOPTX */
14904 /* Description: Stop UART transmitter */
14905 
14906 /* Bit 0 : Stop UART transmitter */
14907 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
14908 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
14909 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
14910 
14911 /* Register: UARTE_TASKS_FLUSHRX */
14912 /* Description: Flush RX FIFO into RX buffer */
14913 
14914 /* Bit 0 : Flush RX FIFO into RX buffer */
14915 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
14916 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
14917 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
14918 
14919 /* Register: UARTE_EVENTS_CTS */
14920 /* Description: CTS is activated (set low). Clear To Send. */
14921 
14922 /* Bit 0 : CTS is activated (set low). Clear To Send. */
14923 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
14924 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
14925 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
14926 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
14927 
14928 /* Register: UARTE_EVENTS_NCTS */
14929 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14930 
14931 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
14932 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
14933 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
14934 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
14935 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
14936 
14937 /* Register: UARTE_EVENTS_RXDRDY */
14938 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
14939 
14940 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
14941 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
14942 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
14943 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
14944 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
14945 
14946 /* Register: UARTE_EVENTS_ENDRX */
14947 /* Description: Receive buffer is filled up */
14948 
14949 /* Bit 0 : Receive buffer is filled up */
14950 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
14951 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
14952 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
14953 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
14954 
14955 /* Register: UARTE_EVENTS_TXDRDY */
14956 /* Description: Data sent from TXD */
14957 
14958 /* Bit 0 : Data sent from TXD */
14959 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
14960 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
14961 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
14962 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
14963 
14964 /* Register: UARTE_EVENTS_ENDTX */
14965 /* Description: Last TX byte transmitted */
14966 
14967 /* Bit 0 : Last TX byte transmitted */
14968 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
14969 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
14970 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
14971 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
14972 
14973 /* Register: UARTE_EVENTS_ERROR */
14974 /* Description: Error detected */
14975 
14976 /* Bit 0 : Error detected */
14977 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14978 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14979 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14980 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14981 
14982 /* Register: UARTE_EVENTS_RXTO */
14983 /* Description: Receiver timeout */
14984 
14985 /* Bit 0 : Receiver timeout */
14986 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
14987 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
14988 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
14989 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
14990 
14991 /* Register: UARTE_EVENTS_RXSTARTED */
14992 /* Description: UART receiver has started */
14993 
14994 /* Bit 0 : UART receiver has started */
14995 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14996 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14997 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14998 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14999 
15000 /* Register: UARTE_EVENTS_TXSTARTED */
15001 /* Description: UART transmitter has started */
15002 
15003 /* Bit 0 : UART transmitter has started */
15004 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15005 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15006 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15007 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
15008 
15009 /* Register: UARTE_EVENTS_TXSTOPPED */
15010 /* Description: Transmitter stopped */
15011 
15012 /* Bit 0 : Transmitter stopped */
15013 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
15014 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
15015 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
15016 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
15017 
15018 /* Register: UARTE_SHORTS */
15019 /* Description: Shortcuts between local events and tasks */
15020 
15021 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
15022 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
15023 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
15024 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
15025 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
15026 
15027 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
15028 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
15029 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
15030 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
15031 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
15032 
15033 /* Register: UARTE_INTEN */
15034 /* Description: Enable or disable interrupt */
15035 
15036 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
15037 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15038 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15039 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
15040 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
15041 
15042 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15043 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15044 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15045 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
15046 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
15047 
15048 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15049 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15050 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15051 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
15052 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
15053 
15054 /* Bit 17 : Enable or disable interrupt for event RXTO */
15055 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15056 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
15057 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
15058 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
15059 
15060 /* Bit 9 : Enable or disable interrupt for event ERROR */
15061 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15062 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15063 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
15064 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
15065 
15066 /* Bit 8 : Enable or disable interrupt for event ENDTX */
15067 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15068 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15069 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
15070 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
15071 
15072 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
15073 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15074 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15075 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
15076 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
15077 
15078 /* Bit 4 : Enable or disable interrupt for event ENDRX */
15079 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15080 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15081 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
15082 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
15083 
15084 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
15085 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15086 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15087 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
15088 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
15089 
15090 /* Bit 1 : Enable or disable interrupt for event NCTS */
15091 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15092 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
15093 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
15094 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
15095 
15096 /* Bit 0 : Enable or disable interrupt for event CTS */
15097 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
15098 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
15099 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
15100 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
15101 
15102 /* Register: UARTE_INTENSET */
15103 /* Description: Enable interrupt */
15104 
15105 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
15106 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15107 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15108 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15109 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15110 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
15111 
15112 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15113 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15114 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15115 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15116 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15117 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
15118 
15119 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15120 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15121 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15122 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15123 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15124 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
15125 
15126 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
15127 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15128 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
15129 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
15130 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
15131 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
15132 
15133 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15134 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15135 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15136 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
15137 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
15138 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
15139 
15140 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
15141 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15142 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15143 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15144 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15145 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
15146 
15147 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
15148 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15149 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15150 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15151 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15152 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
15153 
15154 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
15155 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15156 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15157 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15158 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15159 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
15160 
15161 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
15162 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15163 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15164 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15165 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15166 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
15167 
15168 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
15169 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15170 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
15171 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
15172 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
15173 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
15174 
15175 /* Bit 0 : Write '1' to enable interrupt for event CTS */
15176 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
15177 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
15178 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
15179 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
15180 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
15181 
15182 /* Register: UARTE_INTENCLR */
15183 /* Description: Disable interrupt */
15184 
15185 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
15186 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15187 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15188 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15189 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15190 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
15191 
15192 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15193 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15194 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15195 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15196 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15197 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
15198 
15199 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15200 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15201 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15202 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15203 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15204 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
15205 
15206 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
15207 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15208 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
15209 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
15210 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
15211 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
15212 
15213 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15214 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15215 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15216 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15217 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15218 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
15219 
15220 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
15221 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15222 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15223 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15224 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15225 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
15226 
15227 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
15228 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15229 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15230 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15231 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15232 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
15233 
15234 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
15235 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15236 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15237 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15238 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15239 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
15240 
15241 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
15242 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15243 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15244 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15245 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15246 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
15247 
15248 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
15249 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15250 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
15251 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
15252 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
15253 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
15254 
15255 /* Bit 0 : Write '1' to disable interrupt for event CTS */
15256 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
15257 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
15258 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
15259 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
15260 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
15261 
15262 /* Register: UARTE_ERRORSRC */
15263 /* Description: Error source This register is read/write one to clear. */
15264 
15265 /* Bit 3 : Break condition */
15266 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
15267 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
15268 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
15269 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
15270 
15271 /* Bit 2 : Framing error occurred */
15272 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
15273 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
15274 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
15275 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
15276 
15277 /* Bit 1 : Parity error */
15278 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15279 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
15280 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
15281 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
15282 
15283 /* Bit 0 : Overrun error */
15284 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15285 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15286 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
15287 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
15288 
15289 /* Register: UARTE_ENABLE */
15290 /* Description: Enable UART */
15291 
15292 /* Bits 3..0 : Enable or disable UARTE */
15293 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15294 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15295 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
15296 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
15297 
15298 /* Register: UARTE_PSEL_RTS */
15299 /* Description: Pin select for RTS signal */
15300 
15301 /* Bit 31 : Connection */
15302 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15303 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15304 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
15305 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15306 
15307 /* Bit 5 : Port number */
15308 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15309 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
15310 
15311 /* Bits 4..0 : Pin number */
15312 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15313 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
15314 
15315 /* Register: UARTE_PSEL_TXD */
15316 /* Description: Pin select for TXD signal */
15317 
15318 /* Bit 31 : Connection */
15319 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15320 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15321 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
15322 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15323 
15324 /* Bit 5 : Port number */
15325 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15326 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
15327 
15328 /* Bits 4..0 : Pin number */
15329 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15330 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
15331 
15332 /* Register: UARTE_PSEL_CTS */
15333 /* Description: Pin select for CTS signal */
15334 
15335 /* Bit 31 : Connection */
15336 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15337 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15338 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
15339 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15340 
15341 /* Bit 5 : Port number */
15342 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15343 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
15344 
15345 /* Bits 4..0 : Pin number */
15346 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15347 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
15348 
15349 /* Register: UARTE_PSEL_RXD */
15350 /* Description: Pin select for RXD signal */
15351 
15352 /* Bit 31 : Connection */
15353 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15354 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15355 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
15356 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15357 
15358 /* Bit 5 : Port number */
15359 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15360 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
15361 
15362 /* Bits 4..0 : Pin number */
15363 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15364 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
15365 
15366 /* Register: UARTE_BAUDRATE */
15367 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
15368 
15369 /* Bits 31..0 : Baud rate */
15370 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
15371 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
15372 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
15373 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
15374 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
15375 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
15376 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
15377 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
15378 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
15379 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
15380 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
15381 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
15382 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
15383 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
15384 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
15385 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
15386 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
15387 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
15388 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
15389 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
15390 
15391 /* Register: UARTE_RXD_PTR */
15392 /* Description: Data pointer */
15393 
15394 /* Bits 31..0 : Data pointer */
15395 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15396 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15397 
15398 /* Register: UARTE_RXD_MAXCNT */
15399 /* Description: Maximum number of bytes in receive buffer */
15400 
15401 /* Bits 15..0 : Maximum number of bytes in receive buffer */
15402 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15403 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15404 
15405 /* Register: UARTE_RXD_AMOUNT */
15406 /* Description: Number of bytes transferred in the last transaction */
15407 
15408 /* Bits 15..0 : Number of bytes transferred in the last transaction */
15409 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15410 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15411 
15412 /* Register: UARTE_TXD_PTR */
15413 /* Description: Data pointer */
15414 
15415 /* Bits 31..0 : Data pointer */
15416 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15417 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15418 
15419 /* Register: UARTE_TXD_MAXCNT */
15420 /* Description: Maximum number of bytes in transmit buffer */
15421 
15422 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
15423 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15424 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15425 
15426 /* Register: UARTE_TXD_AMOUNT */
15427 /* Description: Number of bytes transferred in the last transaction */
15428 
15429 /* Bits 15..0 : Number of bytes transferred in the last transaction */
15430 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15431 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15432 
15433 /* Register: UARTE_CONFIG */
15434 /* Description: Configuration of parity and hardware flow control */
15435 
15436 /* Bit 8 : Even or odd parity type */
15437 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
15438 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
15439 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
15440 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
15441 
15442 /* Bit 4 : Stop bits */
15443 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
15444 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
15445 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
15446 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
15447 
15448 /* Bits 3..1 : Parity */
15449 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15450 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
15451 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
15452 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
15453 
15454 /* Bit 0 : Hardware flow control */
15455 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
15456 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
15457 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
15458 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
15459 
15460 
15461 /* Peripheral: UICR */
15462 /* Description: User information configuration registers */
15463 
15464 /* Register: UICR_NRFFW */
15465 /* Description: Description collection: Reserved for Nordic firmware design */
15466 
15467 /* Bits 31..0 : Reserved for Nordic firmware design */
15468 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
15469 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
15470 
15471 /* Register: UICR_NRFHW */
15472 /* Description: Description collection: Reserved for Nordic hardware design */
15473 
15474 /* Bits 31..0 : Reserved for Nordic hardware design */
15475 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
15476 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
15477 
15478 /* Register: UICR_CUSTOMER */
15479 /* Description: Description collection: Reserved for customer */
15480 
15481 /* Bits 31..0 : Reserved for customer */
15482 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
15483 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
15484 
15485 /* Register: UICR_PSELRESET */
15486 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
15487 
15488 /* Bit 31 : Connection */
15489 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15490 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15491 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
15492 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
15493 
15494 /* Bit 5 : Port number onto which nRESET is exposed */
15495 #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
15496 #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
15497 
15498 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
15499 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
15500 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
15501 
15502 /* Register: UICR_APPROTECT */
15503 /* Description: Access port protection */
15504 
15505 /* Bits 7..0 : Enable or disable access port protection. */
15506 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
15507 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
15508 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
15509 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
15510 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
15511 
15512 /* Register: UICR_NFCPINS */
15513 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
15514 
15515 /* Bit 0 : Setting of pins dedicated to NFC functionality */
15516 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
15517 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
15518 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */
15519 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */
15520 
15521 /* Register: UICR_DEBUGCTRL */
15522 /* Description: Processor debug control */
15523 
15524 /* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */
15525 #define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */
15526 #define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */
15527 #define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */
15528 #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
15529 
15530 /* Bits 7..0 : Configure CPU non-intrusive debug features */
15531 #define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */
15532 #define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */
15533 #define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
15534 #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
15535 
15536 /* Register: UICR_REGOUT0 */
15537 /* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */
15538 
15539 /* Bits 2..0 : Output voltage from REG0 regulator stage. */
15540 #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
15541 #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
15542 #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
15543 #define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
15544 #define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
15545 #define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
15546 #define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
15547 #define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
15548 #define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
15549 
15550 
15551 /* Peripheral: USBD */
15552 /* Description: Universal serial bus device */
15553 
15554 /* Register: USBD_TASKS_STARTEPIN */
15555 /* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
15556 
15557 /* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
15558 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
15559 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
15560 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */
15561 
15562 /* Register: USBD_TASKS_STARTISOIN */
15563 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
15564 
15565 /* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
15566 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
15567 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
15568 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */
15569 
15570 /* Register: USBD_TASKS_STARTEPOUT */
15571 /* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
15572 
15573 /* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
15574 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
15575 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
15576 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */
15577 
15578 /* Register: USBD_TASKS_STARTISOOUT */
15579 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
15580 
15581 /* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
15582 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
15583 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
15584 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */
15585 
15586 /* Register: USBD_TASKS_EP0RCVOUT */
15587 /* Description: Allows OUT data stage on control endpoint 0 */
15588 
15589 /* Bit 0 : Allows OUT data stage on control endpoint 0 */
15590 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
15591 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
15592 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */
15593 
15594 /* Register: USBD_TASKS_EP0STATUS */
15595 /* Description: Allows status stage on control endpoint 0 */
15596 
15597 /* Bit 0 : Allows status stage on control endpoint 0 */
15598 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
15599 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
15600 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */
15601 
15602 /* Register: USBD_TASKS_EP0STALL */
15603 /* Description: Stalls data and status stage on control endpoint 0 */
15604 
15605 /* Bit 0 : Stalls data and status stage on control endpoint 0 */
15606 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
15607 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
15608 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */
15609 
15610 /* Register: USBD_TASKS_DPDMDRIVE */
15611 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15612 
15613 /* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15614 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
15615 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
15616 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */
15617 
15618 /* Register: USBD_TASKS_DPDMNODRIVE */
15619 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
15620 
15621 /* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
15622 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
15623 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
15624 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */
15625 
15626 /* Register: USBD_EVENTS_USBRESET */
15627 /* Description: Signals that a USB reset condition has been detected on USB lines */
15628 
15629 /* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
15630 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
15631 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
15632 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */
15633 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */
15634 
15635 /* Register: USBD_EVENTS_STARTED */
15636 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
15637 
15638 /* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
15639 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
15640 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
15641 #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
15642 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
15643 
15644 /* Register: USBD_EVENTS_ENDEPIN */
15645 /* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
15646 
15647 /* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
15648 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
15649 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
15650 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
15651 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */
15652 
15653 /* Register: USBD_EVENTS_EP0DATADONE */
15654 /* Description: An acknowledged data transfer has taken place on the control endpoint */
15655 
15656 /* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
15657 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
15658 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
15659 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */
15660 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
15661 
15662 /* Register: USBD_EVENTS_ENDISOIN */
15663 /* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
15664 
15665 /* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
15666 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
15667 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
15668 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
15669 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
15670 
15671 /* Register: USBD_EVENTS_ENDEPOUT */
15672 /* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
15673 
15674 /* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
15675 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
15676 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
15677 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
15678 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
15679 
15680 /* Register: USBD_EVENTS_ENDISOOUT */
15681 /* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
15682 
15683 /* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
15684 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
15685 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
15686 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
15687 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */
15688 
15689 /* Register: USBD_EVENTS_SOF */
15690 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
15691 
15692 /* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
15693 #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
15694 #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
15695 #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */
15696 #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */
15697 
15698 /* Register: USBD_EVENTS_USBEVENT */
15699 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
15700 
15701 /* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
15702 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
15703 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
15704 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */
15705 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */
15706 
15707 /* Register: USBD_EVENTS_EP0SETUP */
15708 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
15709 
15710 /* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
15711 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
15712 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
15713 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */
15714 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */
15715 
15716 /* Register: USBD_EVENTS_EPDATA */
15717 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
15718 
15719 /* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
15720 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
15721 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
15722 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */
15723 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */
15724 
15725 /* Register: USBD_SHORTS */
15726 /* Description: Shortcuts between local events and tasks */
15727 
15728 /* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
15729 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
15730 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
15731 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
15732 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
15733 
15734 /* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
15735 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
15736 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
15737 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
15738 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
15739 
15740 /* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
15741 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
15742 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
15743 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
15744 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
15745 
15746 /* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
15747 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
15748 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
15749 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
15750 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
15751 
15752 /* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
15753 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
15754 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
15755 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
15756 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
15757 
15758 /* Register: USBD_INTEN */
15759 /* Description: Enable or disable interrupt */
15760 
15761 /* Bit 24 : Enable or disable interrupt for event EPDATA */
15762 #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
15763 #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
15764 #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
15765 #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
15766 
15767 /* Bit 23 : Enable or disable interrupt for event EP0SETUP */
15768 #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
15769 #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
15770 #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
15771 #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
15772 
15773 /* Bit 22 : Enable or disable interrupt for event USBEVENT */
15774 #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
15775 #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
15776 #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
15777 #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
15778 
15779 /* Bit 21 : Enable or disable interrupt for event SOF */
15780 #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
15781 #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
15782 #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
15783 #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
15784 
15785 /* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
15786 #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
15787 #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
15788 #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
15789 #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
15790 
15791 /* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
15792 #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
15793 #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
15794 #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
15795 #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
15796 
15797 /* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
15798 #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
15799 #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
15800 #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
15801 #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
15802 
15803 /* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
15804 #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
15805 #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
15806 #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
15807 #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
15808 
15809 /* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
15810 #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
15811 #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
15812 #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
15813 #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
15814 
15815 /* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
15816 #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
15817 #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
15818 #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
15819 #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
15820 
15821 /* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
15822 #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
15823 #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
15824 #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
15825 #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
15826 
15827 /* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
15828 #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
15829 #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
15830 #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
15831 #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
15832 
15833 /* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
15834 #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
15835 #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
15836 #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
15837 #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
15838 
15839 /* Bit 11 : Enable or disable interrupt for event ENDISOIN */
15840 #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
15841 #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
15842 #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
15843 #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
15844 
15845 /* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
15846 #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
15847 #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
15848 #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
15849 #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
15850 
15851 /* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
15852 #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
15853 #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
15854 #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
15855 #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
15856 
15857 /* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
15858 #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
15859 #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
15860 #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
15861 #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
15862 
15863 /* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
15864 #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
15865 #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
15866 #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
15867 #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
15868 
15869 /* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
15870 #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
15871 #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
15872 #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
15873 #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
15874 
15875 /* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
15876 #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
15877 #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
15878 #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
15879 #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
15880 
15881 /* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
15882 #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
15883 #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
15884 #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
15885 #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
15886 
15887 /* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
15888 #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
15889 #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
15890 #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
15891 #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
15892 
15893 /* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
15894 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
15895 #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
15896 #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
15897 #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
15898 
15899 /* Bit 1 : Enable or disable interrupt for event STARTED */
15900 #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
15901 #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
15902 #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
15903 #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
15904 
15905 /* Bit 0 : Enable or disable interrupt for event USBRESET */
15906 #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
15907 #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
15908 #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
15909 #define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
15910 
15911 /* Register: USBD_INTENSET */
15912 /* Description: Enable interrupt */
15913 
15914 /* Bit 24 : Write '1' to enable interrupt for event EPDATA */
15915 #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
15916 #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
15917 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
15918 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
15919 #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
15920 
15921 /* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
15922 #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
15923 #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
15924 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
15925 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
15926 #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
15927 
15928 /* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
15929 #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
15930 #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
15931 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
15932 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
15933 #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
15934 
15935 /* Bit 21 : Write '1' to enable interrupt for event SOF */
15936 #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
15937 #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
15938 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
15939 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
15940 #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
15941 
15942 /* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
15943 #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
15944 #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
15945 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
15946 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
15947 #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
15948 
15949 /* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
15950 #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
15951 #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
15952 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
15953 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
15954 #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
15955 
15956 /* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
15957 #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
15958 #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
15959 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
15960 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
15961 #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
15962 
15963 /* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
15964 #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
15965 #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
15966 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
15967 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
15968 #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
15969 
15970 /* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
15971 #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
15972 #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
15973 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
15974 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
15975 #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
15976 
15977 /* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
15978 #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
15979 #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
15980 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
15981 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
15982 #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
15983 
15984 /* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
15985 #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
15986 #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
15987 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
15988 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
15989 #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
15990 
15991 /* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
15992 #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
15993 #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
15994 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
15995 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
15996 #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
15997 
15998 /* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
15999 #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
16000 #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
16001 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
16002 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
16003 #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
16004 
16005 /* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
16006 #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
16007 #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
16008 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
16009 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
16010 #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
16011 
16012 /* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
16013 #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
16014 #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
16015 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
16016 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
16017 #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
16018 
16019 /* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
16020 #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
16021 #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
16022 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16023 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16024 #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
16025 
16026 /* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
16027 #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
16028 #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
16029 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16030 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16031 #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
16032 
16033 /* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
16034 #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
16035 #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
16036 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16037 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16038 #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
16039 
16040 /* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
16041 #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
16042 #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
16043 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16044 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16045 #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
16046 
16047 /* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
16048 #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
16049 #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
16050 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16051 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16052 #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
16053 
16054 /* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
16055 #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
16056 #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
16057 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16058 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16059 #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
16060 
16061 /* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
16062 #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
16063 #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
16064 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16065 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16066 #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
16067 
16068 /* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
16069 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16070 #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
16071 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16072 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16073 #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
16074 
16075 /* Bit 1 : Write '1' to enable interrupt for event STARTED */
16076 #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
16077 #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
16078 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
16079 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
16080 #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
16081 
16082 /* Bit 0 : Write '1' to enable interrupt for event USBRESET */
16083 #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
16084 #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
16085 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16086 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16087 #define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
16088 
16089 /* Register: USBD_INTENCLR */
16090 /* Description: Disable interrupt */
16091 
16092 /* Bit 24 : Write '1' to disable interrupt for event EPDATA */
16093 #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
16094 #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
16095 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
16096 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
16097 #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
16098 
16099 /* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
16100 #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
16101 #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
16102 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
16103 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
16104 #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
16105 
16106 /* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
16107 #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
16108 #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
16109 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
16110 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
16111 #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
16112 
16113 /* Bit 21 : Write '1' to disable interrupt for event SOF */
16114 #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
16115 #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
16116 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
16117 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
16118 #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
16119 
16120 /* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
16121 #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
16122 #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
16123 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
16124 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
16125 #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
16126 
16127 /* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
16128 #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
16129 #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
16130 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
16131 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
16132 #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
16133 
16134 /* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
16135 #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
16136 #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
16137 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
16138 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
16139 #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
16140 
16141 /* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
16142 #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
16143 #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
16144 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
16145 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
16146 #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
16147 
16148 /* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
16149 #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
16150 #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
16151 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
16152 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
16153 #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
16154 
16155 /* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
16156 #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
16157 #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
16158 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
16159 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
16160 #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
16161 
16162 /* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
16163 #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
16164 #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
16165 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
16166 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
16167 #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
16168 
16169 /* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
16170 #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
16171 #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
16172 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
16173 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
16174 #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
16175 
16176 /* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
16177 #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
16178 #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
16179 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
16180 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
16181 #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
16182 
16183 /* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
16184 #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
16185 #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
16186 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
16187 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
16188 #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
16189 
16190 /* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
16191 #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
16192 #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
16193 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
16194 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
16195 #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
16196 
16197 /* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
16198 #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
16199 #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
16200 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16201 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16202 #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
16203 
16204 /* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
16205 #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
16206 #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
16207 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16208 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16209 #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
16210 
16211 /* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
16212 #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
16213 #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
16214 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16215 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16216 #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
16217 
16218 /* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
16219 #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
16220 #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
16221 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16222 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16223 #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
16224 
16225 /* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
16226 #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
16227 #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
16228 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16229 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16230 #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
16231 
16232 /* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
16233 #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
16234 #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
16235 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16236 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16237 #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
16238 
16239 /* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
16240 #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
16241 #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
16242 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16243 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16244 #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
16245 
16246 /* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
16247 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16248 #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
16249 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16250 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16251 #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
16252 
16253 /* Bit 1 : Write '1' to disable interrupt for event STARTED */
16254 #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
16255 #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
16256 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
16257 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
16258 #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
16259 
16260 /* Bit 0 : Write '1' to disable interrupt for event USBRESET */
16261 #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
16262 #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
16263 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16264 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16265 #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
16266 
16267 /* Register: USBD_EVENTCAUSE */
16268 /* Description: Details on what caused the USBEVENT event */
16269 
16270 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
16271 #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
16272 #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
16273 #define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
16274 #define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
16275 
16276 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
16277 #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
16278 #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
16279 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
16280 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
16281 
16282 /* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
16283 #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
16284 #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
16285 #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
16286 #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
16287 
16288 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
16289 #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
16290 #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
16291 #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
16292 #define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
16293 
16294 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
16295 #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
16296 #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
16297 #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
16298 #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
16299 
16300 /* Register: USBD_HALTED_EPIN */
16301 /* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16302 
16303 /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16304 #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
16305 #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
16306 #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
16307 #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
16308 
16309 /* Register: USBD_HALTED_EPOUT */
16310 /* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16311 
16312 /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16313 #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
16314 #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
16315 #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
16316 #define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
16317 
16318 /* Register: USBD_EPSTATUS */
16319 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
16320 
16321 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16322 #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
16323 #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
16324 #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16325 #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16326 
16327 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16328 #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
16329 #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
16330 #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16331 #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16332 
16333 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16334 #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
16335 #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
16336 #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16337 #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16338 
16339 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16340 #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
16341 #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
16342 #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16343 #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16344 
16345 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16346 #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
16347 #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
16348 #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16349 #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16350 
16351 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16352 #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
16353 #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
16354 #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16355 #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16356 
16357 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16358 #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
16359 #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
16360 #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16361 #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16362 
16363 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16364 #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
16365 #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
16366 #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16367 #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16368 
16369 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16370 #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
16371 #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
16372 #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16373 #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16374 
16375 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16376 #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
16377 #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
16378 #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16379 #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16380 
16381 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16382 #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
16383 #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
16384 #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16385 #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16386 
16387 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16388 #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
16389 #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
16390 #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16391 #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16392 
16393 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16394 #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
16395 #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
16396 #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16397 #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16398 
16399 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16400 #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
16401 #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
16402 #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16403 #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16404 
16405 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16406 #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
16407 #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
16408 #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16409 #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16410 
16411 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16412 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16413 #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
16414 #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16415 #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16416 
16417 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16418 #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
16419 #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
16420 #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16421 #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16422 
16423 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16424 #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
16425 #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
16426 #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16427 #define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16428 
16429 /* Register: USBD_EPDATASTATUS */
16430 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
16431 
16432 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16433 #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
16434 #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
16435 #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16436 #define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16437 
16438 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16439 #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
16440 #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
16441 #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16442 #define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16443 
16444 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16445 #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
16446 #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
16447 #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16448 #define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16449 
16450 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16451 #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
16452 #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
16453 #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16454 #define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16455 
16456 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16457 #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
16458 #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
16459 #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16460 #define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16461 
16462 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16463 #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
16464 #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
16465 #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16466 #define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16467 
16468 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16469 #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
16470 #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
16471 #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16472 #define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16473 
16474 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16475 #define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
16476 #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
16477 #define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16478 #define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16479 
16480 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16481 #define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
16482 #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
16483 #define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16484 #define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16485 
16486 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16487 #define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
16488 #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
16489 #define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16490 #define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16491 
16492 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16493 #define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
16494 #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
16495 #define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16496 #define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16497 
16498 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16499 #define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
16500 #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
16501 #define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16502 #define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16503 
16504 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16505 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16506 #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
16507 #define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16508 #define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16509 
16510 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16511 #define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
16512 #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
16513 #define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16514 #define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16515 
16516 /* Register: USBD_USBADDR */
16517 /* Description: Device USB address */
16518 
16519 /* Bits 6..0 : Device USB address */
16520 #define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
16521 #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
16522 
16523 /* Register: USBD_BMREQUESTTYPE */
16524 /* Description: SETUP data, byte 0, bmRequestType */
16525 
16526 /* Bit 7 : Data transfer direction */
16527 #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
16528 #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
16529 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
16530 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
16531 
16532 /* Bits 6..5 : Data transfer type */
16533 #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
16534 #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
16535 #define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
16536 #define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
16537 #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
16538 
16539 /* Bits 4..0 : Data transfer type */
16540 #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
16541 #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
16542 #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
16543 #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
16544 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
16545 #define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
16546 
16547 /* Register: USBD_BREQUEST */
16548 /* Description: SETUP data, byte 1, bRequest */
16549 
16550 /* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
16551 #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
16552 #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
16553 #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
16554 #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
16555 #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
16556 #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
16557 #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
16558 #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
16559 #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
16560 #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
16561 #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
16562 #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
16563 #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
16564 
16565 /* Register: USBD_WVALUEL */
16566 /* Description: SETUP data, byte 2, LSB of wValue */
16567 
16568 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
16569 #define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
16570 #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
16571 
16572 /* Register: USBD_WVALUEH */
16573 /* Description: SETUP data, byte 3, MSB of wValue */
16574 
16575 /* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
16576 #define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
16577 #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
16578 
16579 /* Register: USBD_WINDEXL */
16580 /* Description: SETUP data, byte 4, LSB of wIndex */
16581 
16582 /* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
16583 #define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
16584 #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
16585 
16586 /* Register: USBD_WINDEXH */
16587 /* Description: SETUP data, byte 5, MSB of wIndex */
16588 
16589 /* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
16590 #define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
16591 #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
16592 
16593 /* Register: USBD_WLENGTHL */
16594 /* Description: SETUP data, byte 6, LSB of wLength */
16595 
16596 /* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
16597 #define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
16598 #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
16599 
16600 /* Register: USBD_WLENGTHH */
16601 /* Description: SETUP data, byte 7, MSB of wLength */
16602 
16603 /* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
16604 #define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
16605 #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
16606 
16607 /* Register: USBD_SIZE_EPOUT */
16608 /* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
16609 
16610 /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
16611 #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
16612 #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
16613 
16614 /* Register: USBD_SIZE_ISOOUT */
16615 /* Description: Number of bytes received last on this ISO OUT data endpoint */
16616 
16617 /* Bit 16 : Zero-length data packet received */
16618 #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
16619 #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
16620 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
16621 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
16622 
16623 /* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
16624 #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
16625 #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
16626 
16627 /* Register: USBD_ENABLE */
16628 /* Description: Enable USB */
16629 
16630 /* Bit 0 : Enable USB */
16631 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16632 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16633 #define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
16634 #define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
16635 
16636 /* Register: USBD_USBPULLUP */
16637 /* Description: Control of the USB pull-up */
16638 
16639 /* Bit 0 : Control of the USB pull-up on the D+ line */
16640 #define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
16641 #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16642 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
16643 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
16644 
16645 /* Register: USBD_DPDMVALUE */
16646 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
16647 
16648 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
16649 #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
16650 #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
16651 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
16652 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
16653 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
16654 
16655 /* Register: USBD_DTOGGLE */
16656 /* Description: Data toggle control and status */
16657 
16658 /* Bits 9..8 : Data toggle value */
16659 #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
16660 #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
16661 #define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
16662 #define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
16663 #define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
16664 
16665 /* Bit 7 : Selects IN or OUT endpoint */
16666 #define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
16667 #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
16668 #define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
16669 #define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
16670 
16671 /* Bits 2..0 : Select bulk endpoint number */
16672 #define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
16673 #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
16674 
16675 /* Register: USBD_EPINEN */
16676 /* Description: Endpoint IN enable */
16677 
16678 /* Bit 8 : Enable ISO IN endpoint */
16679 #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
16680 #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
16681 #define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
16682 #define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
16683 
16684 /* Bit 7 : Enable IN endpoint 7 */
16685 #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
16686 #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
16687 #define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
16688 #define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
16689 
16690 /* Bit 6 : Enable IN endpoint 6 */
16691 #define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
16692 #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
16693 #define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
16694 #define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
16695 
16696 /* Bit 5 : Enable IN endpoint 5 */
16697 #define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
16698 #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
16699 #define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
16700 #define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
16701 
16702 /* Bit 4 : Enable IN endpoint 4 */
16703 #define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
16704 #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
16705 #define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
16706 #define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
16707 
16708 /* Bit 3 : Enable IN endpoint 3 */
16709 #define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
16710 #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
16711 #define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
16712 #define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
16713 
16714 /* Bit 2 : Enable IN endpoint 2 */
16715 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
16716 #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
16717 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
16718 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
16719 
16720 /* Bit 1 : Enable IN endpoint 1 */
16721 #define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
16722 #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
16723 #define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
16724 #define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
16725 
16726 /* Bit 0 : Enable IN endpoint 0 */
16727 #define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
16728 #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
16729 #define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
16730 #define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
16731 
16732 /* Register: USBD_EPOUTEN */
16733 /* Description: Endpoint OUT enable */
16734 
16735 /* Bit 8 : Enable ISO OUT endpoint 8 */
16736 #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
16737 #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
16738 #define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
16739 #define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
16740 
16741 /* Bit 7 : Enable OUT endpoint 7 */
16742 #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
16743 #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
16744 #define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
16745 #define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
16746 
16747 /* Bit 6 : Enable OUT endpoint 6 */
16748 #define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
16749 #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
16750 #define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
16751 #define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
16752 
16753 /* Bit 5 : Enable OUT endpoint 5 */
16754 #define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
16755 #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
16756 #define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
16757 #define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
16758 
16759 /* Bit 4 : Enable OUT endpoint 4 */
16760 #define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
16761 #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
16762 #define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
16763 #define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
16764 
16765 /* Bit 3 : Enable OUT endpoint 3 */
16766 #define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
16767 #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
16768 #define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
16769 #define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
16770 
16771 /* Bit 2 : Enable OUT endpoint 2 */
16772 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
16773 #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
16774 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
16775 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
16776 
16777 /* Bit 1 : Enable OUT endpoint 1 */
16778 #define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
16779 #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
16780 #define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
16781 #define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
16782 
16783 /* Bit 0 : Enable OUT endpoint 0 */
16784 #define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
16785 #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
16786 #define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
16787 #define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
16788 
16789 /* Register: USBD_EPSTALL */
16790 /* Description: STALL endpoints */
16791 
16792 /* Bit 8 : Stall selected endpoint */
16793 #define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
16794 #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
16795 #define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
16796 #define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
16797 
16798 /* Bit 7 : Selects IN or OUT endpoint */
16799 #define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
16800 #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
16801 #define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
16802 #define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
16803 
16804 /* Bits 2..0 : Select endpoint number */
16805 #define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
16806 #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
16807 
16808 /* Register: USBD_ISOSPLIT */
16809 /* Description: Controls the split of ISO buffers */
16810 
16811 /* Bits 15..0 : Controls the split of ISO buffers */
16812 #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
16813 #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
16814 #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
16815 #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
16816 
16817 /* Register: USBD_FRAMECNTR */
16818 /* Description: Returns the current value of the start of frame counter */
16819 
16820 /* Bits 10..0 : Returns the current value of the start of frame counter */
16821 #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
16822 #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
16823 
16824 /* Register: USBD_LOWPOWER */
16825 /* Description: Controls USBD peripheral low power mode during USB suspend */
16826 
16827 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
16828 #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
16829 #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
16830 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
16831 #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
16832 
16833 /* Register: USBD_ISOINCONFIG */
16834 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
16835 
16836 /* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
16837 #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
16838 #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
16839 #define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
16840 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
16841 
16842 /* Register: USBD_EPIN_PTR */
16843 /* Description: Description cluster: Data pointer */
16844 
16845 /* Bits 31..0 : Data pointer */
16846 #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16847 #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16848 
16849 /* Register: USBD_EPIN_MAXCNT */
16850 /* Description: Description cluster: Maximum number of bytes to transfer */
16851 
16852 /* Bits 6..0 : Maximum number of bytes to transfer */
16853 #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16854 #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16855 
16856 /* Register: USBD_EPIN_AMOUNT */
16857 /* Description: Description cluster: Number of bytes transferred in the last transaction */
16858 
16859 /* Bits 6..0 : Number of bytes transferred in the last transaction */
16860 #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16861 #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16862 
16863 /* Register: USBD_ISOIN_PTR */
16864 /* Description: Data pointer */
16865 
16866 /* Bits 31..0 : Data pointer */
16867 #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16868 #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16869 
16870 /* Register: USBD_ISOIN_MAXCNT */
16871 /* Description: Maximum number of bytes to transfer */
16872 
16873 /* Bits 9..0 : Maximum number of bytes to transfer */
16874 #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16875 #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16876 
16877 /* Register: USBD_ISOIN_AMOUNT */
16878 /* Description: Number of bytes transferred in the last transaction */
16879 
16880 /* Bits 9..0 : Number of bytes transferred in the last transaction */
16881 #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16882 #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16883 
16884 /* Register: USBD_EPOUT_PTR */
16885 /* Description: Description cluster: Data pointer */
16886 
16887 /* Bits 31..0 : Data pointer */
16888 #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16889 #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16890 
16891 /* Register: USBD_EPOUT_MAXCNT */
16892 /* Description: Description cluster: Maximum number of bytes to transfer */
16893 
16894 /* Bits 6..0 : Maximum number of bytes to transfer */
16895 #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16896 #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16897 
16898 /* Register: USBD_EPOUT_AMOUNT */
16899 /* Description: Description cluster: Number of bytes transferred in the last transaction */
16900 
16901 /* Bits 6..0 : Number of bytes transferred in the last transaction */
16902 #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16903 #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16904 
16905 /* Register: USBD_ISOOUT_PTR */
16906 /* Description: Data pointer */
16907 
16908 /* Bits 31..0 : Data pointer */
16909 #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16910 #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16911 
16912 /* Register: USBD_ISOOUT_MAXCNT */
16913 /* Description: Maximum number of bytes to transfer */
16914 
16915 /* Bits 9..0 : Maximum number of bytes to transfer */
16916 #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16917 #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16918 
16919 /* Register: USBD_ISOOUT_AMOUNT */
16920 /* Description: Number of bytes transferred in the last transaction */
16921 
16922 /* Bits 9..0 : Number of bytes transferred in the last transaction */
16923 #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16924 #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16925 
16926 
16927 /* Peripheral: WDT */
16928 /* Description: Watchdog Timer */
16929 
16930 /* Register: WDT_TASKS_START */
16931 /* Description: Start the watchdog */
16932 
16933 /* Bit 0 : Start the watchdog */
16934 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
16935 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
16936 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
16937 
16938 /* Register: WDT_EVENTS_TIMEOUT */
16939 /* Description: Watchdog timeout */
16940 
16941 /* Bit 0 : Watchdog timeout */
16942 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
16943 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
16944 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
16945 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
16946 
16947 /* Register: WDT_INTENSET */
16948 /* Description: Enable interrupt */
16949 
16950 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
16951 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
16952 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
16953 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
16954 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
16955 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
16956 
16957 /* Register: WDT_INTENCLR */
16958 /* Description: Disable interrupt */
16959 
16960 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
16961 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
16962 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
16963 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
16964 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
16965 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
16966 
16967 /* Register: WDT_RUNSTATUS */
16968 /* Description: Run status */
16969 
16970 /* Bit 0 : Indicates whether or not the watchdog is running */
16971 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
16972 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
16973 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
16974 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
16975 
16976 /* Register: WDT_REQSTATUS */
16977 /* Description: Request status */
16978 
16979 /* Bit 7 : Request status for RR[7] register */
16980 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
16981 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
16982 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
16983 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
16984 
16985 /* Bit 6 : Request status for RR[6] register */
16986 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
16987 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
16988 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
16989 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
16990 
16991 /* Bit 5 : Request status for RR[5] register */
16992 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
16993 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
16994 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
16995 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
16996 
16997 /* Bit 4 : Request status for RR[4] register */
16998 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
16999 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
17000 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
17001 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
17002 
17003 /* Bit 3 : Request status for RR[3] register */
17004 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
17005 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
17006 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
17007 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
17008 
17009 /* Bit 2 : Request status for RR[2] register */
17010 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
17011 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
17012 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
17013 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
17014 
17015 /* Bit 1 : Request status for RR[1] register */
17016 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
17017 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
17018 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
17019 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
17020 
17021 /* Bit 0 : Request status for RR[0] register */
17022 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
17023 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
17024 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
17025 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
17026 
17027 /* Register: WDT_CRV */
17028 /* Description: Counter reload value */
17029 
17030 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
17031 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
17032 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
17033 
17034 /* Register: WDT_RREN */
17035 /* Description: Enable register for reload request registers */
17036 
17037 /* Bit 7 : Enable or disable RR[7] register */
17038 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
17039 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
17040 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
17041 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
17042 
17043 /* Bit 6 : Enable or disable RR[6] register */
17044 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
17045 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
17046 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
17047 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
17048 
17049 /* Bit 5 : Enable or disable RR[5] register */
17050 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
17051 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
17052 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
17053 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
17054 
17055 /* Bit 4 : Enable or disable RR[4] register */
17056 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
17057 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
17058 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
17059 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
17060 
17061 /* Bit 3 : Enable or disable RR[3] register */
17062 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
17063 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
17064 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
17065 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
17066 
17067 /* Bit 2 : Enable or disable RR[2] register */
17068 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
17069 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
17070 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
17071 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
17072 
17073 /* Bit 1 : Enable or disable RR[1] register */
17074 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
17075 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
17076 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
17077 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
17078 
17079 /* Bit 0 : Enable or disable RR[0] register */
17080 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
17081 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
17082 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
17083 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
17084 
17085 /* Register: WDT_CONFIG */
17086 /* Description: Configuration register */
17087 
17088 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
17089 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
17090 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
17091 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
17092 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
17093 
17094 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
17095 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
17096 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
17097 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
17098 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
17099 
17100 /* Register: WDT_RR */
17101 /* Description: Description collection: Reload request n */
17102 
17103 /* Bits 31..0 : Reload request register */
17104 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
17105 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
17106 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
17107 
17108 
17109 /*lint --flb "Leave library region" */
17110 #endif
17111