1 /*
2 
3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52820_BITS_H
36 #define __NRF52820_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: ACL */
180 /* Description: Access control lists */
181 
182 /* Register: ACL_ACL_ADDR */
183 /* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */
184 
185 /* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */
186 #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
187 #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
188 
189 /* Register: ACL_ACL_SIZE */
190 /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
191 
192 /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
193 #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
194 #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
195 
196 /* Register: ACL_ACL_PERM */
197 /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
198 
199 /* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
200 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
201 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
202 #define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
203 #define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
204 
205 /* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
206 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
207 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
208 #define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
209 #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
210 
211 
212 /* Peripheral: APPROTECT */
213 /* Description: Access Port Protection */
214 
215 /* Register: APPROTECT_FORCEPROTECT */
216 /* Description: Software force enable APPROTECT mechanism until next reset. */
217 
218 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
219 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
220 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
221 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */
222 
223 /* Register: APPROTECT_DISABLE */
224 /* Description: Software disable APPROTECT mechanism */
225 
226 /* Bits 7..0 : Software disable APPROTECT mechanism */
227 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
228 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
229 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
230 
231 
232 /* Peripheral: CCM */
233 /* Description: AES CCM mode encryption */
234 
235 /* Register: CCM_TASKS_KSGEN */
236 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
237 
238 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
239 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
240 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
241 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
242 
243 /* Register: CCM_TASKS_CRYPT */
244 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
245 
246 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
247 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
248 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
249 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
250 
251 /* Register: CCM_TASKS_STOP */
252 /* Description: Stop encryption/decryption */
253 
254 /* Bit 0 : Stop encryption/decryption */
255 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
256 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
257 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
258 
259 /* Register: CCM_TASKS_RATEOVERRIDE */
260 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
261 
262 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
263 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
264 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
265 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
266 
267 /* Register: CCM_EVENTS_ENDKSGEN */
268 /* Description: Keystream generation complete */
269 
270 /* Bit 0 : Keystream generation complete */
271 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
272 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
273 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
274 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
275 
276 /* Register: CCM_EVENTS_ENDCRYPT */
277 /* Description: Encrypt/decrypt complete */
278 
279 /* Bit 0 : Encrypt/decrypt complete */
280 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
281 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
282 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
283 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
284 
285 /* Register: CCM_EVENTS_ERROR */
286 /* Description: Deprecated register - CCM error event */
287 
288 /* Bit 0 : Deprecated field -  CCM error event */
289 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
290 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
291 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
292 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
293 
294 /* Register: CCM_SHORTS */
295 /* Description: Shortcuts between local events and tasks */
296 
297 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
298 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
299 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
300 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
301 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
302 
303 /* Register: CCM_INTENSET */
304 /* Description: Enable interrupt */
305 
306 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
307 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
308 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
309 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
310 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
311 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
312 
313 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
314 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
315 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
316 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
317 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
318 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
319 
320 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
321 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
322 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
323 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
324 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
325 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
326 
327 /* Register: CCM_INTENCLR */
328 /* Description: Disable interrupt */
329 
330 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
331 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
332 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
333 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
334 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
335 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
336 
337 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
338 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
339 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
340 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
341 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
342 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
343 
344 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
345 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
346 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
347 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
348 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
349 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
350 
351 /* Register: CCM_MICSTATUS */
352 /* Description: MIC check result */
353 
354 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
355 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
356 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
357 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
358 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
359 
360 /* Register: CCM_ENABLE */
361 /* Description: Enable */
362 
363 /* Bits 1..0 : Enable or disable CCM */
364 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
365 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
366 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
367 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
368 
369 /* Register: CCM_MODE */
370 /* Description: Operation mode */
371 
372 /* Bit 24 : Packet length configuration */
373 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
374 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
375 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
376 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
377 
378 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
379 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
380 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
381 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
382 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
383 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
384 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
385 
386 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
387 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
388 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
389 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
390 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
391 
392 /* Register: CCM_CNFPTR */
393 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
394 
395 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
396 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
397 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
398 
399 /* Register: CCM_INPTR */
400 /* Description: Input pointer */
401 
402 /* Bits 31..0 : Input pointer */
403 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
404 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
405 
406 /* Register: CCM_OUTPTR */
407 /* Description: Output pointer */
408 
409 /* Bits 31..0 : Output pointer */
410 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
411 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
412 
413 /* Register: CCM_SCRATCHPTR */
414 /* Description: Pointer to data area used for temporary storage */
415 
416 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
417         MIC generation and encryption/decryption. */
418 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
419 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
420 
421 /* Register: CCM_MAXPACKETSIZE */
422 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
423 
424 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
425 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
426 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
427 
428 /* Register: CCM_RATEOVERRIDE */
429 /* Description: Data rate override setting. */
430 
431 /* Bits 1..0 : Data rate override setting */
432 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
433 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
434 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
435 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
436 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
437 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
438 
439 /* Register: CCM_HEADERMASK */
440 /* Description: Header (S0) mask. */
441 
442 /* Bits 7..0 : Header (S0) mask */
443 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
444 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
445 
446 
447 /* Peripheral: CLOCK */
448 /* Description: Clock control */
449 
450 /* Register: CLOCK_TASKS_HFCLKSTART */
451 /* Description: Start HFXO crystal oscillator */
452 
453 /* Bit 0 : Start HFXO crystal oscillator */
454 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
455 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
456 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
457 
458 /* Register: CLOCK_TASKS_HFCLKSTOP */
459 /* Description: Stop HFXO crystal oscillator */
460 
461 /* Bit 0 : Stop HFXO crystal oscillator */
462 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
463 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
464 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
465 
466 /* Register: CLOCK_TASKS_LFCLKSTART */
467 /* Description: Start LFCLK */
468 
469 /* Bit 0 : Start LFCLK */
470 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
471 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
472 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
473 
474 /* Register: CLOCK_TASKS_LFCLKSTOP */
475 /* Description: Stop LFCLK */
476 
477 /* Bit 0 : Stop LFCLK */
478 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
479 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
480 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
481 
482 /* Register: CLOCK_TASKS_CAL */
483 /* Description: Start calibration of LFRC */
484 
485 /* Bit 0 : Start calibration of LFRC */
486 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
487 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
488 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
489 
490 /* Register: CLOCK_TASKS_CTSTART */
491 /* Description: Start calibration timer */
492 
493 /* Bit 0 : Start calibration timer */
494 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
495 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
496 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
497 
498 /* Register: CLOCK_TASKS_CTSTOP */
499 /* Description: Stop calibration timer */
500 
501 /* Bit 0 : Stop calibration timer */
502 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
503 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
504 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
505 
506 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
507 /* Description: HFXO crystal oscillator started */
508 
509 /* Bit 0 : HFXO crystal oscillator started */
510 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
511 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
512 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
513 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
514 
515 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
516 /* Description: LFCLK started */
517 
518 /* Bit 0 : LFCLK started */
519 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
520 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
521 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
522 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
523 
524 /* Register: CLOCK_EVENTS_DONE */
525 /* Description: Calibration of LFRC completed */
526 
527 /* Bit 0 : Calibration of LFRC completed */
528 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
529 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
530 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
531 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
532 
533 /* Register: CLOCK_EVENTS_CTTO */
534 /* Description: Calibration timer timeout */
535 
536 /* Bit 0 : Calibration timer timeout */
537 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
538 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
539 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
540 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
541 
542 /* Register: CLOCK_EVENTS_CTSTARTED */
543 /* Description: Calibration timer has been started and is ready to process new tasks */
544 
545 /* Bit 0 : Calibration timer has been started and is ready to process new tasks */
546 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */
547 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */
548 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */
549 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */
550 
551 /* Register: CLOCK_EVENTS_CTSTOPPED */
552 /* Description: Calibration timer has been stopped and is ready to process new tasks */
553 
554 /* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */
555 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */
556 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */
557 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */
558 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */
559 
560 /* Register: CLOCK_INTENSET */
561 /* Description: Enable interrupt */
562 
563 /* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */
564 #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
565 #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
566 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
567 #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
568 #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
569 
570 /* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */
571 #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
572 #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
573 #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
574 #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
575 #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
576 
577 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
578 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
579 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
580 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
581 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
582 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
583 
584 /* Bit 3 : Write '1' to enable interrupt for event DONE */
585 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
586 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
587 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
588 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
589 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
590 
591 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
592 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
593 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
594 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
595 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
596 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
597 
598 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
599 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
600 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
601 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
602 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
603 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
604 
605 /* Register: CLOCK_INTENCLR */
606 /* Description: Disable interrupt */
607 
608 /* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */
609 #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
610 #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
611 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
612 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
613 #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
614 
615 /* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */
616 #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
617 #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
618 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
619 #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
620 #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
621 
622 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
623 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
624 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
625 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
626 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
627 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
628 
629 /* Bit 3 : Write '1' to disable interrupt for event DONE */
630 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
631 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
632 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
633 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
634 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
635 
636 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
637 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
638 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
639 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
640 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
641 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
642 
643 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
644 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
645 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
646 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
647 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
648 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
649 
650 /* Register: CLOCK_HFCLKRUN */
651 /* Description: Status indicating that HFCLKSTART task has been triggered */
652 
653 /* Bit 0 : HFCLKSTART task triggered or not */
654 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
655 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
656 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
657 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
658 
659 /* Register: CLOCK_HFCLKSTAT */
660 /* Description: HFCLK status */
661 
662 /* Bit 16 : HFCLK state */
663 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
664 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
665 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
666 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
667 
668 /* Bit 0 : Source of HFCLK */
669 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
670 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
671 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
672 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
673 
674 /* Register: CLOCK_LFCLKRUN */
675 /* Description: Status indicating that LFCLKSTART task has been triggered */
676 
677 /* Bit 0 : LFCLKSTART task triggered or not */
678 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
679 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
680 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
681 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
682 
683 /* Register: CLOCK_LFCLKSTAT */
684 /* Description: LFCLK status */
685 
686 /* Bit 16 : LFCLK state */
687 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
688 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
689 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
690 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
691 
692 /* Bits 1..0 : Source of LFCLK */
693 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
694 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
695 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
696 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
697 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
698 
699 /* Register: CLOCK_LFCLKSRCCOPY */
700 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
701 
702 /* Bits 1..0 : Clock source */
703 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
704 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
705 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
706 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
707 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
708 
709 /* Register: CLOCK_LFCLKSRC */
710 /* Description: Clock source for the LFCLK */
711 
712 /* Bit 17 : Enable or disable external source for LFCLK */
713 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
714 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
715 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
716 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
717 
718 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
719 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
720 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
721 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
722 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
723 
724 /* Bits 1..0 : Clock source */
725 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
726 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
727 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
728 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
729 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
730 
731 /* Register: CLOCK_HFXODEBOUNCE */
732 /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
733 
734 /* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */
735 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */
736 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */
737 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for 1.6 mm x 2.0 mm crystals and larger. */
738 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. */
739 
740 /* Register: CLOCK_LFXODEBOUNCE */
741 /* Description: LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. */
742 
743 /* Bit 0 : LFXO debounce time. */
744 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos (0UL) /*!< Position of LFXODEBOUNCE field. */
745 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Msk (0x1UL << CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos) /*!< Bit mask of LFXODEBOUNCE field. */
746 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Normal (0UL) /*!< 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. */
747 #define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Extended (1UL) /*!< 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. */
748 
749 /* Register: CLOCK_CTIV */
750 /* Description: Calibration timer interval */
751 
752 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
753 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
754 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
755 
756 
757 /* Peripheral: COMP */
758 /* Description: Comparator */
759 
760 /* Register: COMP_TASKS_START */
761 /* Description: Start comparator */
762 
763 /* Bit 0 : Start comparator */
764 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
765 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
766 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
767 
768 /* Register: COMP_TASKS_STOP */
769 /* Description: Stop comparator */
770 
771 /* Bit 0 : Stop comparator */
772 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
773 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
774 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
775 
776 /* Register: COMP_TASKS_SAMPLE */
777 /* Description: Sample comparator value */
778 
779 /* Bit 0 : Sample comparator value */
780 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
781 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
782 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
783 
784 /* Register: COMP_EVENTS_READY */
785 /* Description: COMP is ready and output is valid */
786 
787 /* Bit 0 : COMP is ready and output is valid */
788 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
789 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
790 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
791 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
792 
793 /* Register: COMP_EVENTS_DOWN */
794 /* Description: Downward crossing */
795 
796 /* Bit 0 : Downward crossing */
797 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
798 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
799 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
800 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
801 
802 /* Register: COMP_EVENTS_UP */
803 /* Description: Upward crossing */
804 
805 /* Bit 0 : Upward crossing */
806 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
807 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
808 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
809 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
810 
811 /* Register: COMP_EVENTS_CROSS */
812 /* Description: Downward or upward crossing */
813 
814 /* Bit 0 : Downward or upward crossing */
815 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
816 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
817 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
818 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
819 
820 /* Register: COMP_SHORTS */
821 /* Description: Shortcuts between local events and tasks */
822 
823 /* Bit 4 : Shortcut between event CROSS and task STOP */
824 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
825 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
826 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
827 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
828 
829 /* Bit 3 : Shortcut between event UP and task STOP */
830 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
831 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
832 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
833 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
834 
835 /* Bit 2 : Shortcut between event DOWN and task STOP */
836 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
837 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
838 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
839 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
840 
841 /* Bit 1 : Shortcut between event READY and task STOP */
842 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
843 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
844 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
845 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
846 
847 /* Bit 0 : Shortcut between event READY and task SAMPLE */
848 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
849 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
850 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
851 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
852 
853 /* Register: COMP_INTEN */
854 /* Description: Enable or disable interrupt */
855 
856 /* Bit 3 : Enable or disable interrupt for event CROSS */
857 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
858 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
859 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
860 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
861 
862 /* Bit 2 : Enable or disable interrupt for event UP */
863 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
864 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
865 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
866 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
867 
868 /* Bit 1 : Enable or disable interrupt for event DOWN */
869 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
870 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
871 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
872 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
873 
874 /* Bit 0 : Enable or disable interrupt for event READY */
875 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
876 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
877 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
878 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
879 
880 /* Register: COMP_INTENSET */
881 /* Description: Enable interrupt */
882 
883 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
884 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
885 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
886 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
887 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
888 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
889 
890 /* Bit 2 : Write '1' to enable interrupt for event UP */
891 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
892 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
893 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
894 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
895 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
896 
897 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
898 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
899 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
900 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
901 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
902 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
903 
904 /* Bit 0 : Write '1' to enable interrupt for event READY */
905 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
906 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
907 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
908 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
909 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
910 
911 /* Register: COMP_INTENCLR */
912 /* Description: Disable interrupt */
913 
914 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
915 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
916 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
917 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
918 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
919 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
920 
921 /* Bit 2 : Write '1' to disable interrupt for event UP */
922 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
923 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
924 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
925 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
926 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
927 
928 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
929 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
930 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
931 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
932 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
933 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
934 
935 /* Bit 0 : Write '1' to disable interrupt for event READY */
936 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
937 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
938 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
939 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
940 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
941 
942 /* Register: COMP_RESULT */
943 /* Description: Compare result */
944 
945 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
946 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
947 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
948 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
949 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
950 
951 /* Register: COMP_ENABLE */
952 /* Description: COMP enable */
953 
954 /* Bits 1..0 : Enable or disable COMP */
955 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
956 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
957 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
958 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
959 
960 /* Register: COMP_PSEL */
961 /* Description: Pin select */
962 
963 /* Bits 2..0 : Analog pin select */
964 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
965 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
966 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
967 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
968 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
969 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
970 #define COMP_PSEL_PSEL_VddhDiv5 (7UL) /*!< VDDH/5 selected as analog input */
971 
972 /* Register: COMP_REFSEL */
973 /* Description: Reference source select for single-ended mode */
974 
975 /* Bits 2..0 : Reference select */
976 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
977 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
978 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
979 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
980 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
981 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
982 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */
983 
984 /* Register: COMP_EXTREFSEL */
985 /* Description: External reference select */
986 
987 /* Bits 2..0 : External analog reference select */
988 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
989 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
990 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
991 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
992 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
993 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
994 
995 /* Register: COMP_TH */
996 /* Description: Threshold configuration for hysteresis unit */
997 
998 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
999 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1000 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1001 
1002 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1003 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1004 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1005 
1006 /* Register: COMP_MODE */
1007 /* Description: Mode configuration */
1008 
1009 /* Bit 8 : Main operation modes */
1010 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1011 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1012 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1013 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1014 
1015 /* Bits 1..0 : Speed and power modes */
1016 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1017 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1018 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1019 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1020 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1021 
1022 /* Register: COMP_HYST */
1023 /* Description: Comparator hysteresis enable */
1024 
1025 /* Bit 0 : Comparator hysteresis */
1026 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1027 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1028 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1029 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1030 
1031 
1032 /* Peripheral: ECB */
1033 /* Description: AES ECB Mode Encryption */
1034 
1035 /* Register: ECB_TASKS_STARTECB */
1036 /* Description: Start ECB block encrypt */
1037 
1038 /* Bit 0 : Start ECB block encrypt */
1039 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1040 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1041 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1042 
1043 /* Register: ECB_TASKS_STOPECB */
1044 /* Description: Abort a possible executing ECB operation */
1045 
1046 /* Bit 0 : Abort a possible executing ECB operation */
1047 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1048 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1049 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1050 
1051 /* Register: ECB_EVENTS_ENDECB */
1052 /* Description: ECB block encrypt complete */
1053 
1054 /* Bit 0 : ECB block encrypt complete */
1055 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1056 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1057 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1058 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1059 
1060 /* Register: ECB_EVENTS_ERRORECB */
1061 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1062 
1063 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1064 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1065 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1066 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1067 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1068 
1069 /* Register: ECB_INTENSET */
1070 /* Description: Enable interrupt */
1071 
1072 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1073 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1074 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1075 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1076 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1077 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1078 
1079 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1080 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1081 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1082 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1083 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1084 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1085 
1086 /* Register: ECB_INTENCLR */
1087 /* Description: Disable interrupt */
1088 
1089 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1090 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1091 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1092 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1093 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1094 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1095 
1096 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1097 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1098 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1099 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1100 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1101 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1102 
1103 /* Register: ECB_ECBDATAPTR */
1104 /* Description: ECB block encrypt memory pointers */
1105 
1106 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1107 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1108 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1109 
1110 
1111 /* Peripheral: EGU */
1112 /* Description: Event generator unit 0 */
1113 
1114 /* Register: EGU_TASKS_TRIGGER */
1115 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1116 
1117 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1118 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1119 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1120 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1121 
1122 /* Register: EGU_EVENTS_TRIGGERED */
1123 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1124 
1125 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1126 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1127 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1128 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1129 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1130 
1131 /* Register: EGU_INTEN */
1132 /* Description: Enable or disable interrupt */
1133 
1134 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1135 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1136 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1137 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1138 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1139 
1140 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1141 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1142 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1143 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1144 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1145 
1146 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1147 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1148 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1149 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1150 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1151 
1152 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1153 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1154 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1155 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1156 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1157 
1158 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1159 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1160 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1161 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1162 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1163 
1164 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1165 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1166 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1167 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1168 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1169 
1170 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1171 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1172 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1173 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1174 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1175 
1176 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1177 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1178 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1179 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1180 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1181 
1182 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1183 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1184 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1185 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1186 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1187 
1188 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1189 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1190 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1191 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1192 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1193 
1194 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1195 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1196 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1197 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1198 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1199 
1200 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1201 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1202 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1203 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1204 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1205 
1206 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1207 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1208 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1209 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1210 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1211 
1212 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1213 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1214 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1215 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1216 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1217 
1218 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1219 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1220 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1221 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1222 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1223 
1224 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1225 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1226 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1227 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1228 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1229 
1230 /* Register: EGU_INTENSET */
1231 /* Description: Enable interrupt */
1232 
1233 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1234 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1235 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1236 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1237 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1238 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1239 
1240 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1241 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1242 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1243 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1244 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1245 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1246 
1247 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1248 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1249 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1250 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1251 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1252 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1253 
1254 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1255 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1256 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1257 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1258 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1259 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1260 
1261 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1262 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1263 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1264 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1265 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1266 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1267 
1268 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1269 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1270 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1271 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1272 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1273 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1274 
1275 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1276 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1277 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1278 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1279 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1280 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1281 
1282 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1283 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1284 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1285 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1286 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1287 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1288 
1289 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1290 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1291 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1292 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1293 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1294 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1295 
1296 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1297 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1298 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1299 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1300 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1301 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1302 
1303 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1304 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1305 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1306 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1307 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1308 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1309 
1310 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1311 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1312 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1313 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1314 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1315 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1316 
1317 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1318 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1319 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1320 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1321 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1322 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1323 
1324 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1325 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1326 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1327 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1328 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1329 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1330 
1331 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1332 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1333 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1334 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1335 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1336 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1337 
1338 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1339 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1340 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1341 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1342 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1343 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1344 
1345 /* Register: EGU_INTENCLR */
1346 /* Description: Disable interrupt */
1347 
1348 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1349 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1350 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1351 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1352 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1353 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1354 
1355 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1356 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1357 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1358 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1359 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1360 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1361 
1362 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1363 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1364 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1365 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1366 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1367 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1368 
1369 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1370 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1371 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1372 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1373 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1374 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1375 
1376 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1377 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1378 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1379 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1380 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1381 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1382 
1383 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1384 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1385 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1386 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1387 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1388 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1389 
1390 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1391 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1392 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1393 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1394 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1395 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1396 
1397 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1398 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1399 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1400 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1401 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1402 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1403 
1404 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1405 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1406 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1407 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1408 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1409 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1410 
1411 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1412 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1413 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1414 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1415 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1416 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1417 
1418 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1419 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1420 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1421 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1422 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1423 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1424 
1425 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1426 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1427 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1428 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1429 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1430 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1431 
1432 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1433 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1434 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1435 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1436 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1437 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1438 
1439 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1440 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1441 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1442 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1443 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1444 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1445 
1446 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1447 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1448 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1449 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1450 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1451 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1452 
1453 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1454 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1455 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1456 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1457 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1458 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1459 
1460 
1461 /* Peripheral: FICR */
1462 /* Description: Factory information configuration registers */
1463 
1464 /* Register: FICR_CODEPAGESIZE */
1465 /* Description: Code memory page size */
1466 
1467 /* Bits 31..0 : Code memory page size */
1468 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1469 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1470 
1471 /* Register: FICR_CODESIZE */
1472 /* Description: Code memory size */
1473 
1474 /* Bits 31..0 : Code memory size in number of pages */
1475 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1476 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1477 
1478 /* Register: FICR_DEVICEID */
1479 /* Description: Description collection: Device identifier */
1480 
1481 /* Bits 31..0 : 64 bit unique device identifier */
1482 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1483 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1484 
1485 /* Register: FICR_ER */
1486 /* Description: Description collection: Encryption root, word n */
1487 
1488 /* Bits 31..0 : Encryption root, word n */
1489 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1490 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1491 
1492 /* Register: FICR_IR */
1493 /* Description: Description collection: Identity Root, word n */
1494 
1495 /* Bits 31..0 : Identity Root, word n */
1496 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1497 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1498 
1499 /* Register: FICR_DEVICEADDRTYPE */
1500 /* Description: Device address type */
1501 
1502 /* Bit 0 : Device address type */
1503 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1504 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1505 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1506 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1507 
1508 /* Register: FICR_DEVICEADDR */
1509 /* Description: Description collection: Device address n */
1510 
1511 /* Bits 31..0 : 48 bit device address */
1512 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1513 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1514 
1515 /* Register: FICR_INFO_PART */
1516 /* Description: Part code */
1517 
1518 /* Bits 31..0 : Part code */
1519 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1520 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1521 #define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */
1522 #define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */
1523 #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
1524 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1525 
1526 /* Register: FICR_INFO_VARIANT */
1527 /* Description: Build code (hardware version and production configuration) */
1528 
1529 /* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */
1530 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1531 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1532 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1533 #define FICR_INFO_VARIANT_VARIANT_AABC (0x41414243UL) /*!< AABC */
1534 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
1535 #define FICR_INFO_VARIANT_VARIANT_AAC1 (0x41414331UL) /*!< AAC1 */
1536 #define FICR_INFO_VARIANT_VARIANT_AAD0 (0x41414430UL) /*!< AAD0 */
1537 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1538 
1539 /* Register: FICR_INFO_PACKAGE */
1540 /* Description: Package option */
1541 
1542 /* Bits 31..0 : Package option */
1543 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1544 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1545 #define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 5x5 40-pin QFN */
1546 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1547 
1548 /* Register: FICR_INFO_RAM */
1549 /* Description: RAM variant */
1550 
1551 /* Bits 31..0 : RAM variant */
1552 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1553 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1554 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kB RAM */
1555 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kB RAM */
1556 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kB RAM */
1557 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kB RAM */
1558 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kB RAM */
1559 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1560 
1561 /* Register: FICR_INFO_FLASH */
1562 /* Description: Flash variant */
1563 
1564 /* Bits 31..0 : Flash variant */
1565 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1566 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1567 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kB FLASH */
1568 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kB FLASH */
1569 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kB FLASH */
1570 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MB FLASH */
1571 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MB FLASH */
1572 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1573 
1574 /* Register: FICR_PRODTEST */
1575 /* Description: Description collection: Production test signature n */
1576 
1577 /* Bits 31..0 : Production test signature n */
1578 #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */
1579 #define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */
1580 #define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */
1581 #define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */
1582 
1583 /* Register: FICR_TEMP_A0 */
1584 /* Description: Slope definition A0 */
1585 
1586 /* Bits 11..0 : A (slope definition) register. */
1587 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1588 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1589 
1590 /* Register: FICR_TEMP_A1 */
1591 /* Description: Slope definition A1 */
1592 
1593 /* Bits 11..0 : A (slope definition) register. */
1594 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1595 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1596 
1597 /* Register: FICR_TEMP_A2 */
1598 /* Description: Slope definition A2 */
1599 
1600 /* Bits 11..0 : A (slope definition) register. */
1601 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1602 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1603 
1604 /* Register: FICR_TEMP_A3 */
1605 /* Description: Slope definition A3 */
1606 
1607 /* Bits 11..0 : A (slope definition) register. */
1608 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1609 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1610 
1611 /* Register: FICR_TEMP_A4 */
1612 /* Description: Slope definition A4 */
1613 
1614 /* Bits 11..0 : A (slope definition) register. */
1615 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1616 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1617 
1618 /* Register: FICR_TEMP_A5 */
1619 /* Description: Slope definition A5 */
1620 
1621 /* Bits 11..0 : A (slope definition) register. */
1622 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1623 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1624 
1625 /* Register: FICR_TEMP_B0 */
1626 /* Description: Y-intercept B0 */
1627 
1628 /* Bits 13..0 : B (y-intercept) */
1629 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1630 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1631 
1632 /* Register: FICR_TEMP_B1 */
1633 /* Description: Y-intercept B1 */
1634 
1635 /* Bits 13..0 : B (y-intercept) */
1636 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
1637 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
1638 
1639 /* Register: FICR_TEMP_B2 */
1640 /* Description: Y-intercept B2 */
1641 
1642 /* Bits 13..0 : B (y-intercept) */
1643 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
1644 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
1645 
1646 /* Register: FICR_TEMP_B3 */
1647 /* Description: Y-intercept B3 */
1648 
1649 /* Bits 13..0 : B (y-intercept) */
1650 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
1651 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
1652 
1653 /* Register: FICR_TEMP_B4 */
1654 /* Description: Y-intercept B4 */
1655 
1656 /* Bits 13..0 : B (y-intercept) */
1657 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
1658 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
1659 
1660 /* Register: FICR_TEMP_B5 */
1661 /* Description: Y-intercept B5 */
1662 
1663 /* Bits 13..0 : B (y-intercept) */
1664 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
1665 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1666 
1667 /* Register: FICR_TEMP_T0 */
1668 /* Description: Segment end T0 */
1669 
1670 /* Bits 7..0 : T (segment end) register */
1671 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
1672 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
1673 
1674 /* Register: FICR_TEMP_T1 */
1675 /* Description: Segment end T1 */
1676 
1677 /* Bits 7..0 : T (segment end) register */
1678 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
1679 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
1680 
1681 /* Register: FICR_TEMP_T2 */
1682 /* Description: Segment end T2 */
1683 
1684 /* Bits 7..0 : T (segment end) register */
1685 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
1686 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
1687 
1688 /* Register: FICR_TEMP_T3 */
1689 /* Description: Segment end T3 */
1690 
1691 /* Bits 7..0 : T (segment end) register */
1692 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
1693 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
1694 
1695 /* Register: FICR_TEMP_T4 */
1696 /* Description: Segment end T4 */
1697 
1698 /* Bits 7..0 : T (segment end) register */
1699 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
1700 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
1701 
1702 
1703 /* Peripheral: GPIOTE */
1704 /* Description: GPIO Tasks and Events */
1705 
1706 /* Register: GPIOTE_TASKS_OUT */
1707 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1708 
1709 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1710 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1711 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1712 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1713 
1714 /* Register: GPIOTE_TASKS_SET */
1715 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1716 
1717 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1718 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1719 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1720 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1721 
1722 /* Register: GPIOTE_TASKS_CLR */
1723 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1724 
1725 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1726 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1727 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1728 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1729 
1730 /* Register: GPIOTE_EVENTS_IN */
1731 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1732 
1733 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1734 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1735 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1736 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1737 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1738 
1739 /* Register: GPIOTE_EVENTS_PORT */
1740 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1741 
1742 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1743 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1744 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1745 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1746 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1747 
1748 /* Register: GPIOTE_INTENSET */
1749 /* Description: Enable interrupt */
1750 
1751 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1752 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1753 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
1754 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1755 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1756 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1757 
1758 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1759 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
1760 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
1761 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1762 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1763 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1764 
1765 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1766 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
1767 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
1768 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1769 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1770 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1771 
1772 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1773 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
1774 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
1775 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1776 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1777 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1778 
1779 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1780 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
1781 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
1782 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1783 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1784 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1785 
1786 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1787 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
1788 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
1789 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1790 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1791 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1792 
1793 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1794 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1795 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
1796 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1797 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1798 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1799 
1800 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1801 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
1802 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
1803 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1804 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1805 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1806 
1807 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1808 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
1809 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
1810 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1811 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1812 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1813 
1814 /* Register: GPIOTE_INTENCLR */
1815 /* Description: Disable interrupt */
1816 
1817 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1818 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
1819 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
1820 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1821 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1822 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1823 
1824 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1825 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
1826 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
1827 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1828 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1829 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1830 
1831 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1832 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
1833 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
1834 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1835 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1836 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1837 
1838 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1839 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
1840 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
1841 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1842 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1843 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1844 
1845 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1846 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
1847 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
1848 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1849 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1850 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1851 
1852 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1853 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
1854 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
1855 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1856 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1857 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1858 
1859 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1860 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
1861 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
1862 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1863 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1864 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1865 
1866 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1867 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
1868 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
1869 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1870 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1871 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1872 
1873 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1874 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
1875 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
1876 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1877 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1878 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1879 
1880 /* Register: GPIOTE_CONFIG */
1881 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
1882 
1883 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
1884 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
1885 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
1886 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
1887 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
1888 
1889 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
1890 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
1891 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
1892 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
1893 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
1894 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
1895 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
1896 
1897 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
1898 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
1899 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
1900 
1901 /* Bits 1..0 : Mode */
1902 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
1903 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
1904 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
1905 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
1906 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
1907 
1908 
1909 /* Peripheral: NVMC */
1910 /* Description: Non Volatile Memory Controller */
1911 
1912 /* Register: NVMC_READY */
1913 /* Description: Ready flag */
1914 
1915 /* Bit 0 : NVMC is ready or busy */
1916 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
1917 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
1918 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
1919 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
1920 
1921 /* Register: NVMC_READYNEXT */
1922 /* Description: Ready flag */
1923 
1924 /* Bit 0 : NVMC can accept a new write operation */
1925 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
1926 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
1927 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
1928 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
1929 
1930 /* Register: NVMC_CONFIG */
1931 /* Description: Configuration register */
1932 
1933 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */
1934 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
1935 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
1936 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
1937 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
1938 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
1939 
1940 /* Register: NVMC_ERASEPAGE */
1941 /* Description: Register for erasing a page in code area */
1942 
1943 /* Bits 31..0 : Register for starting erase of a page in code area */
1944 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
1945 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
1946 
1947 /* Register: NVMC_ERASEPCR1 */
1948 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
1949 
1950 /* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */
1951 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
1952 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
1953 
1954 /* Register: NVMC_ERASEALL */
1955 /* Description: Register for erasing all non-volatile user memory */
1956 
1957 /* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
1958 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
1959 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
1960 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
1961 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
1962 
1963 /* Register: NVMC_ERASEPCR0 */
1964 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
1965 
1966 /* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */
1967 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
1968 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
1969 
1970 /* Register: NVMC_ERASEUICR */
1971 /* Description: Register for erasing user information configuration registers */
1972 
1973 /* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */
1974 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
1975 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
1976 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
1977 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
1978 
1979 /* Register: NVMC_ERASEPAGEPARTIAL */
1980 /* Description: Register for partial erase of a page in code area */
1981 
1982 /* Bits 31..0 : Register for starting partial erase of a page in code area */
1983 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
1984 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
1985 
1986 /* Register: NVMC_ERASEPAGEPARTIALCFG */
1987 /* Description: Register for partial erase configuration */
1988 
1989 /* Bits 6..0 : Duration of the partial erase in milliseconds */
1990 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
1991 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
1992 
1993 
1994 /* Peripheral: GPIO */
1995 /* Description: GPIO Port 1 */
1996 
1997 /* Register: GPIO_OUT */
1998 /* Description: Write GPIO port */
1999 
2000 /* Bit 31 : Pin 31 */
2001 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2002 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2003 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
2004 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2005 
2006 /* Bit 30 : Pin 30 */
2007 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2008 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2009 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
2010 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2011 
2012 /* Bit 29 : Pin 29 */
2013 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2014 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2015 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
2016 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2017 
2018 /* Bit 28 : Pin 28 */
2019 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2020 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2021 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
2022 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2023 
2024 /* Bit 27 : Pin 27 */
2025 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2026 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2027 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
2028 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2029 
2030 /* Bit 26 : Pin 26 */
2031 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2032 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2033 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
2034 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2035 
2036 /* Bit 25 : Pin 25 */
2037 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2038 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2039 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
2040 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2041 
2042 /* Bit 24 : Pin 24 */
2043 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2044 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2045 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
2046 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2047 
2048 /* Bit 23 : Pin 23 */
2049 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2050 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2051 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
2052 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2053 
2054 /* Bit 22 : Pin 22 */
2055 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2056 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2057 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
2058 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2059 
2060 /* Bit 21 : Pin 21 */
2061 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2062 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2063 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
2064 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2065 
2066 /* Bit 20 : Pin 20 */
2067 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2068 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2069 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
2070 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2071 
2072 /* Bit 19 : Pin 19 */
2073 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2074 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2075 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
2076 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2077 
2078 /* Bit 18 : Pin 18 */
2079 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2080 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2081 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
2082 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2083 
2084 /* Bit 17 : Pin 17 */
2085 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2086 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2087 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
2088 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2089 
2090 /* Bit 16 : Pin 16 */
2091 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2092 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2093 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
2094 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2095 
2096 /* Bit 15 : Pin 15 */
2097 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2098 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2099 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
2100 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2101 
2102 /* Bit 14 : Pin 14 */
2103 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2104 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2105 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
2106 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2107 
2108 /* Bit 13 : Pin 13 */
2109 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2110 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2111 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
2112 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2113 
2114 /* Bit 12 : Pin 12 */
2115 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2116 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2117 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
2118 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2119 
2120 /* Bit 11 : Pin 11 */
2121 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2122 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2123 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
2124 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2125 
2126 /* Bit 10 : Pin 10 */
2127 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2128 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2129 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
2130 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2131 
2132 /* Bit 9 : Pin 9 */
2133 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2134 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2135 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
2136 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2137 
2138 /* Bit 8 : Pin 8 */
2139 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2140 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2141 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
2142 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2143 
2144 /* Bit 7 : Pin 7 */
2145 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2146 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2147 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
2148 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2149 
2150 /* Bit 6 : Pin 6 */
2151 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2152 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2153 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
2154 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2155 
2156 /* Bit 5 : Pin 5 */
2157 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2158 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2159 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
2160 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2161 
2162 /* Bit 4 : Pin 4 */
2163 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2164 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2165 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
2166 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2167 
2168 /* Bit 3 : Pin 3 */
2169 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2170 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2171 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
2172 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2173 
2174 /* Bit 2 : Pin 2 */
2175 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2176 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2177 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
2178 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2179 
2180 /* Bit 1 : Pin 1 */
2181 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2182 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2183 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
2184 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2185 
2186 /* Bit 0 : Pin 0 */
2187 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2188 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2189 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
2190 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2191 
2192 /* Register: GPIO_OUTSET */
2193 /* Description: Set individual bits in GPIO port */
2194 
2195 /* Bit 31 : Pin 31 */
2196 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2197 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2198 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2199 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2200 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2201 
2202 /* Bit 30 : Pin 30 */
2203 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2204 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2205 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2206 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2207 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2208 
2209 /* Bit 29 : Pin 29 */
2210 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2211 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2212 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2213 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2214 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2215 
2216 /* Bit 28 : Pin 28 */
2217 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2218 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2219 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2220 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2221 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2222 
2223 /* Bit 27 : Pin 27 */
2224 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2225 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2226 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2227 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2228 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2229 
2230 /* Bit 26 : Pin 26 */
2231 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2232 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2233 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2234 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2235 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2236 
2237 /* Bit 25 : Pin 25 */
2238 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2239 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2240 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2241 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2242 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2243 
2244 /* Bit 24 : Pin 24 */
2245 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2246 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2247 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
2248 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2249 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2250 
2251 /* Bit 23 : Pin 23 */
2252 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2253 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2254 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
2255 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2256 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2257 
2258 /* Bit 22 : Pin 22 */
2259 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2260 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2261 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
2262 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2263 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2264 
2265 /* Bit 21 : Pin 21 */
2266 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2267 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2268 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
2269 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2270 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2271 
2272 /* Bit 20 : Pin 20 */
2273 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2274 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2275 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
2276 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2277 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2278 
2279 /* Bit 19 : Pin 19 */
2280 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2281 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2282 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
2283 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2284 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2285 
2286 /* Bit 18 : Pin 18 */
2287 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2288 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2289 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
2290 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2291 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2292 
2293 /* Bit 17 : Pin 17 */
2294 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2295 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2296 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
2297 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2298 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2299 
2300 /* Bit 16 : Pin 16 */
2301 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2302 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2303 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
2304 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2305 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2306 
2307 /* Bit 15 : Pin 15 */
2308 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2309 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2310 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
2311 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2312 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2313 
2314 /* Bit 14 : Pin 14 */
2315 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2316 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2317 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
2318 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
2319 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2320 
2321 /* Bit 13 : Pin 13 */
2322 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2323 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2324 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
2325 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
2326 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2327 
2328 /* Bit 12 : Pin 12 */
2329 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2330 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2331 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
2332 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
2333 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2334 
2335 /* Bit 11 : Pin 11 */
2336 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2337 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2338 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
2339 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
2340 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2341 
2342 /* Bit 10 : Pin 10 */
2343 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2344 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2345 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
2346 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
2347 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2348 
2349 /* Bit 9 : Pin 9 */
2350 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2351 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2352 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
2353 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
2354 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2355 
2356 /* Bit 8 : Pin 8 */
2357 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2358 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2359 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
2360 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
2361 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2362 
2363 /* Bit 7 : Pin 7 */
2364 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2365 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2366 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
2367 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
2368 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2369 
2370 /* Bit 6 : Pin 6 */
2371 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2372 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2373 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
2374 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
2375 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2376 
2377 /* Bit 5 : Pin 5 */
2378 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2379 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2380 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
2381 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
2382 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2383 
2384 /* Bit 4 : Pin 4 */
2385 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2386 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2387 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
2388 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
2389 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2390 
2391 /* Bit 3 : Pin 3 */
2392 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2393 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2394 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
2395 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
2396 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2397 
2398 /* Bit 2 : Pin 2 */
2399 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2400 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2401 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
2402 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
2403 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2404 
2405 /* Bit 1 : Pin 1 */
2406 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2407 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2408 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
2409 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
2410 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2411 
2412 /* Bit 0 : Pin 0 */
2413 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2414 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2415 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
2416 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
2417 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
2418 
2419 /* Register: GPIO_OUTCLR */
2420 /* Description: Clear individual bits in GPIO port */
2421 
2422 /* Bit 31 : Pin 31 */
2423 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2424 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2425 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
2426 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
2427 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2428 
2429 /* Bit 30 : Pin 30 */
2430 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2431 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2432 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
2433 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
2434 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2435 
2436 /* Bit 29 : Pin 29 */
2437 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2438 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2439 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
2440 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
2441 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2442 
2443 /* Bit 28 : Pin 28 */
2444 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2445 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2446 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
2447 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
2448 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2449 
2450 /* Bit 27 : Pin 27 */
2451 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2452 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2453 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
2454 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
2455 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2456 
2457 /* Bit 26 : Pin 26 */
2458 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2459 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2460 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
2461 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
2462 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2463 
2464 /* Bit 25 : Pin 25 */
2465 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2466 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2467 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
2468 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
2469 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2470 
2471 /* Bit 24 : Pin 24 */
2472 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2473 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2474 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
2475 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
2476 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2477 
2478 /* Bit 23 : Pin 23 */
2479 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2480 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2481 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
2482 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
2483 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2484 
2485 /* Bit 22 : Pin 22 */
2486 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2487 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2488 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
2489 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
2490 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2491 
2492 /* Bit 21 : Pin 21 */
2493 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2494 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2495 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
2496 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
2497 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2498 
2499 /* Bit 20 : Pin 20 */
2500 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2501 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2502 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
2503 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
2504 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2505 
2506 /* Bit 19 : Pin 19 */
2507 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2508 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2509 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
2510 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
2511 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2512 
2513 /* Bit 18 : Pin 18 */
2514 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2515 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2516 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
2517 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
2518 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2519 
2520 /* Bit 17 : Pin 17 */
2521 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2522 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2523 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
2524 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
2525 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2526 
2527 /* Bit 16 : Pin 16 */
2528 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2529 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2530 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
2531 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
2532 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2533 
2534 /* Bit 15 : Pin 15 */
2535 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2536 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2537 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
2538 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
2539 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2540 
2541 /* Bit 14 : Pin 14 */
2542 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2543 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2544 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
2545 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
2546 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2547 
2548 /* Bit 13 : Pin 13 */
2549 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2550 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2551 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
2552 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
2553 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2554 
2555 /* Bit 12 : Pin 12 */
2556 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2557 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2558 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
2559 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
2560 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2561 
2562 /* Bit 11 : Pin 11 */
2563 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2564 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2565 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
2566 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
2567 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2568 
2569 /* Bit 10 : Pin 10 */
2570 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2571 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2572 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
2573 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
2574 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2575 
2576 /* Bit 9 : Pin 9 */
2577 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2578 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2579 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
2580 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
2581 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2582 
2583 /* Bit 8 : Pin 8 */
2584 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2585 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2586 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
2587 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
2588 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2589 
2590 /* Bit 7 : Pin 7 */
2591 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2592 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2593 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
2594 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
2595 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2596 
2597 /* Bit 6 : Pin 6 */
2598 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2599 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2600 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
2601 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
2602 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2603 
2604 /* Bit 5 : Pin 5 */
2605 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2606 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2607 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
2608 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
2609 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2610 
2611 /* Bit 4 : Pin 4 */
2612 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2613 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2614 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
2615 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
2616 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2617 
2618 /* Bit 3 : Pin 3 */
2619 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2620 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2621 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
2622 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
2623 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2624 
2625 /* Bit 2 : Pin 2 */
2626 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2627 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2628 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
2629 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
2630 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2631 
2632 /* Bit 1 : Pin 1 */
2633 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2634 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2635 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
2636 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
2637 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2638 
2639 /* Bit 0 : Pin 0 */
2640 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2641 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2642 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
2643 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
2644 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
2645 
2646 /* Register: GPIO_IN */
2647 /* Description: Read GPIO port */
2648 
2649 /* Bit 31 : Pin 31 */
2650 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2651 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2652 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
2653 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
2654 
2655 /* Bit 30 : Pin 30 */
2656 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2657 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2658 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
2659 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
2660 
2661 /* Bit 29 : Pin 29 */
2662 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2663 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2664 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
2665 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
2666 
2667 /* Bit 28 : Pin 28 */
2668 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2669 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2670 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
2671 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
2672 
2673 /* Bit 27 : Pin 27 */
2674 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2675 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2676 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
2677 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
2678 
2679 /* Bit 26 : Pin 26 */
2680 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2681 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2682 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
2683 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
2684 
2685 /* Bit 25 : Pin 25 */
2686 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2687 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2688 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
2689 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
2690 
2691 /* Bit 24 : Pin 24 */
2692 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2693 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2694 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
2695 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
2696 
2697 /* Bit 23 : Pin 23 */
2698 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2699 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2700 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
2701 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
2702 
2703 /* Bit 22 : Pin 22 */
2704 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2705 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2706 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
2707 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
2708 
2709 /* Bit 21 : Pin 21 */
2710 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2711 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2712 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
2713 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
2714 
2715 /* Bit 20 : Pin 20 */
2716 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2717 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2718 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
2719 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
2720 
2721 /* Bit 19 : Pin 19 */
2722 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2723 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2724 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
2725 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
2726 
2727 /* Bit 18 : Pin 18 */
2728 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2729 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2730 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
2731 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
2732 
2733 /* Bit 17 : Pin 17 */
2734 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2735 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2736 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
2737 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
2738 
2739 /* Bit 16 : Pin 16 */
2740 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2741 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2742 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
2743 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
2744 
2745 /* Bit 15 : Pin 15 */
2746 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2747 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2748 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
2749 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
2750 
2751 /* Bit 14 : Pin 14 */
2752 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2753 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2754 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
2755 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
2756 
2757 /* Bit 13 : Pin 13 */
2758 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2759 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2760 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
2761 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
2762 
2763 /* Bit 12 : Pin 12 */
2764 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2765 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2766 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
2767 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
2768 
2769 /* Bit 11 : Pin 11 */
2770 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2771 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2772 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
2773 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
2774 
2775 /* Bit 10 : Pin 10 */
2776 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2777 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2778 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
2779 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
2780 
2781 /* Bit 9 : Pin 9 */
2782 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2783 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2784 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
2785 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
2786 
2787 /* Bit 8 : Pin 8 */
2788 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2789 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2790 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
2791 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
2792 
2793 /* Bit 7 : Pin 7 */
2794 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2795 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2796 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
2797 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
2798 
2799 /* Bit 6 : Pin 6 */
2800 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2801 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2802 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
2803 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
2804 
2805 /* Bit 5 : Pin 5 */
2806 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2807 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2808 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
2809 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
2810 
2811 /* Bit 4 : Pin 4 */
2812 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2813 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2814 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
2815 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
2816 
2817 /* Bit 3 : Pin 3 */
2818 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2819 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2820 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
2821 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
2822 
2823 /* Bit 2 : Pin 2 */
2824 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2825 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2826 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
2827 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
2828 
2829 /* Bit 1 : Pin 1 */
2830 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2831 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2832 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
2833 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
2834 
2835 /* Bit 0 : Pin 0 */
2836 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2837 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2838 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
2839 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
2840 
2841 /* Register: GPIO_DIR */
2842 /* Description: Direction of GPIO pins */
2843 
2844 /* Bit 31 : Pin 31 */
2845 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2846 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2847 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
2848 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
2849 
2850 /* Bit 30 : Pin 30 */
2851 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2852 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2853 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
2854 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
2855 
2856 /* Bit 29 : Pin 29 */
2857 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2858 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2859 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
2860 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
2861 
2862 /* Bit 28 : Pin 28 */
2863 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2864 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2865 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
2866 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
2867 
2868 /* Bit 27 : Pin 27 */
2869 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2870 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2871 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
2872 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
2873 
2874 /* Bit 26 : Pin 26 */
2875 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2876 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2877 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
2878 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
2879 
2880 /* Bit 25 : Pin 25 */
2881 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2882 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2883 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
2884 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
2885 
2886 /* Bit 24 : Pin 24 */
2887 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2888 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2889 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
2890 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
2891 
2892 /* Bit 23 : Pin 23 */
2893 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2894 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2895 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
2896 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
2897 
2898 /* Bit 22 : Pin 22 */
2899 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2900 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2901 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
2902 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
2903 
2904 /* Bit 21 : Pin 21 */
2905 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2906 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2907 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
2908 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
2909 
2910 /* Bit 20 : Pin 20 */
2911 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2912 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2913 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
2914 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
2915 
2916 /* Bit 19 : Pin 19 */
2917 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2918 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2919 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
2920 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
2921 
2922 /* Bit 18 : Pin 18 */
2923 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2924 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2925 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
2926 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
2927 
2928 /* Bit 17 : Pin 17 */
2929 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2930 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2931 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
2932 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
2933 
2934 /* Bit 16 : Pin 16 */
2935 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2936 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2937 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
2938 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
2939 
2940 /* Bit 15 : Pin 15 */
2941 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2942 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2943 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
2944 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
2945 
2946 /* Bit 14 : Pin 14 */
2947 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2948 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2949 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
2950 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
2951 
2952 /* Bit 13 : Pin 13 */
2953 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2954 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2955 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
2956 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
2957 
2958 /* Bit 12 : Pin 12 */
2959 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2960 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2961 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
2962 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
2963 
2964 /* Bit 11 : Pin 11 */
2965 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2966 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2967 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
2968 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
2969 
2970 /* Bit 10 : Pin 10 */
2971 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2972 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2973 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
2974 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
2975 
2976 /* Bit 9 : Pin 9 */
2977 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2978 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2979 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
2980 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
2981 
2982 /* Bit 8 : Pin 8 */
2983 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2984 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2985 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
2986 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
2987 
2988 /* Bit 7 : Pin 7 */
2989 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2990 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2991 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
2992 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
2993 
2994 /* Bit 6 : Pin 6 */
2995 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2996 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2997 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
2998 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
2999 
3000 /* Bit 5 : Pin 5 */
3001 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3002 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3003 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
3004 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
3005 
3006 /* Bit 4 : Pin 4 */
3007 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3008 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3009 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
3010 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
3011 
3012 /* Bit 3 : Pin 3 */
3013 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3014 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3015 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
3016 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
3017 
3018 /* Bit 2 : Pin 2 */
3019 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3020 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3021 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
3022 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
3023 
3024 /* Bit 1 : Pin 1 */
3025 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3026 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3027 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
3028 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
3029 
3030 /* Bit 0 : Pin 0 */
3031 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3032 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3033 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
3034 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
3035 
3036 /* Register: GPIO_DIRSET */
3037 /* Description: DIR set register */
3038 
3039 /* Bit 31 : Set as output pin 31 */
3040 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3041 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3042 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3043 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3044 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3045 
3046 /* Bit 30 : Set as output pin 30 */
3047 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3048 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3049 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3050 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3051 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3052 
3053 /* Bit 29 : Set as output pin 29 */
3054 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3055 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3056 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3057 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3058 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3059 
3060 /* Bit 28 : Set as output pin 28 */
3061 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3062 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3063 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3064 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3065 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3066 
3067 /* Bit 27 : Set as output pin 27 */
3068 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3069 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3070 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3071 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3072 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3073 
3074 /* Bit 26 : Set as output pin 26 */
3075 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3076 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3077 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3078 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3079 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3080 
3081 /* Bit 25 : Set as output pin 25 */
3082 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3083 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3084 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3085 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3086 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3087 
3088 /* Bit 24 : Set as output pin 24 */
3089 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3090 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3091 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3092 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3093 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3094 
3095 /* Bit 23 : Set as output pin 23 */
3096 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3097 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3098 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3099 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3100 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3101 
3102 /* Bit 22 : Set as output pin 22 */
3103 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3104 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3105 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3106 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3107 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3108 
3109 /* Bit 21 : Set as output pin 21 */
3110 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3111 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3112 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3113 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3114 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3115 
3116 /* Bit 20 : Set as output pin 20 */
3117 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3118 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3119 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3120 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3121 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3122 
3123 /* Bit 19 : Set as output pin 19 */
3124 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3125 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3126 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3127 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3128 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3129 
3130 /* Bit 18 : Set as output pin 18 */
3131 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3132 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3133 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3134 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3135 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3136 
3137 /* Bit 17 : Set as output pin 17 */
3138 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3139 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3140 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3141 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3142 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3143 
3144 /* Bit 16 : Set as output pin 16 */
3145 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3146 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3147 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3148 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3149 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3150 
3151 /* Bit 15 : Set as output pin 15 */
3152 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3153 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3154 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3155 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3156 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3157 
3158 /* Bit 14 : Set as output pin 14 */
3159 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3160 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3161 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3162 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3163 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3164 
3165 /* Bit 13 : Set as output pin 13 */
3166 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3167 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3168 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3169 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3170 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3171 
3172 /* Bit 12 : Set as output pin 12 */
3173 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3174 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3175 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3176 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3177 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3178 
3179 /* Bit 11 : Set as output pin 11 */
3180 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3181 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3182 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3183 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3184 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3185 
3186 /* Bit 10 : Set as output pin 10 */
3187 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3188 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3189 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3190 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3191 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3192 
3193 /* Bit 9 : Set as output pin 9 */
3194 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3195 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3196 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3197 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3198 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3199 
3200 /* Bit 8 : Set as output pin 8 */
3201 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3202 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3203 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3204 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3205 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3206 
3207 /* Bit 7 : Set as output pin 7 */
3208 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3209 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3210 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3211 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3212 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3213 
3214 /* Bit 6 : Set as output pin 6 */
3215 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3216 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3217 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3218 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3219 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3220 
3221 /* Bit 5 : Set as output pin 5 */
3222 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3223 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3224 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3225 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3226 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3227 
3228 /* Bit 4 : Set as output pin 4 */
3229 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3230 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3231 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3232 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3233 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3234 
3235 /* Bit 3 : Set as output pin 3 */
3236 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3237 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3238 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3239 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3240 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3241 
3242 /* Bit 2 : Set as output pin 2 */
3243 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3244 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3245 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
3246 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3247 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3248 
3249 /* Bit 1 : Set as output pin 1 */
3250 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3251 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3252 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
3253 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3254 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3255 
3256 /* Bit 0 : Set as output pin 0 */
3257 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3258 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3259 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
3260 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3261 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
3262 
3263 /* Register: GPIO_DIRCLR */
3264 /* Description: DIR clear register */
3265 
3266 /* Bit 31 : Set as input pin 31 */
3267 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3268 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3269 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
3270 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3271 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3272 
3273 /* Bit 30 : Set as input pin 30 */
3274 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3275 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3276 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
3277 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3278 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3279 
3280 /* Bit 29 : Set as input pin 29 */
3281 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3282 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3283 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
3284 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3285 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3286 
3287 /* Bit 28 : Set as input pin 28 */
3288 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3289 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3290 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
3291 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3292 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3293 
3294 /* Bit 27 : Set as input pin 27 */
3295 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3296 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3297 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
3298 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3299 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3300 
3301 /* Bit 26 : Set as input pin 26 */
3302 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3303 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3304 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
3305 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3306 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3307 
3308 /* Bit 25 : Set as input pin 25 */
3309 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3310 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3311 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
3312 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
3313 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3314 
3315 /* Bit 24 : Set as input pin 24 */
3316 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3317 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3318 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
3319 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
3320 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3321 
3322 /* Bit 23 : Set as input pin 23 */
3323 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3324 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3325 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
3326 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
3327 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3328 
3329 /* Bit 22 : Set as input pin 22 */
3330 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3331 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3332 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
3333 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
3334 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3335 
3336 /* Bit 21 : Set as input pin 21 */
3337 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3338 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3339 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
3340 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
3341 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3342 
3343 /* Bit 20 : Set as input pin 20 */
3344 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3345 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3346 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
3347 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
3348 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3349 
3350 /* Bit 19 : Set as input pin 19 */
3351 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3352 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3353 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
3354 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
3355 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3356 
3357 /* Bit 18 : Set as input pin 18 */
3358 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3359 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3360 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
3361 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
3362 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3363 
3364 /* Bit 17 : Set as input pin 17 */
3365 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3366 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3367 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
3368 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
3369 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3370 
3371 /* Bit 16 : Set as input pin 16 */
3372 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3373 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3374 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
3375 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
3376 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3377 
3378 /* Bit 15 : Set as input pin 15 */
3379 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3380 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3381 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
3382 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
3383 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3384 
3385 /* Bit 14 : Set as input pin 14 */
3386 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3387 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3388 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
3389 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
3390 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3391 
3392 /* Bit 13 : Set as input pin 13 */
3393 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3394 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3395 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
3396 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
3397 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3398 
3399 /* Bit 12 : Set as input pin 12 */
3400 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3401 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3402 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
3403 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
3404 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3405 
3406 /* Bit 11 : Set as input pin 11 */
3407 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3408 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3409 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
3410 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
3411 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3412 
3413 /* Bit 10 : Set as input pin 10 */
3414 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3415 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3416 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
3417 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
3418 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3419 
3420 /* Bit 9 : Set as input pin 9 */
3421 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3422 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3423 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
3424 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
3425 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3426 
3427 /* Bit 8 : Set as input pin 8 */
3428 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3429 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3430 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
3431 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
3432 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3433 
3434 /* Bit 7 : Set as input pin 7 */
3435 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3436 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3437 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
3438 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
3439 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3440 
3441 /* Bit 6 : Set as input pin 6 */
3442 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3443 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3444 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
3445 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
3446 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3447 
3448 /* Bit 5 : Set as input pin 5 */
3449 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3450 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3451 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
3452 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
3453 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3454 
3455 /* Bit 4 : Set as input pin 4 */
3456 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3457 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3458 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
3459 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
3460 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3461 
3462 /* Bit 3 : Set as input pin 3 */
3463 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3464 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3465 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
3466 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
3467 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3468 
3469 /* Bit 2 : Set as input pin 2 */
3470 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3471 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3472 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
3473 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
3474 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3475 
3476 /* Bit 1 : Set as input pin 1 */
3477 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3478 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3479 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
3480 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
3481 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3482 
3483 /* Bit 0 : Set as input pin 0 */
3484 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3485 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3486 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
3487 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
3488 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
3489 
3490 /* Register: GPIO_LATCH */
3491 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
3492 
3493 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
3494 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3495 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3496 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
3497 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
3498 
3499 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
3500 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3501 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3502 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
3503 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
3504 
3505 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
3506 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3507 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3508 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
3509 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
3510 
3511 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
3512 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3513 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3514 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
3515 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
3516 
3517 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
3518 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3519 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3520 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
3521 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
3522 
3523 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
3524 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3525 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3526 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
3527 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
3528 
3529 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
3530 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3531 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3532 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
3533 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
3534 
3535 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
3536 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3537 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3538 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
3539 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
3540 
3541 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
3542 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3543 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3544 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
3545 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
3546 
3547 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
3548 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3549 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3550 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
3551 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
3552 
3553 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
3554 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3555 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3556 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
3557 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
3558 
3559 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
3560 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3561 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3562 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
3563 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
3564 
3565 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
3566 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3567 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3568 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
3569 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
3570 
3571 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
3572 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3573 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3574 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
3575 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
3576 
3577 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
3578 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3579 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3580 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
3581 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
3582 
3583 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
3584 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3585 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3586 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
3587 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
3588 
3589 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
3590 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3591 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3592 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
3593 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
3594 
3595 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
3596 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3597 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3598 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
3599 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
3600 
3601 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
3602 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3603 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3604 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
3605 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
3606 
3607 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
3608 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3609 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3610 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
3611 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
3612 
3613 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
3614 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3615 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3616 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
3617 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
3618 
3619 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
3620 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3621 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3622 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
3623 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
3624 
3625 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
3626 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3627 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3628 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
3629 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
3630 
3631 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
3632 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3633 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3634 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
3635 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
3636 
3637 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
3638 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3639 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3640 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
3641 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
3642 
3643 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
3644 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3645 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3646 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
3647 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
3648 
3649 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
3650 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3651 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3652 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
3653 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
3654 
3655 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
3656 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3657 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3658 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
3659 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
3660 
3661 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
3662 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3663 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3664 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
3665 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
3666 
3667 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
3668 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3669 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3670 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
3671 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
3672 
3673 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
3674 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3675 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3676 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
3677 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
3678 
3679 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
3680 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3681 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3682 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
3683 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
3684 
3685 /* Register: GPIO_DETECTMODE */
3686 /* Description: Select between default DETECT signal behavior and LDETECT mode */
3687 
3688 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
3689 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
3690 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
3691 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
3692 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
3693 
3694 /* Register: GPIO_PIN_CNF */
3695 /* Description: Description collection: Configuration of GPIO pins */
3696 
3697 /* Bits 17..16 : Pin sensing mechanism */
3698 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
3699 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
3700 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
3701 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
3702 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
3703 
3704 /* Bits 10..8 : Drive configuration */
3705 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
3706 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
3707 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
3708 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
3709 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
3710 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
3711 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
3712 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
3713 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
3714 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
3715 
3716 /* Bits 3..2 : Pull configuration */
3717 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
3718 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
3719 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
3720 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
3721 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
3722 
3723 /* Bit 1 : Connect or disconnect input buffer */
3724 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
3725 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
3726 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
3727 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
3728 
3729 /* Bit 0 : Pin direction. Same physical register as DIR register */
3730 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
3731 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
3732 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
3733 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
3734 
3735 
3736 /* Peripheral: POWER */
3737 /* Description: Power control */
3738 
3739 /* Register: POWER_TASKS_CONSTLAT */
3740 /* Description: Enable Constant Latency mode */
3741 
3742 /* Bit 0 : Enable Constant Latency mode */
3743 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
3744 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
3745 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
3746 
3747 /* Register: POWER_TASKS_LOWPWR */
3748 /* Description: Enable Low-power mode (variable latency) */
3749 
3750 /* Bit 0 : Enable Low-power mode (variable latency) */
3751 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
3752 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
3753 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
3754 
3755 /* Register: POWER_EVENTS_POFWARN */
3756 /* Description: Power failure warning */
3757 
3758 /* Bit 0 : Power failure warning */
3759 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
3760 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
3761 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
3762 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
3763 
3764 /* Register: POWER_EVENTS_SLEEPENTER */
3765 /* Description: CPU entered WFI/WFE sleep */
3766 
3767 /* Bit 0 : CPU entered WFI/WFE sleep */
3768 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
3769 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
3770 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
3771 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
3772 
3773 /* Register: POWER_EVENTS_SLEEPEXIT */
3774 /* Description: CPU exited WFI/WFE sleep */
3775 
3776 /* Bit 0 : CPU exited WFI/WFE sleep */
3777 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
3778 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
3779 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
3780 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
3781 
3782 /* Register: POWER_EVENTS_USBDETECTED */
3783 /* Description: Voltage supply detected on VBUS */
3784 
3785 /* Bit 0 : Voltage supply detected on VBUS */
3786 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
3787 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
3788 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */
3789 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */
3790 
3791 /* Register: POWER_EVENTS_USBREMOVED */
3792 /* Description: Voltage supply removed from VBUS */
3793 
3794 /* Bit 0 : Voltage supply removed from VBUS */
3795 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
3796 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
3797 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */
3798 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */
3799 
3800 /* Register: POWER_EVENTS_USBPWRRDY */
3801 /* Description: USB 3.3 V supply ready */
3802 
3803 /* Bit 0 : USB 3.3 V supply ready */
3804 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
3805 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
3806 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */
3807 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */
3808 
3809 /* Register: POWER_INTENSET */
3810 /* Description: Enable interrupt */
3811 
3812 /* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */
3813 #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
3814 #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
3815 #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
3816 #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
3817 #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
3818 
3819 /* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */
3820 #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
3821 #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
3822 #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
3823 #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
3824 #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
3825 
3826 /* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */
3827 #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
3828 #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
3829 #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
3830 #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
3831 #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
3832 
3833 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
3834 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
3835 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
3836 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
3837 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
3838 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
3839 
3840 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
3841 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
3842 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
3843 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
3844 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
3845 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
3846 
3847 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
3848 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
3849 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
3850 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
3851 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
3852 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
3853 
3854 /* Register: POWER_INTENCLR */
3855 /* Description: Disable interrupt */
3856 
3857 /* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */
3858 #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
3859 #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
3860 #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
3861 #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
3862 #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
3863 
3864 /* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */
3865 #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
3866 #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
3867 #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
3868 #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
3869 #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
3870 
3871 /* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */
3872 #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
3873 #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
3874 #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
3875 #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
3876 #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
3877 
3878 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
3879 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
3880 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
3881 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
3882 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
3883 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
3884 
3885 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
3886 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
3887 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
3888 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
3889 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
3890 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
3891 
3892 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
3893 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
3894 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
3895 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
3896 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
3897 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
3898 
3899 /* Register: POWER_RESETREAS */
3900 /* Description: Reset reason */
3901 
3902 /* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
3903 #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
3904 #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
3905 #define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
3906 #define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
3907 
3908 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
3909 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
3910 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
3911 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
3912 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
3913 
3914 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
3915 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
3916 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
3917 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
3918 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
3919 
3920 /* Bit 3 : Reset from CPU lock-up detected */
3921 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
3922 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
3923 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
3924 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
3925 
3926 /* Bit 2 : Reset from soft reset detected */
3927 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
3928 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
3929 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
3930 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
3931 
3932 /* Bit 1 : Reset from watchdog detected */
3933 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
3934 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
3935 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
3936 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
3937 
3938 /* Bit 0 : Reset from pin-reset detected */
3939 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
3940 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
3941 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
3942 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
3943 
3944 /* Register: POWER_RAMSTATUS */
3945 /* Description: Deprecated register - RAM status register */
3946 
3947 /* Bit 1 : RAM block 1 is on or off/powering up */
3948 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
3949 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
3950 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
3951 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
3952 
3953 /* Bit 0 : RAM block 0 is on or off/powering up */
3954 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
3955 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
3956 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
3957 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
3958 
3959 /* Register: POWER_USBREGSTATUS */
3960 /* Description: USB supply status */
3961 
3962 /* Bit 1 : USB supply output settling time elapsed */
3963 #define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
3964 #define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
3965 #define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
3966 #define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
3967 
3968 /* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
3969 #define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
3970 #define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
3971 #define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
3972 #define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
3973 
3974 /* Register: POWER_SYSTEMOFF */
3975 /* Description: System OFF register */
3976 
3977 /* Bit 0 : Enable System OFF mode */
3978 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
3979 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
3980 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
3981 
3982 /* Register: POWER_POFCON */
3983 /* Description: Power-fail comparator configuration */
3984 
3985 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */
3986 #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
3987 #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
3988 #define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
3989 #define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
3990 #define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
3991 #define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
3992 #define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
3993 #define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
3994 #define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
3995 #define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
3996 #define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
3997 #define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
3998 #define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
3999 #define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
4000 #define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
4001 #define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
4002 #define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
4003 #define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
4004 
4005 /* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */
4006 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
4007 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
4008 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
4009 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
4010 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
4011 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
4012 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
4013 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
4014 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
4015 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
4016 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
4017 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
4018 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
4019 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
4020 
4021 /* Bit 0 : Enable or disable power failure warning */
4022 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
4023 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
4024 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
4025 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
4026 
4027 /* Register: POWER_GPREGRET */
4028 /* Description: General purpose retention register */
4029 
4030 /* Bits 7..0 : General purpose retention register */
4031 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
4032 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
4033 
4034 /* Register: POWER_GPREGRET2 */
4035 /* Description: General purpose retention register */
4036 
4037 /* Bits 7..0 : General purpose retention register */
4038 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
4039 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
4040 
4041 /* Register: POWER_DCDCEN */
4042 /* Description: Enable DC/DC converter for REG1 stage */
4043 
4044 /* Bit 0 : Enable DC/DC converter for REG1 stage. */
4045 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
4046 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
4047 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
4048 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
4049 
4050 /* Register: POWER_MAINREGSTATUS */
4051 /* Description: Main supply status */
4052 
4053 /* Bit 0 : Main supply status */
4054 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
4055 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
4056 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
4057 #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
4058 
4059 /* Register: POWER_RAM_POWER */
4060 /* Description: Description cluster: RAMn power control register */
4061 
4062 /* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
4063 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4064 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4065 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
4066 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
4067 
4068 /* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
4069 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4070 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4071 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
4072 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
4073 
4074 /* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
4075 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4076 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4077 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
4078 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
4079 
4080 /* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
4081 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4082 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4083 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
4084 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
4085 
4086 /* Register: POWER_RAM_POWERSET */
4087 /* Description: Description cluster: RAMn power control set register */
4088 
4089 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
4090 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4091 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4092 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
4093 
4094 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
4095 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4096 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4097 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
4098 
4099 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
4100 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4101 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4102 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
4103 
4104 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
4105 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4106 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4107 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
4108 
4109 /* Register: POWER_RAM_POWERCLR */
4110 /* Description: Description cluster: RAMn power control clear register */
4111 
4112 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
4113 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4114 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4115 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
4116 
4117 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
4118 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4119 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4120 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
4121 
4122 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
4123 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4124 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4125 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
4126 
4127 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
4128 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4129 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4130 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
4131 
4132 
4133 /* Peripheral: PPI */
4134 /* Description: Programmable Peripheral Interconnect */
4135 
4136 /* Register: PPI_TASKS_CHG_EN */
4137 /* Description: Description cluster: Enable channel group n */
4138 
4139 /* Bit 0 : Enable channel group n */
4140 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
4141 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
4142 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
4143 
4144 /* Register: PPI_TASKS_CHG_DIS */
4145 /* Description: Description cluster: Disable channel group n */
4146 
4147 /* Bit 0 : Disable channel group n */
4148 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
4149 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
4150 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
4151 
4152 /* Register: PPI_CHEN */
4153 /* Description: Channel enable register */
4154 
4155 /* Bit 31 : Enable or disable channel 31 */
4156 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
4157 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
4158 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
4159 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
4160 
4161 /* Bit 30 : Enable or disable channel 30 */
4162 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
4163 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
4164 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
4165 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
4166 
4167 /* Bit 29 : Enable or disable channel 29 */
4168 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
4169 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
4170 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
4171 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
4172 
4173 /* Bit 28 : Enable or disable channel 28 */
4174 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
4175 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
4176 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
4177 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
4178 
4179 /* Bit 27 : Enable or disable channel 27 */
4180 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
4181 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
4182 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
4183 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
4184 
4185 /* Bit 26 : Enable or disable channel 26 */
4186 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
4187 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
4188 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
4189 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
4190 
4191 /* Bit 25 : Enable or disable channel 25 */
4192 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
4193 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
4194 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
4195 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
4196 
4197 /* Bit 24 : Enable or disable channel 24 */
4198 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
4199 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
4200 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
4201 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
4202 
4203 /* Bit 23 : Enable or disable channel 23 */
4204 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
4205 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
4206 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
4207 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
4208 
4209 /* Bit 22 : Enable or disable channel 22 */
4210 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
4211 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
4212 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
4213 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
4214 
4215 /* Bit 21 : Enable or disable channel 21 */
4216 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
4217 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
4218 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
4219 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
4220 
4221 /* Bit 20 : Enable or disable channel 20 */
4222 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
4223 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
4224 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
4225 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
4226 
4227 /* Bit 19 : Enable or disable channel 19 */
4228 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
4229 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
4230 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
4231 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
4232 
4233 /* Bit 18 : Enable or disable channel 18 */
4234 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
4235 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
4236 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
4237 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
4238 
4239 /* Bit 17 : Enable or disable channel 17 */
4240 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
4241 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
4242 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
4243 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
4244 
4245 /* Bit 16 : Enable or disable channel 16 */
4246 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
4247 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
4248 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
4249 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
4250 
4251 /* Bit 15 : Enable or disable channel 15 */
4252 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
4253 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
4254 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
4255 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
4256 
4257 /* Bit 14 : Enable or disable channel 14 */
4258 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
4259 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
4260 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
4261 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
4262 
4263 /* Bit 13 : Enable or disable channel 13 */
4264 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
4265 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
4266 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
4267 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
4268 
4269 /* Bit 12 : Enable or disable channel 12 */
4270 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
4271 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
4272 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
4273 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
4274 
4275 /* Bit 11 : Enable or disable channel 11 */
4276 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
4277 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
4278 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
4279 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
4280 
4281 /* Bit 10 : Enable or disable channel 10 */
4282 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
4283 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
4284 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
4285 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
4286 
4287 /* Bit 9 : Enable or disable channel 9 */
4288 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
4289 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
4290 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
4291 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
4292 
4293 /* Bit 8 : Enable or disable channel 8 */
4294 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
4295 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
4296 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
4297 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
4298 
4299 /* Bit 7 : Enable or disable channel 7 */
4300 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
4301 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
4302 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
4303 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
4304 
4305 /* Bit 6 : Enable or disable channel 6 */
4306 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
4307 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
4308 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
4309 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
4310 
4311 /* Bit 5 : Enable or disable channel 5 */
4312 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
4313 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
4314 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
4315 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
4316 
4317 /* Bit 4 : Enable or disable channel 4 */
4318 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
4319 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
4320 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
4321 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
4322 
4323 /* Bit 3 : Enable or disable channel 3 */
4324 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
4325 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
4326 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
4327 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
4328 
4329 /* Bit 2 : Enable or disable channel 2 */
4330 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
4331 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
4332 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
4333 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
4334 
4335 /* Bit 1 : Enable or disable channel 1 */
4336 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
4337 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
4338 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
4339 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
4340 
4341 /* Bit 0 : Enable or disable channel 0 */
4342 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
4343 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
4344 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
4345 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
4346 
4347 /* Register: PPI_CHENSET */
4348 /* Description: Channel enable set register */
4349 
4350 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect. */
4351 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
4352 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
4353 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
4354 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
4355 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
4356 
4357 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect. */
4358 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
4359 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
4360 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
4361 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
4362 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
4363 
4364 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect. */
4365 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
4366 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
4367 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
4368 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
4369 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
4370 
4371 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect. */
4372 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
4373 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
4374 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
4375 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
4376 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
4377 
4378 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect. */
4379 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
4380 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
4381 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
4382 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
4383 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
4384 
4385 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect. */
4386 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
4387 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
4388 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
4389 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
4390 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
4391 
4392 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect. */
4393 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
4394 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
4395 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
4396 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
4397 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
4398 
4399 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect. */
4400 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
4401 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
4402 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
4403 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
4404 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
4405 
4406 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect. */
4407 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
4408 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
4409 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
4410 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
4411 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
4412 
4413 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect. */
4414 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
4415 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
4416 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
4417 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
4418 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
4419 
4420 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect. */
4421 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
4422 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
4423 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
4424 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
4425 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
4426 
4427 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect. */
4428 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
4429 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
4430 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
4431 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
4432 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
4433 
4434 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect. */
4435 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
4436 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
4437 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
4438 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
4439 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
4440 
4441 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect. */
4442 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
4443 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
4444 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
4445 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
4446 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
4447 
4448 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect. */
4449 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
4450 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
4451 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
4452 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
4453 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
4454 
4455 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect. */
4456 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
4457 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
4458 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
4459 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
4460 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
4461 
4462 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect. */
4463 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
4464 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
4465 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
4466 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
4467 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
4468 
4469 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect. */
4470 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
4471 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
4472 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
4473 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
4474 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
4475 
4476 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect. */
4477 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
4478 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
4479 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
4480 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
4481 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
4482 
4483 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect. */
4484 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
4485 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
4486 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
4487 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
4488 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
4489 
4490 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect. */
4491 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
4492 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
4493 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
4494 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
4495 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
4496 
4497 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect. */
4498 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
4499 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
4500 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
4501 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
4502 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
4503 
4504 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect. */
4505 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
4506 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
4507 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
4508 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
4509 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
4510 
4511 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect. */
4512 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
4513 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
4514 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
4515 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
4516 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
4517 
4518 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect. */
4519 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
4520 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
4521 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
4522 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
4523 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
4524 
4525 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect. */
4526 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
4527 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
4528 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
4529 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
4530 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
4531 
4532 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect. */
4533 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
4534 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
4535 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
4536 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
4537 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
4538 
4539 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect. */
4540 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
4541 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
4542 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
4543 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
4544 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
4545 
4546 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect. */
4547 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
4548 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
4549 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
4550 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
4551 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
4552 
4553 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect. */
4554 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
4555 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
4556 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
4557 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
4558 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
4559 
4560 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect. */
4561 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
4562 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
4563 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
4564 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
4565 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
4566 
4567 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect. */
4568 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
4569 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
4570 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
4571 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
4572 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
4573 
4574 /* Register: PPI_CHENCLR */
4575 /* Description: Channel enable clear register */
4576 
4577 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect. */
4578 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
4579 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
4580 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
4581 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
4582 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
4583 
4584 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect. */
4585 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
4586 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
4587 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
4588 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
4589 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
4590 
4591 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect. */
4592 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
4593 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
4594 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
4595 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
4596 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
4597 
4598 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect. */
4599 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
4600 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
4601 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
4602 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
4603 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
4604 
4605 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect. */
4606 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
4607 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
4608 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
4609 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
4610 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
4611 
4612 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect. */
4613 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
4614 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
4615 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
4616 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
4617 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
4618 
4619 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect. */
4620 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
4621 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
4622 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
4623 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
4624 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
4625 
4626 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect. */
4627 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
4628 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
4629 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
4630 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
4631 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
4632 
4633 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect. */
4634 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
4635 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
4636 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
4637 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
4638 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
4639 
4640 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect. */
4641 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
4642 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
4643 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
4644 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
4645 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
4646 
4647 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect. */
4648 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
4649 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
4650 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
4651 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
4652 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
4653 
4654 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect. */
4655 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
4656 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
4657 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
4658 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
4659 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
4660 
4661 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect. */
4662 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
4663 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
4664 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
4665 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
4666 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
4667 
4668 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect. */
4669 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
4670 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
4671 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
4672 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
4673 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
4674 
4675 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect. */
4676 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
4677 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
4678 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
4679 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
4680 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
4681 
4682 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect. */
4683 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
4684 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
4685 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
4686 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
4687 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
4688 
4689 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect. */
4690 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
4691 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
4692 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
4693 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
4694 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
4695 
4696 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect. */
4697 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
4698 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
4699 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
4700 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
4701 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
4702 
4703 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect. */
4704 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
4705 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
4706 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
4707 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
4708 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
4709 
4710 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect. */
4711 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
4712 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
4713 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
4714 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
4715 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
4716 
4717 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect. */
4718 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
4719 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
4720 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
4721 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
4722 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
4723 
4724 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect. */
4725 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
4726 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
4727 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
4728 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
4729 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
4730 
4731 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect. */
4732 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
4733 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
4734 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
4735 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
4736 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
4737 
4738 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect. */
4739 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
4740 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
4741 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
4742 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
4743 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
4744 
4745 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect. */
4746 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
4747 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
4748 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
4749 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
4750 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
4751 
4752 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect. */
4753 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
4754 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
4755 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
4756 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
4757 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
4758 
4759 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect. */
4760 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
4761 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
4762 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
4763 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
4764 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
4765 
4766 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect. */
4767 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
4768 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
4769 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
4770 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
4771 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
4772 
4773 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect. */
4774 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
4775 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
4776 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
4777 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
4778 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
4779 
4780 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect. */
4781 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
4782 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
4783 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
4784 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
4785 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
4786 
4787 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect. */
4788 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
4789 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
4790 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
4791 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
4792 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
4793 
4794 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect. */
4795 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
4796 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
4797 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
4798 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
4799 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
4800 
4801 /* Register: PPI_CH_EEP */
4802 /* Description: Description cluster: Channel n event endpoint */
4803 
4804 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
4805 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
4806 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
4807 
4808 /* Register: PPI_CH_TEP */
4809 /* Description: Description cluster: Channel n task endpoint */
4810 
4811 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
4812 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
4813 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
4814 
4815 /* Register: PPI_CHG */
4816 /* Description: Description collection: Channel group n */
4817 
4818 /* Bit 31 : Include or exclude channel 31 */
4819 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
4820 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
4821 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
4822 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
4823 
4824 /* Bit 30 : Include or exclude channel 30 */
4825 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
4826 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
4827 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
4828 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
4829 
4830 /* Bit 29 : Include or exclude channel 29 */
4831 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
4832 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
4833 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
4834 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
4835 
4836 /* Bit 28 : Include or exclude channel 28 */
4837 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
4838 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
4839 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
4840 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
4841 
4842 /* Bit 27 : Include or exclude channel 27 */
4843 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
4844 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
4845 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
4846 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
4847 
4848 /* Bit 26 : Include or exclude channel 26 */
4849 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
4850 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
4851 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
4852 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
4853 
4854 /* Bit 25 : Include or exclude channel 25 */
4855 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
4856 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
4857 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
4858 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
4859 
4860 /* Bit 24 : Include or exclude channel 24 */
4861 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
4862 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
4863 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
4864 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
4865 
4866 /* Bit 23 : Include or exclude channel 23 */
4867 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
4868 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
4869 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
4870 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
4871 
4872 /* Bit 22 : Include or exclude channel 22 */
4873 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
4874 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
4875 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
4876 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
4877 
4878 /* Bit 21 : Include or exclude channel 21 */
4879 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
4880 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
4881 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
4882 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
4883 
4884 /* Bit 20 : Include or exclude channel 20 */
4885 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
4886 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
4887 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
4888 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
4889 
4890 /* Bit 19 : Include or exclude channel 19 */
4891 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
4892 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
4893 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
4894 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
4895 
4896 /* Bit 18 : Include or exclude channel 18 */
4897 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
4898 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
4899 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
4900 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
4901 
4902 /* Bit 17 : Include or exclude channel 17 */
4903 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
4904 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
4905 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
4906 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
4907 
4908 /* Bit 16 : Include or exclude channel 16 */
4909 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
4910 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
4911 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
4912 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
4913 
4914 /* Bit 15 : Include or exclude channel 15 */
4915 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
4916 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
4917 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
4918 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
4919 
4920 /* Bit 14 : Include or exclude channel 14 */
4921 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
4922 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
4923 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
4924 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
4925 
4926 /* Bit 13 : Include or exclude channel 13 */
4927 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
4928 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
4929 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
4930 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
4931 
4932 /* Bit 12 : Include or exclude channel 12 */
4933 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
4934 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
4935 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
4936 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
4937 
4938 /* Bit 11 : Include or exclude channel 11 */
4939 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
4940 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
4941 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
4942 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
4943 
4944 /* Bit 10 : Include or exclude channel 10 */
4945 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
4946 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
4947 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
4948 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
4949 
4950 /* Bit 9 : Include or exclude channel 9 */
4951 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
4952 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
4953 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
4954 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
4955 
4956 /* Bit 8 : Include or exclude channel 8 */
4957 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
4958 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
4959 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
4960 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
4961 
4962 /* Bit 7 : Include or exclude channel 7 */
4963 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
4964 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
4965 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
4966 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
4967 
4968 /* Bit 6 : Include or exclude channel 6 */
4969 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
4970 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
4971 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
4972 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
4973 
4974 /* Bit 5 : Include or exclude channel 5 */
4975 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
4976 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
4977 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
4978 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
4979 
4980 /* Bit 4 : Include or exclude channel 4 */
4981 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
4982 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
4983 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
4984 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
4985 
4986 /* Bit 3 : Include or exclude channel 3 */
4987 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
4988 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
4989 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
4990 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
4991 
4992 /* Bit 2 : Include or exclude channel 2 */
4993 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
4994 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
4995 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
4996 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
4997 
4998 /* Bit 1 : Include or exclude channel 1 */
4999 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
5000 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
5001 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
5002 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
5003 
5004 /* Bit 0 : Include or exclude channel 0 */
5005 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
5006 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
5007 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
5008 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
5009 
5010 /* Register: PPI_FORK_TEP */
5011 /* Description: Description cluster: Channel n task endpoint */
5012 
5013 /* Bits 31..0 : Pointer to task register */
5014 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
5015 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
5016 
5017 
5018 /* Peripheral: QDEC */
5019 /* Description: Quadrature Decoder */
5020 
5021 /* Register: QDEC_TASKS_START */
5022 /* Description: Task starting the quadrature decoder */
5023 
5024 /* Bit 0 : Task starting the quadrature decoder */
5025 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5026 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5027 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5028 
5029 /* Register: QDEC_TASKS_STOP */
5030 /* Description: Task stopping the quadrature decoder */
5031 
5032 /* Bit 0 : Task stopping the quadrature decoder */
5033 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5034 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5035 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5036 
5037 /* Register: QDEC_TASKS_READCLRACC */
5038 /* Description: Read and clear ACC and ACCDBL */
5039 
5040 /* Bit 0 : Read and clear ACC and ACCDBL */
5041 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
5042 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
5043 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
5044 
5045 /* Register: QDEC_TASKS_RDCLRACC */
5046 /* Description: Read and clear ACC */
5047 
5048 /* Bit 0 : Read and clear ACC */
5049 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
5050 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
5051 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
5052 
5053 /* Register: QDEC_TASKS_RDCLRDBL */
5054 /* Description: Read and clear ACCDBL */
5055 
5056 /* Bit 0 : Read and clear ACCDBL */
5057 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
5058 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
5059 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
5060 
5061 /* Register: QDEC_EVENTS_SAMPLERDY */
5062 /* Description: Event being generated for every new sample value written to the SAMPLE register */
5063 
5064 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
5065 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
5066 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
5067 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
5068 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
5069 
5070 /* Register: QDEC_EVENTS_REPORTRDY */
5071 /* Description: Non-null report ready */
5072 
5073 /* Bit 0 : Non-null report ready */
5074 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
5075 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
5076 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
5077 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
5078 
5079 /* Register: QDEC_EVENTS_ACCOF */
5080 /* Description: ACC or ACCDBL register overflow */
5081 
5082 /* Bit 0 : ACC or ACCDBL register overflow */
5083 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
5084 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
5085 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
5086 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
5087 
5088 /* Register: QDEC_EVENTS_DBLRDY */
5089 /* Description: Double displacement(s) detected */
5090 
5091 /* Bit 0 : Double displacement(s) detected */
5092 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
5093 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
5094 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
5095 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
5096 
5097 /* Register: QDEC_EVENTS_STOPPED */
5098 /* Description: QDEC has been stopped */
5099 
5100 /* Bit 0 : QDEC has been stopped */
5101 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
5102 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
5103 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
5104 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5105 
5106 /* Register: QDEC_SHORTS */
5107 /* Description: Shortcuts between local events and tasks */
5108 
5109 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
5110 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
5111 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
5112 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5113 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5114 
5115 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
5116 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
5117 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
5118 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5119 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5120 
5121 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
5122 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
5123 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
5124 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
5125 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
5126 
5127 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
5128 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
5129 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
5130 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5131 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5132 
5133 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
5134 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
5135 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
5136 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
5137 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
5138 
5139 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
5140 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
5141 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
5142 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5143 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5144 
5145 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
5146 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
5147 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
5148 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5149 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5150 
5151 /* Register: QDEC_INTENSET */
5152 /* Description: Enable interrupt */
5153 
5154 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
5155 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
5156 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5157 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5158 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5159 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5160 
5161 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
5162 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
5163 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
5164 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5165 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5166 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
5167 
5168 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
5169 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5170 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
5171 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5172 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5173 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
5174 
5175 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
5176 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
5177 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
5178 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5179 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5180 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
5181 
5182 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
5183 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
5184 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
5185 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5186 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5187 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
5188 
5189 /* Register: QDEC_INTENCLR */
5190 /* Description: Disable interrupt */
5191 
5192 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
5193 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
5194 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5195 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5196 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5197 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5198 
5199 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
5200 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
5201 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
5202 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5203 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5204 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
5205 
5206 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
5207 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5208 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
5209 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5210 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5211 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
5212 
5213 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
5214 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
5215 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
5216 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5217 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5218 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
5219 
5220 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
5221 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
5222 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
5223 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5224 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5225 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
5226 
5227 /* Register: QDEC_ENABLE */
5228 /* Description: Enable the quadrature decoder */
5229 
5230 /* Bit 0 : Enable or disable the quadrature decoder */
5231 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5232 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5233 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
5234 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5235 
5236 /* Register: QDEC_LEDPOL */
5237 /* Description: LED output pin polarity */
5238 
5239 /* Bit 0 : LED output pin polarity */
5240 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
5241 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
5242 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
5243 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
5244 
5245 /* Register: QDEC_SAMPLEPER */
5246 /* Description: Sample period */
5247 
5248 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
5249 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
5250 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
5251 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
5252 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
5253 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
5254 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
5255 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
5256 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
5257 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
5258 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
5259 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
5260 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
5261 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
5262 
5263 /* Register: QDEC_SAMPLE */
5264 /* Description: Motion sample value */
5265 
5266 /* Bits 31..0 : Last motion sample */
5267 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
5268 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
5269 
5270 /* Register: QDEC_REPORTPER */
5271 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
5272 
5273 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
5274 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
5275 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
5276 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */
5277 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */
5278 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */
5279 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */
5280 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */
5281 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */
5282 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */
5283 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */
5284 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */
5285 
5286 /* Register: QDEC_ACC */
5287 /* Description: Register accumulating the valid transitions */
5288 
5289 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
5290 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
5291 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
5292 
5293 /* Register: QDEC_ACCREAD */
5294 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
5295 
5296 /* Bits 31..0 : Snapshot of the ACC register. */
5297 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
5298 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
5299 
5300 /* Register: QDEC_PSEL_LED */
5301 /* Description: Pin select for LED signal */
5302 
5303 /* Bit 31 : Connection */
5304 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5305 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5306 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
5307 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
5308 
5309 /* Bits 4..0 : Pin number */
5310 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
5311 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
5312 
5313 /* Register: QDEC_PSEL_A */
5314 /* Description: Pin select for A signal */
5315 
5316 /* Bit 31 : Connection */
5317 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5318 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5319 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
5320 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
5321 
5322 /* Bits 4..0 : Pin number */
5323 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
5324 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
5325 
5326 /* Register: QDEC_PSEL_B */
5327 /* Description: Pin select for B signal */
5328 
5329 /* Bit 31 : Connection */
5330 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5331 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5332 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
5333 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
5334 
5335 /* Bits 4..0 : Pin number */
5336 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
5337 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
5338 
5339 /* Register: QDEC_DBFEN */
5340 /* Description: Enable input debounce filters */
5341 
5342 /* Bit 0 : Enable input debounce filters */
5343 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
5344 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
5345 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
5346 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
5347 
5348 /* Register: QDEC_LEDPRE */
5349 /* Description: Time period the LED is switched ON prior to sampling */
5350 
5351 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
5352 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
5353 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
5354 
5355 /* Register: QDEC_ACCDBL */
5356 /* Description: Register accumulating the number of detected double transitions */
5357 
5358 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
5359 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
5360 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
5361 
5362 /* Register: QDEC_ACCDBLREAD */
5363 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
5364 
5365 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
5366 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
5367 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
5368 
5369 
5370 /* Peripheral: RADIO */
5371 /* Description: 2.4 GHz radio */
5372 
5373 /* Register: RADIO_TASKS_TXEN */
5374 /* Description: Enable RADIO in TX mode */
5375 
5376 /* Bit 0 : Enable RADIO in TX mode */
5377 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
5378 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
5379 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
5380 
5381 /* Register: RADIO_TASKS_RXEN */
5382 /* Description: Enable RADIO in RX mode */
5383 
5384 /* Bit 0 : Enable RADIO in RX mode */
5385 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
5386 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
5387 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
5388 
5389 /* Register: RADIO_TASKS_START */
5390 /* Description: Start RADIO */
5391 
5392 /* Bit 0 : Start RADIO */
5393 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5394 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5395 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5396 
5397 /* Register: RADIO_TASKS_STOP */
5398 /* Description: Stop RADIO */
5399 
5400 /* Bit 0 : Stop RADIO */
5401 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5402 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5403 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5404 
5405 /* Register: RADIO_TASKS_DISABLE */
5406 /* Description: Disable RADIO */
5407 
5408 /* Bit 0 : Disable RADIO */
5409 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
5410 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
5411 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
5412 
5413 /* Register: RADIO_TASKS_RSSISTART */
5414 /* Description: Start the RSSI and take one single sample of the receive signal strength */
5415 
5416 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
5417 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
5418 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
5419 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
5420 
5421 /* Register: RADIO_TASKS_RSSISTOP */
5422 /* Description: Stop the RSSI measurement */
5423 
5424 /* Bit 0 : Stop the RSSI measurement */
5425 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
5426 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
5427 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
5428 
5429 /* Register: RADIO_TASKS_BCSTART */
5430 /* Description: Start the bit counter */
5431 
5432 /* Bit 0 : Start the bit counter */
5433 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
5434 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
5435 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
5436 
5437 /* Register: RADIO_TASKS_BCSTOP */
5438 /* Description: Stop the bit counter */
5439 
5440 /* Bit 0 : Stop the bit counter */
5441 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
5442 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
5443 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
5444 
5445 /* Register: RADIO_TASKS_EDSTART */
5446 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
5447 
5448 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
5449 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
5450 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
5451 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
5452 
5453 /* Register: RADIO_TASKS_EDSTOP */
5454 /* Description: Stop the energy detect measurement */
5455 
5456 /* Bit 0 : Stop the energy detect measurement */
5457 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
5458 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
5459 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
5460 
5461 /* Register: RADIO_TASKS_CCASTART */
5462 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
5463 
5464 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
5465 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
5466 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
5467 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
5468 
5469 /* Register: RADIO_TASKS_CCASTOP */
5470 /* Description: Stop the clear channel assessment */
5471 
5472 /* Bit 0 : Stop the clear channel assessment */
5473 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
5474 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
5475 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
5476 
5477 /* Register: RADIO_EVENTS_READY */
5478 /* Description: RADIO has ramped up and is ready to be started */
5479 
5480 /* Bit 0 : RADIO has ramped up and is ready to be started */
5481 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
5482 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
5483 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
5484 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
5485 
5486 /* Register: RADIO_EVENTS_ADDRESS */
5487 /* Description: Address sent or received */
5488 
5489 /* Bit 0 : Address sent or received */
5490 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
5491 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
5492 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
5493 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
5494 
5495 /* Register: RADIO_EVENTS_PAYLOAD */
5496 /* Description: Packet payload sent or received */
5497 
5498 /* Bit 0 : Packet payload sent or received */
5499 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
5500 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
5501 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
5502 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
5503 
5504 /* Register: RADIO_EVENTS_END */
5505 /* Description: Packet sent or received */
5506 
5507 /* Bit 0 : Packet sent or received */
5508 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
5509 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
5510 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
5511 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
5512 
5513 /* Register: RADIO_EVENTS_DISABLED */
5514 /* Description: RADIO has been disabled */
5515 
5516 /* Bit 0 : RADIO has been disabled */
5517 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
5518 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
5519 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
5520 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
5521 
5522 /* Register: RADIO_EVENTS_DEVMATCH */
5523 /* Description: A device address match occurred on the last received packet */
5524 
5525 /* Bit 0 : A device address match occurred on the last received packet */
5526 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
5527 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
5528 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
5529 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
5530 
5531 /* Register: RADIO_EVENTS_DEVMISS */
5532 /* Description: No device address match occurred on the last received packet */
5533 
5534 /* Bit 0 : No device address match occurred on the last received packet */
5535 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
5536 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
5537 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
5538 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
5539 
5540 /* Register: RADIO_EVENTS_RSSIEND */
5541 /* Description: Sampling of receive signal strength complete */
5542 
5543 /* Bit 0 : Sampling of receive signal strength complete */
5544 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
5545 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
5546 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
5547 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
5548 
5549 /* Register: RADIO_EVENTS_BCMATCH */
5550 /* Description: Bit counter reached bit count value */
5551 
5552 /* Bit 0 : Bit counter reached bit count value */
5553 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
5554 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
5555 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
5556 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
5557 
5558 /* Register: RADIO_EVENTS_CRCOK */
5559 /* Description: Packet received with CRC ok */
5560 
5561 /* Bit 0 : Packet received with CRC ok */
5562 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
5563 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
5564 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
5565 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
5566 
5567 /* Register: RADIO_EVENTS_CRCERROR */
5568 /* Description: Packet received with CRC error */
5569 
5570 /* Bit 0 : Packet received with CRC error */
5571 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
5572 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
5573 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
5574 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
5575 
5576 /* Register: RADIO_EVENTS_FRAMESTART */
5577 /* Description: IEEE 802.15.4 length field received */
5578 
5579 /* Bit 0 : IEEE 802.15.4 length field received */
5580 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
5581 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
5582 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
5583 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
5584 
5585 /* Register: RADIO_EVENTS_EDEND */
5586 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
5587 
5588 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
5589 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
5590 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
5591 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
5592 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
5593 
5594 /* Register: RADIO_EVENTS_EDSTOPPED */
5595 /* Description: The sampling of energy detection has stopped */
5596 
5597 /* Bit 0 : The sampling of energy detection has stopped */
5598 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
5599 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
5600 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
5601 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
5602 
5603 /* Register: RADIO_EVENTS_CCAIDLE */
5604 /* Description: Wireless medium in idle - clear to send */
5605 
5606 /* Bit 0 : Wireless medium in idle - clear to send */
5607 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
5608 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
5609 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
5610 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
5611 
5612 /* Register: RADIO_EVENTS_CCABUSY */
5613 /* Description: Wireless medium busy - do not send */
5614 
5615 /* Bit 0 : Wireless medium busy - do not send */
5616 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
5617 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
5618 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
5619 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
5620 
5621 /* Register: RADIO_EVENTS_CCASTOPPED */
5622 /* Description: The CCA has stopped */
5623 
5624 /* Bit 0 : The CCA has stopped */
5625 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
5626 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
5627 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
5628 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
5629 
5630 /* Register: RADIO_EVENTS_RATEBOOST */
5631 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
5632 
5633 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
5634 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
5635 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
5636 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
5637 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
5638 
5639 /* Register: RADIO_EVENTS_TXREADY */
5640 /* Description: RADIO has ramped up and is ready to be started TX path */
5641 
5642 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
5643 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
5644 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
5645 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
5646 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
5647 
5648 /* Register: RADIO_EVENTS_RXREADY */
5649 /* Description: RADIO has ramped up and is ready to be started RX path */
5650 
5651 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
5652 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
5653 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
5654 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
5655 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
5656 
5657 /* Register: RADIO_EVENTS_MHRMATCH */
5658 /* Description: MAC header match found */
5659 
5660 /* Bit 0 : MAC header match found */
5661 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
5662 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
5663 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
5664 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
5665 
5666 /* Register: RADIO_EVENTS_SYNC */
5667 /* Description: Preamble indicator */
5668 
5669 /* Bit 0 : Preamble indicator */
5670 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
5671 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
5672 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */
5673 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */
5674 
5675 /* Register: RADIO_EVENTS_PHYEND */
5676 /* Description: Generated when last bit is sent on air, or received from air */
5677 
5678 /* Bit 0 : Generated when last bit is sent on air, or received from air */
5679 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
5680 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
5681 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
5682 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
5683 
5684 /* Register: RADIO_EVENTS_CTEPRESENT */
5685 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */
5686 
5687 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
5688 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
5689 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
5690 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
5691 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
5692 
5693 /* Register: RADIO_SHORTS */
5694 /* Description: Shortcuts between local events and tasks */
5695 
5696 /* Bit 21 : Shortcut between event PHYEND and task START */
5697 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
5698 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
5699 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
5700 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
5701 
5702 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
5703 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
5704 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
5705 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
5706 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
5707 
5708 /* Bit 19 : Shortcut between event RXREADY and task START */
5709 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
5710 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
5711 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
5712 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
5713 
5714 /* Bit 18 : Shortcut between event TXREADY and task START */
5715 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
5716 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
5717 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
5718 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
5719 
5720 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
5721 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
5722 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
5723 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
5724 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
5725 
5726 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
5727 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
5728 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
5729 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
5730 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
5731 
5732 /* Bit 15 : Shortcut between event READY and task EDSTART */
5733 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
5734 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
5735 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
5736 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
5737 
5738 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
5739 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
5740 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
5741 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
5742 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
5743 
5744 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
5745 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
5746 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
5747 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
5748 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
5749 
5750 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
5751 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
5752 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
5753 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
5754 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
5755 
5756 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
5757 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
5758 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
5759 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
5760 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
5761 
5762 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
5763 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
5764 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
5765 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
5766 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
5767 
5768 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
5769 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
5770 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
5771 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
5772 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
5773 
5774 /* Bit 5 : Shortcut between event END and task START */
5775 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
5776 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
5777 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
5778 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
5779 
5780 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
5781 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
5782 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
5783 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
5784 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
5785 
5786 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
5787 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
5788 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
5789 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
5790 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
5791 
5792 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
5793 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
5794 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
5795 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
5796 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
5797 
5798 /* Bit 1 : Shortcut between event END and task DISABLE */
5799 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
5800 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
5801 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
5802 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
5803 
5804 /* Bit 0 : Shortcut between event READY and task START */
5805 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
5806 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
5807 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
5808 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
5809 
5810 /* Register: RADIO_INTENSET */
5811 /* Description: Enable interrupt */
5812 
5813 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
5814 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
5815 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
5816 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
5817 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
5818 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
5819 
5820 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
5821 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
5822 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
5823 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
5824 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
5825 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
5826 
5827 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
5828 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
5829 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
5830 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */
5831 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */
5832 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */
5833 
5834 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
5835 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
5836 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
5837 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
5838 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
5839 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
5840 
5841 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
5842 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
5843 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
5844 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
5845 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
5846 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
5847 
5848 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
5849 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
5850 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
5851 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
5852 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
5853 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
5854 
5855 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
5856 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
5857 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
5858 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
5859 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
5860 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
5861 
5862 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
5863 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
5864 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
5865 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
5866 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
5867 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
5868 
5869 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
5870 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
5871 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
5872 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
5873 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
5874 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
5875 
5876 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
5877 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
5878 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
5879 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
5880 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
5881 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
5882 
5883 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
5884 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
5885 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
5886 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
5887 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
5888 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
5889 
5890 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
5891 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
5892 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
5893 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
5894 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
5895 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
5896 
5897 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
5898 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
5899 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
5900 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
5901 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
5902 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
5903 
5904 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
5905 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
5906 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
5907 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
5908 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
5909 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
5910 
5911 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
5912 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
5913 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
5914 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
5915 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
5916 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
5917 
5918 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
5919 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
5920 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
5921 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
5922 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
5923 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
5924 
5925 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
5926 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
5927 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
5928 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
5929 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
5930 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
5931 
5932 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
5933 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
5934 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
5935 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
5936 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
5937 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
5938 
5939 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
5940 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
5941 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
5942 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
5943 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
5944 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
5945 
5946 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
5947 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
5948 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
5949 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
5950 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
5951 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
5952 
5953 /* Bit 3 : Write '1' to enable interrupt for event END */
5954 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
5955 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
5956 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
5957 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
5958 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
5959 
5960 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
5961 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
5962 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
5963 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
5964 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
5965 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
5966 
5967 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
5968 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
5969 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
5970 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
5971 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
5972 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
5973 
5974 /* Bit 0 : Write '1' to enable interrupt for event READY */
5975 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
5976 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
5977 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
5978 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
5979 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
5980 
5981 /* Register: RADIO_INTENCLR */
5982 /* Description: Disable interrupt */
5983 
5984 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
5985 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
5986 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
5987 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
5988 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
5989 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
5990 
5991 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
5992 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
5993 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
5994 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
5995 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
5996 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
5997 
5998 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
5999 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
6000 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
6001 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */
6002 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */
6003 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */
6004 
6005 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
6006 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
6007 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
6008 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
6009 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
6010 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
6011 
6012 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
6013 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
6014 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
6015 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
6016 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
6017 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
6018 
6019 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
6020 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
6021 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
6022 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
6023 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
6024 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
6025 
6026 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
6027 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
6028 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
6029 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
6030 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
6031 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
6032 
6033 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
6034 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
6035 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
6036 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
6037 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
6038 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
6039 
6040 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
6041 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
6042 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
6043 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
6044 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
6045 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
6046 
6047 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
6048 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
6049 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
6050 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
6051 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
6052 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
6053 
6054 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
6055 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
6056 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
6057 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
6058 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
6059 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
6060 
6061 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
6062 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
6063 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
6064 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
6065 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
6066 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
6067 
6068 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
6069 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
6070 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
6071 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
6072 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
6073 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
6074 
6075 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
6076 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
6077 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
6078 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6079 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6080 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
6081 
6082 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
6083 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
6084 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
6085 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6086 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6087 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
6088 
6089 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
6090 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
6091 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
6092 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6093 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6094 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
6095 
6096 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
6097 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
6098 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
6099 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6100 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6101 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
6102 
6103 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
6104 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
6105 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
6106 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6107 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6108 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
6109 
6110 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
6111 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
6112 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
6113 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6114 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6115 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
6116 
6117 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
6118 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
6119 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
6120 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6121 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6122 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
6123 
6124 /* Bit 3 : Write '1' to disable interrupt for event END */
6125 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
6126 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6127 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6128 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6129 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
6130 
6131 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
6132 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
6133 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
6134 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6135 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6136 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
6137 
6138 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
6139 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
6140 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
6141 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6142 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6143 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
6144 
6145 /* Bit 0 : Write '1' to disable interrupt for event READY */
6146 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
6147 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
6148 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6149 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
6150 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
6151 
6152 /* Register: RADIO_CRCSTATUS */
6153 /* Description: CRC status */
6154 
6155 /* Bit 0 : CRC status of packet received */
6156 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
6157 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
6158 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
6159 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
6160 
6161 /* Register: RADIO_RXMATCH */
6162 /* Description: Received address */
6163 
6164 /* Bits 2..0 : Received address */
6165 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
6166 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
6167 
6168 /* Register: RADIO_RXCRC */
6169 /* Description: CRC field of previously received packet */
6170 
6171 /* Bits 23..0 : CRC field of previously received packet */
6172 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
6173 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
6174 
6175 /* Register: RADIO_DAI */
6176 /* Description: Device address match index */
6177 
6178 /* Bits 2..0 : Device address match index */
6179 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
6180 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
6181 
6182 /* Register: RADIO_PDUSTAT */
6183 /* Description: Payload status */
6184 
6185 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
6186 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
6187 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
6188 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */
6189 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */
6190 
6191 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
6192 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
6193 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
6194 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
6195 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
6196 
6197 /* Register: RADIO_CTESTATUS */
6198 /* Description: CTEInfo parsed from received packet */
6199 
6200 /* Bits 7..6 : CTEType parsed from packet */
6201 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
6202 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
6203 
6204 /* Bit 5 : RFU parsed from packet */
6205 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
6206 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
6207 
6208 /* Bits 4..0 : CTETime parsed from packet */
6209 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
6210 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
6211 
6212 /* Register: RADIO_DFESTATUS */
6213 /* Description: DFE status information */
6214 
6215 /* Bit 4 : Internal state of sampling state machine */
6216 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
6217 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
6218 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
6219 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
6220 
6221 /* Bits 2..0 : Internal state of switching state machine */
6222 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
6223 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
6224 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
6225 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
6226 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
6227 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
6228 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
6229 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
6230 
6231 /* Register: RADIO_PACKETPTR */
6232 /* Description: Packet pointer */
6233 
6234 /* Bits 31..0 : Packet pointer */
6235 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
6236 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
6237 
6238 /* Register: RADIO_FREQUENCY */
6239 /* Description: Frequency */
6240 
6241 /* Bit 8 : Channel map selection */
6242 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
6243 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
6244 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */
6245 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */
6246 
6247 /* Bits 6..0 : Radio channel frequency */
6248 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
6249 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
6250 
6251 /* Register: RADIO_TXPOWER */
6252 /* Description: Output power */
6253 
6254 /* Bits 7..0 : RADIO output power */
6255 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
6256 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
6257 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
6258 #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
6259 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
6260 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
6261 #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
6262 #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
6263 #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
6264 #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
6265 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
6266 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
6267 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
6268 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
6269 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
6270 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
6271 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
6272 
6273 /* Register: RADIO_MODE */
6274 /* Description: Data rate and modulation */
6275 
6276 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
6277 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
6278 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
6279 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
6280 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
6281 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
6282 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
6283 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */
6284 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */
6285 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
6286 
6287 /* Register: RADIO_PCNF0 */
6288 /* Description: Packet configuration register 0 */
6289 
6290 /* Bits 30..29 : Length of TERM field in Long Range operation */
6291 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
6292 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
6293 
6294 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
6295 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
6296 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
6297 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
6298 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
6299 
6300 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
6301 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
6302 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
6303 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
6304 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
6305 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
6306 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */
6307 
6308 /* Bits 23..22 : Length of code indicator - Long Range */
6309 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
6310 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
6311 
6312 /* Bit 20 : Include or exclude S1 field in RAM */
6313 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
6314 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
6315 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
6316 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
6317 
6318 /* Bits 19..16 : Length on air of S1 field in number of bits */
6319 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
6320 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
6321 
6322 /* Bit 8 : Length on air of S0 field in number of bytes */
6323 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
6324 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
6325 
6326 /* Bits 3..0 : Length on air of LENGTH field in number of bits */
6327 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
6328 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
6329 
6330 /* Register: RADIO_PCNF1 */
6331 /* Description: Packet configuration register 1 */
6332 
6333 /* Bit 25 : Enable or disable packet whitening */
6334 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
6335 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
6336 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
6337 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
6338 
6339 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
6340 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
6341 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
6342 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
6343 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
6344 
6345 /* Bits 18..16 : Base address length in number of bytes */
6346 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
6347 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
6348 
6349 /* Bits 15..8 : Static length in number of bytes */
6350 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
6351 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
6352 
6353 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
6354 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
6355 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
6356 
6357 /* Register: RADIO_BASE0 */
6358 /* Description: Base address 0 */
6359 
6360 /* Bits 31..0 : Base address 0 */
6361 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
6362 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
6363 
6364 /* Register: RADIO_BASE1 */
6365 /* Description: Base address 1 */
6366 
6367 /* Bits 31..0 : Base address 1 */
6368 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
6369 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
6370 
6371 /* Register: RADIO_PREFIX0 */
6372 /* Description: Prefixes bytes for logical addresses 0-3 */
6373 
6374 /* Bits 31..24 : Address prefix 3. */
6375 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
6376 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
6377 
6378 /* Bits 23..16 : Address prefix 2. */
6379 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
6380 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
6381 
6382 /* Bits 15..8 : Address prefix 1. */
6383 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
6384 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
6385 
6386 /* Bits 7..0 : Address prefix 0. */
6387 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
6388 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
6389 
6390 /* Register: RADIO_PREFIX1 */
6391 /* Description: Prefixes bytes for logical addresses 4-7 */
6392 
6393 /* Bits 31..24 : Address prefix 7. */
6394 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
6395 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
6396 
6397 /* Bits 23..16 : Address prefix 6. */
6398 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
6399 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
6400 
6401 /* Bits 15..8 : Address prefix 5. */
6402 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
6403 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
6404 
6405 /* Bits 7..0 : Address prefix 4. */
6406 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
6407 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
6408 
6409 /* Register: RADIO_TXADDRESS */
6410 /* Description: Transmit address select */
6411 
6412 /* Bits 2..0 : Transmit address select */
6413 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
6414 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
6415 
6416 /* Register: RADIO_RXADDRESSES */
6417 /* Description: Receive address select */
6418 
6419 /* Bit 7 : Enable or disable reception on logical address 7. */
6420 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
6421 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
6422 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
6423 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
6424 
6425 /* Bit 6 : Enable or disable reception on logical address 6. */
6426 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
6427 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
6428 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
6429 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
6430 
6431 /* Bit 5 : Enable or disable reception on logical address 5. */
6432 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
6433 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
6434 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
6435 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
6436 
6437 /* Bit 4 : Enable or disable reception on logical address 4. */
6438 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
6439 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
6440 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
6441 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
6442 
6443 /* Bit 3 : Enable or disable reception on logical address 3. */
6444 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
6445 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
6446 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
6447 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
6448 
6449 /* Bit 2 : Enable or disable reception on logical address 2. */
6450 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
6451 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
6452 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
6453 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
6454 
6455 /* Bit 1 : Enable or disable reception on logical address 1. */
6456 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
6457 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
6458 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
6459 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
6460 
6461 /* Bit 0 : Enable or disable reception on logical address 0. */
6462 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
6463 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
6464 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
6465 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
6466 
6467 /* Register: RADIO_CRCCNF */
6468 /* Description: CRC configuration */
6469 
6470 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
6471 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
6472 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
6473 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
6474 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
6475 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
6476 
6477 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */
6478 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
6479 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
6480 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
6481 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
6482 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
6483 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
6484 
6485 /* Register: RADIO_CRCPOLY */
6486 /* Description: CRC polynomial */
6487 
6488 /* Bits 23..0 : CRC polynomial */
6489 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
6490 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
6491 
6492 /* Register: RADIO_CRCINIT */
6493 /* Description: CRC initial value */
6494 
6495 /* Bits 23..0 : CRC initial value */
6496 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
6497 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
6498 
6499 /* Register: RADIO_TIFS */
6500 /* Description: Interframe spacing in us */
6501 
6502 /* Bits 9..0 : Interframe spacing in us. */
6503 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
6504 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
6505 
6506 /* Register: RADIO_RSSISAMPLE */
6507 /* Description: RSSI sample */
6508 
6509 /* Bits 6..0 : RSSI sample. */
6510 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
6511 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
6512 
6513 /* Register: RADIO_STATE */
6514 /* Description: Current radio state */
6515 
6516 /* Bits 3..0 : Current radio state */
6517 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
6518 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
6519 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
6520 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
6521 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
6522 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
6523 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
6524 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
6525 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
6526 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
6527 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
6528 
6529 /* Register: RADIO_DATAWHITEIV */
6530 /* Description: Data whitening initial value */
6531 
6532 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
6533 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
6534 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
6535 
6536 /* Register: RADIO_BCC */
6537 /* Description: Bit counter compare */
6538 
6539 /* Bits 31..0 : Bit counter compare */
6540 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
6541 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
6542 
6543 /* Register: RADIO_DAB */
6544 /* Description: Description collection: Device address base segment n */
6545 
6546 /* Bits 31..0 : Device address base segment n */
6547 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
6548 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
6549 
6550 /* Register: RADIO_DAP */
6551 /* Description: Description collection: Device address prefix n */
6552 
6553 /* Bits 15..0 : Device address prefix n */
6554 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
6555 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
6556 
6557 /* Register: RADIO_DACNF */
6558 /* Description: Device address match configuration */
6559 
6560 /* Bit 15 : TxAdd for device address 7 */
6561 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
6562 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
6563 
6564 /* Bit 14 : TxAdd for device address 6 */
6565 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
6566 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
6567 
6568 /* Bit 13 : TxAdd for device address 5 */
6569 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
6570 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
6571 
6572 /* Bit 12 : TxAdd for device address 4 */
6573 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
6574 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
6575 
6576 /* Bit 11 : TxAdd for device address 3 */
6577 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
6578 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
6579 
6580 /* Bit 10 : TxAdd for device address 2 */
6581 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
6582 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
6583 
6584 /* Bit 9 : TxAdd for device address 1 */
6585 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
6586 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
6587 
6588 /* Bit 8 : TxAdd for device address 0 */
6589 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
6590 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
6591 
6592 /* Bit 7 : Enable or disable device address matching using device address 7 */
6593 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
6594 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
6595 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
6596 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
6597 
6598 /* Bit 6 : Enable or disable device address matching using device address 6 */
6599 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
6600 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
6601 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
6602 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
6603 
6604 /* Bit 5 : Enable or disable device address matching using device address 5 */
6605 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
6606 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
6607 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
6608 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
6609 
6610 /* Bit 4 : Enable or disable device address matching using device address 4 */
6611 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
6612 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
6613 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
6614 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
6615 
6616 /* Bit 3 : Enable or disable device address matching using device address 3 */
6617 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
6618 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
6619 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
6620 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
6621 
6622 /* Bit 2 : Enable or disable device address matching using device address 2 */
6623 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
6624 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
6625 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
6626 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
6627 
6628 /* Bit 1 : Enable or disable device address matching using device address 1 */
6629 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
6630 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
6631 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
6632 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
6633 
6634 /* Bit 0 : Enable or disable device address matching using device address 0 */
6635 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
6636 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
6637 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
6638 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
6639 
6640 /* Register: RADIO_MHRMATCHCONF */
6641 /* Description: Search pattern configuration */
6642 
6643 /* Bits 31..0 : Search pattern configuration */
6644 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
6645 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
6646 
6647 /* Register: RADIO_MHRMATCHMAS */
6648 /* Description: Pattern mask */
6649 
6650 /* Bits 31..0 : Pattern mask */
6651 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
6652 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
6653 
6654 /* Register: RADIO_MODECNF0 */
6655 /* Description: Radio mode configuration register 0 */
6656 
6657 /* Bits 9..8 : Default TX value */
6658 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
6659 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
6660 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
6661 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
6662 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
6663 
6664 /* Bit 0 : Radio ramp-up time */
6665 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
6666 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
6667 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
6668 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */
6669 
6670 /* Register: RADIO_SFD */
6671 /* Description: IEEE 802.15.4 start of frame delimiter */
6672 
6673 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
6674 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
6675 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
6676 
6677 /* Register: RADIO_EDCNT */
6678 /* Description: IEEE 802.15.4 energy detect loop count */
6679 
6680 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
6681 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
6682 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
6683 
6684 /* Register: RADIO_EDSAMPLE */
6685 /* Description: IEEE 802.15.4 energy detect level */
6686 
6687 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
6688 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
6689 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
6690 
6691 /* Register: RADIO_CCACTRL */
6692 /* Description: IEEE 802.15.4 clear channel assessment control */
6693 
6694 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
6695 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
6696 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
6697 
6698 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
6699 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
6700 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
6701 
6702 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
6703 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
6704 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
6705 
6706 /* Bits 2..0 : CCA mode of operation */
6707 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
6708 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
6709 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
6710 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
6711 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
6712 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
6713 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
6714 
6715 /* Register: RADIO_DFEMODE */
6716 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
6717 
6718 /* Bits 1..0 : Direction finding operation mode */
6719 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
6720 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
6721 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
6722 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
6723 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
6724 
6725 /* Register: RADIO_CTEINLINECONF */
6726 /* Description: Configuration for CTE inline mode */
6727 
6728 /* Bits 31..24 : S0 bit mask to set which bit to match */
6729 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
6730 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
6731 
6732 /* Bits 23..16 : S0 bit pattern to match */
6733 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
6734 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
6735 
6736 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
6737 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
6738 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
6739 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */
6740 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */
6741 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */
6742 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */
6743 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */
6744 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */
6745 
6746 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
6747 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
6748 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
6749 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */
6750 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */
6751 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */
6752 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */
6753 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */
6754 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */
6755 
6756 /* Bits 7..6 : Max range of CTETime */
6757 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
6758 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
6759 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */
6760 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */
6761 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */
6762 
6763 /* Bit 4 : Sampling/switching if CRC is not OK */
6764 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
6765 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
6766 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
6767 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
6768 
6769 /* Bit 3 : CTEInfo is S1 byte or not */
6770 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
6771 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
6772 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
6773 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
6774 
6775 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
6776 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
6777 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
6778 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
6779 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
6780 
6781 /* Register: RADIO_DFECTRL1 */
6782 /* Description: Various configuration for Direction finding */
6783 
6784 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
6785 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
6786 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
6787 
6788 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */
6789 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */
6790 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */
6791 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */
6792 
6793 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
6794 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
6795 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
6796 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */
6797 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */
6798 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */
6799 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */
6800 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */
6801 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */
6802 
6803 /* Bit 15 : Whether to sample I/Q or magnitude/phase */
6804 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
6805 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
6806 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
6807 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
6808 
6809 /* Bits 14..12 : Interval between samples in the REFERENCE period */
6810 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
6811 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
6812 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */
6813 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */
6814 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */
6815 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */
6816 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */
6817 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */
6818 
6819 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
6820 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
6821 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
6822 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */
6823 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */
6824 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */
6825 
6826 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
6827 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
6828 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
6829 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
6830 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
6831 
6832 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
6833 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
6834 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
6835 
6836 /* Register: RADIO_DFECTRL2 */
6837 /* Description: Start offset for Direction finding */
6838 
6839 /* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */
6840 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
6841 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
6842 
6843 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */
6844 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
6845 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
6846 
6847 /* Register: RADIO_SWITCHPATTERN */
6848 /* Description: GPIO patterns to be used for each antenna */
6849 
6850 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */
6851 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
6852 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
6853 
6854 /* Register: RADIO_CLEARPATTERN */
6855 /* Description: Clear the GPIO pattern array for antenna control */
6856 
6857 /* Bit 0 : Clears GPIO pattern array for antenna control */
6858 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
6859 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
6860 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
6861 
6862 /* Register: RADIO_PSEL_DFEGPIO */
6863 /* Description: Description collection: Pin select for DFE pin n */
6864 
6865 /* Bit 31 : Connection */
6866 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6867 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6868 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
6869 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
6870 
6871 /* Bits 4..0 : Pin number */
6872 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
6873 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
6874 
6875 /* Register: RADIO_DFEPACKET_PTR */
6876 /* Description: Data pointer */
6877 
6878 /* Bits 31..0 : Data pointer */
6879 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6880 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6881 
6882 /* Register: RADIO_DFEPACKET_MAXCNT */
6883 /* Description: Maximum number of buffer words to transfer */
6884 
6885 /* Bits 13..0 : Maximum number of buffer words to transfer */
6886 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6887 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6888 
6889 /* Register: RADIO_DFEPACKET_AMOUNT */
6890 /* Description: Number of samples transferred in the last transaction */
6891 
6892 /* Bits 15..0 : Number of samples transferred in the last transaction */
6893 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
6894 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
6895 
6896 /* Register: RADIO_POWER */
6897 /* Description: Peripheral power control */
6898 
6899 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
6900 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
6901 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
6902 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
6903 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
6904 
6905 
6906 /* Peripheral: RNG */
6907 /* Description: Random Number Generator */
6908 
6909 /* Register: RNG_TASKS_START */
6910 /* Description: Task starting the random number generator */
6911 
6912 /* Bit 0 : Task starting the random number generator */
6913 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6914 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6915 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6916 
6917 /* Register: RNG_TASKS_STOP */
6918 /* Description: Task stopping the random number generator */
6919 
6920 /* Bit 0 : Task stopping the random number generator */
6921 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6922 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6923 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6924 
6925 /* Register: RNG_EVENTS_VALRDY */
6926 /* Description: Event being generated for every new random number written to the VALUE register */
6927 
6928 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
6929 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
6930 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
6931 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
6932 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
6933 
6934 /* Register: RNG_SHORTS */
6935 /* Description: Shortcuts between local events and tasks */
6936 
6937 /* Bit 0 : Shortcut between event VALRDY and task STOP */
6938 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
6939 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
6940 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
6941 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
6942 
6943 /* Register: RNG_INTENSET */
6944 /* Description: Enable interrupt */
6945 
6946 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
6947 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
6948 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
6949 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6950 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6951 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
6952 
6953 /* Register: RNG_INTENCLR */
6954 /* Description: Disable interrupt */
6955 
6956 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
6957 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
6958 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
6959 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6960 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6961 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
6962 
6963 /* Register: RNG_CONFIG */
6964 /* Description: Configuration register */
6965 
6966 /* Bit 0 : Bias correction */
6967 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
6968 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
6969 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
6970 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
6971 
6972 /* Register: RNG_VALUE */
6973 /* Description: Output random number */
6974 
6975 /* Bits 7..0 : Generated random number */
6976 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
6977 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
6978 
6979 
6980 /* Peripheral: RTC */
6981 /* Description: Real time counter 0 */
6982 
6983 /* Register: RTC_TASKS_START */
6984 /* Description: Start RTC COUNTER */
6985 
6986 /* Bit 0 : Start RTC COUNTER */
6987 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6988 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6989 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6990 
6991 /* Register: RTC_TASKS_STOP */
6992 /* Description: Stop RTC COUNTER */
6993 
6994 /* Bit 0 : Stop RTC COUNTER */
6995 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6996 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6997 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6998 
6999 /* Register: RTC_TASKS_CLEAR */
7000 /* Description: Clear RTC COUNTER */
7001 
7002 /* Bit 0 : Clear RTC COUNTER */
7003 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
7004 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
7005 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
7006 
7007 /* Register: RTC_TASKS_TRIGOVRFLW */
7008 /* Description: Set COUNTER to 0xFFFFF0 */
7009 
7010 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
7011 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
7012 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
7013 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
7014 
7015 /* Register: RTC_EVENTS_TICK */
7016 /* Description: Event on COUNTER increment */
7017 
7018 /* Bit 0 : Event on COUNTER increment */
7019 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
7020 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
7021 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
7022 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
7023 
7024 /* Register: RTC_EVENTS_OVRFLW */
7025 /* Description: Event on COUNTER overflow */
7026 
7027 /* Bit 0 : Event on COUNTER overflow */
7028 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
7029 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
7030 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
7031 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
7032 
7033 /* Register: RTC_EVENTS_COMPARE */
7034 /* Description: Description collection: Compare event on CC[n] match */
7035 
7036 /* Bit 0 : Compare event on CC[n] match */
7037 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
7038 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
7039 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
7040 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
7041 
7042 /* Register: RTC_INTENSET */
7043 /* Description: Enable interrupt */
7044 
7045 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
7046 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7047 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7048 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7049 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7050 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
7051 
7052 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
7053 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7054 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7055 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7056 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7057 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
7058 
7059 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
7060 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7061 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7062 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7063 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7064 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
7065 
7066 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
7067 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7068 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7069 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7070 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7071 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
7072 
7073 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
7074 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7075 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7076 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7077 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7078 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
7079 
7080 /* Bit 0 : Write '1' to enable interrupt for event TICK */
7081 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
7082 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
7083 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
7084 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
7085 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
7086 
7087 /* Register: RTC_INTENCLR */
7088 /* Description: Disable interrupt */
7089 
7090 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
7091 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7092 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7093 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7094 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7095 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
7096 
7097 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
7098 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7099 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7100 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7101 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7102 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
7103 
7104 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
7105 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7106 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7107 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7108 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7109 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
7110 
7111 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
7112 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7113 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7114 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7115 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7116 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
7117 
7118 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
7119 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7120 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7121 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7122 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7123 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
7124 
7125 /* Bit 0 : Write '1' to disable interrupt for event TICK */
7126 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
7127 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
7128 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
7129 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7130 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
7131 
7132 /* Register: RTC_EVTEN */
7133 /* Description: Enable or disable event routing */
7134 
7135 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
7136 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7137 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7138 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
7139 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
7140 
7141 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
7142 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7143 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7144 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
7145 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
7146 
7147 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
7148 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7149 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7150 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
7151 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
7152 
7153 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
7154 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7155 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7156 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
7157 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
7158 
7159 /* Bit 1 : Enable or disable event routing for event OVRFLW */
7160 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7161 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7162 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
7163 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
7164 
7165 /* Bit 0 : Enable or disable event routing for event TICK */
7166 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
7167 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
7168 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
7169 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
7170 
7171 /* Register: RTC_EVTENSET */
7172 /* Description: Enable event routing */
7173 
7174 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
7175 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7176 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7177 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7178 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7179 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
7180 
7181 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
7182 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7183 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7184 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7185 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7186 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
7187 
7188 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
7189 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7190 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7191 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7192 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7193 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
7194 
7195 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
7196 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7197 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7198 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7199 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7200 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
7201 
7202 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
7203 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7204 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7205 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7206 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7207 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
7208 
7209 /* Bit 0 : Write '1' to enable event routing for event TICK */
7210 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
7211 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
7212 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
7213 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
7214 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
7215 
7216 /* Register: RTC_EVTENCLR */
7217 /* Description: Disable event routing */
7218 
7219 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
7220 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7221 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7222 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7223 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7224 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
7225 
7226 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
7227 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7228 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7229 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7230 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7231 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
7232 
7233 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
7234 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7235 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7236 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7237 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7238 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
7239 
7240 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
7241 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7242 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7243 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7244 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7245 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
7246 
7247 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
7248 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7249 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7250 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7251 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7252 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
7253 
7254 /* Bit 0 : Write '1' to disable event routing for event TICK */
7255 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
7256 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
7257 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
7258 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7259 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
7260 
7261 /* Register: RTC_COUNTER */
7262 /* Description: Current COUNTER value */
7263 
7264 /* Bits 23..0 : Counter value */
7265 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
7266 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
7267 
7268 /* Register: RTC_PRESCALER */
7269 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
7270 
7271 /* Bits 11..0 : Prescaler value */
7272 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
7273 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
7274 
7275 /* Register: RTC_CC */
7276 /* Description: Description collection: Compare register n */
7277 
7278 /* Bits 23..0 : Compare value */
7279 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
7280 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
7281 
7282 
7283 /* Peripheral: SPI */
7284 /* Description: Serial Peripheral Interface 0 */
7285 
7286 /* Register: SPI_EVENTS_READY */
7287 /* Description: TXD byte sent and RXD byte received */
7288 
7289 /* Bit 0 : TXD byte sent and RXD byte received */
7290 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
7291 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
7292 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
7293 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
7294 
7295 /* Register: SPI_INTENSET */
7296 /* Description: Enable interrupt */
7297 
7298 /* Bit 2 : Write '1' to enable interrupt for event READY */
7299 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
7300 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
7301 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
7302 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
7303 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
7304 
7305 /* Register: SPI_INTENCLR */
7306 /* Description: Disable interrupt */
7307 
7308 /* Bit 2 : Write '1' to disable interrupt for event READY */
7309 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
7310 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
7311 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
7312 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
7313 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
7314 
7315 /* Register: SPI_ENABLE */
7316 /* Description: Enable SPI */
7317 
7318 /* Bits 3..0 : Enable or disable SPI */
7319 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7320 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7321 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
7322 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
7323 
7324 /* Register: SPI_PSEL_SCK */
7325 /* Description: Pin select for SCK */
7326 
7327 /* Bit 31 : Connection */
7328 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7329 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7330 #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7331 #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7332 
7333 /* Bits 4..0 : Pin number */
7334 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7335 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7336 
7337 /* Register: SPI_PSEL_MOSI */
7338 /* Description: Pin select for MOSI signal */
7339 
7340 /* Bit 31 : Connection */
7341 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7342 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7343 #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7344 #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7345 
7346 /* Bits 4..0 : Pin number */
7347 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7348 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7349 
7350 /* Register: SPI_PSEL_MISO */
7351 /* Description: Pin select for MISO signal */
7352 
7353 /* Bit 31 : Connection */
7354 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7355 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7356 #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7357 #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7358 
7359 /* Bits 4..0 : Pin number */
7360 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7361 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7362 
7363 /* Register: SPI_RXD */
7364 /* Description: RXD register */
7365 
7366 /* Bits 7..0 : RX data received. Double buffered */
7367 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
7368 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
7369 
7370 /* Register: SPI_TXD */
7371 /* Description: TXD register */
7372 
7373 /* Bits 7..0 : TX data to send. Double buffered. */
7374 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
7375 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
7376 
7377 /* Register: SPI_FREQUENCY */
7378 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7379 
7380 /* Bits 31..0 : SPI master data rate */
7381 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7382 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7383 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
7384 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
7385 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
7386 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7387 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7388 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7389 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7390 
7391 /* Register: SPI_CONFIG */
7392 /* Description: Configuration register */
7393 
7394 /* Bit 2 : Serial clock (SCK) polarity */
7395 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7396 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7397 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7398 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7399 
7400 /* Bit 1 : Serial clock (SCK) phase */
7401 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7402 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7403 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7404 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7405 
7406 /* Bit 0 : Bit order */
7407 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7408 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7409 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7410 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7411 
7412 
7413 /* Peripheral: SPIM */
7414 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
7415 
7416 /* Register: SPIM_TASKS_START */
7417 /* Description: Start SPI transaction */
7418 
7419 /* Bit 0 : Start SPI transaction */
7420 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
7421 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
7422 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
7423 
7424 /* Register: SPIM_TASKS_STOP */
7425 /* Description: Stop SPI transaction */
7426 
7427 /* Bit 0 : Stop SPI transaction */
7428 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
7429 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
7430 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
7431 
7432 /* Register: SPIM_TASKS_SUSPEND */
7433 /* Description: Suspend SPI transaction */
7434 
7435 /* Bit 0 : Suspend SPI transaction */
7436 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
7437 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
7438 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
7439 
7440 /* Register: SPIM_TASKS_RESUME */
7441 /* Description: Resume SPI transaction */
7442 
7443 /* Bit 0 : Resume SPI transaction */
7444 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
7445 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
7446 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
7447 
7448 /* Register: SPIM_EVENTS_STOPPED */
7449 /* Description: SPI transaction has stopped */
7450 
7451 /* Bit 0 : SPI transaction has stopped */
7452 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
7453 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
7454 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
7455 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
7456 
7457 /* Register: SPIM_EVENTS_ENDRX */
7458 /* Description: End of RXD buffer reached */
7459 
7460 /* Bit 0 : End of RXD buffer reached */
7461 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
7462 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
7463 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
7464 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
7465 
7466 /* Register: SPIM_EVENTS_END */
7467 /* Description: End of RXD buffer and TXD buffer reached */
7468 
7469 /* Bit 0 : End of RXD buffer and TXD buffer reached */
7470 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7471 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7472 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7473 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7474 
7475 /* Register: SPIM_EVENTS_ENDTX */
7476 /* Description: End of TXD buffer reached */
7477 
7478 /* Bit 0 : End of TXD buffer reached */
7479 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
7480 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
7481 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
7482 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
7483 
7484 /* Register: SPIM_EVENTS_STARTED */
7485 /* Description: Transaction started */
7486 
7487 /* Bit 0 : Transaction started */
7488 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
7489 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
7490 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
7491 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
7492 
7493 /* Register: SPIM_SHORTS */
7494 /* Description: Shortcuts between local events and tasks */
7495 
7496 /* Bit 17 : Shortcut between event END and task START */
7497 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
7498 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
7499 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
7500 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
7501 
7502 /* Register: SPIM_INTENSET */
7503 /* Description: Enable interrupt */
7504 
7505 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
7506 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
7507 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
7508 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7509 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7510 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
7511 
7512 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
7513 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
7514 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
7515 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7516 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7517 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
7518 
7519 /* Bit 6 : Write '1' to enable interrupt for event END */
7520 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
7521 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
7522 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7523 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7524 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
7525 
7526 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7527 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7528 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7529 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7530 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7531 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7532 
7533 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7534 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7535 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7536 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7537 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7538 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7539 
7540 /* Register: SPIM_INTENCLR */
7541 /* Description: Disable interrupt */
7542 
7543 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
7544 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
7545 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
7546 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7547 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7548 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7549 
7550 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
7551 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
7552 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
7553 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7554 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7555 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7556 
7557 /* Bit 6 : Write '1' to disable interrupt for event END */
7558 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
7559 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7560 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7561 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7562 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7563 
7564 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7565 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7566 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7567 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7568 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7569 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7570 
7571 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7572 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7573 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7574 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7575 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7576 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7577 
7578 /* Register: SPIM_ENABLE */
7579 /* Description: Enable SPIM */
7580 
7581 /* Bits 3..0 : Enable or disable SPIM */
7582 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7583 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7584 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
7585 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
7586 
7587 /* Register: SPIM_PSEL_SCK */
7588 /* Description: Pin select for SCK */
7589 
7590 /* Bit 31 : Connection */
7591 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7592 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7593 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7594 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7595 
7596 /* Bits 4..0 : Pin number */
7597 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7598 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7599 
7600 /* Register: SPIM_PSEL_MOSI */
7601 /* Description: Pin select for MOSI signal */
7602 
7603 /* Bit 31 : Connection */
7604 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7605 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7606 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7607 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7608 
7609 /* Bits 4..0 : Pin number */
7610 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7611 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7612 
7613 /* Register: SPIM_PSEL_MISO */
7614 /* Description: Pin select for MISO signal */
7615 
7616 /* Bit 31 : Connection */
7617 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7618 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7619 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7620 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7621 
7622 /* Bits 4..0 : Pin number */
7623 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7624 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7625 
7626 /* Register: SPIM_FREQUENCY */
7627 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7628 
7629 /* Bits 31..0 : SPI master data rate */
7630 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7631 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7632 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
7633 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
7634 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
7635 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7636 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7637 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7638 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7639 
7640 /* Register: SPIM_RXD_PTR */
7641 /* Description: Data pointer */
7642 
7643 /* Bits 31..0 : Data pointer */
7644 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7645 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7646 
7647 /* Register: SPIM_RXD_MAXCNT */
7648 /* Description: Maximum number of bytes in receive buffer */
7649 
7650 /* Bits 14..0 : Maximum number of bytes in receive buffer */
7651 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7652 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7653 
7654 /* Register: SPIM_RXD_AMOUNT */
7655 /* Description: Number of bytes transferred in the last transaction */
7656 
7657 /* Bits 14..0 : Number of bytes transferred in the last transaction */
7658 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7659 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7660 
7661 /* Register: SPIM_RXD_LIST */
7662 /* Description: EasyDMA list type */
7663 
7664 /* Bits 1..0 : List type */
7665 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7666 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7667 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7668 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7669 
7670 /* Register: SPIM_TXD_PTR */
7671 /* Description: Data pointer */
7672 
7673 /* Bits 31..0 : Data pointer */
7674 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7675 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7676 
7677 /* Register: SPIM_TXD_MAXCNT */
7678 /* Description: Number of bytes in transmit buffer */
7679 
7680 /* Bits 14..0 : Maximum number of bytes in transmit buffer */
7681 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7682 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7683 
7684 /* Register: SPIM_TXD_AMOUNT */
7685 /* Description: Number of bytes transferred in the last transaction */
7686 
7687 /* Bits 14..0 : Number of bytes transferred in the last transaction */
7688 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7689 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7690 
7691 /* Register: SPIM_TXD_LIST */
7692 /* Description: EasyDMA list type */
7693 
7694 /* Bits 1..0 : List type */
7695 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7696 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7697 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7698 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7699 
7700 /* Register: SPIM_CONFIG */
7701 /* Description: Configuration register */
7702 
7703 /* Bit 2 : Serial clock (SCK) polarity */
7704 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7705 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7706 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7707 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7708 
7709 /* Bit 1 : Serial clock (SCK) phase */
7710 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7711 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7712 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7713 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7714 
7715 /* Bit 0 : Bit order */
7716 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7717 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7718 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7719 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7720 
7721 /* Register: SPIM_ORC */
7722 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
7723 
7724 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
7725 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
7726 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
7727 
7728 
7729 /* Peripheral: SPIS */
7730 /* Description: SPI Slave 0 */
7731 
7732 /* Register: SPIS_TASKS_ACQUIRE */
7733 /* Description: Acquire SPI semaphore */
7734 
7735 /* Bit 0 : Acquire SPI semaphore */
7736 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
7737 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
7738 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
7739 
7740 /* Register: SPIS_TASKS_RELEASE */
7741 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
7742 
7743 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
7744 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
7745 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
7746 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
7747 
7748 /* Register: SPIS_EVENTS_END */
7749 /* Description: Granted transaction completed */
7750 
7751 /* Bit 0 : Granted transaction completed */
7752 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7753 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7754 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7755 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7756 
7757 /* Register: SPIS_EVENTS_ENDRX */
7758 /* Description: End of RXD buffer reached */
7759 
7760 /* Bit 0 : End of RXD buffer reached */
7761 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
7762 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
7763 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
7764 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
7765 
7766 /* Register: SPIS_EVENTS_ACQUIRED */
7767 /* Description: Semaphore acquired */
7768 
7769 /* Bit 0 : Semaphore acquired */
7770 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
7771 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
7772 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
7773 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
7774 
7775 /* Register: SPIS_SHORTS */
7776 /* Description: Shortcuts between local events and tasks */
7777 
7778 /* Bit 2 : Shortcut between event END and task ACQUIRE */
7779 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
7780 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
7781 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
7782 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
7783 
7784 /* Register: SPIS_INTENSET */
7785 /* Description: Enable interrupt */
7786 
7787 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
7788 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7789 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7790 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7791 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7792 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
7793 
7794 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7795 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7796 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7797 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7798 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7799 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7800 
7801 /* Bit 1 : Write '1' to enable interrupt for event END */
7802 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
7803 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
7804 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7805 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7806 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
7807 
7808 /* Register: SPIS_INTENCLR */
7809 /* Description: Disable interrupt */
7810 
7811 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
7812 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7813 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7814 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7815 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7816 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
7817 
7818 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7819 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7820 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7821 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7822 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7823 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7824 
7825 /* Bit 1 : Write '1' to disable interrupt for event END */
7826 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
7827 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7828 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7829 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7830 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
7831 
7832 /* Register: SPIS_SEMSTAT */
7833 /* Description: Semaphore status register */
7834 
7835 /* Bits 1..0 : Semaphore status */
7836 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
7837 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
7838 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
7839 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
7840 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
7841 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
7842 
7843 /* Register: SPIS_STATUS */
7844 /* Description: Status from last transaction */
7845 
7846 /* Bit 1 : RX buffer overflow detected, and prevented */
7847 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
7848 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
7849 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
7850 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
7851 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
7852 
7853 /* Bit 0 : TX buffer over-read detected, and prevented */
7854 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
7855 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
7856 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
7857 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
7858 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
7859 
7860 /* Register: SPIS_ENABLE */
7861 /* Description: Enable SPI slave */
7862 
7863 /* Bits 3..0 : Enable or disable SPI slave */
7864 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7865 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7866 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
7867 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
7868 
7869 /* Register: SPIS_PSEL_SCK */
7870 /* Description: Pin select for SCK */
7871 
7872 /* Bit 31 : Connection */
7873 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7874 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7875 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7876 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7877 
7878 /* Bits 4..0 : Pin number */
7879 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7880 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7881 
7882 /* Register: SPIS_PSEL_MISO */
7883 /* Description: Pin select for MISO signal */
7884 
7885 /* Bit 31 : Connection */
7886 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7887 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7888 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7889 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7890 
7891 /* Bits 4..0 : Pin number */
7892 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7893 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7894 
7895 /* Register: SPIS_PSEL_MOSI */
7896 /* Description: Pin select for MOSI signal */
7897 
7898 /* Bit 31 : Connection */
7899 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7900 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7901 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7902 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7903 
7904 /* Bits 4..0 : Pin number */
7905 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7906 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7907 
7908 /* Register: SPIS_PSEL_CSN */
7909 /* Description: Pin select for CSN signal */
7910 
7911 /* Bit 31 : Connection */
7912 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7913 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7914 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
7915 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7916 
7917 /* Bits 4..0 : Pin number */
7918 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
7919 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
7920 
7921 /* Register: SPIS_RXD_PTR */
7922 /* Description: RXD data pointer */
7923 
7924 /* Bits 31..0 : RXD data pointer */
7925 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7926 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7927 
7928 /* Register: SPIS_RXD_MAXCNT */
7929 /* Description: Maximum number of bytes in receive buffer */
7930 
7931 /* Bits 14..0 : Maximum number of bytes in receive buffer */
7932 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7933 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7934 
7935 /* Register: SPIS_RXD_AMOUNT */
7936 /* Description: Number of bytes received in last granted transaction */
7937 
7938 /* Bits 14..0 : Number of bytes received in the last granted transaction */
7939 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7940 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7941 
7942 /* Register: SPIS_RXD_LIST */
7943 /* Description: EasyDMA list type */
7944 
7945 /* Bits 1..0 : List type */
7946 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7947 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7948 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7949 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7950 
7951 /* Register: SPIS_TXD_PTR */
7952 /* Description: TXD data pointer */
7953 
7954 /* Bits 31..0 : TXD data pointer */
7955 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7956 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7957 
7958 /* Register: SPIS_TXD_MAXCNT */
7959 /* Description: Maximum number of bytes in transmit buffer */
7960 
7961 /* Bits 14..0 : Maximum number of bytes in transmit buffer */
7962 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7963 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7964 
7965 /* Register: SPIS_TXD_AMOUNT */
7966 /* Description: Number of bytes transmitted in last granted transaction */
7967 
7968 /* Bits 14..0 : Number of bytes transmitted in last granted transaction */
7969 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7970 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7971 
7972 /* Register: SPIS_TXD_LIST */
7973 /* Description: EasyDMA list type */
7974 
7975 /* Bits 1..0 : List type */
7976 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7977 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7978 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7979 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7980 
7981 /* Register: SPIS_CONFIG */
7982 /* Description: Configuration register */
7983 
7984 /* Bit 2 : Serial clock (SCK) polarity */
7985 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7986 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7987 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7988 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7989 
7990 /* Bit 1 : Serial clock (SCK) phase */
7991 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7992 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7993 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7994 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7995 
7996 /* Bit 0 : Bit order */
7997 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7998 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7999 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
8000 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
8001 
8002 /* Register: SPIS_DEF */
8003 /* Description: Default character. Character clocked out in case of an ignored transaction. */
8004 
8005 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
8006 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
8007 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
8008 
8009 /* Register: SPIS_ORC */
8010 /* Description: Over-read character */
8011 
8012 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
8013 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
8014 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
8015 
8016 
8017 /* Peripheral: TEMP */
8018 /* Description: Temperature Sensor */
8019 
8020 /* Register: TEMP_TASKS_START */
8021 /* Description: Start temperature measurement */
8022 
8023 /* Bit 0 : Start temperature measurement */
8024 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8025 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8026 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8027 
8028 /* Register: TEMP_TASKS_STOP */
8029 /* Description: Stop temperature measurement */
8030 
8031 /* Bit 0 : Stop temperature measurement */
8032 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8033 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8034 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8035 
8036 /* Register: TEMP_EVENTS_DATARDY */
8037 /* Description: Temperature measurement complete, data ready */
8038 
8039 /* Bit 0 : Temperature measurement complete, data ready */
8040 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
8041 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
8042 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
8043 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
8044 
8045 /* Register: TEMP_INTENSET */
8046 /* Description: Enable interrupt */
8047 
8048 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
8049 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
8050 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
8051 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8052 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8053 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
8054 
8055 /* Register: TEMP_INTENCLR */
8056 /* Description: Disable interrupt */
8057 
8058 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
8059 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
8060 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
8061 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8062 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8063 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
8064 
8065 /* Register: TEMP_TEMP */
8066 /* Description: Temperature in degC (0.25deg steps) */
8067 
8068 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
8069 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
8070 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
8071 
8072 /* Register: TEMP_A0 */
8073 /* Description: Slope of first piecewise linear function */
8074 
8075 /* Bits 11..0 : Slope of first piecewise linear function */
8076 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
8077 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
8078 
8079 /* Register: TEMP_A1 */
8080 /* Description: Slope of second piecewise linear function */
8081 
8082 /* Bits 11..0 : Slope of second piecewise linear function */
8083 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
8084 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
8085 
8086 /* Register: TEMP_A2 */
8087 /* Description: Slope of third piecewise linear function */
8088 
8089 /* Bits 11..0 : Slope of third piecewise linear function */
8090 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
8091 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
8092 
8093 /* Register: TEMP_A3 */
8094 /* Description: Slope of fourth piecewise linear function */
8095 
8096 /* Bits 11..0 : Slope of fourth piecewise linear function */
8097 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
8098 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
8099 
8100 /* Register: TEMP_A4 */
8101 /* Description: Slope of fifth piecewise linear function */
8102 
8103 /* Bits 11..0 : Slope of fifth piecewise linear function */
8104 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
8105 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
8106 
8107 /* Register: TEMP_A5 */
8108 /* Description: Slope of sixth piecewise linear function */
8109 
8110 /* Bits 11..0 : Slope of sixth piecewise linear function */
8111 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
8112 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
8113 
8114 /* Register: TEMP_B0 */
8115 /* Description: y-intercept of first piecewise linear function */
8116 
8117 /* Bits 13..0 : y-intercept of first piecewise linear function */
8118 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
8119 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
8120 
8121 /* Register: TEMP_B1 */
8122 /* Description: y-intercept of second piecewise linear function */
8123 
8124 /* Bits 13..0 : y-intercept of second piecewise linear function */
8125 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
8126 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
8127 
8128 /* Register: TEMP_B2 */
8129 /* Description: y-intercept of third piecewise linear function */
8130 
8131 /* Bits 13..0 : y-intercept of third piecewise linear function */
8132 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
8133 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
8134 
8135 /* Register: TEMP_B3 */
8136 /* Description: y-intercept of fourth piecewise linear function */
8137 
8138 /* Bits 13..0 : y-intercept of fourth piecewise linear function */
8139 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
8140 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
8141 
8142 /* Register: TEMP_B4 */
8143 /* Description: y-intercept of fifth piecewise linear function */
8144 
8145 /* Bits 13..0 : y-intercept of fifth piecewise linear function */
8146 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
8147 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
8148 
8149 /* Register: TEMP_B5 */
8150 /* Description: y-intercept of sixth piecewise linear function */
8151 
8152 /* Bits 13..0 : y-intercept of sixth piecewise linear function */
8153 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
8154 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
8155 
8156 /* Register: TEMP_T0 */
8157 /* Description: End point of first piecewise linear function */
8158 
8159 /* Bits 7..0 : End point of first piecewise linear function */
8160 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
8161 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
8162 
8163 /* Register: TEMP_T1 */
8164 /* Description: End point of second piecewise linear function */
8165 
8166 /* Bits 7..0 : End point of second piecewise linear function */
8167 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
8168 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
8169 
8170 /* Register: TEMP_T2 */
8171 /* Description: End point of third piecewise linear function */
8172 
8173 /* Bits 7..0 : End point of third piecewise linear function */
8174 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
8175 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
8176 
8177 /* Register: TEMP_T3 */
8178 /* Description: End point of fourth piecewise linear function */
8179 
8180 /* Bits 7..0 : End point of fourth piecewise linear function */
8181 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
8182 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
8183 
8184 /* Register: TEMP_T4 */
8185 /* Description: End point of fifth piecewise linear function */
8186 
8187 /* Bits 7..0 : End point of fifth piecewise linear function */
8188 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
8189 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
8190 
8191 
8192 /* Peripheral: TIMER */
8193 /* Description: Timer/Counter 0 */
8194 
8195 /* Register: TIMER_TASKS_START */
8196 /* Description: Start Timer */
8197 
8198 /* Bit 0 : Start Timer */
8199 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8200 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8201 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8202 
8203 /* Register: TIMER_TASKS_STOP */
8204 /* Description: Stop Timer */
8205 
8206 /* Bit 0 : Stop Timer */
8207 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8208 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8209 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8210 
8211 /* Register: TIMER_TASKS_COUNT */
8212 /* Description: Increment Timer (Counter mode only) */
8213 
8214 /* Bit 0 : Increment Timer (Counter mode only) */
8215 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
8216 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
8217 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
8218 
8219 /* Register: TIMER_TASKS_CLEAR */
8220 /* Description: Clear time */
8221 
8222 /* Bit 0 : Clear time */
8223 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
8224 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
8225 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8226 
8227 /* Register: TIMER_TASKS_SHUTDOWN */
8228 /* Description: Deprecated register - Shut down timer */
8229 
8230 /* Bit 0 : Deprecated field -  Shut down timer */
8231 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
8232 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
8233 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
8234 
8235 /* Register: TIMER_TASKS_CAPTURE */
8236 /* Description: Description collection: Capture Timer value to CC[n] register */
8237 
8238 /* Bit 0 : Capture Timer value to CC[n] register */
8239 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
8240 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
8241 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8242 
8243 /* Register: TIMER_EVENTS_COMPARE */
8244 /* Description: Description collection: Compare event on CC[n] match */
8245 
8246 /* Bit 0 : Compare event on CC[n] match */
8247 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
8248 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
8249 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
8250 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8251 
8252 /* Register: TIMER_SHORTS */
8253 /* Description: Shortcuts between local events and tasks */
8254 
8255 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
8256 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
8257 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
8258 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8259 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8260 
8261 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
8262 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
8263 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
8264 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8265 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8266 
8267 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
8268 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
8269 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
8270 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8271 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8272 
8273 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
8274 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
8275 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
8276 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8277 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8278 
8279 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
8280 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
8281 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
8282 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8283 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8284 
8285 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
8286 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
8287 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
8288 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8289 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8290 
8291 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
8292 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
8293 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
8294 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8295 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8296 
8297 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
8298 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
8299 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
8300 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8301 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8302 
8303 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
8304 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
8305 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
8306 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8307 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8308 
8309 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8310 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8311 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
8312 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8313 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8314 
8315 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8316 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8317 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
8318 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8319 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8320 
8321 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
8322 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
8323 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
8324 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8325 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8326 
8327 /* Register: TIMER_INTENSET */
8328 /* Description: Enable interrupt */
8329 
8330 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8331 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8332 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8333 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8334 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8335 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8336 
8337 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8338 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8339 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8340 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8341 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8342 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8343 
8344 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8345 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8346 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8347 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8348 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8349 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8350 
8351 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8352 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8353 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8354 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8355 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8356 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8357 
8358 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8359 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8360 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8361 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8362 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8363 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8364 
8365 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8366 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8367 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8368 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8369 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8370 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8371 
8372 /* Register: TIMER_INTENCLR */
8373 /* Description: Disable interrupt */
8374 
8375 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
8376 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8377 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8378 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8379 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8380 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8381 
8382 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
8383 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8384 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8385 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8386 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8387 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8388 
8389 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8390 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8391 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8392 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8393 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8394 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8395 
8396 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8397 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8398 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8399 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8400 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8401 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8402 
8403 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8404 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8405 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8406 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8407 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8408 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8409 
8410 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8411 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8412 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8413 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8414 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8415 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8416 
8417 /* Register: TIMER_MODE */
8418 /* Description: Timer mode selection */
8419 
8420 /* Bits 1..0 : Timer mode */
8421 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
8422 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
8423 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
8424 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
8425 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
8426 
8427 /* Register: TIMER_BITMODE */
8428 /* Description: Configure the number of bits used by the TIMER */
8429 
8430 /* Bits 1..0 : Timer bit width */
8431 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
8432 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
8433 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
8434 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
8435 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
8436 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
8437 
8438 /* Register: TIMER_PRESCALER */
8439 /* Description: Timer prescaler register */
8440 
8441 /* Bits 3..0 : Prescaler value */
8442 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8443 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8444 
8445 /* Register: TIMER_CC */
8446 /* Description: Description collection: Capture/Compare register n */
8447 
8448 /* Bits 31..0 : Capture/Compare value */
8449 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
8450 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
8451 
8452 
8453 /* Peripheral: TWI */
8454 /* Description: I2C compatible Two-Wire Interface 0 */
8455 
8456 /* Register: TWI_TASKS_STARTRX */
8457 /* Description: Start TWI receive sequence */
8458 
8459 /* Bit 0 : Start TWI receive sequence */
8460 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
8461 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
8462 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
8463 
8464 /* Register: TWI_TASKS_STARTTX */
8465 /* Description: Start TWI transmit sequence */
8466 
8467 /* Bit 0 : Start TWI transmit sequence */
8468 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
8469 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
8470 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
8471 
8472 /* Register: TWI_TASKS_STOP */
8473 /* Description: Stop TWI transaction */
8474 
8475 /* Bit 0 : Stop TWI transaction */
8476 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8477 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8478 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8479 
8480 /* Register: TWI_TASKS_SUSPEND */
8481 /* Description: Suspend TWI transaction */
8482 
8483 /* Bit 0 : Suspend TWI transaction */
8484 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8485 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8486 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8487 
8488 /* Register: TWI_TASKS_RESUME */
8489 /* Description: Resume TWI transaction */
8490 
8491 /* Bit 0 : Resume TWI transaction */
8492 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8493 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8494 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8495 
8496 /* Register: TWI_EVENTS_STOPPED */
8497 /* Description: TWI stopped */
8498 
8499 /* Bit 0 : TWI stopped */
8500 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8501 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8502 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8503 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8504 
8505 /* Register: TWI_EVENTS_RXDREADY */
8506 /* Description: TWI RXD byte received */
8507 
8508 /* Bit 0 : TWI RXD byte received */
8509 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
8510 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
8511 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
8512 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
8513 
8514 /* Register: TWI_EVENTS_TXDSENT */
8515 /* Description: TWI TXD byte sent */
8516 
8517 /* Bit 0 : TWI TXD byte sent */
8518 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
8519 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
8520 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
8521 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
8522 
8523 /* Register: TWI_EVENTS_ERROR */
8524 /* Description: TWI error */
8525 
8526 /* Bit 0 : TWI error */
8527 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
8528 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
8529 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
8530 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
8531 
8532 /* Register: TWI_EVENTS_BB */
8533 /* Description: TWI byte boundary, generated before each byte that is sent or received */
8534 
8535 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
8536 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
8537 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
8538 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
8539 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
8540 
8541 /* Register: TWI_EVENTS_SUSPENDED */
8542 /* Description: TWI entered the suspended state */
8543 
8544 /* Bit 0 : TWI entered the suspended state */
8545 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
8546 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
8547 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
8548 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
8549 
8550 /* Register: TWI_SHORTS */
8551 /* Description: Shortcuts between local events and tasks */
8552 
8553 /* Bit 1 : Shortcut between event BB and task STOP */
8554 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
8555 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
8556 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
8557 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
8558 
8559 /* Bit 0 : Shortcut between event BB and task SUSPEND */
8560 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
8561 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
8562 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8563 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8564 
8565 /* Register: TWI_INTENSET */
8566 /* Description: Enable interrupt */
8567 
8568 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
8569 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
8570 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
8571 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8572 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8573 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
8574 
8575 /* Bit 14 : Write '1' to enable interrupt for event BB */
8576 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
8577 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
8578 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
8579 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
8580 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
8581 
8582 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
8583 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
8584 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
8585 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
8586 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
8587 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
8588 
8589 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
8590 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
8591 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
8592 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
8593 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
8594 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
8595 
8596 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
8597 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
8598 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
8599 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
8600 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
8601 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
8602 
8603 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8604 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8605 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8606 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8607 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8608 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8609 
8610 /* Register: TWI_INTENCLR */
8611 /* Description: Disable interrupt */
8612 
8613 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
8614 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
8615 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
8616 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8617 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8618 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
8619 
8620 /* Bit 14 : Write '1' to disable interrupt for event BB */
8621 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
8622 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
8623 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
8624 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
8625 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
8626 
8627 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
8628 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
8629 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
8630 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
8631 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
8632 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
8633 
8634 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
8635 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
8636 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
8637 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
8638 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
8639 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
8640 
8641 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
8642 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
8643 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
8644 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
8645 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
8646 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
8647 
8648 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8649 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8650 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8651 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8652 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8653 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8654 
8655 /* Register: TWI_ERRORSRC */
8656 /* Description: Error source */
8657 
8658 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
8659 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
8660 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
8661 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
8662 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
8663 
8664 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
8665 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
8666 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
8667 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
8668 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
8669 
8670 /* Bit 0 : Overrun error */
8671 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
8672 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
8673 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
8674 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
8675 
8676 /* Register: TWI_ENABLE */
8677 /* Description: Enable TWI */
8678 
8679 /* Bits 3..0 : Enable or disable TWI */
8680 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8681 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8682 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
8683 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
8684 
8685 /* Register: TWI_PSEL_SCL */
8686 /* Description: Pin select for SCL */
8687 
8688 /* Bit 31 : Connection */
8689 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8690 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8691 #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
8692 #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
8693 
8694 /* Bits 4..0 : Pin number */
8695 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
8696 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
8697 
8698 /* Register: TWI_PSEL_SDA */
8699 /* Description: Pin select for SDA */
8700 
8701 /* Bit 31 : Connection */
8702 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8703 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8704 #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
8705 #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
8706 
8707 /* Bits 4..0 : Pin number */
8708 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
8709 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
8710 
8711 /* Register: TWI_RXD */
8712 /* Description: RXD register */
8713 
8714 /* Bits 7..0 : RXD register */
8715 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
8716 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
8717 
8718 /* Register: TWI_TXD */
8719 /* Description: TXD register */
8720 
8721 /* Bits 7..0 : TXD register */
8722 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
8723 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
8724 
8725 /* Register: TWI_FREQUENCY */
8726 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
8727 
8728 /* Bits 31..0 : TWI master clock frequency */
8729 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
8730 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
8731 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
8732 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
8733 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
8734 
8735 /* Register: TWI_ADDRESS */
8736 /* Description: Address used in the TWI transfer */
8737 
8738 /* Bits 6..0 : Address used in the TWI transfer */
8739 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
8740 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
8741 
8742 
8743 /* Peripheral: TWIM */
8744 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
8745 
8746 /* Register: TWIM_TASKS_STARTRX */
8747 /* Description: Start TWI receive sequence */
8748 
8749 /* Bit 0 : Start TWI receive sequence */
8750 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
8751 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
8752 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
8753 
8754 /* Register: TWIM_TASKS_STARTTX */
8755 /* Description: Start TWI transmit sequence */
8756 
8757 /* Bit 0 : Start TWI transmit sequence */
8758 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
8759 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
8760 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
8761 
8762 /* Register: TWIM_TASKS_STOP */
8763 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8764 
8765 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8766 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8767 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8768 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8769 
8770 /* Register: TWIM_TASKS_SUSPEND */
8771 /* Description: Suspend TWI transaction */
8772 
8773 /* Bit 0 : Suspend TWI transaction */
8774 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8775 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8776 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8777 
8778 /* Register: TWIM_TASKS_RESUME */
8779 /* Description: Resume TWI transaction */
8780 
8781 /* Bit 0 : Resume TWI transaction */
8782 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8783 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8784 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8785 
8786 /* Register: TWIM_EVENTS_STOPPED */
8787 /* Description: TWI stopped */
8788 
8789 /* Bit 0 : TWI stopped */
8790 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8791 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8792 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8793 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8794 
8795 /* Register: TWIM_EVENTS_ERROR */
8796 /* Description: TWI error */
8797 
8798 /* Bit 0 : TWI error */
8799 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
8800 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
8801 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
8802 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
8803 
8804 /* Register: TWIM_EVENTS_SUSPENDED */
8805 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
8806 
8807 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
8808 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
8809 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
8810 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
8811 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
8812 
8813 /* Register: TWIM_EVENTS_RXSTARTED */
8814 /* Description: Receive sequence started */
8815 
8816 /* Bit 0 : Receive sequence started */
8817 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
8818 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
8819 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8820 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
8821 
8822 /* Register: TWIM_EVENTS_TXSTARTED */
8823 /* Description: Transmit sequence started */
8824 
8825 /* Bit 0 : Transmit sequence started */
8826 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
8827 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
8828 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8829 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
8830 
8831 /* Register: TWIM_EVENTS_LASTRX */
8832 /* Description: Byte boundary, starting to receive the last byte */
8833 
8834 /* Bit 0 : Byte boundary, starting to receive the last byte */
8835 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
8836 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
8837 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
8838 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
8839 
8840 /* Register: TWIM_EVENTS_LASTTX */
8841 /* Description: Byte boundary, starting to transmit the last byte */
8842 
8843 /* Bit 0 : Byte boundary, starting to transmit the last byte */
8844 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
8845 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
8846 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
8847 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
8848 
8849 /* Register: TWIM_SHORTS */
8850 /* Description: Shortcuts between local events and tasks */
8851 
8852 /* Bit 12 : Shortcut between event LASTRX and task STOP */
8853 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
8854 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
8855 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
8856 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
8857 
8858 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
8859 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
8860 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
8861 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8862 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8863 
8864 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
8865 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
8866 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
8867 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
8868 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
8869 
8870 /* Bit 9 : Shortcut between event LASTTX and task STOP */
8871 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
8872 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
8873 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
8874 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
8875 
8876 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
8877 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
8878 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
8879 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8880 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8881 
8882 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
8883 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
8884 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
8885 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
8886 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
8887 
8888 /* Register: TWIM_INTEN */
8889 /* Description: Enable or disable interrupt */
8890 
8891 /* Bit 24 : Enable or disable interrupt for event LASTTX */
8892 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
8893 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
8894 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
8895 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
8896 
8897 /* Bit 23 : Enable or disable interrupt for event LASTRX */
8898 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
8899 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
8900 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
8901 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
8902 
8903 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
8904 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
8905 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
8906 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
8907 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
8908 
8909 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
8910 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
8911 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
8912 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
8913 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
8914 
8915 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
8916 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
8917 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
8918 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
8919 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
8920 
8921 /* Bit 9 : Enable or disable interrupt for event ERROR */
8922 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
8923 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
8924 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
8925 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
8926 
8927 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8928 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8929 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8930 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8931 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8932 
8933 /* Register: TWIM_INTENSET */
8934 /* Description: Enable interrupt */
8935 
8936 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
8937 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
8938 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
8939 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8940 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8941 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
8942 
8943 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
8944 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
8945 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
8946 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8947 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8948 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
8949 
8950 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
8951 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
8952 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
8953 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8954 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8955 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
8956 
8957 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
8958 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
8959 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
8960 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8961 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8962 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
8963 
8964 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
8965 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
8966 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
8967 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8968 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8969 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
8970 
8971 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
8972 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
8973 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
8974 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
8975 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
8976 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
8977 
8978 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8979 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8980 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8981 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8982 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8983 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8984 
8985 /* Register: TWIM_INTENCLR */
8986 /* Description: Disable interrupt */
8987 
8988 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
8989 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
8990 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
8991 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8992 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8993 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
8994 
8995 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
8996 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
8997 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
8998 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8999 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9000 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9001 
9002 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9003 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9004 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9005 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9006 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9007 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9008 
9009 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9010 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9011 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9012 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9013 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9014 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9015 
9016 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9017 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9018 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9019 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9020 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9021 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9022 
9023 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9024 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9025 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9026 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9027 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9028 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9029 
9030 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9031 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9032 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9033 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9034 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9035 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9036 
9037 /* Register: TWIM_ERRORSRC */
9038 /* Description: Error source */
9039 
9040 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9041 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9042 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9043 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9044 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9045 
9046 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9047 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9048 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
9049 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
9050 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
9051 
9052 /* Bit 0 : Overrun error */
9053 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9054 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9055 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
9056 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
9057 
9058 /* Register: TWIM_ENABLE */
9059 /* Description: Enable TWIM */
9060 
9061 /* Bits 3..0 : Enable or disable TWIM */
9062 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9063 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9064 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9065 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9066 
9067 /* Register: TWIM_PSEL_SCL */
9068 /* Description: Pin select for SCL signal */
9069 
9070 /* Bit 31 : Connection */
9071 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9072 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9073 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9074 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9075 
9076 /* Bits 4..0 : Pin number */
9077 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9078 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9079 
9080 /* Register: TWIM_PSEL_SDA */
9081 /* Description: Pin select for SDA signal */
9082 
9083 /* Bit 31 : Connection */
9084 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9085 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9086 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9087 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9088 
9089 /* Bits 4..0 : Pin number */
9090 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9091 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9092 
9093 /* Register: TWIM_FREQUENCY */
9094 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9095 
9096 /* Bits 31..0 : TWI master clock frequency */
9097 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9098 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9099 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
9100 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9101 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
9102 
9103 /* Register: TWIM_RXD_PTR */
9104 /* Description: Data pointer */
9105 
9106 /* Bits 31..0 : Data pointer */
9107 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9108 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9109 
9110 /* Register: TWIM_RXD_MAXCNT */
9111 /* Description: Maximum number of bytes in receive buffer */
9112 
9113 /* Bits 14..0 : Maximum number of bytes in receive buffer */
9114 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9115 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9116 
9117 /* Register: TWIM_RXD_AMOUNT */
9118 /* Description: Number of bytes transferred in the last transaction */
9119 
9120 /* Bits 14..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9121 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9122 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9123 
9124 /* Register: TWIM_RXD_LIST */
9125 /* Description: EasyDMA list type */
9126 
9127 /* Bits 2..0 : List type */
9128 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9129 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9130 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9131 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9132 
9133 /* Register: TWIM_TXD_PTR */
9134 /* Description: Data pointer */
9135 
9136 /* Bits 31..0 : Data pointer */
9137 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9138 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9139 
9140 /* Register: TWIM_TXD_MAXCNT */
9141 /* Description: Maximum number of bytes in transmit buffer */
9142 
9143 /* Bits 14..0 : Maximum number of bytes in transmit buffer */
9144 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9145 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9146 
9147 /* Register: TWIM_TXD_AMOUNT */
9148 /* Description: Number of bytes transferred in the last transaction */
9149 
9150 /* Bits 14..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9151 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9152 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9153 
9154 /* Register: TWIM_TXD_LIST */
9155 /* Description: EasyDMA list type */
9156 
9157 /* Bits 2..0 : List type */
9158 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9159 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9160 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9161 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9162 
9163 /* Register: TWIM_ADDRESS */
9164 /* Description: Address used in the TWI transfer */
9165 
9166 /* Bits 6..0 : Address used in the TWI transfer */
9167 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9168 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9169 
9170 
9171 /* Peripheral: TWIS */
9172 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
9173 
9174 /* Register: TWIS_TASKS_STOP */
9175 /* Description: Stop TWI transaction */
9176 
9177 /* Bit 0 : Stop TWI transaction */
9178 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9179 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9180 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9181 
9182 /* Register: TWIS_TASKS_SUSPEND */
9183 /* Description: Suspend TWI transaction */
9184 
9185 /* Bit 0 : Suspend TWI transaction */
9186 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9187 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9188 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9189 
9190 /* Register: TWIS_TASKS_RESUME */
9191 /* Description: Resume TWI transaction */
9192 
9193 /* Bit 0 : Resume TWI transaction */
9194 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9195 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9196 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9197 
9198 /* Register: TWIS_TASKS_PREPARERX */
9199 /* Description: Prepare the TWI slave to respond to a write command */
9200 
9201 /* Bit 0 : Prepare the TWI slave to respond to a write command */
9202 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
9203 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
9204 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
9205 
9206 /* Register: TWIS_TASKS_PREPARETX */
9207 /* Description: Prepare the TWI slave to respond to a read command */
9208 
9209 /* Bit 0 : Prepare the TWI slave to respond to a read command */
9210 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
9211 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
9212 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
9213 
9214 /* Register: TWIS_EVENTS_STOPPED */
9215 /* Description: TWI stopped */
9216 
9217 /* Bit 0 : TWI stopped */
9218 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9219 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9220 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9221 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9222 
9223 /* Register: TWIS_EVENTS_ERROR */
9224 /* Description: TWI error */
9225 
9226 /* Bit 0 : TWI error */
9227 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9228 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9229 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9230 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9231 
9232 /* Register: TWIS_EVENTS_RXSTARTED */
9233 /* Description: Receive sequence started */
9234 
9235 /* Bit 0 : Receive sequence started */
9236 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9237 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9238 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9239 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9240 
9241 /* Register: TWIS_EVENTS_TXSTARTED */
9242 /* Description: Transmit sequence started */
9243 
9244 /* Bit 0 : Transmit sequence started */
9245 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9246 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9247 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9248 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9249 
9250 /* Register: TWIS_EVENTS_WRITE */
9251 /* Description: Write command received */
9252 
9253 /* Bit 0 : Write command received */
9254 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
9255 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
9256 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
9257 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
9258 
9259 /* Register: TWIS_EVENTS_READ */
9260 /* Description: Read command received */
9261 
9262 /* Bit 0 : Read command received */
9263 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
9264 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
9265 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
9266 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
9267 
9268 /* Register: TWIS_SHORTS */
9269 /* Description: Shortcuts between local events and tasks */
9270 
9271 /* Bit 14 : Shortcut between event READ and task SUSPEND */
9272 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
9273 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
9274 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9275 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9276 
9277 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
9278 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
9279 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
9280 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9281 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9282 
9283 /* Register: TWIS_INTEN */
9284 /* Description: Enable or disable interrupt */
9285 
9286 /* Bit 26 : Enable or disable interrupt for event READ */
9287 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9288 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9289 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9290 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9291 
9292 /* Bit 25 : Enable or disable interrupt for event WRITE */
9293 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9294 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
9295 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9296 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9297 
9298 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9299 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9300 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9301 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9302 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9303 
9304 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9305 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9306 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9307 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9308 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9309 
9310 /* Bit 9 : Enable or disable interrupt for event ERROR */
9311 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9312 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9313 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9314 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9315 
9316 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9317 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9318 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9319 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9320 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9321 
9322 /* Register: TWIS_INTENSET */
9323 /* Description: Enable interrupt */
9324 
9325 /* Bit 26 : Write '1' to enable interrupt for event READ */
9326 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9327 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9328 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9329 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9330 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9331 
9332 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9333 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9334 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
9335 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9336 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9337 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9338 
9339 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9340 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9341 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9342 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9343 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9344 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9345 
9346 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9347 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9348 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9349 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9350 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9351 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9352 
9353 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9354 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9355 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9356 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9357 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9358 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9359 
9360 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9361 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9362 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9363 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9364 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9365 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9366 
9367 /* Register: TWIS_INTENCLR */
9368 /* Description: Disable interrupt */
9369 
9370 /* Bit 26 : Write '1' to disable interrupt for event READ */
9371 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
9372 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
9373 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9374 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9375 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9376 
9377 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
9378 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9379 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
9380 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9381 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9382 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9383 
9384 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9385 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9386 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9387 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9388 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9389 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9390 
9391 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9392 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9393 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9394 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9395 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9396 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9397 
9398 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9399 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9400 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9401 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9402 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9403 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9404 
9405 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9406 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9407 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9408 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9409 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9410 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9411 
9412 /* Register: TWIS_ERRORSRC */
9413 /* Description: Error source */
9414 
9415 /* Bit 3 : TX buffer over-read detected, and prevented */
9416 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
9417 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
9418 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
9419 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
9420 
9421 /* Bit 2 : NACK sent after receiving a data byte */
9422 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9423 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9424 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9425 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9426 
9427 /* Bit 0 : RX buffer overflow detected, and prevented */
9428 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
9429 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
9430 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
9431 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
9432 
9433 /* Register: TWIS_MATCH */
9434 /* Description: Status register indicating which address had a match */
9435 
9436 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
9437 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
9438 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
9439 
9440 /* Register: TWIS_ENABLE */
9441 /* Description: Enable TWIS */
9442 
9443 /* Bits 3..0 : Enable or disable TWIS */
9444 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9445 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9446 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
9447 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
9448 
9449 /* Register: TWIS_PSEL_SCL */
9450 /* Description: Pin select for SCL signal */
9451 
9452 /* Bit 31 : Connection */
9453 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9454 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9455 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9456 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9457 
9458 /* Bits 4..0 : Pin number */
9459 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9460 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9461 
9462 /* Register: TWIS_PSEL_SDA */
9463 /* Description: Pin select for SDA signal */
9464 
9465 /* Bit 31 : Connection */
9466 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9467 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9468 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9469 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9470 
9471 /* Bits 4..0 : Pin number */
9472 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9473 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9474 
9475 /* Register: TWIS_RXD_PTR */
9476 /* Description: RXD Data pointer */
9477 
9478 /* Bits 31..0 : RXD Data pointer */
9479 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9480 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9481 
9482 /* Register: TWIS_RXD_MAXCNT */
9483 /* Description: Maximum number of bytes in RXD buffer */
9484 
9485 /* Bits 14..0 : Maximum number of bytes in RXD buffer */
9486 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9487 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9488 
9489 /* Register: TWIS_RXD_AMOUNT */
9490 /* Description: Number of bytes transferred in the last RXD transaction */
9491 
9492 /* Bits 14..0 : Number of bytes transferred in the last RXD transaction */
9493 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9494 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9495 
9496 /* Register: TWIS_RXD_LIST */
9497 /* Description: EasyDMA list type */
9498 
9499 /* Bits 1..0 : List type */
9500 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9501 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9502 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9503 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9504 
9505 /* Register: TWIS_TXD_PTR */
9506 /* Description: TXD Data pointer */
9507 
9508 /* Bits 31..0 : TXD Data pointer */
9509 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9510 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9511 
9512 /* Register: TWIS_TXD_MAXCNT */
9513 /* Description: Maximum number of bytes in TXD buffer */
9514 
9515 /* Bits 14..0 : Maximum number of bytes in TXD buffer */
9516 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9517 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9518 
9519 /* Register: TWIS_TXD_AMOUNT */
9520 /* Description: Number of bytes transferred in the last TXD transaction */
9521 
9522 /* Bits 14..0 : Number of bytes transferred in the last TXD transaction */
9523 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9524 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9525 
9526 /* Register: TWIS_TXD_LIST */
9527 /* Description: EasyDMA list type */
9528 
9529 /* Bits 1..0 : List type */
9530 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9531 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9532 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9533 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9534 
9535 /* Register: TWIS_ADDRESS */
9536 /* Description: Description collection: TWI slave address n */
9537 
9538 /* Bits 6..0 : TWI slave address */
9539 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9540 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9541 
9542 /* Register: TWIS_CONFIG */
9543 /* Description: Configuration register for the address match mechanism */
9544 
9545 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9546 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
9547 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
9548 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
9549 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9550 
9551 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9552 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
9553 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
9554 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
9555 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
9556 
9557 /* Register: TWIS_ORC */
9558 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9559 
9560 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9561 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
9562 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
9563 
9564 
9565 /* Peripheral: UART */
9566 /* Description: Universal Asynchronous Receiver/Transmitter */
9567 
9568 /* Register: UART_TASKS_STARTRX */
9569 /* Description: Start UART receiver */
9570 
9571 /* Bit 0 : Start UART receiver */
9572 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9573 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9574 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9575 
9576 /* Register: UART_TASKS_STOPRX */
9577 /* Description: Stop UART receiver */
9578 
9579 /* Bit 0 : Stop UART receiver */
9580 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
9581 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
9582 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
9583 
9584 /* Register: UART_TASKS_STARTTX */
9585 /* Description: Start UART transmitter */
9586 
9587 /* Bit 0 : Start UART transmitter */
9588 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9589 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9590 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9591 
9592 /* Register: UART_TASKS_STOPTX */
9593 /* Description: Stop UART transmitter */
9594 
9595 /* Bit 0 : Stop UART transmitter */
9596 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
9597 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
9598 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
9599 
9600 /* Register: UART_TASKS_SUSPEND */
9601 /* Description: Suspend UART */
9602 
9603 /* Bit 0 : Suspend UART */
9604 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9605 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9606 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9607 
9608 /* Register: UART_EVENTS_CTS */
9609 /* Description: CTS is activated (set low). Clear To Send. */
9610 
9611 /* Bit 0 : CTS is activated (set low). Clear To Send. */
9612 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
9613 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
9614 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
9615 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
9616 
9617 /* Register: UART_EVENTS_NCTS */
9618 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9619 
9620 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
9621 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
9622 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
9623 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
9624 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
9625 
9626 /* Register: UART_EVENTS_RXDRDY */
9627 /* Description: Data received in RXD */
9628 
9629 /* Bit 0 : Data received in RXD */
9630 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
9631 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
9632 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
9633 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
9634 
9635 /* Register: UART_EVENTS_TXDRDY */
9636 /* Description: Data sent from TXD */
9637 
9638 /* Bit 0 : Data sent from TXD */
9639 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
9640 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
9641 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
9642 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
9643 
9644 /* Register: UART_EVENTS_ERROR */
9645 /* Description: Error detected */
9646 
9647 /* Bit 0 : Error detected */
9648 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9649 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9650 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9651 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9652 
9653 /* Register: UART_EVENTS_RXTO */
9654 /* Description: Receiver timeout */
9655 
9656 /* Bit 0 : Receiver timeout */
9657 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
9658 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
9659 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
9660 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
9661 
9662 /* Register: UART_SHORTS */
9663 /* Description: Shortcuts between local events and tasks */
9664 
9665 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
9666 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
9667 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
9668 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
9669 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
9670 
9671 /* Bit 3 : Shortcut between event CTS and task STARTRX */
9672 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
9673 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
9674 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
9675 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
9676 
9677 /* Register: UART_INTENSET */
9678 /* Description: Enable interrupt */
9679 
9680 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
9681 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
9682 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
9683 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
9684 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
9685 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
9686 
9687 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9688 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9689 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9690 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9691 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9692 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
9693 
9694 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
9695 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
9696 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
9697 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9698 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9699 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
9700 
9701 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
9702 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
9703 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
9704 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9705 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9706 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
9707 
9708 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
9709 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
9710 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
9711 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
9712 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
9713 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
9714 
9715 /* Bit 0 : Write '1' to enable interrupt for event CTS */
9716 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
9717 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
9718 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
9719 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
9720 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
9721 
9722 /* Register: UART_INTENCLR */
9723 /* Description: Disable interrupt */
9724 
9725 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
9726 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
9727 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
9728 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
9729 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
9730 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
9731 
9732 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9733 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9734 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9735 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9736 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9737 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9738 
9739 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
9740 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
9741 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
9742 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9743 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9744 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
9745 
9746 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
9747 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
9748 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
9749 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9750 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9751 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
9752 
9753 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
9754 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
9755 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
9756 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
9757 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
9758 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
9759 
9760 /* Bit 0 : Write '1' to disable interrupt for event CTS */
9761 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
9762 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
9763 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
9764 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
9765 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
9766 
9767 /* Register: UART_ERRORSRC */
9768 /* Description: Error source */
9769 
9770 /* Bit 3 : Break condition */
9771 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
9772 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
9773 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
9774 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
9775 
9776 /* Bit 2 : Framing error occurred */
9777 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
9778 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
9779 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
9780 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
9781 
9782 /* Bit 1 : Parity error */
9783 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
9784 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
9785 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
9786 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
9787 
9788 /* Bit 0 : Overrun error */
9789 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9790 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9791 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
9792 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
9793 
9794 /* Register: UART_ENABLE */
9795 /* Description: Enable UART */
9796 
9797 /* Bits 3..0 : Enable or disable UART */
9798 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9799 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9800 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
9801 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
9802 
9803 /* Register: UART_PSEL_RTS */
9804 /* Description: Pin select for RTS */
9805 
9806 /* Bit 31 : Connection */
9807 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9808 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9809 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
9810 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
9811 
9812 /* Bits 4..0 : Pin number */
9813 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
9814 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
9815 
9816 /* Register: UART_PSEL_TXD */
9817 /* Description: Pin select for TXD */
9818 
9819 /* Bit 31 : Connection */
9820 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9821 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9822 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
9823 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
9824 
9825 /* Bits 4..0 : Pin number */
9826 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
9827 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
9828 
9829 /* Register: UART_PSEL_CTS */
9830 /* Description: Pin select for CTS */
9831 
9832 /* Bit 31 : Connection */
9833 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9834 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9835 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
9836 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
9837 
9838 /* Bits 4..0 : Pin number */
9839 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
9840 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
9841 
9842 /* Register: UART_PSEL_RXD */
9843 /* Description: Pin select for RXD */
9844 
9845 /* Bit 31 : Connection */
9846 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9847 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9848 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
9849 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
9850 
9851 /* Bits 4..0 : Pin number */
9852 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
9853 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
9854 
9855 /* Register: UART_RXD */
9856 /* Description: RXD register */
9857 
9858 /* Bits 7..0 : RX data received in previous transfers, double buffered */
9859 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
9860 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
9861 
9862 /* Register: UART_TXD */
9863 /* Description: TXD register */
9864 
9865 /* Bits 7..0 : TX data to be transferred */
9866 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
9867 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
9868 
9869 /* Register: UART_BAUDRATE */
9870 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
9871 
9872 /* Bits 31..0 : Baud rate */
9873 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
9874 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
9875 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
9876 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
9877 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
9878 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
9879 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
9880 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
9881 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
9882 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
9883 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
9884 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
9885 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
9886 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
9887 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
9888 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
9889 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
9890 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
9891 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
9892 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
9893 
9894 /* Register: UART_CONFIG */
9895 /* Description: Configuration of parity and hardware flow control */
9896 
9897 /* Bit 8 : Even or odd parity type */
9898 #define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
9899 #define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
9900 #define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
9901 #define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
9902 
9903 /* Bit 4 : Stop bits */
9904 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
9905 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
9906 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
9907 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
9908 
9909 /* Bits 3..1 : Parity */
9910 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
9911 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
9912 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
9913 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
9914 
9915 /* Bit 0 : Hardware flow control */
9916 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
9917 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
9918 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
9919 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
9920 
9921 
9922 /* Peripheral: UARTE */
9923 /* Description: UART with EasyDMA */
9924 
9925 /* Register: UARTE_TASKS_STARTRX */
9926 /* Description: Start UART receiver */
9927 
9928 /* Bit 0 : Start UART receiver */
9929 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9930 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9931 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9932 
9933 /* Register: UARTE_TASKS_STOPRX */
9934 /* Description: Stop UART receiver */
9935 
9936 /* Bit 0 : Stop UART receiver */
9937 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
9938 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
9939 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
9940 
9941 /* Register: UARTE_TASKS_STARTTX */
9942 /* Description: Start UART transmitter */
9943 
9944 /* Bit 0 : Start UART transmitter */
9945 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9946 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9947 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9948 
9949 /* Register: UARTE_TASKS_STOPTX */
9950 /* Description: Stop UART transmitter */
9951 
9952 /* Bit 0 : Stop UART transmitter */
9953 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
9954 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
9955 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
9956 
9957 /* Register: UARTE_TASKS_FLUSHRX */
9958 /* Description: Flush RX FIFO into RX buffer */
9959 
9960 /* Bit 0 : Flush RX FIFO into RX buffer */
9961 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
9962 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
9963 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
9964 
9965 /* Register: UARTE_EVENTS_CTS */
9966 /* Description: CTS is activated (set low). Clear To Send. */
9967 
9968 /* Bit 0 : CTS is activated (set low). Clear To Send. */
9969 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
9970 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
9971 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
9972 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
9973 
9974 /* Register: UARTE_EVENTS_NCTS */
9975 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9976 
9977 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
9978 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
9979 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
9980 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
9981 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
9982 
9983 /* Register: UARTE_EVENTS_RXDRDY */
9984 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
9985 
9986 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
9987 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
9988 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
9989 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
9990 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
9991 
9992 /* Register: UARTE_EVENTS_ENDRX */
9993 /* Description: Receive buffer is filled up */
9994 
9995 /* Bit 0 : Receive buffer is filled up */
9996 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
9997 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
9998 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
9999 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
10000 
10001 /* Register: UARTE_EVENTS_TXDRDY */
10002 /* Description: Data sent from TXD */
10003 
10004 /* Bit 0 : Data sent from TXD */
10005 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
10006 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
10007 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
10008 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
10009 
10010 /* Register: UARTE_EVENTS_ENDTX */
10011 /* Description: Last TX byte transmitted */
10012 
10013 /* Bit 0 : Last TX byte transmitted */
10014 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
10015 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
10016 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
10017 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
10018 
10019 /* Register: UARTE_EVENTS_ERROR */
10020 /* Description: Error detected */
10021 
10022 /* Bit 0 : Error detected */
10023 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
10024 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
10025 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
10026 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
10027 
10028 /* Register: UARTE_EVENTS_RXTO */
10029 /* Description: Receiver timeout */
10030 
10031 /* Bit 0 : Receiver timeout */
10032 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
10033 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
10034 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
10035 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
10036 
10037 /* Register: UARTE_EVENTS_RXSTARTED */
10038 /* Description: UART receiver has started */
10039 
10040 /* Bit 0 : UART receiver has started */
10041 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
10042 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
10043 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10044 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
10045 
10046 /* Register: UARTE_EVENTS_TXSTARTED */
10047 /* Description: UART transmitter has started */
10048 
10049 /* Bit 0 : UART transmitter has started */
10050 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
10051 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
10052 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10053 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
10054 
10055 /* Register: UARTE_EVENTS_TXSTOPPED */
10056 /* Description: Transmitter stopped */
10057 
10058 /* Bit 0 : Transmitter stopped */
10059 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
10060 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
10061 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
10062 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
10063 
10064 /* Register: UARTE_SHORTS */
10065 /* Description: Shortcuts between local events and tasks */
10066 
10067 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
10068 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
10069 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
10070 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10071 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10072 
10073 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
10074 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
10075 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
10076 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10077 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10078 
10079 /* Register: UARTE_INTEN */
10080 /* Description: Enable or disable interrupt */
10081 
10082 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10083 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10084 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10085 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
10086 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10087 
10088 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10089 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10090 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10091 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10092 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10093 
10094 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10095 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10096 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10097 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10098 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10099 
10100 /* Bit 17 : Enable or disable interrupt for event RXTO */
10101 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10102 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
10103 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
10104 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10105 
10106 /* Bit 9 : Enable or disable interrupt for event ERROR */
10107 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10108 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
10109 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10110 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10111 
10112 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10113 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10114 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10115 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
10116 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10117 
10118 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10119 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10120 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10121 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
10122 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10123 
10124 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10125 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10126 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10127 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
10128 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10129 
10130 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10131 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10132 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10133 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
10134 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10135 
10136 /* Bit 1 : Enable or disable interrupt for event NCTS */
10137 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10138 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
10139 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
10140 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10141 
10142 /* Bit 0 : Enable or disable interrupt for event CTS */
10143 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
10144 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
10145 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
10146 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10147 
10148 /* Register: UARTE_INTENSET */
10149 /* Description: Enable interrupt */
10150 
10151 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10152 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10153 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10154 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10155 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10156 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10157 
10158 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10159 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10160 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10161 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10162 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10163 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10164 
10165 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10166 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10167 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10168 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10169 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10170 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10171 
10172 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10173 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10174 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
10175 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10176 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10177 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10178 
10179 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10180 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10181 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10182 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10183 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10184 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10185 
10186 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10187 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10188 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10189 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10190 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10191 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10192 
10193 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10194 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10195 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10196 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10197 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10198 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10199 
10200 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10201 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10202 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10203 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10204 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10205 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10206 
10207 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10208 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10209 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10210 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10211 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10212 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10213 
10214 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10215 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10216 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
10217 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10218 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10219 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10220 
10221 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10222 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
10223 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
10224 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10225 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10226 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10227 
10228 /* Register: UARTE_INTENCLR */
10229 /* Description: Disable interrupt */
10230 
10231 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10232 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10233 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10234 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10235 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10236 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10237 
10238 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10239 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10240 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10241 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10242 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10243 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10244 
10245 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10246 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10247 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10248 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10249 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10250 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10251 
10252 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10253 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10254 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
10255 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10256 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10257 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10258 
10259 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10260 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10261 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10262 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10263 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10264 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10265 
10266 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10267 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10268 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10269 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10270 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10271 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10272 
10273 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10274 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10275 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10276 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10277 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10278 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10279 
10280 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10281 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10282 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10283 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10284 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10285 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10286 
10287 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10288 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10289 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10290 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10291 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10292 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10293 
10294 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10295 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10296 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
10297 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10298 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10299 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10300 
10301 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10302 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
10303 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
10304 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10305 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10306 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10307 
10308 /* Register: UARTE_ERRORSRC */
10309 /* Description: Error source This register is read/write one to clear. */
10310 
10311 /* Bit 3 : Break condition */
10312 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
10313 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
10314 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10315 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10316 
10317 /* Bit 2 : Framing error occurred */
10318 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10319 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
10320 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10321 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10322 
10323 /* Bit 1 : Parity error */
10324 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10325 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
10326 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10327 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10328 
10329 /* Bit 0 : Overrun error */
10330 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10331 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10332 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10333 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10334 
10335 /* Register: UARTE_ENABLE */
10336 /* Description: Enable UART */
10337 
10338 /* Bits 3..0 : Enable or disable UARTE */
10339 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10340 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10341 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10342 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10343 
10344 /* Register: UARTE_PSEL_RTS */
10345 /* Description: Pin select for RTS signal */
10346 
10347 /* Bit 31 : Connection */
10348 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10349 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10350 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
10351 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10352 
10353 /* Bits 4..0 : Pin number */
10354 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10355 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
10356 
10357 /* Register: UARTE_PSEL_TXD */
10358 /* Description: Pin select for TXD signal */
10359 
10360 /* Bit 31 : Connection */
10361 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10362 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10363 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
10364 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10365 
10366 /* Bits 4..0 : Pin number */
10367 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10368 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
10369 
10370 /* Register: UARTE_PSEL_CTS */
10371 /* Description: Pin select for CTS signal */
10372 
10373 /* Bit 31 : Connection */
10374 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10375 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10376 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
10377 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10378 
10379 /* Bits 4..0 : Pin number */
10380 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10381 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
10382 
10383 /* Register: UARTE_PSEL_RXD */
10384 /* Description: Pin select for RXD signal */
10385 
10386 /* Bit 31 : Connection */
10387 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10388 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10389 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
10390 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10391 
10392 /* Bits 4..0 : Pin number */
10393 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10394 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
10395 
10396 /* Register: UARTE_BAUDRATE */
10397 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
10398 
10399 /* Bits 31..0 : Baud rate */
10400 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
10401 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
10402 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
10403 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
10404 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
10405 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
10406 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
10407 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
10408 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
10409 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
10410 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
10411 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
10412 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
10413 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
10414 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
10415 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
10416 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
10417 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
10418 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
10419 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
10420 
10421 /* Register: UARTE_RXD_PTR */
10422 /* Description: Data pointer */
10423 
10424 /* Bits 31..0 : Data pointer */
10425 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10426 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10427 
10428 /* Register: UARTE_RXD_MAXCNT */
10429 /* Description: Maximum number of bytes in receive buffer */
10430 
10431 /* Bits 14..0 : Maximum number of bytes in receive buffer */
10432 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10433 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10434 
10435 /* Register: UARTE_RXD_AMOUNT */
10436 /* Description: Number of bytes transferred in the last transaction */
10437 
10438 /* Bits 14..0 : Number of bytes transferred in the last transaction */
10439 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10440 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10441 
10442 /* Register: UARTE_TXD_PTR */
10443 /* Description: Data pointer */
10444 
10445 /* Bits 31..0 : Data pointer */
10446 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10447 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10448 
10449 /* Register: UARTE_TXD_MAXCNT */
10450 /* Description: Maximum number of bytes in transmit buffer */
10451 
10452 /* Bits 14..0 : Maximum number of bytes in transmit buffer */
10453 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10454 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10455 
10456 /* Register: UARTE_TXD_AMOUNT */
10457 /* Description: Number of bytes transferred in the last transaction */
10458 
10459 /* Bits 14..0 : Number of bytes transferred in the last transaction */
10460 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10461 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10462 
10463 /* Register: UARTE_CONFIG */
10464 /* Description: Configuration of parity and hardware flow control */
10465 
10466 /* Bit 8 : Even or odd parity type */
10467 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
10468 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
10469 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
10470 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
10471 
10472 /* Bit 4 : Stop bits */
10473 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
10474 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
10475 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
10476 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10477 
10478 /* Bits 3..1 : Parity */
10479 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10480 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
10481 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
10482 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
10483 
10484 /* Bit 0 : Hardware flow control */
10485 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
10486 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
10487 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10488 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10489 
10490 
10491 /* Peripheral: UICR */
10492 /* Description: User information configuration registers */
10493 
10494 /* Register: UICR_NRFFW */
10495 /* Description: Description collection: Reserved for Nordic firmware design */
10496 
10497 /* Bits 31..0 : Reserved for Nordic firmware design */
10498 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
10499 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
10500 
10501 /* Register: UICR_NRFHW */
10502 /* Description: Description collection: Reserved for Nordic hardware design */
10503 
10504 /* Bits 31..0 : Reserved for Nordic hardware design */
10505 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
10506 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
10507 
10508 /* Register: UICR_CUSTOMER */
10509 /* Description: Description collection: Reserved for customer */
10510 
10511 /* Bits 31..0 : Reserved for customer */
10512 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
10513 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
10514 
10515 /* Register: UICR_PSELRESET */
10516 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
10517 
10518 /* Bit 31 : Connection */
10519 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10520 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10521 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
10522 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
10523 
10524 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
10525 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
10526 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
10527 
10528 /* Register: UICR_APPROTECT */
10529 /* Description: Access port protection */
10530 
10531 /* Bits 7..0 : Enable or disable access port protection. */
10532 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10533 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10534 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
10535 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
10536 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
10537 
10538 /* Register: UICR_DEBUGCTRL */
10539 /* Description: Processor debug control */
10540 
10541 /* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */
10542 #define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */
10543 #define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */
10544 #define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */
10545 #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
10546 
10547 /* Register: UICR_REGOUT0 */
10548 /* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */
10549 
10550 /* Bits 2..0 : Output voltage from REG0 regulator stage. */
10551 #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
10552 #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
10553 #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
10554 #define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
10555 #define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
10556 #define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
10557 #define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
10558 #define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
10559 #define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
10560 
10561 
10562 /* Peripheral: USBD */
10563 /* Description: Universal serial bus device */
10564 
10565 /* Register: USBD_TASKS_STARTEPIN */
10566 /* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
10567 
10568 /* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
10569 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
10570 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
10571 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */
10572 
10573 /* Register: USBD_TASKS_STARTISOIN */
10574 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
10575 
10576 /* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
10577 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
10578 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
10579 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */
10580 
10581 /* Register: USBD_TASKS_STARTEPOUT */
10582 /* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
10583 
10584 /* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
10585 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
10586 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
10587 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */
10588 
10589 /* Register: USBD_TASKS_STARTISOOUT */
10590 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
10591 
10592 /* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
10593 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
10594 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
10595 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */
10596 
10597 /* Register: USBD_TASKS_EP0RCVOUT */
10598 /* Description: Allows OUT data stage on control endpoint 0 */
10599 
10600 /* Bit 0 : Allows OUT data stage on control endpoint 0 */
10601 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
10602 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
10603 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */
10604 
10605 /* Register: USBD_TASKS_EP0STATUS */
10606 /* Description: Allows status stage on control endpoint 0 */
10607 
10608 /* Bit 0 : Allows status stage on control endpoint 0 */
10609 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
10610 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
10611 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */
10612 
10613 /* Register: USBD_TASKS_EP0STALL */
10614 /* Description: Stalls data and status stage on control endpoint 0 */
10615 
10616 /* Bit 0 : Stalls data and status stage on control endpoint 0 */
10617 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
10618 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
10619 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */
10620 
10621 /* Register: USBD_TASKS_DPDMDRIVE */
10622 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
10623 
10624 /* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
10625 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
10626 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
10627 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */
10628 
10629 /* Register: USBD_TASKS_DPDMNODRIVE */
10630 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
10631 
10632 /* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
10633 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
10634 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
10635 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */
10636 
10637 /* Register: USBD_EVENTS_USBRESET */
10638 /* Description: Signals that a USB reset condition has been detected on USB lines */
10639 
10640 /* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
10641 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
10642 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
10643 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */
10644 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */
10645 
10646 /* Register: USBD_EVENTS_STARTED */
10647 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
10648 
10649 /* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
10650 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
10651 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
10652 #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
10653 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
10654 
10655 /* Register: USBD_EVENTS_ENDEPIN */
10656 /* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
10657 
10658 /* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
10659 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
10660 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
10661 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
10662 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */
10663 
10664 /* Register: USBD_EVENTS_EP0DATADONE */
10665 /* Description: An acknowledged data transfer has taken place on the control endpoint */
10666 
10667 /* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
10668 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
10669 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
10670 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */
10671 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
10672 
10673 /* Register: USBD_EVENTS_ENDISOIN */
10674 /* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
10675 
10676 /* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
10677 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
10678 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
10679 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
10680 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
10681 
10682 /* Register: USBD_EVENTS_ENDEPOUT */
10683 /* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
10684 
10685 /* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
10686 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
10687 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
10688 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
10689 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
10690 
10691 /* Register: USBD_EVENTS_ENDISOOUT */
10692 /* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
10693 
10694 /* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
10695 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
10696 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
10697 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
10698 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */
10699 
10700 /* Register: USBD_EVENTS_SOF */
10701 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
10702 
10703 /* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
10704 #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
10705 #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
10706 #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */
10707 #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */
10708 
10709 /* Register: USBD_EVENTS_USBEVENT */
10710 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
10711 
10712 /* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
10713 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
10714 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
10715 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */
10716 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */
10717 
10718 /* Register: USBD_EVENTS_EP0SETUP */
10719 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
10720 
10721 /* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
10722 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
10723 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
10724 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */
10725 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */
10726 
10727 /* Register: USBD_EVENTS_EPDATA */
10728 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
10729 
10730 /* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
10731 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
10732 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
10733 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */
10734 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */
10735 
10736 /* Register: USBD_SHORTS */
10737 /* Description: Shortcuts between local events and tasks */
10738 
10739 /* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
10740 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
10741 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
10742 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
10743 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
10744 
10745 /* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
10746 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
10747 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
10748 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
10749 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
10750 
10751 /* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
10752 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
10753 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
10754 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
10755 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
10756 
10757 /* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
10758 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
10759 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
10760 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
10761 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
10762 
10763 /* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
10764 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
10765 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
10766 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
10767 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
10768 
10769 /* Register: USBD_INTEN */
10770 /* Description: Enable or disable interrupt */
10771 
10772 /* Bit 24 : Enable or disable interrupt for event EPDATA */
10773 #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
10774 #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
10775 #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
10776 #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
10777 
10778 /* Bit 23 : Enable or disable interrupt for event EP0SETUP */
10779 #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
10780 #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
10781 #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
10782 #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
10783 
10784 /* Bit 22 : Enable or disable interrupt for event USBEVENT */
10785 #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
10786 #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
10787 #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
10788 #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
10789 
10790 /* Bit 21 : Enable or disable interrupt for event SOF */
10791 #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
10792 #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
10793 #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
10794 #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
10795 
10796 /* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
10797 #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
10798 #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
10799 #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
10800 #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
10801 
10802 /* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
10803 #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
10804 #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
10805 #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
10806 #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
10807 
10808 /* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
10809 #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
10810 #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
10811 #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
10812 #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
10813 
10814 /* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
10815 #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
10816 #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
10817 #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
10818 #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
10819 
10820 /* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
10821 #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
10822 #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
10823 #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
10824 #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
10825 
10826 /* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
10827 #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
10828 #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
10829 #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
10830 #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
10831 
10832 /* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
10833 #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
10834 #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
10835 #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
10836 #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
10837 
10838 /* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
10839 #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
10840 #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
10841 #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
10842 #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
10843 
10844 /* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
10845 #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
10846 #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
10847 #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
10848 #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
10849 
10850 /* Bit 11 : Enable or disable interrupt for event ENDISOIN */
10851 #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
10852 #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
10853 #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
10854 #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
10855 
10856 /* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
10857 #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
10858 #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
10859 #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
10860 #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
10861 
10862 /* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
10863 #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
10864 #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
10865 #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
10866 #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
10867 
10868 /* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
10869 #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
10870 #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
10871 #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
10872 #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
10873 
10874 /* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
10875 #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
10876 #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
10877 #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
10878 #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
10879 
10880 /* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
10881 #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
10882 #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
10883 #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
10884 #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
10885 
10886 /* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
10887 #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
10888 #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
10889 #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
10890 #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
10891 
10892 /* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
10893 #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
10894 #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
10895 #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
10896 #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
10897 
10898 /* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
10899 #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
10900 #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
10901 #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
10902 #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
10903 
10904 /* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
10905 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
10906 #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
10907 #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
10908 #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
10909 
10910 /* Bit 1 : Enable or disable interrupt for event STARTED */
10911 #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
10912 #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
10913 #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
10914 #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
10915 
10916 /* Bit 0 : Enable or disable interrupt for event USBRESET */
10917 #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
10918 #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
10919 #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
10920 #define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
10921 
10922 /* Register: USBD_INTENSET */
10923 /* Description: Enable interrupt */
10924 
10925 /* Bit 24 : Write '1' to enable interrupt for event EPDATA */
10926 #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
10927 #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
10928 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
10929 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
10930 #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
10931 
10932 /* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
10933 #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
10934 #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
10935 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
10936 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
10937 #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
10938 
10939 /* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
10940 #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
10941 #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
10942 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
10943 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
10944 #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
10945 
10946 /* Bit 21 : Write '1' to enable interrupt for event SOF */
10947 #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
10948 #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
10949 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
10950 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
10951 #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
10952 
10953 /* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
10954 #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
10955 #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
10956 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
10957 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
10958 #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
10959 
10960 /* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
10961 #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
10962 #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
10963 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
10964 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
10965 #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
10966 
10967 /* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
10968 #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
10969 #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
10970 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
10971 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
10972 #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
10973 
10974 /* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
10975 #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
10976 #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
10977 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
10978 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
10979 #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
10980 
10981 /* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
10982 #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
10983 #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
10984 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
10985 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
10986 #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
10987 
10988 /* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
10989 #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
10990 #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
10991 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
10992 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
10993 #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
10994 
10995 /* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
10996 #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
10997 #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
10998 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
10999 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
11000 #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
11001 
11002 /* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
11003 #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
11004 #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
11005 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
11006 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
11007 #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
11008 
11009 /* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
11010 #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
11011 #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
11012 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
11013 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
11014 #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
11015 
11016 /* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
11017 #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
11018 #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
11019 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
11020 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
11021 #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
11022 
11023 /* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
11024 #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
11025 #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
11026 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
11027 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
11028 #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
11029 
11030 /* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
11031 #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
11032 #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
11033 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
11034 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
11035 #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
11036 
11037 /* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
11038 #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
11039 #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
11040 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
11041 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
11042 #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
11043 
11044 /* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
11045 #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
11046 #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
11047 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
11048 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
11049 #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
11050 
11051 /* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
11052 #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
11053 #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
11054 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
11055 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
11056 #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
11057 
11058 /* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
11059 #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
11060 #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
11061 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
11062 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
11063 #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
11064 
11065 /* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
11066 #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
11067 #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
11068 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
11069 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
11070 #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
11071 
11072 /* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
11073 #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
11074 #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
11075 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
11076 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
11077 #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
11078 
11079 /* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
11080 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
11081 #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
11082 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
11083 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
11084 #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
11085 
11086 /* Bit 1 : Write '1' to enable interrupt for event STARTED */
11087 #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
11088 #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11089 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11090 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11091 #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
11092 
11093 /* Bit 0 : Write '1' to enable interrupt for event USBRESET */
11094 #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
11095 #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
11096 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
11097 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
11098 #define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
11099 
11100 /* Register: USBD_INTENCLR */
11101 /* Description: Disable interrupt */
11102 
11103 /* Bit 24 : Write '1' to disable interrupt for event EPDATA */
11104 #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
11105 #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
11106 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
11107 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
11108 #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
11109 
11110 /* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
11111 #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
11112 #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
11113 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
11114 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
11115 #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
11116 
11117 /* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
11118 #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
11119 #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
11120 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
11121 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
11122 #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
11123 
11124 /* Bit 21 : Write '1' to disable interrupt for event SOF */
11125 #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
11126 #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
11127 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
11128 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
11129 #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
11130 
11131 /* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
11132 #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
11133 #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
11134 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
11135 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
11136 #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
11137 
11138 /* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
11139 #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
11140 #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
11141 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
11142 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
11143 #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
11144 
11145 /* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
11146 #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
11147 #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
11148 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
11149 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
11150 #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
11151 
11152 /* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
11153 #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
11154 #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
11155 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
11156 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
11157 #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
11158 
11159 /* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
11160 #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
11161 #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
11162 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
11163 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
11164 #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
11165 
11166 /* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
11167 #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
11168 #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
11169 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
11170 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
11171 #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
11172 
11173 /* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
11174 #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
11175 #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
11176 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
11177 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
11178 #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
11179 
11180 /* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
11181 #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
11182 #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
11183 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
11184 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
11185 #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
11186 
11187 /* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
11188 #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
11189 #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
11190 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
11191 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
11192 #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
11193 
11194 /* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
11195 #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
11196 #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
11197 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
11198 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
11199 #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
11200 
11201 /* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
11202 #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
11203 #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
11204 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
11205 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
11206 #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
11207 
11208 /* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
11209 #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
11210 #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
11211 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
11212 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
11213 #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
11214 
11215 /* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
11216 #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
11217 #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
11218 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
11219 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
11220 #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
11221 
11222 /* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
11223 #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
11224 #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
11225 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
11226 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
11227 #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
11228 
11229 /* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
11230 #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
11231 #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
11232 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
11233 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
11234 #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
11235 
11236 /* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
11237 #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
11238 #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
11239 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
11240 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
11241 #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
11242 
11243 /* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
11244 #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
11245 #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
11246 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
11247 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
11248 #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
11249 
11250 /* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
11251 #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
11252 #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
11253 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
11254 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
11255 #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
11256 
11257 /* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
11258 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
11259 #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
11260 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
11261 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
11262 #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
11263 
11264 /* Bit 1 : Write '1' to disable interrupt for event STARTED */
11265 #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
11266 #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
11267 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11268 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
11269 #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
11270 
11271 /* Bit 0 : Write '1' to disable interrupt for event USBRESET */
11272 #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
11273 #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
11274 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
11275 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
11276 #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
11277 
11278 /* Register: USBD_EVENTCAUSE */
11279 /* Description: Details on what caused the USBEVENT event */
11280 
11281 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
11282 #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
11283 #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
11284 #define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
11285 #define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
11286 
11287 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
11288 #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
11289 #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
11290 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
11291 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
11292 
11293 /* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
11294 #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
11295 #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
11296 #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
11297 #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
11298 
11299 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
11300 #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
11301 #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
11302 #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
11303 #define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
11304 
11305 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
11306 #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
11307 #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
11308 #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
11309 #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
11310 
11311 /* Register: USBD_HALTED_EPIN */
11312 /* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
11313 
11314 /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
11315 #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
11316 #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
11317 #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
11318 #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
11319 
11320 /* Register: USBD_HALTED_EPOUT */
11321 /* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
11322 
11323 /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
11324 #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
11325 #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
11326 #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
11327 #define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
11328 
11329 /* Register: USBD_EPSTATUS */
11330 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
11331 
11332 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11333 #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
11334 #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
11335 #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11336 #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11337 
11338 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11339 #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
11340 #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
11341 #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11342 #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11343 
11344 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11345 #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
11346 #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
11347 #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11348 #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11349 
11350 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11351 #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
11352 #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
11353 #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11354 #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11355 
11356 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11357 #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
11358 #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
11359 #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11360 #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11361 
11362 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11363 #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
11364 #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
11365 #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11366 #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11367 
11368 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11369 #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
11370 #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
11371 #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11372 #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11373 
11374 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11375 #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
11376 #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
11377 #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11378 #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11379 
11380 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11381 #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
11382 #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
11383 #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11384 #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11385 
11386 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11387 #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
11388 #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
11389 #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11390 #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11391 
11392 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11393 #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
11394 #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
11395 #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11396 #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11397 
11398 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11399 #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
11400 #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
11401 #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11402 #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11403 
11404 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11405 #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
11406 #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
11407 #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11408 #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11409 
11410 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11411 #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
11412 #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
11413 #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11414 #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11415 
11416 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11417 #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
11418 #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
11419 #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11420 #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11421 
11422 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11423 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
11424 #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
11425 #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11426 #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11427 
11428 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11429 #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
11430 #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
11431 #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11432 #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11433 
11434 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
11435 #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
11436 #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
11437 #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
11438 #define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
11439 
11440 /* Register: USBD_EPDATASTATUS */
11441 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
11442 
11443 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11444 #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
11445 #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
11446 #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11447 #define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11448 
11449 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11450 #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
11451 #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
11452 #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11453 #define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11454 
11455 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11456 #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
11457 #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
11458 #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11459 #define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11460 
11461 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11462 #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
11463 #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
11464 #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11465 #define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11466 
11467 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11468 #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
11469 #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
11470 #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11471 #define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11472 
11473 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11474 #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
11475 #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
11476 #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11477 #define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11478 
11479 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
11480 #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
11481 #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
11482 #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
11483 #define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11484 
11485 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11486 #define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
11487 #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
11488 #define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11489 #define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11490 
11491 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11492 #define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
11493 #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
11494 #define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11495 #define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11496 
11497 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11498 #define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
11499 #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
11500 #define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11501 #define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11502 
11503 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11504 #define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
11505 #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
11506 #define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11507 #define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11508 
11509 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11510 #define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
11511 #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
11512 #define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11513 #define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11514 
11515 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11516 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
11517 #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
11518 #define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11519 #define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11520 
11521 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
11522 #define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
11523 #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
11524 #define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
11525 #define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
11526 
11527 /* Register: USBD_USBADDR */
11528 /* Description: Device USB address */
11529 
11530 /* Bits 6..0 : Device USB address */
11531 #define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
11532 #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
11533 
11534 /* Register: USBD_BMREQUESTTYPE */
11535 /* Description: SETUP data, byte 0, bmRequestType */
11536 
11537 /* Bit 7 : Data transfer direction */
11538 #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
11539 #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
11540 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
11541 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
11542 
11543 /* Bits 6..5 : Data transfer type */
11544 #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
11545 #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
11546 #define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
11547 #define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
11548 #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
11549 
11550 /* Bits 4..0 : Data transfer type */
11551 #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
11552 #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
11553 #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
11554 #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
11555 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
11556 #define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
11557 
11558 /* Register: USBD_BREQUEST */
11559 /* Description: SETUP data, byte 1, bRequest */
11560 
11561 /* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
11562 #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
11563 #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
11564 #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
11565 #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
11566 #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
11567 #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
11568 #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
11569 #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
11570 #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
11571 #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
11572 #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
11573 #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
11574 #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
11575 
11576 /* Register: USBD_WVALUEL */
11577 /* Description: SETUP data, byte 2, LSB of wValue */
11578 
11579 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
11580 #define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
11581 #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
11582 
11583 /* Register: USBD_WVALUEH */
11584 /* Description: SETUP data, byte 3, MSB of wValue */
11585 
11586 /* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
11587 #define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
11588 #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
11589 
11590 /* Register: USBD_WINDEXL */
11591 /* Description: SETUP data, byte 4, LSB of wIndex */
11592 
11593 /* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
11594 #define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
11595 #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
11596 
11597 /* Register: USBD_WINDEXH */
11598 /* Description: SETUP data, byte 5, MSB of wIndex */
11599 
11600 /* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
11601 #define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
11602 #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
11603 
11604 /* Register: USBD_WLENGTHL */
11605 /* Description: SETUP data, byte 6, LSB of wLength */
11606 
11607 /* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
11608 #define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
11609 #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
11610 
11611 /* Register: USBD_WLENGTHH */
11612 /* Description: SETUP data, byte 7, MSB of wLength */
11613 
11614 /* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
11615 #define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
11616 #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
11617 
11618 /* Register: USBD_SIZE_EPOUT */
11619 /* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
11620 
11621 /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
11622 #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
11623 #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
11624 
11625 /* Register: USBD_SIZE_ISOOUT */
11626 /* Description: Number of bytes received last on this ISO OUT data endpoint */
11627 
11628 /* Bit 16 : Zero-length data packet received */
11629 #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
11630 #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
11631 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
11632 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
11633 
11634 /* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
11635 #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
11636 #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
11637 
11638 /* Register: USBD_ENABLE */
11639 /* Description: Enable USB */
11640 
11641 /* Bit 0 : Enable USB */
11642 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11643 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11644 #define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
11645 #define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
11646 
11647 /* Register: USBD_USBPULLUP */
11648 /* Description: Control of the USB pull-up */
11649 
11650 /* Bit 0 : Control of the USB pull-up on the D+ line */
11651 #define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
11652 #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11653 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
11654 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
11655 
11656 /* Register: USBD_DPDMVALUE */
11657 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
11658 
11659 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
11660 #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
11661 #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
11662 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
11663 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
11664 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
11665 
11666 /* Register: USBD_DTOGGLE */
11667 /* Description: Data toggle control and status */
11668 
11669 /* Bits 9..8 : Data toggle value */
11670 #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
11671 #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
11672 #define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
11673 #define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
11674 #define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
11675 
11676 /* Bit 7 : Selects IN or OUT endpoint */
11677 #define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
11678 #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
11679 #define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
11680 #define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
11681 
11682 /* Bits 2..0 : Select bulk endpoint number */
11683 #define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
11684 #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
11685 
11686 /* Register: USBD_EPINEN */
11687 /* Description: Endpoint IN enable */
11688 
11689 /* Bit 8 : Enable ISO IN endpoint */
11690 #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
11691 #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
11692 #define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
11693 #define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
11694 
11695 /* Bit 7 : Enable IN endpoint 7 */
11696 #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
11697 #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
11698 #define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
11699 #define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
11700 
11701 /* Bit 6 : Enable IN endpoint 6 */
11702 #define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
11703 #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
11704 #define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
11705 #define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
11706 
11707 /* Bit 5 : Enable IN endpoint 5 */
11708 #define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
11709 #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
11710 #define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
11711 #define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
11712 
11713 /* Bit 4 : Enable IN endpoint 4 */
11714 #define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
11715 #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
11716 #define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
11717 #define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
11718 
11719 /* Bit 3 : Enable IN endpoint 3 */
11720 #define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
11721 #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
11722 #define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
11723 #define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
11724 
11725 /* Bit 2 : Enable IN endpoint 2 */
11726 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
11727 #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
11728 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
11729 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
11730 
11731 /* Bit 1 : Enable IN endpoint 1 */
11732 #define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
11733 #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
11734 #define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
11735 #define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
11736 
11737 /* Bit 0 : Enable IN endpoint 0 */
11738 #define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
11739 #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
11740 #define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
11741 #define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
11742 
11743 /* Register: USBD_EPOUTEN */
11744 /* Description: Endpoint OUT enable */
11745 
11746 /* Bit 8 : Enable ISO OUT endpoint 8 */
11747 #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
11748 #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
11749 #define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
11750 #define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
11751 
11752 /* Bit 7 : Enable OUT endpoint 7 */
11753 #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
11754 #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
11755 #define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
11756 #define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
11757 
11758 /* Bit 6 : Enable OUT endpoint 6 */
11759 #define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
11760 #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
11761 #define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
11762 #define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
11763 
11764 /* Bit 5 : Enable OUT endpoint 5 */
11765 #define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
11766 #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
11767 #define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
11768 #define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
11769 
11770 /* Bit 4 : Enable OUT endpoint 4 */
11771 #define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
11772 #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
11773 #define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
11774 #define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
11775 
11776 /* Bit 3 : Enable OUT endpoint 3 */
11777 #define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
11778 #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
11779 #define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
11780 #define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
11781 
11782 /* Bit 2 : Enable OUT endpoint 2 */
11783 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
11784 #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
11785 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
11786 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
11787 
11788 /* Bit 1 : Enable OUT endpoint 1 */
11789 #define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
11790 #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
11791 #define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
11792 #define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
11793 
11794 /* Bit 0 : Enable OUT endpoint 0 */
11795 #define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
11796 #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
11797 #define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
11798 #define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
11799 
11800 /* Register: USBD_EPSTALL */
11801 /* Description: STALL endpoints */
11802 
11803 /* Bit 8 : Stall selected endpoint */
11804 #define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
11805 #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
11806 #define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
11807 #define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
11808 
11809 /* Bit 7 : Selects IN or OUT endpoint */
11810 #define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
11811 #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
11812 #define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
11813 #define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
11814 
11815 /* Bits 2..0 : Select endpoint number */
11816 #define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
11817 #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
11818 
11819 /* Register: USBD_ISOSPLIT */
11820 /* Description: Controls the split of ISO buffers */
11821 
11822 /* Bits 15..0 : Controls the split of ISO buffers */
11823 #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
11824 #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
11825 #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
11826 #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
11827 
11828 /* Register: USBD_FRAMECNTR */
11829 /* Description: Returns the current value of the start of frame counter */
11830 
11831 /* Bits 10..0 : Returns the current value of the start of frame counter */
11832 #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
11833 #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
11834 
11835 /* Register: USBD_LOWPOWER */
11836 /* Description: Controls USBD peripheral low power mode during USB suspend */
11837 
11838 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
11839 #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
11840 #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
11841 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
11842 #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
11843 
11844 /* Register: USBD_ISOINCONFIG */
11845 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
11846 
11847 /* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
11848 #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
11849 #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
11850 #define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
11851 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
11852 
11853 /* Register: USBD_EPIN_PTR */
11854 /* Description: Description cluster: Data pointer */
11855 
11856 /* Bits 31..0 : Data pointer */
11857 #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11858 #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11859 
11860 /* Register: USBD_EPIN_MAXCNT */
11861 /* Description: Description cluster: Maximum number of bytes to transfer */
11862 
11863 /* Bits 6..0 : Maximum number of bytes to transfer */
11864 #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11865 #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11866 
11867 /* Register: USBD_EPIN_AMOUNT */
11868 /* Description: Description cluster: Number of bytes transferred in the last transaction */
11869 
11870 /* Bits 6..0 : Number of bytes transferred in the last transaction */
11871 #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11872 #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11873 
11874 /* Register: USBD_ISOIN_PTR */
11875 /* Description: Data pointer */
11876 
11877 /* Bits 31..0 : Data pointer */
11878 #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11879 #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11880 
11881 /* Register: USBD_ISOIN_MAXCNT */
11882 /* Description: Maximum number of bytes to transfer */
11883 
11884 /* Bits 9..0 : Maximum number of bytes to transfer */
11885 #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11886 #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11887 
11888 /* Register: USBD_ISOIN_AMOUNT */
11889 /* Description: Number of bytes transferred in the last transaction */
11890 
11891 /* Bits 9..0 : Number of bytes transferred in the last transaction */
11892 #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11893 #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11894 
11895 /* Register: USBD_EPOUT_PTR */
11896 /* Description: Description cluster: Data pointer */
11897 
11898 /* Bits 31..0 : Data pointer */
11899 #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11900 #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11901 
11902 /* Register: USBD_EPOUT_MAXCNT */
11903 /* Description: Description cluster: Maximum number of bytes to transfer */
11904 
11905 /* Bits 6..0 : Maximum number of bytes to transfer */
11906 #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11907 #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11908 
11909 /* Register: USBD_EPOUT_AMOUNT */
11910 /* Description: Description cluster: Number of bytes transferred in the last transaction */
11911 
11912 /* Bits 6..0 : Number of bytes transferred in the last transaction */
11913 #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11914 #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11915 
11916 /* Register: USBD_ISOOUT_PTR */
11917 /* Description: Data pointer */
11918 
11919 /* Bits 31..0 : Data pointer */
11920 #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11921 #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11922 
11923 /* Register: USBD_ISOOUT_MAXCNT */
11924 /* Description: Maximum number of bytes to transfer */
11925 
11926 /* Bits 9..0 : Maximum number of bytes to transfer */
11927 #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11928 #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11929 
11930 /* Register: USBD_ISOOUT_AMOUNT */
11931 /* Description: Number of bytes transferred in the last transaction */
11932 
11933 /* Bits 9..0 : Number of bytes transferred in the last transaction */
11934 #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11935 #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11936 
11937 
11938 /* Peripheral: WDT */
11939 /* Description: Watchdog Timer */
11940 
11941 /* Register: WDT_TASKS_START */
11942 /* Description: Start the watchdog */
11943 
11944 /* Bit 0 : Start the watchdog */
11945 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11946 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11947 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11948 
11949 /* Register: WDT_EVENTS_TIMEOUT */
11950 /* Description: Watchdog timeout */
11951 
11952 /* Bit 0 : Watchdog timeout */
11953 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
11954 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
11955 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
11956 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
11957 
11958 /* Register: WDT_INTENSET */
11959 /* Description: Enable interrupt */
11960 
11961 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
11962 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
11963 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
11964 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
11965 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
11966 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
11967 
11968 /* Register: WDT_INTENCLR */
11969 /* Description: Disable interrupt */
11970 
11971 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
11972 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
11973 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
11974 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
11975 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
11976 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
11977 
11978 /* Register: WDT_RUNSTATUS */
11979 /* Description: Run status */
11980 
11981 /* Bit 0 : Indicates whether or not the watchdog is running */
11982 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
11983 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
11984 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
11985 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
11986 
11987 /* Register: WDT_REQSTATUS */
11988 /* Description: Request status */
11989 
11990 /* Bit 7 : Request status for RR[7] register */
11991 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
11992 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
11993 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
11994 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
11995 
11996 /* Bit 6 : Request status for RR[6] register */
11997 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
11998 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
11999 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
12000 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
12001 
12002 /* Bit 5 : Request status for RR[5] register */
12003 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
12004 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
12005 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
12006 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
12007 
12008 /* Bit 4 : Request status for RR[4] register */
12009 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
12010 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
12011 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
12012 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
12013 
12014 /* Bit 3 : Request status for RR[3] register */
12015 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
12016 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
12017 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
12018 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
12019 
12020 /* Bit 2 : Request status for RR[2] register */
12021 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
12022 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
12023 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
12024 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
12025 
12026 /* Bit 1 : Request status for RR[1] register */
12027 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
12028 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
12029 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
12030 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
12031 
12032 /* Bit 0 : Request status for RR[0] register */
12033 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
12034 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
12035 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
12036 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
12037 
12038 /* Register: WDT_CRV */
12039 /* Description: Counter reload value */
12040 
12041 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
12042 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
12043 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
12044 
12045 /* Register: WDT_RREN */
12046 /* Description: Enable register for reload request registers */
12047 
12048 /* Bit 7 : Enable or disable RR[7] register */
12049 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
12050 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
12051 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
12052 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12053 
12054 /* Bit 6 : Enable or disable RR[6] register */
12055 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
12056 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
12057 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
12058 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12059 
12060 /* Bit 5 : Enable or disable RR[5] register */
12061 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
12062 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
12063 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
12064 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12065 
12066 /* Bit 4 : Enable or disable RR[4] register */
12067 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
12068 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
12069 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
12070 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12071 
12072 /* Bit 3 : Enable or disable RR[3] register */
12073 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
12074 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
12075 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
12076 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12077 
12078 /* Bit 2 : Enable or disable RR[2] register */
12079 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
12080 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
12081 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12082 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12083 
12084 /* Bit 1 : Enable or disable RR[1] register */
12085 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
12086 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
12087 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12088 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12089 
12090 /* Bit 0 : Enable or disable RR[0] register */
12091 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
12092 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
12093 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
12094 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
12095 
12096 /* Register: WDT_CONFIG */
12097 /* Description: Configuration register */
12098 
12099 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
12100 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
12101 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
12102 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
12103 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
12104 
12105 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
12106 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
12107 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
12108 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
12109 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
12110 
12111 /* Register: WDT_RR */
12112 /* Description: Description collection: Reload request n */
12113 
12114 /* Bits 31..0 : Reload request register */
12115 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
12116 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
12117 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
12118 
12119 
12120 /*lint --flb "Leave library region" */
12121 #endif
12122