1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52820.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:03 37 * from File 'nrf52820.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52820 49 * @{ 50 */ 51 52 53 #ifndef NRF52820_H 54 #define NRF52820_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52820 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 91 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 92 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95 RTC0_IRQn = 11, /*!< 11 RTC0 */ 96 TEMP_IRQn = 12, /*!< 12 TEMP */ 97 RNG_IRQn = 13, /*!< 13 RNG */ 98 ECB_IRQn = 14, /*!< 14 ECB */ 99 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100 WDT_IRQn = 16, /*!< 16 WDT */ 101 RTC1_IRQn = 17, /*!< 17 RTC1 */ 102 QDEC_IRQn = 18, /*!< 18 QDEC */ 103 COMP_IRQn = 19, /*!< 19 COMP */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111 USBD_IRQn = 39 /*!< 39 USBD */ 112 } IRQn_Type; 113 114 115 116 /* =========================================================================================================================== */ 117 /* ================ Processor and Core Peripheral Section ================ */ 118 /* =========================================================================================================================== */ 119 120 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 121 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 122 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 123 #define __DSP_PRESENT 1 /*!< DSP present or not */ 124 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 125 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 126 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 127 #define __MPU_PRESENT 1 /*!< MPU present */ 128 #define __FPU_PRESENT 0 /*!< FPU present */ 129 130 131 /** @} */ /* End of group Configuration_of_CMSIS */ 132 133 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 134 #include "system_nrf52820.h" /*!< nrf52820 System */ 135 136 #ifndef __IM /*!< Fallback for older CMSIS versions */ 137 #define __IM __I 138 #endif 139 #ifndef __OM /*!< Fallback for older CMSIS versions */ 140 #define __OM __O 141 #endif 142 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 143 #define __IOM __IO 144 #endif 145 146 147 /* ======================================== Start of section using anonymous unions ======================================== */ 148 #if defined (__CC_ARM) 149 #pragma push 150 #pragma anon_unions 151 #elif defined (__ICCARM__) 152 #pragma language=extended 153 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 154 #pragma clang diagnostic push 155 #pragma clang diagnostic ignored "-Wc11-extensions" 156 #pragma clang diagnostic ignored "-Wreserved-id-macro" 157 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 158 #pragma clang diagnostic ignored "-Wnested-anon-types" 159 #elif defined (__GNUC__) 160 /* anonymous unions are enabled by default */ 161 #elif defined (__TMS470__) 162 /* anonymous unions are enabled by default */ 163 #elif defined (__TASKING__) 164 #pragma warning 586 165 #elif defined (__CSMC__) 166 /* anonymous unions are enabled by default */ 167 #else 168 #warning Not supported compiler type 169 #endif 170 171 172 /* =========================================================================================================================== */ 173 /* ================ Device Specific Cluster Section ================ */ 174 /* =========================================================================================================================== */ 175 176 177 /** @addtogroup Device_Peripheral_clusters 178 * @{ 179 */ 180 181 182 /** 183 * @brief FICR_INFO [INFO] (Device info) 184 */ 185 typedef struct { 186 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 187 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 188 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 189 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 190 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 191 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 192 193 194 /** 195 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 196 */ 197 typedef struct { 198 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 199 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 200 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 201 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 202 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 203 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 204 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 205 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 206 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 207 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 208 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 209 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 210 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 211 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 212 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 213 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 214 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 215 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 216 217 218 /** 219 * @brief POWER_RAM [RAM] (Unspecified) 220 */ 221 typedef struct { 222 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 223 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 224 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 225 register */ 226 __IM uint32_t RESERVED; 227 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 228 229 230 /** 231 * @brief RADIO_PSEL [PSEL] (Unspecified) 232 */ 233 typedef struct { 234 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 235 n */ 236 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 237 238 239 /** 240 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 241 */ 242 typedef struct { 243 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 244 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 245 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 246 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 247 248 249 /** 250 * @brief UART_PSEL [PSEL] (Unspecified) 251 */ 252 typedef struct { 253 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 254 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 255 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 256 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 257 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 258 259 260 /** 261 * @brief UARTE_PSEL [PSEL] (Unspecified) 262 */ 263 typedef struct { 264 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 265 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 266 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 267 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 268 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 269 270 271 /** 272 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 273 */ 274 typedef struct { 275 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 276 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 277 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 278 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 279 280 281 /** 282 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 283 */ 284 typedef struct { 285 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 286 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 287 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 288 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 289 290 291 /** 292 * @brief SPI_PSEL [PSEL] (Unspecified) 293 */ 294 typedef struct { 295 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 296 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 297 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 298 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 299 300 301 /** 302 * @brief SPIM_PSEL [PSEL] (Unspecified) 303 */ 304 typedef struct { 305 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 306 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 307 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 308 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 309 310 311 /** 312 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 313 */ 314 typedef struct { 315 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 316 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 317 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 318 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 319 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 320 321 322 /** 323 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 324 */ 325 typedef struct { 326 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 327 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 328 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 329 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 330 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 331 332 333 /** 334 * @brief SPIS_PSEL [PSEL] (Unspecified) 335 */ 336 typedef struct { 337 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 338 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 339 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 340 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 341 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 342 343 344 /** 345 * @brief SPIS_RXD [RXD] (Unspecified) 346 */ 347 typedef struct { 348 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 349 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 350 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 351 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 352 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 353 354 355 /** 356 * @brief SPIS_TXD [TXD] (Unspecified) 357 */ 358 typedef struct { 359 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 360 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 361 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 362 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 363 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 364 365 366 /** 367 * @brief TWI_PSEL [PSEL] (Unspecified) 368 */ 369 typedef struct { 370 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 371 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 372 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 373 374 375 /** 376 * @brief TWIM_PSEL [PSEL] (Unspecified) 377 */ 378 typedef struct { 379 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 380 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 381 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 382 383 384 /** 385 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 386 */ 387 typedef struct { 388 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 389 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 390 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 391 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 392 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 393 394 395 /** 396 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 397 */ 398 typedef struct { 399 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 400 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 401 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 402 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 403 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 404 405 406 /** 407 * @brief TWIS_PSEL [PSEL] (Unspecified) 408 */ 409 typedef struct { 410 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 411 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 412 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 413 414 415 /** 416 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 417 */ 418 typedef struct { 419 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 420 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 421 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 422 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 423 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 424 425 426 /** 427 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 428 */ 429 typedef struct { 430 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 431 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 432 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 433 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 434 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 435 436 437 /** 438 * @brief QDEC_PSEL [PSEL] (Unspecified) 439 */ 440 typedef struct { 441 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 442 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 443 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 444 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 445 446 447 /** 448 * @brief ACL_ACL [ACL] (Unspecified) 449 */ 450 typedef struct { 451 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region 452 to protect. The start address must be word-aligned. */ 453 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 454 counting from address ACL[n].ADDR. Writing 455 a '0' has no effect. */ 456 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 457 n as defined by start address ACL[n].ADDR 458 and size ACL[n].SIZE */ 459 __IM uint32_t RESERVED; 460 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 461 462 463 /** 464 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 465 */ 466 typedef struct { 467 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 468 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 469 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 470 471 472 /** 473 * @brief PPI_CH [CH] (PPI Channel) 474 */ 475 typedef struct { 476 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 477 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 478 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 479 480 481 /** 482 * @brief PPI_FORK [FORK] (Fork) 483 */ 484 typedef struct { 485 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 486 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 487 488 489 /** 490 * @brief USBD_HALTED [HALTED] (Unspecified) 491 */ 492 typedef struct { 493 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 494 Can be used as is as response to a GetStatus() 495 request to endpoint. */ 496 __IM uint32_t RESERVED; 497 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 498 Can be used as is as response to a GetStatus() 499 request to endpoint. */ 500 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 501 502 503 /** 504 * @brief USBD_SIZE [SIZE] (Unspecified) 505 */ 506 typedef struct { 507 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 508 last in the data stage of this OUT endpoint */ 509 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 510 data endpoint */ 511 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 512 513 514 /** 515 * @brief USBD_EPIN [EPIN] (Unspecified) 516 */ 517 typedef struct { 518 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 519 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 520 to transfer */ 521 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 522 in the last transaction */ 523 __IM uint32_t RESERVED[2]; 524 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 525 526 527 /** 528 * @brief USBD_ISOIN [ISOIN] (Unspecified) 529 */ 530 typedef struct { 531 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 532 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 533 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 534 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 535 536 537 /** 538 * @brief USBD_EPOUT [EPOUT] (Unspecified) 539 */ 540 typedef struct { 541 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 542 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 543 to transfer */ 544 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 545 in the last transaction */ 546 __IM uint32_t RESERVED[2]; 547 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 548 549 550 /** 551 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 552 */ 553 typedef struct { 554 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 555 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 556 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 557 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 558 559 560 /** @} */ /* End of group Device_Peripheral_clusters */ 561 562 563 /* =========================================================================================================================== */ 564 /* ================ Device Specific Peripheral Section ================ */ 565 /* =========================================================================================================================== */ 566 567 568 /** @addtogroup Device_Peripheral_peripherals 569 * @{ 570 */ 571 572 573 574 /* =========================================================================================================================== */ 575 /* ================ FICR ================ */ 576 /* =========================================================================================================================== */ 577 578 579 /** 580 * @brief Factory information configuration registers (FICR) 581 */ 582 583 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 584 __IM uint32_t RESERVED[4]; 585 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 586 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 587 __IM uint32_t RESERVED1[18]; 588 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 589 __IM uint32_t RESERVED2[6]; 590 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 591 n */ 592 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ 593 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 594 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 595 __IM uint32_t RESERVED3[21]; 596 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 597 __IM uint32_t RESERVED4[143]; 598 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature 599 n */ 600 __IM uint32_t RESERVED5[42]; 601 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 602 coefficients */ 603 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 604 605 606 607 /* =========================================================================================================================== */ 608 /* ================ UICR ================ */ 609 /* =========================================================================================================================== */ 610 611 612 /** 613 * @brief User information configuration registers (UICR) 614 */ 615 616 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 617 __IM uint32_t RESERVED[5]; 618 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 619 design */ 620 __IM uint32_t RESERVED1[2]; 621 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 622 design */ 623 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 624 __IM uint32_t RESERVED2[64]; 625 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 626 function (see POWER chapter for details) */ 627 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 628 __IM uint32_t RESERVED3; 629 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 630 __IM uint32_t RESERVED4[60]; 631 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The 632 maximum output voltage from this stage is 633 given as VDDH - V_VDDH-VDD. */ 634 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 635 636 637 638 /* =========================================================================================================================== */ 639 /* ================ APPROTECT ================ */ 640 /* =========================================================================================================================== */ 641 642 643 /** 644 * @brief Access Port Protection (APPROTECT) 645 */ 646 647 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 648 __IM uint32_t RESERVED[340]; 649 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 650 next reset. */ 651 __IM uint32_t RESERVED1; 652 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 653 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 654 655 656 657 /* =========================================================================================================================== */ 658 /* ================ CLOCK ================ */ 659 /* =========================================================================================================================== */ 660 661 662 /** 663 * @brief Clock control (CLOCK) 664 */ 665 666 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 667 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 668 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 669 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 670 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 671 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 672 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 673 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 674 __IM uint32_t RESERVED[57]; 675 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 676 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 677 __IM uint32_t RESERVED1; 678 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 679 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 680 __IM uint32_t RESERVED2[5]; 681 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 682 to process new tasks */ 683 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 684 to process new tasks */ 685 __IM uint32_t RESERVED3[117]; 686 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 687 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 688 __IM uint32_t RESERVED4[63]; 689 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 690 triggered */ 691 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 692 __IM uint32_t RESERVED5; 693 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 694 triggered */ 695 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 696 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 697 task was triggered */ 698 __IM uint32_t RESERVED6[62]; 699 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 700 __IM uint32_t RESERVED7[3]; 701 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 702 the TASKS_HFCLKSTART task. */ 703 __IOM uint32_t LFXODEBOUNCE; /*!< (@ 0x0000052C) LFXO debounce time. The LFXO is started by triggering 704 the TASKS_LFCLKSTART task when the LFCLKSRC 705 register is configured for Xtal. */ 706 __IM uint32_t RESERVED8[2]; 707 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 708 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 709 710 711 712 /* =========================================================================================================================== */ 713 /* ================ POWER ================ */ 714 /* =========================================================================================================================== */ 715 716 717 /** 718 * @brief Power control (POWER) 719 */ 720 721 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 722 __IM uint32_t RESERVED[30]; 723 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 724 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 725 __IM uint32_t RESERVED1[34]; 726 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 727 __IM uint32_t RESERVED2[2]; 728 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 729 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 730 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 731 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 732 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 733 __IM uint32_t RESERVED3[119]; 734 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 735 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 736 __IM uint32_t RESERVED4[61]; 737 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 738 __IM uint32_t RESERVED5[9]; 739 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 740 __IM uint32_t RESERVED6[3]; 741 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 742 __IM uint32_t RESERVED7[49]; 743 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 744 __IM uint32_t RESERVED8[3]; 745 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 746 __IM uint32_t RESERVED9[2]; 747 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 748 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 749 __IM uint32_t RESERVED10[21]; 750 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ 751 __IM uint32_t RESERVED11[49]; 752 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 753 __IM uint32_t RESERVED12[175]; 754 __IOM POWER_RAM_Type RAM[4]; /*!< (@ 0x00000900) Unspecified */ 755 } NRF_POWER_Type; /*!< Size = 2368 (0x940) */ 756 757 758 759 /* =========================================================================================================================== */ 760 /* ================ P0 ================ */ 761 /* =========================================================================================================================== */ 762 763 764 /** 765 * @brief GPIO Port 1 (P0) 766 */ 767 768 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 769 __IM uint32_t RESERVED[321]; 770 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 771 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 772 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 773 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 774 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 775 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 776 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 777 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 778 have met the criteria set in the PIN_CNF[n].SENSE 779 registers */ 780 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 781 and LDETECT mode */ 782 __IM uint32_t RESERVED1[118]; 783 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 784 pins */ 785 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 786 787 788 789 /* =========================================================================================================================== */ 790 /* ================ RADIO ================ */ 791 /* =========================================================================================================================== */ 792 793 794 /** 795 * @brief 2.4 GHz radio (RADIO) 796 */ 797 798 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 799 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 800 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 801 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 802 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 803 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 804 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 805 the receive signal strength */ 806 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 807 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 808 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 809 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 810 802.15.4 mode */ 811 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 812 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 813 802.15.4 mode */ 814 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 815 __IM uint32_t RESERVED[51]; 816 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 817 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 818 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 819 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 820 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 821 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 822 packet */ 823 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 824 received packet */ 825 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 826 __IM uint32_t RESERVED1[2]; 827 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 828 __IM uint32_t RESERVED2; 829 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 830 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 831 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 832 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 833 ED sample is ready for readout from the 834 RADIO.EDSAMPLE register. */ 835 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 836 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 837 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 838 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 839 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 840 from Ble_LR125Kbit to Ble_LR500Kbit. */ 841 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 842 TX path */ 843 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 844 RX path */ 845 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 846 __IM uint32_t RESERVED3[2]; 847 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 848 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 849 from air */ 850 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 851 CTEInfo byte) */ 852 __IM uint32_t RESERVED4[35]; 853 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 854 __IM uint32_t RESERVED5[64]; 855 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 856 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 857 __IM uint32_t RESERVED6[61]; 858 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 859 __IM uint32_t RESERVED7; 860 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 861 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 862 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 863 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 864 __IM uint32_t RESERVED8[13]; 865 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 866 __IM uint32_t RESERVED9[2]; 867 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 868 __IM uint32_t RESERVED10[42]; 869 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 870 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 871 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 872 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 873 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 874 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 875 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 876 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 877 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 878 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 879 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 880 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 881 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 882 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 883 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 884 __IM uint32_t RESERVED11; 885 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 886 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 887 __IM uint32_t RESERVED12; 888 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 889 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 890 __IM uint32_t RESERVED13[2]; 891 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 892 __IM uint32_t RESERVED14[39]; 893 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 894 n */ 895 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 896 n */ 897 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 898 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 899 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 900 __IM uint32_t RESERVED15; 901 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 902 __IM uint32_t RESERVED16[3]; 903 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 904 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 905 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 906 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 907 __IM uint32_t RESERVED17[164]; 908 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 909 (AOD) */ 910 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 911 __IM uint32_t RESERVED18[2]; 912 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 913 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 914 __IM uint32_t RESERVED19[4]; 915 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 916 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 917 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 918 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 919 __IM uint32_t RESERVED20[424]; 920 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 921 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 922 923 924 925 /* =========================================================================================================================== */ 926 /* ================ UART0 ================ */ 927 /* =========================================================================================================================== */ 928 929 930 /** 931 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 932 */ 933 934 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 935 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 936 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 937 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 938 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 939 __IM uint32_t RESERVED[3]; 940 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 941 __IM uint32_t RESERVED1[56]; 942 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 943 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 944 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 945 __IM uint32_t RESERVED2[4]; 946 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 947 __IM uint32_t RESERVED3; 948 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 949 __IM uint32_t RESERVED4[7]; 950 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 951 __IM uint32_t RESERVED5[46]; 952 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 953 __IM uint32_t RESERVED6[64]; 954 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 955 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 956 __IM uint32_t RESERVED7[93]; 957 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 958 __IM uint32_t RESERVED8[31]; 959 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 960 __IM uint32_t RESERVED9; 961 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 962 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 963 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 964 __IM uint32_t RESERVED10; 965 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 966 selected. */ 967 __IM uint32_t RESERVED11[17]; 968 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 969 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 970 971 972 973 /* =========================================================================================================================== */ 974 /* ================ UARTE0 ================ */ 975 /* =========================================================================================================================== */ 976 977 978 /** 979 * @brief UART with EasyDMA (UARTE0) 980 */ 981 982 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 983 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 984 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 985 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 986 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 987 __IM uint32_t RESERVED[7]; 988 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 989 __IM uint32_t RESERVED1[52]; 990 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 991 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 992 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 993 transferred to Data RAM) */ 994 __IM uint32_t RESERVED2; 995 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 996 __IM uint32_t RESERVED3[2]; 997 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 998 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 999 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1000 __IM uint32_t RESERVED4[7]; 1001 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1002 __IM uint32_t RESERVED5; 1003 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1004 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1005 __IM uint32_t RESERVED6; 1006 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1007 __IM uint32_t RESERVED7[41]; 1008 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1009 __IM uint32_t RESERVED8[63]; 1010 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1011 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1012 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1013 __IM uint32_t RESERVED9[93]; 1014 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1015 to clear. */ 1016 __IM uint32_t RESERVED10[31]; 1017 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1018 __IM uint32_t RESERVED11; 1019 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1020 __IM uint32_t RESERVED12[3]; 1021 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1022 selected. */ 1023 __IM uint32_t RESERVED13[3]; 1024 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1025 __IM uint32_t RESERVED14; 1026 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1027 __IM uint32_t RESERVED15[7]; 1028 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1029 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1030 1031 1032 1033 /* =========================================================================================================================== */ 1034 /* ================ SPI0 ================ */ 1035 /* =========================================================================================================================== */ 1036 1037 1038 /** 1039 * @brief Serial Peripheral Interface 0 (SPI0) 1040 */ 1041 1042 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1043 __IM uint32_t RESERVED[66]; 1044 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1045 __IM uint32_t RESERVED1[126]; 1046 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1047 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1048 __IM uint32_t RESERVED2[125]; 1049 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1050 __IM uint32_t RESERVED3; 1051 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1052 __IM uint32_t RESERVED4; 1053 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1054 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1055 __IM uint32_t RESERVED5; 1056 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1057 source selected. */ 1058 __IM uint32_t RESERVED6[11]; 1059 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1060 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1061 1062 1063 1064 /* =========================================================================================================================== */ 1065 /* ================ SPIM0 ================ */ 1066 /* =========================================================================================================================== */ 1067 1068 1069 /** 1070 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1071 */ 1072 1073 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1074 __IM uint32_t RESERVED[4]; 1075 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1076 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1077 __IM uint32_t RESERVED1; 1078 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1079 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1080 __IM uint32_t RESERVED2[56]; 1081 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1082 __IM uint32_t RESERVED3[2]; 1083 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1084 __IM uint32_t RESERVED4; 1085 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1086 __IM uint32_t RESERVED5; 1087 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1088 __IM uint32_t RESERVED6[10]; 1089 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1090 __IM uint32_t RESERVED7[44]; 1091 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1092 __IM uint32_t RESERVED8[64]; 1093 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1094 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1095 __IM uint32_t RESERVED9[125]; 1096 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1097 __IM uint32_t RESERVED10; 1098 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1099 __IM uint32_t RESERVED11[4]; 1100 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1101 source selected. */ 1102 __IM uint32_t RESERVED12[3]; 1103 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1104 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1105 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1106 __IM uint32_t RESERVED13[26]; 1107 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1108 been transmitted in the case when RXD.MAXCNT 1109 is greater than TXD.MAXCNT */ 1110 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1111 1112 1113 1114 /* =========================================================================================================================== */ 1115 /* ================ SPIS0 ================ */ 1116 /* =========================================================================================================================== */ 1117 1118 1119 /** 1120 * @brief SPI Slave 0 (SPIS0) 1121 */ 1122 1123 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1124 __IM uint32_t RESERVED[9]; 1125 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1126 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1127 to acquire it */ 1128 __IM uint32_t RESERVED1[54]; 1129 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1130 __IM uint32_t RESERVED2[2]; 1131 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1132 __IM uint32_t RESERVED3[5]; 1133 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1134 __IM uint32_t RESERVED4[53]; 1135 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1136 __IM uint32_t RESERVED5[64]; 1137 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1138 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1139 __IM uint32_t RESERVED6[61]; 1140 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1141 __IM uint32_t RESERVED7[15]; 1142 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1143 __IM uint32_t RESERVED8[47]; 1144 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1145 __IM uint32_t RESERVED9; 1146 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1147 __IM uint32_t RESERVED10[7]; 1148 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1149 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1150 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1151 __IM uint32_t RESERVED11; 1152 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1153 of an ignored transaction. */ 1154 __IM uint32_t RESERVED12[24]; 1155 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1156 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1157 1158 1159 1160 /* =========================================================================================================================== */ 1161 /* ================ TWI0 ================ */ 1162 /* =========================================================================================================================== */ 1163 1164 1165 /** 1166 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1167 */ 1168 1169 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1170 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1171 __IM uint32_t RESERVED; 1172 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1173 __IM uint32_t RESERVED1[2]; 1174 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1175 __IM uint32_t RESERVED2; 1176 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1177 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1178 __IM uint32_t RESERVED3[56]; 1179 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1180 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1181 __IM uint32_t RESERVED4[4]; 1182 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1183 __IM uint32_t RESERVED5; 1184 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1185 __IM uint32_t RESERVED6[4]; 1186 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1187 that is sent or received */ 1188 __IM uint32_t RESERVED7[3]; 1189 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1190 __IM uint32_t RESERVED8[45]; 1191 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1192 __IM uint32_t RESERVED9[64]; 1193 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1194 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1195 __IM uint32_t RESERVED10[110]; 1196 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1197 __IM uint32_t RESERVED11[14]; 1198 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1199 __IM uint32_t RESERVED12; 1200 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1201 __IM uint32_t RESERVED13[2]; 1202 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1203 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1204 __IM uint32_t RESERVED14; 1205 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1206 source selected. */ 1207 __IM uint32_t RESERVED15[24]; 1208 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1209 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1210 1211 1212 1213 /* =========================================================================================================================== */ 1214 /* ================ TWIM0 ================ */ 1215 /* =========================================================================================================================== */ 1216 1217 1218 /** 1219 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1220 */ 1221 1222 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1223 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1224 __IM uint32_t RESERVED; 1225 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1226 __IM uint32_t RESERVED1[2]; 1227 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1228 TWI master is not suspended. */ 1229 __IM uint32_t RESERVED2; 1230 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1231 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1232 __IM uint32_t RESERVED3[56]; 1233 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1234 __IM uint32_t RESERVED4[7]; 1235 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1236 __IM uint32_t RESERVED5[8]; 1237 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1238 now suspended. */ 1239 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1240 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1241 __IM uint32_t RESERVED6[2]; 1242 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1243 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1244 byte */ 1245 __IM uint32_t RESERVED7[39]; 1246 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1247 __IM uint32_t RESERVED8[63]; 1248 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1249 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1250 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1251 __IM uint32_t RESERVED9[110]; 1252 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1253 __IM uint32_t RESERVED10[14]; 1254 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1255 __IM uint32_t RESERVED11; 1256 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1257 __IM uint32_t RESERVED12[5]; 1258 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1259 source selected. */ 1260 __IM uint32_t RESERVED13[3]; 1261 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1262 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1263 __IM uint32_t RESERVED14[13]; 1264 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1265 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1266 1267 1268 1269 /* =========================================================================================================================== */ 1270 /* ================ TWIS0 ================ */ 1271 /* =========================================================================================================================== */ 1272 1273 1274 /** 1275 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1276 */ 1277 1278 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1279 __IM uint32_t RESERVED[5]; 1280 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1281 __IM uint32_t RESERVED1; 1282 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1283 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1284 __IM uint32_t RESERVED2[3]; 1285 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1286 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1287 __IM uint32_t RESERVED3[51]; 1288 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1289 __IM uint32_t RESERVED4[7]; 1290 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1291 __IM uint32_t RESERVED5[9]; 1292 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1293 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1294 __IM uint32_t RESERVED6[4]; 1295 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1296 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1297 __IM uint32_t RESERVED7[37]; 1298 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1299 __IM uint32_t RESERVED8[63]; 1300 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1301 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1302 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1303 __IM uint32_t RESERVED9[113]; 1304 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1305 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1306 a match */ 1307 __IM uint32_t RESERVED10[10]; 1308 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1309 __IM uint32_t RESERVED11; 1310 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1311 __IM uint32_t RESERVED12[9]; 1312 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1313 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1314 __IM uint32_t RESERVED13[13]; 1315 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1316 __IM uint32_t RESERVED14; 1317 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1318 mechanism */ 1319 __IM uint32_t RESERVED15[10]; 1320 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1321 of an over-read of the transmit buffer. */ 1322 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1323 1324 1325 1326 /* =========================================================================================================================== */ 1327 /* ================ GPIOTE ================ */ 1328 /* =========================================================================================================================== */ 1329 1330 1331 /** 1332 * @brief GPIO Tasks and Events (GPIOTE) 1333 */ 1334 1335 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1336 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1337 specified in CONFIG[n].PSEL. Action on pin 1338 is configured in CONFIG[n].POLARITY. */ 1339 __IM uint32_t RESERVED[4]; 1340 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1341 specified in CONFIG[n].PSEL. Action on pin 1342 is to set it high. */ 1343 __IM uint32_t RESERVED1[4]; 1344 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1345 specified in CONFIG[n].PSEL. Action on pin 1346 is to set it low. */ 1347 __IM uint32_t RESERVED2[32]; 1348 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1349 pin specified in CONFIG[n].PSEL */ 1350 __IM uint32_t RESERVED3[23]; 1351 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1352 with SENSE mechanism enabled */ 1353 __IM uint32_t RESERVED4[97]; 1354 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1355 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1356 __IM uint32_t RESERVED5[129]; 1357 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1358 SET[n], and CLR[n] tasks and IN[n] event */ 1359 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1360 1361 1362 1363 /* =========================================================================================================================== */ 1364 /* ================ TIMER0 ================ */ 1365 /* =========================================================================================================================== */ 1366 1367 1368 /** 1369 * @brief Timer/Counter 0 (TIMER0) 1370 */ 1371 1372 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1373 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1374 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1375 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1376 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1377 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1378 __IM uint32_t RESERVED[11]; 1379 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1380 CC[n] register */ 1381 __IM uint32_t RESERVED1[58]; 1382 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1383 match */ 1384 __IM uint32_t RESERVED2[42]; 1385 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1386 __IM uint32_t RESERVED3[64]; 1387 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1388 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1389 __IM uint32_t RESERVED4[126]; 1390 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1391 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1392 __IM uint32_t RESERVED5; 1393 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1394 __IM uint32_t RESERVED6[11]; 1395 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1396 n */ 1397 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1398 1399 1400 1401 /* =========================================================================================================================== */ 1402 /* ================ RTC0 ================ */ 1403 /* =========================================================================================================================== */ 1404 1405 1406 /** 1407 * @brief Real time counter 0 (RTC0) 1408 */ 1409 1410 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1411 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1412 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1413 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1414 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1415 __IM uint32_t RESERVED[60]; 1416 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1417 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1418 __IM uint32_t RESERVED1[14]; 1419 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1420 match */ 1421 __IM uint32_t RESERVED2[109]; 1422 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1423 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1424 __IM uint32_t RESERVED3[13]; 1425 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1426 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1427 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1428 __IM uint32_t RESERVED4[110]; 1429 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1430 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 1431 Must be written when RTC is stopped. */ 1432 __IM uint32_t RESERVED5[13]; 1433 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1434 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1435 1436 1437 1438 /* =========================================================================================================================== */ 1439 /* ================ TEMP ================ */ 1440 /* =========================================================================================================================== */ 1441 1442 1443 /** 1444 * @brief Temperature Sensor (TEMP) 1445 */ 1446 1447 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1448 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1449 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1450 __IM uint32_t RESERVED[62]; 1451 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1452 __IM uint32_t RESERVED1[128]; 1453 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1454 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1455 __IM uint32_t RESERVED2[127]; 1456 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1457 __IM uint32_t RESERVED3[5]; 1458 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1459 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1460 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1461 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1462 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1463 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1464 __IM uint32_t RESERVED4[2]; 1465 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1466 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1467 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1468 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1469 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1470 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1471 __IM uint32_t RESERVED5[2]; 1472 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1473 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1474 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1475 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1476 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1477 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1478 1479 1480 1481 /* =========================================================================================================================== */ 1482 /* ================ RNG ================ */ 1483 /* =========================================================================================================================== */ 1484 1485 1486 /** 1487 * @brief Random Number Generator (RNG) 1488 */ 1489 1490 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1491 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1492 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1493 __IM uint32_t RESERVED[62]; 1494 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1495 written to the VALUE register */ 1496 __IM uint32_t RESERVED1[63]; 1497 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1498 __IM uint32_t RESERVED2[64]; 1499 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1500 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1501 __IM uint32_t RESERVED3[126]; 1502 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1503 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1504 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1505 1506 1507 1508 /* =========================================================================================================================== */ 1509 /* ================ ECB ================ */ 1510 /* =========================================================================================================================== */ 1511 1512 1513 /** 1514 * @brief AES ECB Mode Encryption (ECB) 1515 */ 1516 1517 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1518 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1519 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1520 __IM uint32_t RESERVED[62]; 1521 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1522 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1523 task or due to an error */ 1524 __IM uint32_t RESERVED1[127]; 1525 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1526 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1527 __IM uint32_t RESERVED2[126]; 1528 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1529 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1530 1531 1532 1533 /* =========================================================================================================================== */ 1534 /* ================ AAR ================ */ 1535 /* =========================================================================================================================== */ 1536 1537 1538 /** 1539 * @brief Accelerated Address Resolver (AAR) 1540 */ 1541 1542 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1543 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1544 in the IRK data structure */ 1545 __IM uint32_t RESERVED; 1546 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1547 __IM uint32_t RESERVED1[61]; 1548 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1549 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1550 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1551 __IM uint32_t RESERVED2[126]; 1552 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1553 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1554 __IM uint32_t RESERVED3[61]; 1555 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1556 __IM uint32_t RESERVED4[63]; 1557 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1558 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1559 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1560 __IM uint32_t RESERVED5; 1561 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1562 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1563 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1564 1565 1566 1567 /* =========================================================================================================================== */ 1568 /* ================ CCM ================ */ 1569 /* =========================================================================================================================== */ 1570 1571 1572 /** 1573 * @brief AES CCM mode encryption (CCM) 1574 */ 1575 1576 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1577 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1578 will stop by itself when completed. */ 1579 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1580 stop by itself when completed. */ 1581 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1582 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1583 the contents of the RATEOVERRIDE register 1584 for any ongoing encryption/decryption */ 1585 __IM uint32_t RESERVED[60]; 1586 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1587 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1588 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1589 __IM uint32_t RESERVED1[61]; 1590 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1591 __IM uint32_t RESERVED2[64]; 1592 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1593 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1594 __IM uint32_t RESERVED3[61]; 1595 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1596 __IM uint32_t RESERVED4[63]; 1597 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1598 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1599 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 1600 and the NONCE vector */ 1601 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1602 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1603 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1604 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1605 = Extended */ 1606 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1607 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 1608 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 1609 1610 1611 1612 /* =========================================================================================================================== */ 1613 /* ================ WDT ================ */ 1614 /* =========================================================================================================================== */ 1615 1616 1617 /** 1618 * @brief Watchdog Timer (WDT) 1619 */ 1620 1621 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1622 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1623 __IM uint32_t RESERVED[63]; 1624 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1625 __IM uint32_t RESERVED1[128]; 1626 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1627 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1628 __IM uint32_t RESERVED2[61]; 1629 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1630 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1631 __IM uint32_t RESERVED3[63]; 1632 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1633 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1634 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1635 __IM uint32_t RESERVED4[60]; 1636 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1637 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1638 1639 1640 1641 /* =========================================================================================================================== */ 1642 /* ================ QDEC ================ */ 1643 /* =========================================================================================================================== */ 1644 1645 1646 /** 1647 * @brief Quadrature Decoder (QDEC) 1648 */ 1649 1650 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1651 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1652 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1653 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1654 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1655 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1656 __IM uint32_t RESERVED[59]; 1657 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1658 written to the SAMPLE register */ 1659 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1660 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1661 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1662 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1663 __IM uint32_t RESERVED1[59]; 1664 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1665 __IM uint32_t RESERVED2[64]; 1666 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1667 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1668 __IM uint32_t RESERVED3[125]; 1669 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1670 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1671 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1672 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1673 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1674 and DBLRDY events can be generated */ 1675 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1676 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1677 READCLRACC or RDCLRACC task */ 1678 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1679 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1680 __IM uint32_t RESERVED4[5]; 1681 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1682 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1683 double transitions */ 1684 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1685 or RDCLRDBL task */ 1686 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1687 1688 1689 1690 /* =========================================================================================================================== */ 1691 /* ================ COMP ================ */ 1692 /* =========================================================================================================================== */ 1693 1694 1695 /** 1696 * @brief Comparator (COMP) 1697 */ 1698 1699 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1700 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1701 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1702 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1703 __IM uint32_t RESERVED[61]; 1704 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1705 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1706 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1707 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1708 __IM uint32_t RESERVED1[60]; 1709 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1710 __IM uint32_t RESERVED2[63]; 1711 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1712 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1713 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1714 __IM uint32_t RESERVED3[61]; 1715 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1716 __IM uint32_t RESERVED4[63]; 1717 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1718 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1719 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1720 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1721 __IM uint32_t RESERVED5[8]; 1722 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1723 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1724 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1725 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 1726 1727 1728 1729 /* =========================================================================================================================== */ 1730 /* ================ EGU0 ================ */ 1731 /* =========================================================================================================================== */ 1732 1733 1734 /** 1735 * @brief Event generator unit 0 (EGU0) 1736 */ 1737 1738 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1739 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1740 the corresponding TRIGGERED[n] event */ 1741 __IM uint32_t RESERVED[48]; 1742 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1743 by triggering the corresponding TRIGGER[n] 1744 task */ 1745 __IM uint32_t RESERVED1[112]; 1746 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1747 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1748 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1749 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1750 1751 1752 1753 /* =========================================================================================================================== */ 1754 /* ================ SWI0 ================ */ 1755 /* =========================================================================================================================== */ 1756 1757 1758 /** 1759 * @brief Software interrupt 0 (SWI0) 1760 */ 1761 1762 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1763 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1764 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1765 1766 1767 1768 /* =========================================================================================================================== */ 1769 /* ================ ACL ================ */ 1770 /* =========================================================================================================================== */ 1771 1772 1773 /** 1774 * @brief Access control lists (ACL) 1775 */ 1776 1777 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 1778 __IM uint32_t RESERVED[512]; 1779 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 1780 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 1781 1782 1783 1784 /* =========================================================================================================================== */ 1785 /* ================ NVMC ================ */ 1786 /* =========================================================================================================================== */ 1787 1788 1789 /** 1790 * @brief Non Volatile Memory Controller (NVMC) 1791 */ 1792 1793 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1794 __IM uint32_t RESERVED[256]; 1795 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1796 __IM uint32_t RESERVED1; 1797 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1798 __IM uint32_t RESERVED2[62]; 1799 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1800 1801 union { 1802 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1803 __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1804 page in code area, equivalent to ERASEPAGE */ 1805 }; 1806 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1807 __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1808 page in code area, equivalent to ERASEPAGE */ 1809 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1810 registers */ 1811 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1812 area */ 1813 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1814 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1815 1816 1817 1818 /* =========================================================================================================================== */ 1819 /* ================ PPI ================ */ 1820 /* =========================================================================================================================== */ 1821 1822 1823 /** 1824 * @brief Programmable Peripheral Interconnect (PPI) 1825 */ 1826 1827 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1828 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1829 __IM uint32_t RESERVED[308]; 1830 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1831 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1832 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1833 __IM uint32_t RESERVED1; 1834 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 1835 __IM uint32_t RESERVED2[148]; 1836 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 1837 __IM uint32_t RESERVED3[62]; 1838 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1839 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1840 1841 1842 1843 /* =========================================================================================================================== */ 1844 /* ================ USBD ================ */ 1845 /* =========================================================================================================================== */ 1846 1847 1848 /** 1849 * @brief Universal serial bus device (USBD) 1850 */ 1851 1852 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 1853 __IM uint32_t RESERVED; 1854 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 1855 and EPIN[n].MAXCNT registers values, and 1856 enables endpoint IN n to respond to traffic 1857 from host */ 1858 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 1859 values, and enables sending data on ISO 1860 endpoint */ 1861 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 1862 and EPOUT[n].MAXCNT registers values, and 1863 enables endpoint n to respond to traffic 1864 from host */ 1865 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 1866 values, and enables receiving of data on 1867 ISO endpoint */ 1868 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 1869 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 1870 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 1871 0 */ 1872 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 1873 in the DPDMVALUE register */ 1874 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 1875 (USB engine takes control) */ 1876 __IM uint32_t RESERVED1[40]; 1877 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 1878 on USB lines */ 1879 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 1880 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 1881 have been captured on all endpoints reported 1882 in the EPSTATUS register */ 1883 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 1884 has been consumed. The buffer can be accessed 1885 safely by software. */ 1886 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 1887 on the control endpoint */ 1888 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 1889 buffer can be accessed safely by software. */ 1890 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 1891 has been consumed. The buffer can be accessed 1892 safely by software. */ 1893 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 1894 buffer can be accessed safely by software. */ 1895 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 1896 has been detected on USB lines */ 1897 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 1898 events has occurred. Check EVENTCAUSE register 1899 to find the cause. */ 1900 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 1901 on the control endpoint */ 1902 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 1903 indicated by the EPDATASTATUS register */ 1904 __IM uint32_t RESERVED2[39]; 1905 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1906 __IM uint32_t RESERVED3[63]; 1907 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1908 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1909 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1910 __IM uint32_t RESERVED4[61]; 1911 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 1912 __IM uint32_t RESERVED5[7]; 1913 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 1914 __IM uint32_t RESERVED6; 1915 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 1916 registers have been captured */ 1917 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 1918 acknowledged data transfer has occurred 1919 (EPDATA event) */ 1920 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 1921 __IM uint32_t RESERVED7[3]; 1922 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 1923 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 1924 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 1925 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 1926 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 1927 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 1928 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 1929 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 1930 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 1931 __IM uint32_t RESERVED8[15]; 1932 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 1933 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 1934 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 1935 the DPDMDRIVE task. The DPDMNODRIVE task 1936 reverts the control of the lines to MAC 1937 IP (no forcing). */ 1938 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 1939 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 1940 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 1941 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 1942 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 1943 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 1944 counter */ 1945 __IM uint32_t RESERVED9[2]; 1946 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 1947 USB suspend */ 1948 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 1949 to an IN token when no data is ready to 1950 be sent */ 1951 __IM uint32_t RESERVED10[51]; 1952 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 1953 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 1954 __IM uint32_t RESERVED11[21]; 1955 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 1956 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 1957 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 1958 1959 1960 /** @} */ /* End of group Device_Peripheral_peripherals */ 1961 1962 1963 /* =========================================================================================================================== */ 1964 /* ================ Device Specific Peripheral Address Map ================ */ 1965 /* =========================================================================================================================== */ 1966 1967 1968 /** @addtogroup Device_Peripheral_peripheralAddr 1969 * @{ 1970 */ 1971 1972 #define NRF_FICR_BASE 0x10000000UL 1973 #define NRF_UICR_BASE 0x10001000UL 1974 #define NRF_APPROTECT_BASE 0x40000000UL 1975 #define NRF_CLOCK_BASE 0x40000000UL 1976 #define NRF_POWER_BASE 0x40000000UL 1977 #define NRF_P0_BASE 0x50000000UL 1978 #define NRF_RADIO_BASE 0x40001000UL 1979 #define NRF_UART0_BASE 0x40002000UL 1980 #define NRF_UARTE0_BASE 0x40002000UL 1981 #define NRF_SPI0_BASE 0x40003000UL 1982 #define NRF_SPIM0_BASE 0x40003000UL 1983 #define NRF_SPIS0_BASE 0x40003000UL 1984 #define NRF_TWI0_BASE 0x40003000UL 1985 #define NRF_TWIM0_BASE 0x40003000UL 1986 #define NRF_TWIS0_BASE 0x40003000UL 1987 #define NRF_SPI1_BASE 0x40004000UL 1988 #define NRF_SPIM1_BASE 0x40004000UL 1989 #define NRF_SPIS1_BASE 0x40004000UL 1990 #define NRF_TWI1_BASE 0x40004000UL 1991 #define NRF_TWIM1_BASE 0x40004000UL 1992 #define NRF_TWIS1_BASE 0x40004000UL 1993 #define NRF_GPIOTE_BASE 0x40006000UL 1994 #define NRF_TIMER0_BASE 0x40008000UL 1995 #define NRF_TIMER1_BASE 0x40009000UL 1996 #define NRF_TIMER2_BASE 0x4000A000UL 1997 #define NRF_RTC0_BASE 0x4000B000UL 1998 #define NRF_TEMP_BASE 0x4000C000UL 1999 #define NRF_RNG_BASE 0x4000D000UL 2000 #define NRF_ECB_BASE 0x4000E000UL 2001 #define NRF_AAR_BASE 0x4000F000UL 2002 #define NRF_CCM_BASE 0x4000F000UL 2003 #define NRF_WDT_BASE 0x40010000UL 2004 #define NRF_RTC1_BASE 0x40011000UL 2005 #define NRF_QDEC_BASE 0x40012000UL 2006 #define NRF_COMP_BASE 0x40013000UL 2007 #define NRF_EGU0_BASE 0x40014000UL 2008 #define NRF_SWI0_BASE 0x40014000UL 2009 #define NRF_EGU1_BASE 0x40015000UL 2010 #define NRF_SWI1_BASE 0x40015000UL 2011 #define NRF_EGU2_BASE 0x40016000UL 2012 #define NRF_SWI2_BASE 0x40016000UL 2013 #define NRF_EGU3_BASE 0x40017000UL 2014 #define NRF_SWI3_BASE 0x40017000UL 2015 #define NRF_EGU4_BASE 0x40018000UL 2016 #define NRF_SWI4_BASE 0x40018000UL 2017 #define NRF_EGU5_BASE 0x40019000UL 2018 #define NRF_SWI5_BASE 0x40019000UL 2019 #define NRF_TIMER3_BASE 0x4001A000UL 2020 #define NRF_ACL_BASE 0x4001E000UL 2021 #define NRF_NVMC_BASE 0x4001E000UL 2022 #define NRF_PPI_BASE 0x4001F000UL 2023 #define NRF_USBD_BASE 0x40027000UL 2024 2025 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2026 2027 2028 /* =========================================================================================================================== */ 2029 /* ================ Peripheral declaration ================ */ 2030 /* =========================================================================================================================== */ 2031 2032 2033 /** @addtogroup Device_Peripheral_declaration 2034 * @{ 2035 */ 2036 2037 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2038 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2039 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 2040 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2041 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2042 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2043 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2044 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2045 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2046 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2047 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2048 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2049 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2050 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2051 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2052 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2053 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2054 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2055 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2056 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2057 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2058 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2059 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2060 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2061 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2062 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2063 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2064 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2065 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2066 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2067 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2068 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2069 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2070 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2071 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2072 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2073 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2074 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2075 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2076 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2077 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2078 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2079 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2080 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2081 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2082 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2083 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2084 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2085 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2086 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2087 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2088 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2089 2090 /** @} */ /* End of group Device_Peripheral_declaration */ 2091 2092 2093 /* ========================================= End of section using anonymous unions ========================================= */ 2094 #if defined (__CC_ARM) 2095 #pragma pop 2096 #elif defined (__ICCARM__) 2097 /* leave anonymous unions enabled */ 2098 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2099 #pragma clang diagnostic pop 2100 #elif defined (__GNUC__) 2101 /* anonymous unions are enabled by default */ 2102 #elif defined (__TMS470__) 2103 /* anonymous unions are enabled by default */ 2104 #elif defined (__TASKING__) 2105 #pragma warning restore 2106 #elif defined (__CSMC__) 2107 /* anonymous unions are enabled by default */ 2108 #endif 2109 2110 2111 #ifdef __cplusplus 2112 } 2113 #endif 2114 2115 #endif /* NRF52820_H */ 2116 2117 2118 /** @} */ /* End of group nrf52820 */ 2119 2120 /** @} */ /* End of group Nordic Semiconductor */ 2121
