1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52810.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:02 37 * from File 'nrf52810.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52810 49 * @{ 50 */ 51 52 53 #ifndef NRF52810_H 54 #define NRF52810_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 TWIM0_TWIS0_TWI0_IRQn = 3, /*!< 3 TWIM0_TWIS0_TWI0 */ 90 SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ 91 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 92 SAADC_IRQn = 7, /*!< 7 SAADC */ 93 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 94 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 95 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 96 RTC0_IRQn = 11, /*!< 11 RTC0 */ 97 TEMP_IRQn = 12, /*!< 12 TEMP */ 98 RNG_IRQn = 13, /*!< 13 RNG */ 99 ECB_IRQn = 14, /*!< 14 ECB */ 100 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 101 WDT_IRQn = 16, /*!< 16 WDT */ 102 RTC1_IRQn = 17, /*!< 17 RTC1 */ 103 QDEC_IRQn = 18, /*!< 18 QDEC */ 104 COMP_IRQn = 19, /*!< 19 COMP */ 105 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 106 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 107 SWI2_IRQn = 22, /*!< 22 SWI2 */ 108 SWI3_IRQn = 23, /*!< 23 SWI3 */ 109 SWI4_IRQn = 24, /*!< 24 SWI4 */ 110 SWI5_IRQn = 25, /*!< 25 SWI5 */ 111 PWM0_IRQn = 28, /*!< 28 PWM0 */ 112 PDM_IRQn = 29 /*!< 29 PDM */ 113 } IRQn_Type; 114 115 116 117 /* =========================================================================================================================== */ 118 /* ================ Processor and Core Peripheral Section ================ */ 119 /* =========================================================================================================================== */ 120 121 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 122 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 123 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 124 #define __DSP_PRESENT 1 /*!< DSP present or not */ 125 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 126 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 127 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 128 #define __MPU_PRESENT 1 /*!< MPU present */ 129 #define __FPU_PRESENT 0 /*!< FPU present */ 130 131 132 /** @} */ /* End of group Configuration_of_CMSIS */ 133 134 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 135 #include "system_nrf52810.h" /*!< nrf52810 System */ 136 137 #ifndef __IM /*!< Fallback for older CMSIS versions */ 138 #define __IM __I 139 #endif 140 #ifndef __OM /*!< Fallback for older CMSIS versions */ 141 #define __OM __O 142 #endif 143 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 144 #define __IOM __IO 145 #endif 146 147 148 /* ======================================== Start of section using anonymous unions ======================================== */ 149 #if defined (__CC_ARM) 150 #pragma push 151 #pragma anon_unions 152 #elif defined (__ICCARM__) 153 #pragma language=extended 154 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 155 #pragma clang diagnostic push 156 #pragma clang diagnostic ignored "-Wc11-extensions" 157 #pragma clang diagnostic ignored "-Wreserved-id-macro" 158 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 159 #pragma clang diagnostic ignored "-Wnested-anon-types" 160 #elif defined (__GNUC__) 161 /* anonymous unions are enabled by default */ 162 #elif defined (__TMS470__) 163 /* anonymous unions are enabled by default */ 164 #elif defined (__TASKING__) 165 #pragma warning 586 166 #elif defined (__CSMC__) 167 /* anonymous unions are enabled by default */ 168 #else 169 #warning Not supported compiler type 170 #endif 171 172 173 /* =========================================================================================================================== */ 174 /* ================ Device Specific Cluster Section ================ */ 175 /* =========================================================================================================================== */ 176 177 178 /** @addtogroup Device_Peripheral_clusters 179 * @{ 180 */ 181 182 183 /** 184 * @brief FICR_INFO [INFO] (Device info) 185 */ 186 typedef struct { 187 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 188 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 189 configuration */ 190 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 191 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 192 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 193 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 194 195 196 /** 197 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 198 */ 199 typedef struct { 200 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 201 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 202 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 203 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 204 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 205 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 206 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 207 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 208 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 209 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 210 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 211 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 212 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 213 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 214 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 215 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 216 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 217 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 218 219 220 /** 221 * @brief POWER_RAM [RAM] (Unspecified) 222 */ 223 typedef struct { 224 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. 225 The RAM size will vary depending on product 226 variant, and the RAMn register will only 227 be present if the corresponding RAM AHB 228 slave is present on the device. */ 229 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 230 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 231 register */ 232 __IM uint32_t RESERVED; 233 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 234 235 236 /** 237 * @brief UART_PSEL [PSEL] (Unspecified) 238 */ 239 typedef struct { 240 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 241 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 242 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 243 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 244 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 245 246 247 /** 248 * @brief UARTE_PSEL [PSEL] (Unspecified) 249 */ 250 typedef struct { 251 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 252 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 253 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 254 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 255 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 256 257 258 /** 259 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 260 */ 261 typedef struct { 262 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 263 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 264 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 265 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 266 267 268 /** 269 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 270 */ 271 typedef struct { 272 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 273 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 274 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 275 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 276 277 278 /** 279 * @brief TWI_PSEL [PSEL] (Unspecified) 280 */ 281 typedef struct { 282 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 283 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 284 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 285 286 287 /** 288 * @brief TWIM_PSEL [PSEL] (Unspecified) 289 */ 290 typedef struct { 291 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 292 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 293 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 294 295 296 /** 297 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 298 */ 299 typedef struct { 300 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 301 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 302 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 303 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 304 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 305 306 307 /** 308 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 309 */ 310 typedef struct { 311 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 312 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 313 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 314 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 315 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 316 317 318 /** 319 * @brief TWIS_PSEL [PSEL] (Unspecified) 320 */ 321 typedef struct { 322 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 323 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 324 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 325 326 327 /** 328 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 329 */ 330 typedef struct { 331 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 332 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 333 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 334 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 335 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 336 337 338 /** 339 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 340 */ 341 typedef struct { 342 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 343 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 344 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 345 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 346 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 347 348 349 /** 350 * @brief SPI_PSEL [PSEL] (Unspecified) 351 */ 352 typedef struct { 353 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 354 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 355 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 356 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 357 358 359 /** 360 * @brief SPIM_PSEL [PSEL] (Unspecified) 361 */ 362 typedef struct { 363 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 364 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 365 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 366 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 367 368 369 /** 370 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 371 */ 372 typedef struct { 373 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 374 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 375 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 376 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 377 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 378 379 380 /** 381 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 382 */ 383 typedef struct { 384 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 385 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 386 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 387 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 388 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 389 390 391 /** 392 * @brief SPIS_PSEL [PSEL] (Unspecified) 393 */ 394 typedef struct { 395 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 396 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 397 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 398 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 399 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 400 401 402 /** 403 * @brief SPIS_RXD [RXD] (Unspecified) 404 */ 405 typedef struct { 406 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 407 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 408 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 409 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 410 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 411 412 413 /** 414 * @brief SPIS_TXD [TXD] (Unspecified) 415 */ 416 typedef struct { 417 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 418 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 419 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 420 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 421 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 422 423 424 /** 425 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 426 */ 427 typedef struct { 428 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 429 above CH[n].LIMIT.HIGH */ 430 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 431 below CH[n].LIMIT.LOW */ 432 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 433 434 435 /** 436 * @brief SAADC_CH [CH] (Unspecified) 437 */ 438 typedef struct { 439 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 440 for CH[n] */ 441 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 442 for CH[n] */ 443 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 444 CH[n] */ 445 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 446 monitoring a channel */ 447 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 448 449 450 /** 451 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 452 */ 453 typedef struct { 454 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 455 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 456 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 457 START */ 458 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 459 460 461 /** 462 * @brief QDEC_PSEL [PSEL] (Unspecified) 463 */ 464 typedef struct { 465 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 466 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 467 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 468 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 469 470 471 /** 472 * @brief PWM_SEQ [SEQ] (Unspecified) 473 */ 474 typedef struct { 475 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 476 of this sequence */ 477 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 478 in this sequence */ 479 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 480 periods between samples loaded into compare 481 register */ 482 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 483 __IM uint32_t RESERVED[4]; 484 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 485 486 487 /** 488 * @brief PWM_PSEL [PSEL] (Unspecified) 489 */ 490 typedef struct { 491 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 492 PWM channel n */ 493 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 494 495 496 /** 497 * @brief PDM_PSEL [PSEL] (Unspecified) 498 */ 499 typedef struct { 500 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 501 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 502 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 503 504 505 /** 506 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 507 */ 508 typedef struct { 509 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 510 EasyDMA */ 511 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 512 mode */ 513 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 514 515 516 /** 517 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 518 */ 519 typedef struct { 520 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 521 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 522 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 523 524 525 /** 526 * @brief PPI_CH [CH] (PPI Channel) 527 */ 528 typedef struct { 529 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ 530 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ 531 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 532 533 534 /** 535 * @brief PPI_FORK [FORK] (Fork) 536 */ 537 typedef struct { 538 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ 539 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 540 541 542 /** @} */ /* End of group Device_Peripheral_clusters */ 543 544 545 /* =========================================================================================================================== */ 546 /* ================ Device Specific Peripheral Section ================ */ 547 /* =========================================================================================================================== */ 548 549 550 /** @addtogroup Device_Peripheral_peripherals 551 * @{ 552 */ 553 554 555 556 /* =========================================================================================================================== */ 557 /* ================ FICR ================ */ 558 /* =========================================================================================================================== */ 559 560 561 /** 562 * @brief Factory information configuration registers (FICR) 563 */ 564 565 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 566 __IM uint32_t RESERVED[4]; 567 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 568 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 569 __IM uint32_t RESERVED1[18]; 570 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 571 __IM uint32_t RESERVED2[6]; 572 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 573 n */ 574 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ 575 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 576 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 577 __IM uint32_t RESERVED3[21]; 578 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 579 __IM uint32_t RESERVED4[188]; 580 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 581 coefficients */ 582 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 583 584 585 586 /* =========================================================================================================================== */ 587 /* ================ UICR ================ */ 588 /* =========================================================================================================================== */ 589 590 591 /** 592 * @brief User information configuration registers (UICR) 593 */ 594 595 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 596 __IM uint32_t RESERVED[5]; 597 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 598 design */ 599 __IM uint32_t RESERVED1[2]; 600 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 601 design */ 602 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 603 __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ 604 __IM uint32_t RESERVED2[56]; 605 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 606 function (see POWER chapter for details) */ 607 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 608 } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 609 610 611 612 /* =========================================================================================================================== */ 613 /* ================ BPROT ================ */ 614 /* =========================================================================================================================== */ 615 616 617 /** 618 * @brief Block Protect (BPROT) 619 */ 620 621 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 622 __IM uint32_t RESERVED[384]; 623 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 624 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 625 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 626 } NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ 627 628 629 630 /* =========================================================================================================================== */ 631 /* ================ APPROTECT ================ */ 632 /* =========================================================================================================================== */ 633 634 635 /** 636 * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) 637 */ 638 639 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 640 __IM uint32_t RESERVED[340]; 641 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 642 next reset. */ 643 __IM uint32_t RESERVED1; 644 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 645 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 646 647 648 649 /* =========================================================================================================================== */ 650 /* ================ CLOCK ================ */ 651 /* =========================================================================================================================== */ 652 653 654 /** 655 * @brief Clock control (CLOCK) 656 */ 657 658 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 659 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 660 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 661 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 662 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 663 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 664 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 665 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 666 __IM uint32_t RESERVED[57]; 667 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 668 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 669 __IM uint32_t RESERVED1; 670 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 671 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 672 __IM uint32_t RESERVED2[124]; 673 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 674 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 675 __IM uint32_t RESERVED3[63]; 676 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 677 triggered */ 678 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 679 __IM uint32_t RESERVED4; 680 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 681 triggered */ 682 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 683 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 684 task was triggered */ 685 __IM uint32_t RESERVED5[62]; 686 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 687 __IM uint32_t RESERVED6[7]; 688 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 689 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 690 691 692 693 /* =========================================================================================================================== */ 694 /* ================ POWER ================ */ 695 /* =========================================================================================================================== */ 696 697 698 /** 699 * @brief Power control (POWER) 700 */ 701 702 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 703 __IM uint32_t RESERVED[30]; 704 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 705 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 706 __IM uint32_t RESERVED1[34]; 707 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 708 __IM uint32_t RESERVED2[2]; 709 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 710 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 711 __IM uint32_t RESERVED3[122]; 712 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 713 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 714 __IM uint32_t RESERVED4[61]; 715 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 716 __IM uint32_t RESERVED5[63]; 717 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 718 __IM uint32_t RESERVED6[3]; 719 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 720 __IM uint32_t RESERVED7[2]; 721 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 722 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 723 __IM uint32_t RESERVED8[21]; 724 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 725 __IM uint32_t RESERVED9[225]; 726 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 727 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 728 729 730 731 /* =========================================================================================================================== */ 732 /* ================ P0 ================ */ 733 /* =========================================================================================================================== */ 734 735 736 /** 737 * @brief GPIO Port (P0) 738 */ 739 740 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 741 __IM uint32_t RESERVED[321]; 742 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 743 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 744 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 745 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 746 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 747 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 748 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 749 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 750 have met the criteria set in the PIN_CNF[n].SENSE 751 registers */ 752 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 753 and LDETECT mode */ 754 __IM uint32_t RESERVED1[118]; 755 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 756 pins */ 757 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 758 759 760 761 /* =========================================================================================================================== */ 762 /* ================ RADIO ================ */ 763 /* =========================================================================================================================== */ 764 765 766 /** 767 * @brief 2.4 GHz Radio (RADIO) 768 */ 769 770 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 771 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 772 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 773 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 774 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 775 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 776 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 777 the receive signal strength. */ 778 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 779 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 780 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 781 __IM uint32_t RESERVED[55]; 782 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 783 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 784 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 785 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 786 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 787 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 788 packet */ 789 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 790 received packet */ 791 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 792 __IM uint32_t RESERVED1[2]; 793 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 794 __IM uint32_t RESERVED2; 795 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 796 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 797 __IM uint32_t RESERVED3[50]; 798 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 799 __IM uint32_t RESERVED4[64]; 800 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 801 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 802 __IM uint32_t RESERVED5[61]; 803 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 804 __IM uint32_t RESERVED6; 805 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 806 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 807 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 808 __IM uint32_t RESERVED7[60]; 809 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 810 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 811 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 812 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 813 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 814 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 815 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 816 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 817 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 818 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 819 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 820 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 821 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 822 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 823 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 824 __IM uint32_t RESERVED8; 825 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 826 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 827 __IM uint32_t RESERVED9; 828 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 829 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 830 __IM uint32_t RESERVED10[2]; 831 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 832 __IM uint32_t RESERVED11[39]; 833 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 834 n */ 835 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 836 n */ 837 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 838 __IM uint32_t RESERVED12[3]; 839 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 840 __IM uint32_t RESERVED13[618]; 841 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 842 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 843 844 845 846 /* =========================================================================================================================== */ 847 /* ================ UART0 ================ */ 848 /* =========================================================================================================================== */ 849 850 851 /** 852 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 853 */ 854 855 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 856 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 857 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 858 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 859 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 860 __IM uint32_t RESERVED[3]; 861 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 862 __IM uint32_t RESERVED1[56]; 863 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 864 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 865 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 866 __IM uint32_t RESERVED2[4]; 867 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 868 __IM uint32_t RESERVED3; 869 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 870 __IM uint32_t RESERVED4[7]; 871 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 872 __IM uint32_t RESERVED5[46]; 873 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 874 __IM uint32_t RESERVED6[64]; 875 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 876 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 877 __IM uint32_t RESERVED7[93]; 878 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 879 __IM uint32_t RESERVED8[31]; 880 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 881 __IM uint32_t RESERVED9; 882 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 883 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 884 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 885 __IM uint32_t RESERVED10; 886 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 887 selected. */ 888 __IM uint32_t RESERVED11[17]; 889 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 890 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 891 892 893 894 /* =========================================================================================================================== */ 895 /* ================ UARTE0 ================ */ 896 /* =========================================================================================================================== */ 897 898 899 /** 900 * @brief UART with EasyDMA (UARTE0) 901 */ 902 903 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 904 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 905 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 906 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 907 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 908 __IM uint32_t RESERVED[7]; 909 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 910 __IM uint32_t RESERVED1[52]; 911 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 912 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 913 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 914 transferred to Data RAM) */ 915 __IM uint32_t RESERVED2; 916 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 917 __IM uint32_t RESERVED3[2]; 918 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 919 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 920 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 921 __IM uint32_t RESERVED4[7]; 922 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 923 __IM uint32_t RESERVED5; 924 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 925 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 926 __IM uint32_t RESERVED6; 927 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 928 __IM uint32_t RESERVED7[41]; 929 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 930 __IM uint32_t RESERVED8[63]; 931 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 932 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 933 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 934 __IM uint32_t RESERVED9[93]; 935 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 936 one to clear. */ 937 __IM uint32_t RESERVED10[31]; 938 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 939 __IM uint32_t RESERVED11; 940 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 941 __IM uint32_t RESERVED12[3]; 942 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 943 selected. */ 944 __IM uint32_t RESERVED13[3]; 945 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 946 __IM uint32_t RESERVED14; 947 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 948 __IM uint32_t RESERVED15[7]; 949 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 950 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 951 952 953 954 /* =========================================================================================================================== */ 955 /* ================ TWI0 ================ */ 956 /* =========================================================================================================================== */ 957 958 959 /** 960 * @brief I2C compatible Two-Wire Interface (TWI0) 961 */ 962 963 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 964 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 965 __IM uint32_t RESERVED; 966 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 967 __IM uint32_t RESERVED1[2]; 968 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 969 __IM uint32_t RESERVED2; 970 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 971 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 972 __IM uint32_t RESERVED3[56]; 973 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 974 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 975 __IM uint32_t RESERVED4[4]; 976 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 977 __IM uint32_t RESERVED5; 978 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 979 __IM uint32_t RESERVED6[4]; 980 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 981 that is sent or received */ 982 __IM uint32_t RESERVED7[3]; 983 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 984 __IM uint32_t RESERVED8[45]; 985 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 986 __IM uint32_t RESERVED9[64]; 987 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 988 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 989 __IM uint32_t RESERVED10[110]; 990 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 991 __IM uint32_t RESERVED11[14]; 992 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 993 __IM uint32_t RESERVED12; 994 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 995 __IM uint32_t RESERVED13[2]; 996 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 997 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 998 __IM uint32_t RESERVED14; 999 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1000 source selected. */ 1001 __IM uint32_t RESERVED15[24]; 1002 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1003 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1004 1005 1006 1007 /* =========================================================================================================================== */ 1008 /* ================ TWIM0 ================ */ 1009 /* =========================================================================================================================== */ 1010 1011 1012 /** 1013 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 1014 */ 1015 1016 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1017 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1018 __IM uint32_t RESERVED; 1019 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1020 __IM uint32_t RESERVED1[2]; 1021 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1022 TWI master is not suspended. */ 1023 __IM uint32_t RESERVED2; 1024 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1025 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1026 __IM uint32_t RESERVED3[56]; 1027 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1028 __IM uint32_t RESERVED4[7]; 1029 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1030 __IM uint32_t RESERVED5[8]; 1031 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1032 task has been issued, TWI traffic is now 1033 suspended. */ 1034 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1035 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1036 __IM uint32_t RESERVED6[2]; 1037 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1038 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1039 byte */ 1040 __IM uint32_t RESERVED7[39]; 1041 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1042 __IM uint32_t RESERVED8[63]; 1043 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1044 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1045 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1046 __IM uint32_t RESERVED9[110]; 1047 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1048 __IM uint32_t RESERVED10[14]; 1049 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1050 __IM uint32_t RESERVED11; 1051 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1052 __IM uint32_t RESERVED12[5]; 1053 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1054 source selected. */ 1055 __IM uint32_t RESERVED13[3]; 1056 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1057 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1058 __IM uint32_t RESERVED14[13]; 1059 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1060 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1061 1062 1063 1064 /* =========================================================================================================================== */ 1065 /* ================ TWIS0 ================ */ 1066 /* =========================================================================================================================== */ 1067 1068 1069 /** 1070 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 1071 */ 1072 1073 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1074 __IM uint32_t RESERVED[5]; 1075 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1076 __IM uint32_t RESERVED1; 1077 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1078 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1079 __IM uint32_t RESERVED2[3]; 1080 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1081 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1082 __IM uint32_t RESERVED3[51]; 1083 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1084 __IM uint32_t RESERVED4[7]; 1085 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1086 __IM uint32_t RESERVED5[9]; 1087 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1088 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1089 __IM uint32_t RESERVED6[4]; 1090 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1091 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1092 __IM uint32_t RESERVED7[37]; 1093 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1094 __IM uint32_t RESERVED8[63]; 1095 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1096 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1097 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1098 __IM uint32_t RESERVED9[113]; 1099 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1100 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1101 a match */ 1102 __IM uint32_t RESERVED10[10]; 1103 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1104 __IM uint32_t RESERVED11; 1105 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1106 __IM uint32_t RESERVED12[9]; 1107 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1108 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1109 __IM uint32_t RESERVED13[13]; 1110 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1111 __IM uint32_t RESERVED14; 1112 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1113 mechanism */ 1114 __IM uint32_t RESERVED15[10]; 1115 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1116 of an over-read of the transmit buffer. */ 1117 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1118 1119 1120 1121 /* =========================================================================================================================== */ 1122 /* ================ SPI0 ================ */ 1123 /* =========================================================================================================================== */ 1124 1125 1126 /** 1127 * @brief Serial Peripheral Interface (SPI0) 1128 */ 1129 1130 typedef struct { /*!< (@ 0x40004000) SPI0 Structure */ 1131 __IM uint32_t RESERVED[66]; 1132 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1133 __IM uint32_t RESERVED1[126]; 1134 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1135 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1136 __IM uint32_t RESERVED2[125]; 1137 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1138 __IM uint32_t RESERVED3; 1139 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1140 __IM uint32_t RESERVED4; 1141 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1142 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1143 __IM uint32_t RESERVED5; 1144 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1145 source selected. */ 1146 __IM uint32_t RESERVED6[11]; 1147 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1148 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1149 1150 1151 1152 /* =========================================================================================================================== */ 1153 /* ================ SPIM0 ================ */ 1154 /* =========================================================================================================================== */ 1155 1156 1157 /** 1158 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) 1159 */ 1160 1161 typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ 1162 __IM uint32_t RESERVED[4]; 1163 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1164 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1165 __IM uint32_t RESERVED1; 1166 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1167 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1168 __IM uint32_t RESERVED2[56]; 1169 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1170 __IM uint32_t RESERVED3[2]; 1171 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1172 __IM uint32_t RESERVED4; 1173 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1174 __IM uint32_t RESERVED5; 1175 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1176 __IM uint32_t RESERVED6[10]; 1177 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1178 __IM uint32_t RESERVED7[44]; 1179 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1180 __IM uint32_t RESERVED8[64]; 1181 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1182 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1183 __IM uint32_t RESERVED9[125]; 1184 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1185 __IM uint32_t RESERVED10; 1186 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1187 __IM uint32_t RESERVED11[4]; 1188 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1189 source selected. */ 1190 __IM uint32_t RESERVED12[3]; 1191 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1192 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1193 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1194 __IM uint32_t RESERVED13[26]; 1195 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1196 case and over-read of the TXD buffer. */ 1197 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1198 1199 1200 1201 /* =========================================================================================================================== */ 1202 /* ================ SPIS0 ================ */ 1203 /* =========================================================================================================================== */ 1204 1205 1206 /** 1207 * @brief SPI Slave (SPIS0) 1208 */ 1209 1210 typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ 1211 __IM uint32_t RESERVED[9]; 1212 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1213 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1214 to acquire it */ 1215 __IM uint32_t RESERVED1[54]; 1216 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1217 __IM uint32_t RESERVED2[2]; 1218 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1219 __IM uint32_t RESERVED3[5]; 1220 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1221 __IM uint32_t RESERVED4[53]; 1222 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1223 __IM uint32_t RESERVED5[64]; 1224 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1225 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1226 __IM uint32_t RESERVED6[61]; 1227 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1228 __IM uint32_t RESERVED7[15]; 1229 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1230 __IM uint32_t RESERVED8[47]; 1231 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1232 __IM uint32_t RESERVED9; 1233 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1234 __IM uint32_t RESERVED10[7]; 1235 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1236 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1237 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1238 __IM uint32_t RESERVED11; 1239 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1240 of an ignored transaction. */ 1241 __IM uint32_t RESERVED12[24]; 1242 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1243 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1244 1245 1246 1247 /* =========================================================================================================================== */ 1248 /* ================ GPIOTE ================ */ 1249 /* =========================================================================================================================== */ 1250 1251 1252 /** 1253 * @brief GPIO Tasks and Events (GPIOTE) 1254 */ 1255 1256 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1257 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1258 specified in CONFIG[n].PSEL. Action on pin 1259 is configured in CONFIG[n].POLARITY. */ 1260 __IM uint32_t RESERVED[4]; 1261 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1262 specified in CONFIG[n].PSEL. Action on pin 1263 is to set it high. */ 1264 __IM uint32_t RESERVED1[4]; 1265 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1266 specified in CONFIG[n].PSEL. Action on pin 1267 is to set it low. */ 1268 __IM uint32_t RESERVED2[32]; 1269 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1270 pin specified in CONFIG[n].PSEL */ 1271 __IM uint32_t RESERVED3[23]; 1272 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1273 with SENSE mechanism enabled */ 1274 __IM uint32_t RESERVED4[97]; 1275 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1276 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1277 __IM uint32_t RESERVED5[129]; 1278 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1279 SET[n] and CLR[n] tasks and IN[n] event */ 1280 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1281 1282 1283 1284 /* =========================================================================================================================== */ 1285 /* ================ SAADC ================ */ 1286 /* =========================================================================================================================== */ 1287 1288 1289 /** 1290 * @brief Analog to Digital Converter (SAADC) 1291 */ 1292 1293 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1294 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1295 RAM */ 1296 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1297 are sampled */ 1298 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1299 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1300 __IM uint32_t RESERVED[60]; 1301 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1302 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1303 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1304 on the mode, multiple conversions might 1305 be needed for a result to be transferred 1306 to RAM. */ 1307 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1308 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1309 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1310 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1311 __IM uint32_t RESERVED1[106]; 1312 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1313 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1314 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1315 __IM uint32_t RESERVED2[61]; 1316 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1317 __IM uint32_t RESERVED3[63]; 1318 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1319 __IM uint32_t RESERVED4[3]; 1320 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1321 __IM uint32_t RESERVED5[24]; 1322 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1323 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1324 not be combined with SCAN. The RESOLUTION 1325 is applied before averaging, thus for high 1326 OVERSAMPLE a higher RESOLUTION should be 1327 used. */ 1328 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1329 __IM uint32_t RESERVED6[12]; 1330 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1331 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1332 1333 1334 1335 /* =========================================================================================================================== */ 1336 /* ================ TIMER0 ================ */ 1337 /* =========================================================================================================================== */ 1338 1339 1340 /** 1341 * @brief Timer/Counter 0 (TIMER0) 1342 */ 1343 1344 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1345 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1346 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1347 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1348 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1349 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1350 __IM uint32_t RESERVED[11]; 1351 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1352 CC[n] register */ 1353 __IM uint32_t RESERVED1[58]; 1354 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1355 match */ 1356 __IM uint32_t RESERVED2[42]; 1357 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1358 __IM uint32_t RESERVED3[64]; 1359 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1360 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1361 __IM uint32_t RESERVED4[126]; 1362 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1363 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1364 __IM uint32_t RESERVED5; 1365 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1366 __IM uint32_t RESERVED6[11]; 1367 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1368 n */ 1369 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1370 1371 1372 1373 /* =========================================================================================================================== */ 1374 /* ================ RTC0 ================ */ 1375 /* =========================================================================================================================== */ 1376 1377 1378 /** 1379 * @brief Real time counter 0 (RTC0) 1380 */ 1381 1382 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1383 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1384 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1385 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1386 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1387 __IM uint32_t RESERVED[60]; 1388 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1389 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1390 __IM uint32_t RESERVED1[14]; 1391 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1392 match */ 1393 __IM uint32_t RESERVED2[109]; 1394 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1395 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1396 __IM uint32_t RESERVED3[13]; 1397 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1398 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1399 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1400 __IM uint32_t RESERVED4[110]; 1401 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1402 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1403 t be written when RTC is stopped */ 1404 __IM uint32_t RESERVED5[13]; 1405 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1406 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1407 1408 1409 1410 /* =========================================================================================================================== */ 1411 /* ================ TEMP ================ */ 1412 /* =========================================================================================================================== */ 1413 1414 1415 /** 1416 * @brief Temperature Sensor (TEMP) 1417 */ 1418 1419 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1420 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1421 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1422 __IM uint32_t RESERVED[62]; 1423 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1424 __IM uint32_t RESERVED1[128]; 1425 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1426 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1427 __IM uint32_t RESERVED2[127]; 1428 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1429 __IM uint32_t RESERVED3[5]; 1430 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1431 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1432 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1433 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1434 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1435 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1436 __IM uint32_t RESERVED4[2]; 1437 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1438 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1439 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1440 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1441 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1442 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1443 __IM uint32_t RESERVED5[2]; 1444 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1445 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1446 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1447 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1448 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1449 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1450 1451 1452 1453 /* =========================================================================================================================== */ 1454 /* ================ RNG ================ */ 1455 /* =========================================================================================================================== */ 1456 1457 1458 /** 1459 * @brief Random Number Generator (RNG) 1460 */ 1461 1462 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1463 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1464 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1465 __IM uint32_t RESERVED[62]; 1466 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1467 written to the VALUE register */ 1468 __IM uint32_t RESERVED1[63]; 1469 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1470 __IM uint32_t RESERVED2[64]; 1471 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1472 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1473 __IM uint32_t RESERVED3[126]; 1474 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1475 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1476 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1477 1478 1479 1480 /* =========================================================================================================================== */ 1481 /* ================ ECB ================ */ 1482 /* =========================================================================================================================== */ 1483 1484 1485 /** 1486 * @brief AES ECB Mode Encryption (ECB) 1487 */ 1488 1489 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1490 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1491 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1492 __IM uint32_t RESERVED[62]; 1493 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1494 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1495 task or due to an error */ 1496 __IM uint32_t RESERVED1[127]; 1497 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1498 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1499 __IM uint32_t RESERVED2[126]; 1500 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1501 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1502 1503 1504 1505 /* =========================================================================================================================== */ 1506 /* ================ AAR ================ */ 1507 /* =========================================================================================================================== */ 1508 1509 1510 /** 1511 * @brief Accelerated Address Resolver (AAR) 1512 */ 1513 1514 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1515 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1516 in the IRK data structure */ 1517 __IM uint32_t RESERVED; 1518 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1519 __IM uint32_t RESERVED1[61]; 1520 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1521 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1522 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1523 __IM uint32_t RESERVED2[126]; 1524 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1525 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1526 __IM uint32_t RESERVED3[61]; 1527 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1528 __IM uint32_t RESERVED4[63]; 1529 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1530 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1531 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1532 __IM uint32_t RESERVED5; 1533 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1534 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1535 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1536 1537 1538 1539 /* =========================================================================================================================== */ 1540 /* ================ CCM ================ */ 1541 /* =========================================================================================================================== */ 1542 1543 1544 /** 1545 * @brief AES CCM Mode Encryption (CCM) 1546 */ 1547 1548 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1549 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1550 will stop by itself when completed. */ 1551 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1552 stop by itself when completed. */ 1553 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1554 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1555 the contents of the RATEOVERRIDE register 1556 for any ongoing encryption/decryption */ 1557 __IM uint32_t RESERVED[60]; 1558 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1559 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1560 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1561 __IM uint32_t RESERVED1[61]; 1562 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1563 __IM uint32_t RESERVED2[64]; 1564 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1565 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1566 __IM uint32_t RESERVED3[61]; 1567 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1568 __IM uint32_t RESERVED4[63]; 1569 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1570 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1571 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1572 NONCE vector */ 1573 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1574 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1575 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1576 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 1577 = Extended. */ 1578 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1579 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1580 1581 1582 1583 /* =========================================================================================================================== */ 1584 /* ================ WDT ================ */ 1585 /* =========================================================================================================================== */ 1586 1587 1588 /** 1589 * @brief Watchdog Timer (WDT) 1590 */ 1591 1592 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1593 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1594 __IM uint32_t RESERVED[63]; 1595 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1596 __IM uint32_t RESERVED1[128]; 1597 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1598 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1599 __IM uint32_t RESERVED2[61]; 1600 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1601 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1602 __IM uint32_t RESERVED3[63]; 1603 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1604 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1605 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1606 __IM uint32_t RESERVED4[60]; 1607 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1608 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1609 1610 1611 1612 /* =========================================================================================================================== */ 1613 /* ================ QDEC ================ */ 1614 /* =========================================================================================================================== */ 1615 1616 1617 /** 1618 * @brief Quadrature Decoder (QDEC) 1619 */ 1620 1621 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1622 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1623 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1624 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1625 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1626 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1627 __IM uint32_t RESERVED[59]; 1628 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1629 written to the SAMPLE register */ 1630 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1631 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1632 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1633 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1634 __IM uint32_t RESERVED1[59]; 1635 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1636 __IM uint32_t RESERVED2[64]; 1637 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1638 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1639 __IM uint32_t RESERVED3[125]; 1640 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1641 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1642 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1643 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1644 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1645 and DBLRDY events can be generated */ 1646 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1647 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1648 READCLRACC or RDCLRACC task */ 1649 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1650 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1651 __IM uint32_t RESERVED4[5]; 1652 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1653 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1654 double transitions */ 1655 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1656 or RDCLRDBL task */ 1657 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1658 1659 1660 1661 /* =========================================================================================================================== */ 1662 /* ================ COMP ================ */ 1663 /* =========================================================================================================================== */ 1664 1665 1666 /** 1667 * @brief Comparator (COMP) 1668 */ 1669 1670 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1671 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1672 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1673 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1674 __IM uint32_t RESERVED[61]; 1675 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1676 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1677 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1678 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1679 __IM uint32_t RESERVED1[60]; 1680 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1681 __IM uint32_t RESERVED2[63]; 1682 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1683 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1684 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1685 __IM uint32_t RESERVED3[61]; 1686 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1687 __IM uint32_t RESERVED4[63]; 1688 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1689 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1690 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1691 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1692 __IM uint32_t RESERVED5[8]; 1693 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1694 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1695 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1696 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 1697 1698 1699 1700 /* =========================================================================================================================== */ 1701 /* ================ EGU0 ================ */ 1702 /* =========================================================================================================================== */ 1703 1704 1705 /** 1706 * @brief Event Generator Unit 0 (EGU0) 1707 */ 1708 1709 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1710 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1711 the corresponding TRIGGERED[n] event */ 1712 __IM uint32_t RESERVED[48]; 1713 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1714 by triggering the corresponding TRIGGER[n] 1715 task */ 1716 __IM uint32_t RESERVED1[112]; 1717 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1718 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1719 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1720 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1721 1722 1723 1724 /* =========================================================================================================================== */ 1725 /* ================ SWI0 ================ */ 1726 /* =========================================================================================================================== */ 1727 1728 1729 /** 1730 * @brief Software interrupt 0 (SWI0) 1731 */ 1732 1733 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1734 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1735 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1736 1737 1738 1739 /* =========================================================================================================================== */ 1740 /* ================ PWM0 ================ */ 1741 /* =========================================================================================================================== */ 1742 1743 1744 /** 1745 * @brief Pulse width modulation unit (PWM0) 1746 */ 1747 1748 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1749 __IM uint32_t RESERVED; 1750 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1751 the end of current PWM period, and stops 1752 sequence playback */ 1753 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1754 on all enabled channels from sequence n, 1755 and starts playing that sequence at the 1756 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1757 Causes PWM generation to start if not running. */ 1758 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1759 all enabled channels if DECODER.MODE=NextStep. 1760 Does not cause PWM generation to start if 1761 not running. */ 1762 __IM uint32_t RESERVED1[60]; 1763 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1764 are no longer generated */ 1765 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1766 on sequence n */ 1767 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1768 sequence n, when last value from RAM has 1769 been applied to wave counter */ 1770 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1771 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1772 of times defined in LOOP.CNT */ 1773 __IM uint32_t RESERVED2[56]; 1774 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1775 __IM uint32_t RESERVED3[63]; 1776 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1777 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1778 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1779 __IM uint32_t RESERVED4[125]; 1780 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1781 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1782 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1783 counts */ 1784 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1785 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1786 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1787 __IM uint32_t RESERVED5[2]; 1788 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1789 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1790 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1791 1792 1793 1794 /* =========================================================================================================================== */ 1795 /* ================ PDM ================ */ 1796 /* =========================================================================================================================== */ 1797 1798 1799 /** 1800 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 1801 */ 1802 1803 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 1804 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1805 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1806 __IM uint32_t RESERVED[62]; 1807 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1808 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1809 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1810 by SAMPLE.MAXCNT (or the last sample after 1811 a STOP task has been received) to Data RAM */ 1812 __IM uint32_t RESERVED1[125]; 1813 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1814 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1815 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1816 __IM uint32_t RESERVED2[125]; 1817 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1818 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1819 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1820 signals */ 1821 __IM uint32_t RESERVED3[3]; 1822 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1823 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1824 __IM uint32_t RESERVED4[8]; 1825 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1826 __IM uint32_t RESERVED5[6]; 1827 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1828 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1829 1830 1831 1832 /* =========================================================================================================================== */ 1833 /* ================ NVMC ================ */ 1834 /* =========================================================================================================================== */ 1835 1836 1837 /** 1838 * @brief Non-volatile memory controller (NVMC) 1839 */ 1840 1841 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1842 __IM uint32_t RESERVED[256]; 1843 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1844 __IM uint32_t RESERVED1[64]; 1845 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1846 1847 union { 1848 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1849 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1850 page in code area. Equivalent to ERASEPAGE. */ 1851 }; 1852 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1853 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1854 page in code area. Equivalent to ERASEPAGE. */ 1855 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1856 registers */ 1857 __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1858 area */ 1859 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1860 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1861 1862 1863 1864 /* =========================================================================================================================== */ 1865 /* ================ PPI ================ */ 1866 /* =========================================================================================================================== */ 1867 1868 1869 /** 1870 * @brief Programmable Peripheral Interconnect (PPI) 1871 */ 1872 1873 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1874 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1875 __IM uint32_t RESERVED[308]; 1876 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1877 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1878 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1879 __IM uint32_t RESERVED1; 1880 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 1881 __IM uint32_t RESERVED2[148]; 1882 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 1883 __IM uint32_t RESERVED3[62]; 1884 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1885 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1886 1887 1888 /** @} */ /* End of group Device_Peripheral_peripherals */ 1889 1890 1891 /* =========================================================================================================================== */ 1892 /* ================ Device Specific Peripheral Address Map ================ */ 1893 /* =========================================================================================================================== */ 1894 1895 1896 /** @addtogroup Device_Peripheral_peripheralAddr 1897 * @{ 1898 */ 1899 1900 #define NRF_FICR_BASE 0x10000000UL 1901 #define NRF_UICR_BASE 0x10001000UL 1902 #define NRF_BPROT_BASE 0x40000000UL 1903 #define NRF_APPROTECT_BASE 0x40000000UL 1904 #define NRF_CLOCK_BASE 0x40000000UL 1905 #define NRF_POWER_BASE 0x40000000UL 1906 #define NRF_P0_BASE 0x50000000UL 1907 #define NRF_RADIO_BASE 0x40001000UL 1908 #define NRF_UART0_BASE 0x40002000UL 1909 #define NRF_UARTE0_BASE 0x40002000UL 1910 #define NRF_TWI0_BASE 0x40003000UL 1911 #define NRF_TWIM0_BASE 0x40003000UL 1912 #define NRF_TWIS0_BASE 0x40003000UL 1913 #define NRF_SPI0_BASE 0x40004000UL 1914 #define NRF_SPIM0_BASE 0x40004000UL 1915 #define NRF_SPIS0_BASE 0x40004000UL 1916 #define NRF_GPIOTE_BASE 0x40006000UL 1917 #define NRF_SAADC_BASE 0x40007000UL 1918 #define NRF_TIMER0_BASE 0x40008000UL 1919 #define NRF_TIMER1_BASE 0x40009000UL 1920 #define NRF_TIMER2_BASE 0x4000A000UL 1921 #define NRF_RTC0_BASE 0x4000B000UL 1922 #define NRF_TEMP_BASE 0x4000C000UL 1923 #define NRF_RNG_BASE 0x4000D000UL 1924 #define NRF_ECB_BASE 0x4000E000UL 1925 #define NRF_AAR_BASE 0x4000F000UL 1926 #define NRF_CCM_BASE 0x4000F000UL 1927 #define NRF_WDT_BASE 0x40010000UL 1928 #define NRF_RTC1_BASE 0x40011000UL 1929 #define NRF_QDEC_BASE 0x40012000UL 1930 #define NRF_COMP_BASE 0x40013000UL 1931 #define NRF_EGU0_BASE 0x40014000UL 1932 #define NRF_SWI0_BASE 0x40014000UL 1933 #define NRF_EGU1_BASE 0x40015000UL 1934 #define NRF_SWI1_BASE 0x40015000UL 1935 #define NRF_SWI2_BASE 0x40016000UL 1936 #define NRF_SWI3_BASE 0x40017000UL 1937 #define NRF_SWI4_BASE 0x40018000UL 1938 #define NRF_SWI5_BASE 0x40019000UL 1939 #define NRF_PWM0_BASE 0x4001C000UL 1940 #define NRF_PDM_BASE 0x4001D000UL 1941 #define NRF_NVMC_BASE 0x4001E000UL 1942 #define NRF_PPI_BASE 0x4001F000UL 1943 1944 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1945 1946 1947 /* =========================================================================================================================== */ 1948 /* ================ Peripheral declaration ================ */ 1949 /* =========================================================================================================================== */ 1950 1951 1952 /** @addtogroup Device_Peripheral_declaration 1953 * @{ 1954 */ 1955 1956 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1957 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1958 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 1959 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 1960 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1961 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1962 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 1963 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1964 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1965 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 1966 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1967 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 1968 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 1969 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1970 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 1971 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 1972 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1973 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 1974 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1975 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1976 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1977 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1978 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1979 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1980 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1981 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1982 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1983 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1984 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1985 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1986 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 1987 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 1988 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 1989 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 1990 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 1991 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 1992 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 1993 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 1994 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 1995 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 1996 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 1997 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1998 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1999 2000 /** @} */ /* End of group Device_Peripheral_declaration */ 2001 2002 2003 /* ========================================= End of section using anonymous unions ========================================= */ 2004 #if defined (__CC_ARM) 2005 #pragma pop 2006 #elif defined (__ICCARM__) 2007 /* leave anonymous unions enabled */ 2008 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2009 #pragma clang diagnostic pop 2010 #elif defined (__GNUC__) 2011 /* anonymous unions are enabled by default */ 2012 #elif defined (__TMS470__) 2013 /* anonymous unions are enabled by default */ 2014 #elif defined (__TASKING__) 2015 #pragma warning restore 2016 #elif defined (__CSMC__) 2017 /* anonymous unions are enabled by default */ 2018 #endif 2019 2020 2021 #ifdef __cplusplus 2022 } 2023 #endif 2024 2025 #endif /* NRF52810_H */ 2026 2027 2028 /** @} */ /* End of group nrf52810 */ 2029 2030 /** @} */ /* End of group Nordic Semiconductor */ 2031
