1 /* 2 3 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef __NRF52805_BITS_H 36 #define __NRF52805_BITS_H 37 38 /*lint ++flb "Enter library region" */ 39 40 /* Peripheral: AAR */ 41 /* Description: Accelerated Address Resolver */ 42 43 /* Register: AAR_TASKS_START */ 44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ 45 46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ 47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 50 51 /* Register: AAR_TASKS_STOP */ 52 /* Description: Stop resolving addresses */ 53 54 /* Bit 0 : Stop resolving addresses */ 55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 58 59 /* Register: AAR_EVENTS_END */ 60 /* Description: Address resolution procedure complete */ 61 62 /* Bit 0 : Address resolution procedure complete */ 63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 67 68 /* Register: AAR_EVENTS_RESOLVED */ 69 /* Description: Address resolved */ 70 71 /* Bit 0 : Address resolved */ 72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ 73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ 74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ 75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ 76 77 /* Register: AAR_EVENTS_NOTRESOLVED */ 78 /* Description: Address not resolved */ 79 80 /* Bit 0 : Address not resolved */ 81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ 82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ 83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ 84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ 85 86 /* Register: AAR_INTENSET */ 87 /* Description: Enable interrupt */ 88 89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ 90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ 95 96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ 97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ 102 103 /* Bit 0 : Write '1' to enable interrupt for event END */ 104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */ 109 110 /* Register: AAR_INTENCLR */ 111 /* Description: Disable interrupt */ 112 113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ 114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ 119 120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ 121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ 126 127 /* Bit 0 : Write '1' to disable interrupt for event END */ 128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ 133 134 /* Register: AAR_STATUS */ 135 /* Description: Resolution status */ 136 137 /* Bits 3..0 : The IRK that was used last time an address was resolved */ 138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 140 141 /* Register: AAR_ENABLE */ 142 /* Description: Enable AAR */ 143 144 /* Bits 1..0 : Enable or disable AAR */ 145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ 149 150 /* Register: AAR_NIRK */ 151 /* Description: Number of IRKs */ 152 153 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ 154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 156 157 /* Register: AAR_IRKPTR */ 158 /* Description: Pointer to IRK data structure */ 159 160 /* Bits 31..0 : Pointer to the IRK data structure */ 161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ 162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ 163 164 /* Register: AAR_ADDRPTR */ 165 /* Description: Pointer to the resolvable address */ 166 167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ 168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ 169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ 170 171 /* Register: AAR_SCRATCHPTR */ 172 /* Description: Pointer to data area used for temporary storage */ 173 174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ 175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 177 178 179 /* Peripheral: APPROTECT */ 180 /* Description: Only for emulation on devices that support hardened AP-PROTECT. */ 181 182 /* Register: APPROTECT_FORCEPROTECT */ 183 /* Description: Software force enable APPROTECT mechanism until next reset. */ 184 185 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ 186 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ 187 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ 188 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ 189 190 /* Register: APPROTECT_DISABLE */ 191 /* Description: Software disable APPROTECT mechanism */ 192 193 /* Bits 7..0 : Software disable APPROTECT mechanism */ 194 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ 195 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ 196 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ 197 198 199 /* Peripheral: BPROT */ 200 /* Description: Block Protect */ 201 202 /* Register: BPROT_CONFIG0 */ 203 /* Description: Block protect configuration register 0 */ 204 205 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ 206 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ 207 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ 208 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ 209 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */ 210 211 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ 212 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ 213 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ 214 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ 215 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */ 216 217 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ 218 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ 219 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ 220 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ 221 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */ 222 223 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ 224 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ 225 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ 226 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ 227 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */ 228 229 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ 230 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ 231 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ 232 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ 233 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */ 234 235 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ 236 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ 237 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ 238 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ 239 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */ 240 241 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ 242 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ 243 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ 244 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ 245 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */ 246 247 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ 248 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ 249 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ 250 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ 251 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */ 252 253 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ 254 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ 255 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ 256 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ 257 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */ 258 259 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ 260 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ 261 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ 262 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ 263 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */ 264 265 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ 266 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ 267 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ 268 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ 269 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */ 270 271 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ 272 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ 273 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ 274 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ 275 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */ 276 277 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ 278 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ 279 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ 280 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ 281 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */ 282 283 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ 284 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ 285 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ 286 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ 287 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */ 288 289 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ 290 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ 291 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ 292 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ 293 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */ 294 295 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ 296 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ 297 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ 298 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ 299 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */ 300 301 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ 302 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ 303 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ 304 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ 305 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */ 306 307 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ 308 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ 309 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ 310 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ 311 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */ 312 313 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ 314 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ 315 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ 316 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ 317 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */ 318 319 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ 320 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ 321 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ 322 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ 323 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */ 324 325 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ 326 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ 327 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ 328 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ 329 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */ 330 331 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ 332 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ 333 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ 334 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ 335 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */ 336 337 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ 338 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ 339 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ 340 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ 341 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */ 342 343 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ 344 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ 345 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ 346 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ 347 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */ 348 349 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ 350 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ 351 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ 352 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ 353 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */ 354 355 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ 356 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ 357 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ 358 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ 359 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */ 360 361 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ 362 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ 363 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ 364 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ 365 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */ 366 367 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ 368 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ 369 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ 370 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ 371 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */ 372 373 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ 374 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ 375 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ 376 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ 377 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */ 378 379 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ 380 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ 381 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ 382 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ 383 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */ 384 385 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ 386 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ 387 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ 388 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ 389 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */ 390 391 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ 392 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ 393 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ 394 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ 395 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */ 396 397 /* Register: BPROT_CONFIG1 */ 398 /* Description: Block protect configuration register 1 */ 399 400 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ 401 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ 402 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ 403 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ 404 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ 405 406 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ 407 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ 408 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ 409 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ 410 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ 411 412 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ 413 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ 414 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ 415 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ 416 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ 417 418 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ 419 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ 420 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ 421 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ 422 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ 423 424 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ 425 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ 426 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ 427 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ 428 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ 429 430 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ 431 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ 432 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ 433 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ 434 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ 435 436 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ 437 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ 438 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ 439 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ 440 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ 441 442 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ 443 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ 444 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ 445 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ 446 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ 447 448 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ 449 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ 450 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ 451 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ 452 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ 453 454 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ 455 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ 456 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ 457 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ 458 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ 459 460 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ 461 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ 462 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ 463 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ 464 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ 465 466 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ 467 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ 468 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ 469 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ 470 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ 471 472 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ 473 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ 474 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ 475 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ 476 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ 477 478 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ 479 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ 480 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ 481 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ 482 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ 483 484 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ 485 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ 486 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ 487 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ 488 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ 489 490 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ 491 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ 492 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ 493 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ 494 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ 495 496 /* Register: BPROT_DISABLEINDEBUG */ 497 /* Description: Disable protection mechanism in debug mode */ 498 499 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */ 500 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 501 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 502 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */ 503 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */ 504 505 506 /* Peripheral: CCM */ 507 /* Description: AES CCM Mode Encryption */ 508 509 /* Register: CCM_TASKS_KSGEN */ 510 /* Description: Start generation of keystream. This operation will stop by itself when completed. */ 511 512 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ 513 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ 514 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ 515 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ 516 517 /* Register: CCM_TASKS_CRYPT */ 518 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ 519 520 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ 521 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ 522 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ 523 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ 524 525 /* Register: CCM_TASKS_STOP */ 526 /* Description: Stop encryption/decryption */ 527 528 /* Bit 0 : Stop encryption/decryption */ 529 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 530 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 531 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 532 533 /* Register: CCM_TASKS_RATEOVERRIDE */ 534 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 535 536 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 537 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ 538 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ 539 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ 540 541 /* Register: CCM_EVENTS_ENDKSGEN */ 542 /* Description: Keystream generation complete */ 543 544 /* Bit 0 : Keystream generation complete */ 545 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ 546 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ 547 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ 548 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ 549 550 /* Register: CCM_EVENTS_ENDCRYPT */ 551 /* Description: Encrypt/decrypt complete */ 552 553 /* Bit 0 : Encrypt/decrypt complete */ 554 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ 555 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ 556 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ 557 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ 558 559 /* Register: CCM_EVENTS_ERROR */ 560 /* Description: Deprecated register - CCM error event */ 561 562 /* Bit 0 : Deprecated field - CCM error event */ 563 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 564 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 565 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 566 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 567 568 /* Register: CCM_SHORTS */ 569 /* Description: Shortcuts between local events and tasks */ 570 571 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ 572 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 573 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 574 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ 575 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ 576 577 /* Register: CCM_INTENSET */ 578 /* Description: Enable interrupt */ 579 580 /* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ 581 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 582 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 583 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 584 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 585 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 586 587 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ 588 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 589 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 590 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 591 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 592 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ 593 594 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ 595 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 596 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 597 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 598 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 599 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ 600 601 /* Register: CCM_INTENCLR */ 602 /* Description: Disable interrupt */ 603 604 /* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ 605 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 606 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 607 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 608 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 609 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 610 611 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ 612 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 613 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 614 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 615 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 616 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ 617 618 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ 619 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 620 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 621 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 622 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 623 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ 624 625 /* Register: CCM_MICSTATUS */ 626 /* Description: MIC check result */ 627 628 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */ 629 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 630 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 631 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ 632 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ 633 634 /* Register: CCM_ENABLE */ 635 /* Description: Enable */ 636 637 /* Bits 1..0 : Enable or disable CCM */ 638 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 639 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 640 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 641 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 642 643 /* Register: CCM_MODE */ 644 /* Description: Operation mode */ 645 646 /* Bit 24 : Packet length configuration */ 647 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ 648 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ 649 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ 650 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ 651 652 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ 653 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ 654 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ 655 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ 656 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ 657 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ 658 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ 659 660 /* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ 661 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 662 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 663 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ 664 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ 665 666 /* Register: CCM_CNFPTR */ 667 /* Description: Pointer to data structure holding AES key and NONCE vector */ 668 669 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ 670 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ 671 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ 672 673 /* Register: CCM_INPTR */ 674 /* Description: Input pointer */ 675 676 /* Bits 31..0 : Input pointer */ 677 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ 678 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ 679 680 /* Register: CCM_OUTPTR */ 681 /* Description: Output pointer */ 682 683 /* Bits 31..0 : Output pointer */ 684 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ 685 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ 686 687 /* Register: CCM_SCRATCHPTR */ 688 /* Description: Pointer to data area used for temporary storage */ 689 690 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, 691 MIC generation and encryption/decryption. */ 692 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 693 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 694 695 /* Register: CCM_MAXPACKETSIZE */ 696 /* Description: Length of keystream generated when MODE.LENGTH = Extended. */ 697 698 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ 699 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ 700 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ 701 702 /* Register: CCM_RATEOVERRIDE */ 703 /* Description: Data rate override setting. */ 704 705 /* Bits 1..0 : Data rate override setting. */ 706 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ 707 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ 708 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ 709 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ 710 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ 711 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ 712 713 714 /* Peripheral: CLOCK */ 715 /* Description: Clock control */ 716 717 /* Register: CLOCK_TASKS_HFCLKSTART */ 718 /* Description: Start HFCLK crystal oscillator */ 719 720 /* Bit 0 : Start HFCLK crystal oscillator */ 721 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 722 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 723 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ 724 725 /* Register: CLOCK_TASKS_HFCLKSTOP */ 726 /* Description: Stop HFCLK crystal oscillator */ 727 728 /* Bit 0 : Stop HFCLK crystal oscillator */ 729 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 730 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 731 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 732 733 /* Register: CLOCK_TASKS_LFCLKSTART */ 734 /* Description: Start LFCLK source */ 735 736 /* Bit 0 : Start LFCLK source */ 737 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 738 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 739 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ 740 741 /* Register: CLOCK_TASKS_LFCLKSTOP */ 742 /* Description: Stop LFCLK source */ 743 744 /* Bit 0 : Stop LFCLK source */ 745 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 746 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 747 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 748 749 /* Register: CLOCK_TASKS_CAL */ 750 /* Description: Start calibration of LFRC oscillator */ 751 752 /* Bit 0 : Start calibration of LFRC oscillator */ 753 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ 754 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ 755 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ 756 757 /* Register: CLOCK_TASKS_CTSTART */ 758 /* Description: Start calibration timer */ 759 760 /* Bit 0 : Start calibration timer */ 761 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ 762 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ 763 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ 764 765 /* Register: CLOCK_TASKS_CTSTOP */ 766 /* Description: Stop calibration timer */ 767 768 /* Bit 0 : Stop calibration timer */ 769 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ 770 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ 771 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ 772 773 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 774 /* Description: HFCLK oscillator started */ 775 776 /* Bit 0 : HFCLK oscillator started */ 777 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 778 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 779 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 780 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ 781 782 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 783 /* Description: LFCLK started */ 784 785 /* Bit 0 : LFCLK started */ 786 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 787 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 788 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 789 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ 790 791 /* Register: CLOCK_EVENTS_DONE */ 792 /* Description: Calibration of LFCLK RC oscillator complete event */ 793 794 /* Bit 0 : Calibration of LFCLK RC oscillator complete event */ 795 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 796 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 797 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ 798 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ 799 800 /* Register: CLOCK_EVENTS_CTTO */ 801 /* Description: Calibration timer timeout */ 802 803 /* Bit 0 : Calibration timer timeout */ 804 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ 805 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ 806 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ 807 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ 808 809 /* Register: CLOCK_INTENSET */ 810 /* Description: Enable interrupt */ 811 812 /* Bit 4 : Write '1' to enable interrupt for event CTTO */ 813 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 814 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 815 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ 816 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ 817 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ 818 819 /* Bit 3 : Write '1' to enable interrupt for event DONE */ 820 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 821 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 822 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 823 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 824 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ 825 826 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ 827 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 828 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 829 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 830 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 831 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 832 833 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ 834 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 835 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 836 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 837 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 838 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 839 840 /* Register: CLOCK_INTENCLR */ 841 /* Description: Disable interrupt */ 842 843 /* Bit 4 : Write '1' to disable interrupt for event CTTO */ 844 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 845 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 846 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ 847 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ 848 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ 849 850 /* Bit 3 : Write '1' to disable interrupt for event DONE */ 851 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 852 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 853 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 854 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 855 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 856 857 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ 858 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 859 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 860 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 861 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 862 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 863 864 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ 865 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 866 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 867 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 868 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 869 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 870 871 /* Register: CLOCK_HFCLKRUN */ 872 /* Description: Status indicating that HFCLKSTART task has been triggered */ 873 874 /* Bit 0 : HFCLKSTART task triggered or not */ 875 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 876 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 877 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 878 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 879 880 /* Register: CLOCK_HFCLKSTAT */ 881 /* Description: HFCLK status */ 882 883 /* Bit 16 : HFCLK state */ 884 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 885 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 886 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ 887 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ 888 889 /* Bit 0 : Source of HFCLK */ 890 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 891 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 892 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ 893 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ 894 895 /* Register: CLOCK_LFCLKRUN */ 896 /* Description: Status indicating that LFCLKSTART task has been triggered */ 897 898 /* Bit 0 : LFCLKSTART task triggered or not */ 899 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 900 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 901 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 902 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 903 904 /* Register: CLOCK_LFCLKSTAT */ 905 /* Description: LFCLK status */ 906 907 /* Bit 16 : LFCLK state */ 908 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 909 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 910 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ 911 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ 912 913 /* Bits 1..0 : Source of LFCLK */ 914 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 915 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 916 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 917 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 918 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 919 920 /* Register: CLOCK_LFCLKSRCCOPY */ 921 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ 922 923 /* Bits 1..0 : Clock source */ 924 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 925 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 926 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 927 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 928 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 929 930 /* Register: CLOCK_LFCLKSRC */ 931 /* Description: Clock source for the LFCLK */ 932 933 /* Bit 17 : Enable or disable external source for LFCLK */ 934 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ 935 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ 936 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ 937 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ 938 939 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ 940 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ 941 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ 942 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ 943 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ 944 945 /* Bits 1..0 : Clock source */ 946 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 947 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 948 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 949 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 950 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 951 952 /* Register: CLOCK_CTIV */ 953 /* Description: Calibration timer interval */ 954 955 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ 956 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 957 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 958 959 960 /* Peripheral: ECB */ 961 /* Description: AES ECB Mode Encryption */ 962 963 /* Register: ECB_TASKS_STARTECB */ 964 /* Description: Start ECB block encrypt */ 965 966 /* Bit 0 : Start ECB block encrypt */ 967 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ 968 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ 969 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ 970 971 /* Register: ECB_TASKS_STOPECB */ 972 /* Description: Abort a possible executing ECB operation */ 973 974 /* Bit 0 : Abort a possible executing ECB operation */ 975 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ 976 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ 977 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ 978 979 /* Register: ECB_EVENTS_ENDECB */ 980 /* Description: ECB block encrypt complete */ 981 982 /* Bit 0 : ECB block encrypt complete */ 983 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ 984 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ 985 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ 986 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ 987 988 /* Register: ECB_EVENTS_ERRORECB */ 989 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ 990 991 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ 992 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ 993 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ 994 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ 995 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ 996 997 /* Register: ECB_INTENSET */ 998 /* Description: Enable interrupt */ 999 1000 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ 1001 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1002 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1003 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1004 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1005 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ 1006 1007 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */ 1008 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1009 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1010 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1011 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1012 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ 1013 1014 /* Register: ECB_INTENCLR */ 1015 /* Description: Disable interrupt */ 1016 1017 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ 1018 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1019 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1020 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1021 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1022 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ 1023 1024 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */ 1025 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1026 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1027 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1028 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1029 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ 1030 1031 /* Register: ECB_ECBDATAPTR */ 1032 /* Description: ECB block encrypt memory pointers */ 1033 1034 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ 1035 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ 1036 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ 1037 1038 1039 /* Peripheral: EGU */ 1040 /* Description: Event generator unit 0 */ 1041 1042 /* Register: EGU_TASKS_TRIGGER */ 1043 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ 1044 1045 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ 1046 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 1047 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 1048 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ 1049 1050 /* Register: EGU_EVENTS_TRIGGERED */ 1051 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ 1052 1053 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ 1054 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 1055 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 1056 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ 1057 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ 1058 1059 /* Register: EGU_INTEN */ 1060 /* Description: Enable or disable interrupt */ 1061 1062 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ 1063 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1064 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1065 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 1066 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 1067 1068 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ 1069 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1070 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1071 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ 1072 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ 1073 1074 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ 1075 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1076 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1077 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ 1078 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ 1079 1080 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ 1081 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1082 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1083 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ 1084 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ 1085 1086 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ 1087 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1088 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1089 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ 1090 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ 1091 1092 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ 1093 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1094 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1095 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ 1096 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ 1097 1098 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ 1099 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1100 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1101 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ 1102 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ 1103 1104 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ 1105 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1106 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1107 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ 1108 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ 1109 1110 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ 1111 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1112 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1113 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ 1114 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ 1115 1116 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ 1117 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1118 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1119 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ 1120 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ 1121 1122 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ 1123 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1124 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1125 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ 1126 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ 1127 1128 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ 1129 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1130 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1131 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ 1132 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ 1133 1134 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ 1135 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1136 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1137 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ 1138 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ 1139 1140 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ 1141 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1142 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1143 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ 1144 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ 1145 1146 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ 1147 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1148 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1149 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ 1150 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ 1151 1152 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ 1153 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1154 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1155 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 1156 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 1157 1158 /* Register: EGU_INTENSET */ 1159 /* Description: Enable interrupt */ 1160 1161 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ 1162 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1163 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1164 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1165 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1166 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 1167 1168 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ 1169 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1170 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1171 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1172 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1173 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ 1174 1175 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ 1176 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1177 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1178 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1179 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1180 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ 1181 1182 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ 1183 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1184 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1185 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1186 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1187 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ 1188 1189 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ 1190 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1191 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1192 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1193 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1194 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ 1195 1196 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ 1197 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1198 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1199 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1200 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1201 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ 1202 1203 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ 1204 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1205 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1206 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1207 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1208 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ 1209 1210 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ 1211 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1212 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1213 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1214 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1215 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ 1216 1217 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ 1218 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1219 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1220 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1221 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1222 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ 1223 1224 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ 1225 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1226 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1227 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1228 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1229 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ 1230 1231 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ 1232 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1233 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1234 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1235 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1236 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ 1237 1238 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ 1239 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1240 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1241 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1242 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1243 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ 1244 1245 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ 1246 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1247 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1248 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1249 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1250 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ 1251 1252 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ 1253 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1254 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1255 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1256 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1257 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ 1258 1259 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ 1260 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1261 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1262 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1263 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1264 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ 1265 1266 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ 1267 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1268 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1269 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1270 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1271 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 1272 1273 /* Register: EGU_INTENCLR */ 1274 /* Description: Disable interrupt */ 1275 1276 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ 1277 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1278 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1279 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1280 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1281 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 1282 1283 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ 1284 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1285 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1286 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1287 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1288 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ 1289 1290 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ 1291 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1292 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1293 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1294 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1295 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ 1296 1297 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ 1298 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1299 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1300 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1301 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1302 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ 1303 1304 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ 1305 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1306 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1307 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1308 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1309 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ 1310 1311 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ 1312 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1313 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1314 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1315 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1316 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ 1317 1318 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ 1319 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1320 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1321 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1322 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1323 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ 1324 1325 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ 1326 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1327 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1328 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1329 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1330 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ 1331 1332 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ 1333 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1334 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1335 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1336 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1337 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ 1338 1339 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ 1340 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1341 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1342 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1343 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1344 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ 1345 1346 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ 1347 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1348 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1349 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1350 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1351 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ 1352 1353 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ 1354 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1355 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1356 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1357 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1358 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ 1359 1360 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ 1361 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1362 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1363 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1364 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1365 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ 1366 1367 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ 1368 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1369 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1370 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1371 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1372 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ 1373 1374 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ 1375 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1376 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1377 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1378 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1379 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ 1380 1381 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ 1382 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1383 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1384 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1385 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1386 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 1387 1388 1389 /* Peripheral: FICR */ 1390 /* Description: Factory information configuration registers */ 1391 1392 /* Register: FICR_CODEPAGESIZE */ 1393 /* Description: Code memory page size */ 1394 1395 /* Bits 31..0 : Code memory page size */ 1396 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ 1397 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ 1398 1399 /* Register: FICR_CODESIZE */ 1400 /* Description: Code memory size */ 1401 1402 /* Bits 31..0 : Code memory size in number of pages */ 1403 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ 1404 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ 1405 1406 /* Register: FICR_DEVICEID */ 1407 /* Description: Description collection: Device identifier */ 1408 1409 /* Bits 31..0 : 64 bit unique device identifier */ 1410 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ 1411 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ 1412 1413 /* Register: FICR_ER */ 1414 /* Description: Description collection: Encryption root, word n */ 1415 1416 /* Bits 31..0 : Encryption root, word n */ 1417 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ 1418 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ 1419 1420 /* Register: FICR_IR */ 1421 /* Description: Description collection: Identity root, word n */ 1422 1423 /* Bits 31..0 : Identity root, word n */ 1424 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ 1425 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ 1426 1427 /* Register: FICR_DEVICEADDRTYPE */ 1428 /* Description: Device address type */ 1429 1430 /* Bit 0 : Device address type */ 1431 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 1432 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 1433 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ 1434 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ 1435 1436 /* Register: FICR_DEVICEADDR */ 1437 /* Description: Description collection: Device address n */ 1438 1439 /* Bits 31..0 : 48 bit device address */ 1440 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ 1441 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ 1442 1443 /* Register: FICR_INFO_PART */ 1444 /* Description: Part code */ 1445 1446 /* Bits 31..0 : Part code */ 1447 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 1448 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 1449 #define FICR_INFO_PART_PART_N52805 (0x52805UL) /*!< nRF52805 */ 1450 #define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */ 1451 #define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */ 1452 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ 1453 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1454 1455 /* Register: FICR_INFO_VARIANT */ 1456 /* Description: Part variant, hardware version and production configuration */ 1457 1458 /* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */ 1459 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 1460 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 1461 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ 1462 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ 1463 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ 1464 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ 1465 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ 1466 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ 1467 #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ 1468 #define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */ 1469 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1470 1471 /* Register: FICR_INFO_PACKAGE */ 1472 /* Description: Package option */ 1473 1474 /* Bits 31..0 : Package option */ 1475 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 1476 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 1477 #define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */ 1478 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1479 1480 /* Register: FICR_INFO_RAM */ 1481 /* Description: RAM variant */ 1482 1483 /* Bits 31..0 : RAM variant */ 1484 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 1485 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 1486 #define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */ 1487 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1488 1489 /* Register: FICR_INFO_FLASH */ 1490 /* Description: Flash variant */ 1491 1492 /* Bits 31..0 : Flash variant */ 1493 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 1494 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 1495 #define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */ 1496 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1497 1498 /* Register: FICR_TEMP_A0 */ 1499 /* Description: Slope definition A0 */ 1500 1501 /* Bits 11..0 : A (slope definition) register */ 1502 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ 1503 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ 1504 1505 /* Register: FICR_TEMP_A1 */ 1506 /* Description: Slope definition A1 */ 1507 1508 /* Bits 11..0 : A (slope definition) register */ 1509 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ 1510 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ 1511 1512 /* Register: FICR_TEMP_A2 */ 1513 /* Description: Slope definition A2 */ 1514 1515 /* Bits 11..0 : A (slope definition) register */ 1516 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ 1517 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ 1518 1519 /* Register: FICR_TEMP_A3 */ 1520 /* Description: Slope definition A3 */ 1521 1522 /* Bits 11..0 : A (slope definition) register */ 1523 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ 1524 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ 1525 1526 /* Register: FICR_TEMP_A4 */ 1527 /* Description: Slope definition A4 */ 1528 1529 /* Bits 11..0 : A (slope definition) register */ 1530 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ 1531 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ 1532 1533 /* Register: FICR_TEMP_A5 */ 1534 /* Description: Slope definition A5 */ 1535 1536 /* Bits 11..0 : A (slope definition) register */ 1537 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ 1538 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ 1539 1540 /* Register: FICR_TEMP_B0 */ 1541 /* Description: Y-intercept B0 */ 1542 1543 /* Bits 13..0 : B (y-intercept) */ 1544 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ 1545 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ 1546 1547 /* Register: FICR_TEMP_B1 */ 1548 /* Description: Y-intercept B1 */ 1549 1550 /* Bits 13..0 : B (y-intercept) */ 1551 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ 1552 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ 1553 1554 /* Register: FICR_TEMP_B2 */ 1555 /* Description: Y-intercept B2 */ 1556 1557 /* Bits 13..0 : B (y-intercept) */ 1558 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ 1559 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ 1560 1561 /* Register: FICR_TEMP_B3 */ 1562 /* Description: Y-intercept B3 */ 1563 1564 /* Bits 13..0 : B (y-intercept) */ 1565 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ 1566 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ 1567 1568 /* Register: FICR_TEMP_B4 */ 1569 /* Description: Y-intercept B4 */ 1570 1571 /* Bits 13..0 : B (y-intercept) */ 1572 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ 1573 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ 1574 1575 /* Register: FICR_TEMP_B5 */ 1576 /* Description: Y-intercept B5 */ 1577 1578 /* Bits 13..0 : B (y-intercept) */ 1579 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ 1580 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ 1581 1582 /* Register: FICR_TEMP_T0 */ 1583 /* Description: Segment end T0 */ 1584 1585 /* Bits 7..0 : T (segment end) register */ 1586 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ 1587 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ 1588 1589 /* Register: FICR_TEMP_T1 */ 1590 /* Description: Segment end T1 */ 1591 1592 /* Bits 7..0 : T (segment end) register */ 1593 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ 1594 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ 1595 1596 /* Register: FICR_TEMP_T2 */ 1597 /* Description: Segment end T2 */ 1598 1599 /* Bits 7..0 : T (segment end) register */ 1600 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ 1601 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ 1602 1603 /* Register: FICR_TEMP_T3 */ 1604 /* Description: Segment end T3 */ 1605 1606 /* Bits 7..0 : T (segment end) register */ 1607 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ 1608 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ 1609 1610 /* Register: FICR_TEMP_T4 */ 1611 /* Description: Segment end T4 */ 1612 1613 /* Bits 7..0 : T (segment end) register */ 1614 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ 1615 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ 1616 1617 1618 /* Peripheral: GPIOTE */ 1619 /* Description: GPIO Tasks and Events */ 1620 1621 /* Register: GPIOTE_TASKS_OUT */ 1622 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 1623 1624 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 1625 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ 1626 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ 1627 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ 1628 1629 /* Register: GPIOTE_TASKS_SET */ 1630 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 1631 1632 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 1633 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ 1634 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ 1635 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ 1636 1637 /* Register: GPIOTE_TASKS_CLR */ 1638 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 1639 1640 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 1641 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ 1642 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ 1643 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ 1644 1645 /* Register: GPIOTE_EVENTS_IN */ 1646 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ 1647 1648 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ 1649 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ 1650 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ 1651 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ 1652 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ 1653 1654 /* Register: GPIOTE_EVENTS_PORT */ 1655 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 1656 1657 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 1658 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ 1659 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ 1660 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ 1661 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ 1662 1663 /* Register: GPIOTE_INTENSET */ 1664 /* Description: Enable interrupt */ 1665 1666 /* Bit 31 : Write '1' to enable interrupt for event PORT */ 1667 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 1668 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 1669 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ 1670 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ 1671 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ 1672 1673 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */ 1674 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1675 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ 1676 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ 1677 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ 1678 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ 1679 1680 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */ 1681 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1682 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ 1683 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ 1684 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ 1685 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ 1686 1687 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */ 1688 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1689 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ 1690 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ 1691 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ 1692 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ 1693 1694 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */ 1695 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1696 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ 1697 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ 1698 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ 1699 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ 1700 1701 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */ 1702 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1703 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 1704 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ 1705 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ 1706 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ 1707 1708 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */ 1709 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1710 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 1711 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ 1712 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ 1713 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ 1714 1715 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */ 1716 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1717 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 1718 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ 1719 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ 1720 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ 1721 1722 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */ 1723 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1724 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 1725 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ 1726 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ 1727 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ 1728 1729 /* Register: GPIOTE_INTENCLR */ 1730 /* Description: Disable interrupt */ 1731 1732 /* Bit 31 : Write '1' to disable interrupt for event PORT */ 1733 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 1734 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 1735 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ 1736 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ 1737 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ 1738 1739 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */ 1740 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1741 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ 1742 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ 1743 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ 1744 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ 1745 1746 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */ 1747 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1748 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ 1749 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ 1750 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ 1751 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ 1752 1753 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */ 1754 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1755 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ 1756 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ 1757 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ 1758 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ 1759 1760 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */ 1761 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1762 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ 1763 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ 1764 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ 1765 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ 1766 1767 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */ 1768 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1769 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 1770 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ 1771 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ 1772 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ 1773 1774 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */ 1775 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1776 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 1777 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ 1778 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ 1779 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ 1780 1781 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */ 1782 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1783 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 1784 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ 1785 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ 1786 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ 1787 1788 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */ 1789 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1790 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 1791 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ 1792 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ 1793 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ 1794 1795 /* Register: GPIOTE_CONFIG */ 1796 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ 1797 1798 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ 1799 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 1800 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 1801 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ 1802 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ 1803 1804 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ 1805 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 1806 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 1807 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ 1808 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ 1809 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ 1810 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ 1811 1812 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ 1813 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 1814 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 1815 1816 /* Bits 1..0 : Mode */ 1817 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 1818 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 1819 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ 1820 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ 1821 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ 1822 1823 1824 /* Peripheral: NVMC */ 1825 /* Description: Non Volatile Memory Controller */ 1826 1827 /* Register: NVMC_READY */ 1828 /* Description: Ready flag */ 1829 1830 /* Bit 0 : NVMC is ready or busy */ 1831 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 1832 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 1833 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ 1834 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 1835 1836 /* Register: NVMC_CONFIG */ 1837 /* Description: Configuration register */ 1838 1839 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ 1840 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 1841 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 1842 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 1843 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ 1844 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 1845 1846 /* Register: NVMC_ERASEPAGE */ 1847 /* Description: Register for erasing a page in code area */ 1848 1849 /* Bits 31..0 : Register for starting erase of a page in code area */ 1850 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ 1851 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ 1852 1853 /* Register: NVMC_ERASEPCR1 */ 1854 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ 1855 1856 /* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */ 1857 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ 1858 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ 1859 1860 /* Register: NVMC_ERASEALL */ 1861 /* Description: Register for erasing all non-volatile user memory */ 1862 1863 /* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ 1864 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 1865 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 1866 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 1867 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ 1868 1869 /* Register: NVMC_ERASEPCR0 */ 1870 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ 1871 1872 /* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */ 1873 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ 1874 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ 1875 1876 /* Register: NVMC_ERASEUICR */ 1877 /* Description: Register for erasing user information configuration registers */ 1878 1879 /* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */ 1880 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 1881 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 1882 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ 1883 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ 1884 1885 /* Register: NVMC_ERASEPAGEPARTIAL */ 1886 /* Description: Register for partial erase of a page in code area */ 1887 1888 /* Bits 31..0 : Register for starting partial erase of a page in code area */ 1889 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ 1890 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ 1891 1892 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 1893 /* Description: Register for partial erase configuration */ 1894 1895 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 1896 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 1897 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 1898 1899 1900 /* Peripheral: GPIO */ 1901 /* Description: GPIO Port */ 1902 1903 /* Register: GPIO_OUT */ 1904 /* Description: Write GPIO port */ 1905 1906 /* Bit 31 : Pin 31 */ 1907 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1908 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1909 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ 1910 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ 1911 1912 /* Bit 30 : Pin 30 */ 1913 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1914 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1915 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ 1916 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ 1917 1918 /* Bit 29 : Pin 29 */ 1919 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1920 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1921 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ 1922 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ 1923 1924 /* Bit 28 : Pin 28 */ 1925 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1926 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1927 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ 1928 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ 1929 1930 /* Bit 27 : Pin 27 */ 1931 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1932 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1933 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ 1934 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ 1935 1936 /* Bit 26 : Pin 26 */ 1937 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1938 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1939 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ 1940 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ 1941 1942 /* Bit 25 : Pin 25 */ 1943 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1944 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1945 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ 1946 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ 1947 1948 /* Bit 24 : Pin 24 */ 1949 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1950 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1951 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ 1952 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ 1953 1954 /* Bit 23 : Pin 23 */ 1955 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1956 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1957 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ 1958 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ 1959 1960 /* Bit 22 : Pin 22 */ 1961 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1962 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1963 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ 1964 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ 1965 1966 /* Bit 21 : Pin 21 */ 1967 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1968 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1969 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ 1970 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ 1971 1972 /* Bit 20 : Pin 20 */ 1973 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1974 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1975 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ 1976 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ 1977 1978 /* Bit 19 : Pin 19 */ 1979 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1980 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1981 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ 1982 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ 1983 1984 /* Bit 18 : Pin 18 */ 1985 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1986 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1987 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ 1988 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ 1989 1990 /* Bit 17 : Pin 17 */ 1991 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1992 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1993 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ 1994 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ 1995 1996 /* Bit 16 : Pin 16 */ 1997 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1998 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1999 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ 2000 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ 2001 2002 /* Bit 15 : Pin 15 */ 2003 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2004 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2005 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ 2006 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ 2007 2008 /* Bit 14 : Pin 14 */ 2009 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2010 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2011 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ 2012 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ 2013 2014 /* Bit 13 : Pin 13 */ 2015 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2016 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2017 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ 2018 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ 2019 2020 /* Bit 12 : Pin 12 */ 2021 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2022 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2023 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ 2024 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ 2025 2026 /* Bit 11 : Pin 11 */ 2027 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2028 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2029 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ 2030 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ 2031 2032 /* Bit 10 : Pin 10 */ 2033 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2034 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2035 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ 2036 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ 2037 2038 /* Bit 9 : Pin 9 */ 2039 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2040 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2041 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ 2042 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ 2043 2044 /* Bit 8 : Pin 8 */ 2045 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2046 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2047 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ 2048 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ 2049 2050 /* Bit 7 : Pin 7 */ 2051 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2052 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2053 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ 2054 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ 2055 2056 /* Bit 6 : Pin 6 */ 2057 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2058 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2059 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ 2060 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ 2061 2062 /* Bit 5 : Pin 5 */ 2063 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2064 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2065 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ 2066 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ 2067 2068 /* Bit 4 : Pin 4 */ 2069 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2070 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2071 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ 2072 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ 2073 2074 /* Bit 3 : Pin 3 */ 2075 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2076 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2077 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ 2078 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ 2079 2080 /* Bit 2 : Pin 2 */ 2081 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2082 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2083 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ 2084 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ 2085 2086 /* Bit 1 : Pin 1 */ 2087 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2088 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2089 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ 2090 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ 2091 2092 /* Bit 0 : Pin 0 */ 2093 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2094 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2095 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ 2096 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ 2097 2098 /* Register: GPIO_OUTSET */ 2099 /* Description: Set individual bits in GPIO port */ 2100 2101 /* Bit 31 : Pin 31 */ 2102 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2103 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2104 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ 2105 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ 2106 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2107 2108 /* Bit 30 : Pin 30 */ 2109 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2110 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2111 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ 2112 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ 2113 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2114 2115 /* Bit 29 : Pin 29 */ 2116 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2117 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2118 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ 2119 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ 2120 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2121 2122 /* Bit 28 : Pin 28 */ 2123 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2124 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2125 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ 2126 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ 2127 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2128 2129 /* Bit 27 : Pin 27 */ 2130 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2131 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2132 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ 2133 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ 2134 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2135 2136 /* Bit 26 : Pin 26 */ 2137 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2138 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2139 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ 2140 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ 2141 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2142 2143 /* Bit 25 : Pin 25 */ 2144 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2145 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2146 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ 2147 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ 2148 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2149 2150 /* Bit 24 : Pin 24 */ 2151 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2152 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2153 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ 2154 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ 2155 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2156 2157 /* Bit 23 : Pin 23 */ 2158 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2159 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2160 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ 2161 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ 2162 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2163 2164 /* Bit 22 : Pin 22 */ 2165 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2166 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2167 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ 2168 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ 2169 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2170 2171 /* Bit 21 : Pin 21 */ 2172 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2173 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2174 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ 2175 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ 2176 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2177 2178 /* Bit 20 : Pin 20 */ 2179 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2180 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2181 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ 2182 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ 2183 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2184 2185 /* Bit 19 : Pin 19 */ 2186 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2187 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2188 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ 2189 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ 2190 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2191 2192 /* Bit 18 : Pin 18 */ 2193 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2194 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2195 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ 2196 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ 2197 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2198 2199 /* Bit 17 : Pin 17 */ 2200 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2201 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2202 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ 2203 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ 2204 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2205 2206 /* Bit 16 : Pin 16 */ 2207 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2208 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2209 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ 2210 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ 2211 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2212 2213 /* Bit 15 : Pin 15 */ 2214 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2215 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2216 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ 2217 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ 2218 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2219 2220 /* Bit 14 : Pin 14 */ 2221 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2222 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2223 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ 2224 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ 2225 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2226 2227 /* Bit 13 : Pin 13 */ 2228 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2229 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2230 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ 2231 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ 2232 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2233 2234 /* Bit 12 : Pin 12 */ 2235 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2236 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2237 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ 2238 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ 2239 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2240 2241 /* Bit 11 : Pin 11 */ 2242 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2243 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2244 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ 2245 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ 2246 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2247 2248 /* Bit 10 : Pin 10 */ 2249 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2250 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2251 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ 2252 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ 2253 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2254 2255 /* Bit 9 : Pin 9 */ 2256 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2257 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2258 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ 2259 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ 2260 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2261 2262 /* Bit 8 : Pin 8 */ 2263 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2264 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2265 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ 2266 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ 2267 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2268 2269 /* Bit 7 : Pin 7 */ 2270 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2271 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2272 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ 2273 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ 2274 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2275 2276 /* Bit 6 : Pin 6 */ 2277 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2278 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2279 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ 2280 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ 2281 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2282 2283 /* Bit 5 : Pin 5 */ 2284 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2285 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2286 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ 2287 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ 2288 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2289 2290 /* Bit 4 : Pin 4 */ 2291 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2292 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2293 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ 2294 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ 2295 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2296 2297 /* Bit 3 : Pin 3 */ 2298 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2299 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2300 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ 2301 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ 2302 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2303 2304 /* Bit 2 : Pin 2 */ 2305 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2306 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2307 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ 2308 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ 2309 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2310 2311 /* Bit 1 : Pin 1 */ 2312 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2313 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2314 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ 2315 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ 2316 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2317 2318 /* Bit 0 : Pin 0 */ 2319 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2320 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2321 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ 2322 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ 2323 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ 2324 2325 /* Register: GPIO_OUTCLR */ 2326 /* Description: Clear individual bits in GPIO port */ 2327 2328 /* Bit 31 : Pin 31 */ 2329 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2330 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2331 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ 2332 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ 2333 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2334 2335 /* Bit 30 : Pin 30 */ 2336 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2337 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2338 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ 2339 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ 2340 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2341 2342 /* Bit 29 : Pin 29 */ 2343 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2344 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2345 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ 2346 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ 2347 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2348 2349 /* Bit 28 : Pin 28 */ 2350 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2351 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2352 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ 2353 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ 2354 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2355 2356 /* Bit 27 : Pin 27 */ 2357 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2358 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2359 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ 2360 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ 2361 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2362 2363 /* Bit 26 : Pin 26 */ 2364 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2365 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2366 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ 2367 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ 2368 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2369 2370 /* Bit 25 : Pin 25 */ 2371 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2372 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2373 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ 2374 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ 2375 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2376 2377 /* Bit 24 : Pin 24 */ 2378 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2379 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2380 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ 2381 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ 2382 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2383 2384 /* Bit 23 : Pin 23 */ 2385 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2386 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2387 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ 2388 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ 2389 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2390 2391 /* Bit 22 : Pin 22 */ 2392 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2393 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2394 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ 2395 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ 2396 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2397 2398 /* Bit 21 : Pin 21 */ 2399 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2400 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2401 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ 2402 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ 2403 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2404 2405 /* Bit 20 : Pin 20 */ 2406 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2407 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2408 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ 2409 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ 2410 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2411 2412 /* Bit 19 : Pin 19 */ 2413 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2414 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2415 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ 2416 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ 2417 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2418 2419 /* Bit 18 : Pin 18 */ 2420 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2421 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2422 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ 2423 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ 2424 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2425 2426 /* Bit 17 : Pin 17 */ 2427 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2428 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2429 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ 2430 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ 2431 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2432 2433 /* Bit 16 : Pin 16 */ 2434 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2435 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2436 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ 2437 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ 2438 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2439 2440 /* Bit 15 : Pin 15 */ 2441 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2442 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2443 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ 2444 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ 2445 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2446 2447 /* Bit 14 : Pin 14 */ 2448 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2449 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2450 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ 2451 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ 2452 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2453 2454 /* Bit 13 : Pin 13 */ 2455 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2456 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2457 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ 2458 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ 2459 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2460 2461 /* Bit 12 : Pin 12 */ 2462 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2463 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2464 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ 2465 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ 2466 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2467 2468 /* Bit 11 : Pin 11 */ 2469 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2470 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2471 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ 2472 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ 2473 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2474 2475 /* Bit 10 : Pin 10 */ 2476 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2477 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2478 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ 2479 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ 2480 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2481 2482 /* Bit 9 : Pin 9 */ 2483 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2484 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2485 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ 2486 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ 2487 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2488 2489 /* Bit 8 : Pin 8 */ 2490 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2491 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2492 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ 2493 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ 2494 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2495 2496 /* Bit 7 : Pin 7 */ 2497 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2498 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2499 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ 2500 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ 2501 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2502 2503 /* Bit 6 : Pin 6 */ 2504 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2505 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2506 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ 2507 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ 2508 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2509 2510 /* Bit 5 : Pin 5 */ 2511 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2512 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2513 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ 2514 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ 2515 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2516 2517 /* Bit 4 : Pin 4 */ 2518 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2519 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2520 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ 2521 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ 2522 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2523 2524 /* Bit 3 : Pin 3 */ 2525 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2526 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2527 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ 2528 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ 2529 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2530 2531 /* Bit 2 : Pin 2 */ 2532 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2533 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2534 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ 2535 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ 2536 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2537 2538 /* Bit 1 : Pin 1 */ 2539 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2540 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2541 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ 2542 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ 2543 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2544 2545 /* Bit 0 : Pin 0 */ 2546 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2547 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2548 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ 2549 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ 2550 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ 2551 2552 /* Register: GPIO_IN */ 2553 /* Description: Read GPIO port */ 2554 2555 /* Bit 31 : Pin 31 */ 2556 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2557 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2558 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ 2559 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ 2560 2561 /* Bit 30 : Pin 30 */ 2562 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2563 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2564 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ 2565 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ 2566 2567 /* Bit 29 : Pin 29 */ 2568 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2569 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2570 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ 2571 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ 2572 2573 /* Bit 28 : Pin 28 */ 2574 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2575 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2576 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ 2577 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ 2578 2579 /* Bit 27 : Pin 27 */ 2580 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2581 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2582 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ 2583 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ 2584 2585 /* Bit 26 : Pin 26 */ 2586 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2587 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2588 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ 2589 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ 2590 2591 /* Bit 25 : Pin 25 */ 2592 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2593 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2594 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ 2595 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ 2596 2597 /* Bit 24 : Pin 24 */ 2598 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2599 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2600 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ 2601 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ 2602 2603 /* Bit 23 : Pin 23 */ 2604 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2605 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2606 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ 2607 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ 2608 2609 /* Bit 22 : Pin 22 */ 2610 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2611 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2612 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ 2613 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ 2614 2615 /* Bit 21 : Pin 21 */ 2616 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2617 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2618 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ 2619 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ 2620 2621 /* Bit 20 : Pin 20 */ 2622 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2623 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2624 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ 2625 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ 2626 2627 /* Bit 19 : Pin 19 */ 2628 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2629 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2630 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ 2631 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ 2632 2633 /* Bit 18 : Pin 18 */ 2634 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2635 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2636 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ 2637 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ 2638 2639 /* Bit 17 : Pin 17 */ 2640 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2641 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2642 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ 2643 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ 2644 2645 /* Bit 16 : Pin 16 */ 2646 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2647 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2648 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ 2649 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ 2650 2651 /* Bit 15 : Pin 15 */ 2652 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2653 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2654 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ 2655 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ 2656 2657 /* Bit 14 : Pin 14 */ 2658 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2659 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2660 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ 2661 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ 2662 2663 /* Bit 13 : Pin 13 */ 2664 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2665 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2666 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ 2667 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ 2668 2669 /* Bit 12 : Pin 12 */ 2670 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2671 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2672 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ 2673 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ 2674 2675 /* Bit 11 : Pin 11 */ 2676 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2677 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2678 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ 2679 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ 2680 2681 /* Bit 10 : Pin 10 */ 2682 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2683 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2684 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ 2685 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ 2686 2687 /* Bit 9 : Pin 9 */ 2688 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2689 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2690 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ 2691 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ 2692 2693 /* Bit 8 : Pin 8 */ 2694 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2695 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2696 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ 2697 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ 2698 2699 /* Bit 7 : Pin 7 */ 2700 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2701 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2702 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ 2703 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ 2704 2705 /* Bit 6 : Pin 6 */ 2706 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2707 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2708 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ 2709 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ 2710 2711 /* Bit 5 : Pin 5 */ 2712 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2713 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2714 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ 2715 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ 2716 2717 /* Bit 4 : Pin 4 */ 2718 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2719 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2720 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ 2721 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ 2722 2723 /* Bit 3 : Pin 3 */ 2724 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2725 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2726 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ 2727 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ 2728 2729 /* Bit 2 : Pin 2 */ 2730 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2731 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2732 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ 2733 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ 2734 2735 /* Bit 1 : Pin 1 */ 2736 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2737 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2738 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ 2739 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ 2740 2741 /* Bit 0 : Pin 0 */ 2742 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2743 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2744 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ 2745 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ 2746 2747 /* Register: GPIO_DIR */ 2748 /* Description: Direction of GPIO pins */ 2749 2750 /* Bit 31 : Pin 31 */ 2751 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2752 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2753 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ 2754 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ 2755 2756 /* Bit 30 : Pin 30 */ 2757 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2758 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2759 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ 2760 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ 2761 2762 /* Bit 29 : Pin 29 */ 2763 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2764 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2765 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ 2766 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ 2767 2768 /* Bit 28 : Pin 28 */ 2769 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2770 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2771 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ 2772 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ 2773 2774 /* Bit 27 : Pin 27 */ 2775 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2776 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2777 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ 2778 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ 2779 2780 /* Bit 26 : Pin 26 */ 2781 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2782 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2783 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ 2784 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ 2785 2786 /* Bit 25 : Pin 25 */ 2787 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2788 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2789 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ 2790 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ 2791 2792 /* Bit 24 : Pin 24 */ 2793 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2794 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2795 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ 2796 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ 2797 2798 /* Bit 23 : Pin 23 */ 2799 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2800 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2801 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ 2802 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ 2803 2804 /* Bit 22 : Pin 22 */ 2805 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2806 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2807 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ 2808 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ 2809 2810 /* Bit 21 : Pin 21 */ 2811 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2812 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2813 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ 2814 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ 2815 2816 /* Bit 20 : Pin 20 */ 2817 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2818 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2819 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ 2820 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ 2821 2822 /* Bit 19 : Pin 19 */ 2823 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2824 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2825 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ 2826 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ 2827 2828 /* Bit 18 : Pin 18 */ 2829 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2830 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2831 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ 2832 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ 2833 2834 /* Bit 17 : Pin 17 */ 2835 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2836 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2837 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ 2838 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ 2839 2840 /* Bit 16 : Pin 16 */ 2841 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2842 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2843 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ 2844 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ 2845 2846 /* Bit 15 : Pin 15 */ 2847 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2848 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2849 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ 2850 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ 2851 2852 /* Bit 14 : Pin 14 */ 2853 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2854 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2855 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ 2856 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ 2857 2858 /* Bit 13 : Pin 13 */ 2859 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2860 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2861 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ 2862 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ 2863 2864 /* Bit 12 : Pin 12 */ 2865 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2866 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2867 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ 2868 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ 2869 2870 /* Bit 11 : Pin 11 */ 2871 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2872 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2873 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ 2874 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ 2875 2876 /* Bit 10 : Pin 10 */ 2877 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2878 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2879 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ 2880 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ 2881 2882 /* Bit 9 : Pin 9 */ 2883 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2884 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2885 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ 2886 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ 2887 2888 /* Bit 8 : Pin 8 */ 2889 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2890 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2891 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ 2892 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ 2893 2894 /* Bit 7 : Pin 7 */ 2895 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2896 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2897 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ 2898 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ 2899 2900 /* Bit 6 : Pin 6 */ 2901 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2902 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2903 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ 2904 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ 2905 2906 /* Bit 5 : Pin 5 */ 2907 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2908 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2909 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ 2910 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ 2911 2912 /* Bit 4 : Pin 4 */ 2913 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2914 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2915 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ 2916 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ 2917 2918 /* Bit 3 : Pin 3 */ 2919 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2920 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2921 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ 2922 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ 2923 2924 /* Bit 2 : Pin 2 */ 2925 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2926 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2927 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ 2928 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ 2929 2930 /* Bit 1 : Pin 1 */ 2931 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2932 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2933 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ 2934 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ 2935 2936 /* Bit 0 : Pin 0 */ 2937 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2938 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2939 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ 2940 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ 2941 2942 /* Register: GPIO_DIRSET */ 2943 /* Description: DIR set register */ 2944 2945 /* Bit 31 : Set as output pin 31 */ 2946 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2947 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2948 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ 2949 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ 2950 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2951 2952 /* Bit 30 : Set as output pin 30 */ 2953 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2954 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2955 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ 2956 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ 2957 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2958 2959 /* Bit 29 : Set as output pin 29 */ 2960 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2961 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2962 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ 2963 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ 2964 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2965 2966 /* Bit 28 : Set as output pin 28 */ 2967 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2968 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2969 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ 2970 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ 2971 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2972 2973 /* Bit 27 : Set as output pin 27 */ 2974 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2975 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2976 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ 2977 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ 2978 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2979 2980 /* Bit 26 : Set as output pin 26 */ 2981 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2982 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2983 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ 2984 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ 2985 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2986 2987 /* Bit 25 : Set as output pin 25 */ 2988 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2989 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2990 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ 2991 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ 2992 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 2993 2994 /* Bit 24 : Set as output pin 24 */ 2995 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2996 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2997 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ 2998 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ 2999 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3000 3001 /* Bit 23 : Set as output pin 23 */ 3002 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3003 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3004 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ 3005 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ 3006 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3007 3008 /* Bit 22 : Set as output pin 22 */ 3009 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3010 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3011 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ 3012 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ 3013 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3014 3015 /* Bit 21 : Set as output pin 21 */ 3016 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3017 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3018 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ 3019 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ 3020 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3021 3022 /* Bit 20 : Set as output pin 20 */ 3023 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3024 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3025 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ 3026 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ 3027 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3028 3029 /* Bit 19 : Set as output pin 19 */ 3030 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3031 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3032 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ 3033 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ 3034 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3035 3036 /* Bit 18 : Set as output pin 18 */ 3037 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3038 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3039 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ 3040 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ 3041 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3042 3043 /* Bit 17 : Set as output pin 17 */ 3044 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3045 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3046 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ 3047 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ 3048 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3049 3050 /* Bit 16 : Set as output pin 16 */ 3051 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3052 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3053 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ 3054 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ 3055 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3056 3057 /* Bit 15 : Set as output pin 15 */ 3058 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3059 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3060 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ 3061 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ 3062 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3063 3064 /* Bit 14 : Set as output pin 14 */ 3065 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3066 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3067 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ 3068 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ 3069 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3070 3071 /* Bit 13 : Set as output pin 13 */ 3072 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3073 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3074 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ 3075 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ 3076 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3077 3078 /* Bit 12 : Set as output pin 12 */ 3079 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3080 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3081 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ 3082 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ 3083 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3084 3085 /* Bit 11 : Set as output pin 11 */ 3086 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3087 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3088 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ 3089 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ 3090 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3091 3092 /* Bit 10 : Set as output pin 10 */ 3093 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3094 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3095 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ 3096 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ 3097 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3098 3099 /* Bit 9 : Set as output pin 9 */ 3100 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3101 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3102 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ 3103 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ 3104 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3105 3106 /* Bit 8 : Set as output pin 8 */ 3107 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3108 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3109 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ 3110 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ 3111 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3112 3113 /* Bit 7 : Set as output pin 7 */ 3114 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3115 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3116 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ 3117 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ 3118 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3119 3120 /* Bit 6 : Set as output pin 6 */ 3121 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3122 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3123 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ 3124 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ 3125 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3126 3127 /* Bit 5 : Set as output pin 5 */ 3128 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3129 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3130 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ 3131 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ 3132 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3133 3134 /* Bit 4 : Set as output pin 4 */ 3135 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3136 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3137 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ 3138 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ 3139 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3140 3141 /* Bit 3 : Set as output pin 3 */ 3142 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3143 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3144 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ 3145 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ 3146 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3147 3148 /* Bit 2 : Set as output pin 2 */ 3149 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3150 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3151 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ 3152 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ 3153 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3154 3155 /* Bit 1 : Set as output pin 1 */ 3156 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3157 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3158 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ 3159 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ 3160 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3161 3162 /* Bit 0 : Set as output pin 0 */ 3163 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3164 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3165 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ 3166 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ 3167 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ 3168 3169 /* Register: GPIO_DIRCLR */ 3170 /* Description: DIR clear register */ 3171 3172 /* Bit 31 : Set as input pin 31 */ 3173 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3174 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3175 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ 3176 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ 3177 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3178 3179 /* Bit 30 : Set as input pin 30 */ 3180 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3181 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3182 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ 3183 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ 3184 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3185 3186 /* Bit 29 : Set as input pin 29 */ 3187 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3188 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3189 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ 3190 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ 3191 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3192 3193 /* Bit 28 : Set as input pin 28 */ 3194 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3195 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3196 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ 3197 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ 3198 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3199 3200 /* Bit 27 : Set as input pin 27 */ 3201 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3202 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3203 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ 3204 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ 3205 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3206 3207 /* Bit 26 : Set as input pin 26 */ 3208 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3209 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3210 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ 3211 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ 3212 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3213 3214 /* Bit 25 : Set as input pin 25 */ 3215 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3216 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3217 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ 3218 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ 3219 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3220 3221 /* Bit 24 : Set as input pin 24 */ 3222 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3223 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3224 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ 3225 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ 3226 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3227 3228 /* Bit 23 : Set as input pin 23 */ 3229 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3230 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3231 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ 3232 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ 3233 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3234 3235 /* Bit 22 : Set as input pin 22 */ 3236 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3237 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3238 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ 3239 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ 3240 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3241 3242 /* Bit 21 : Set as input pin 21 */ 3243 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3244 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3245 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ 3246 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ 3247 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3248 3249 /* Bit 20 : Set as input pin 20 */ 3250 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3251 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3252 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ 3253 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ 3254 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3255 3256 /* Bit 19 : Set as input pin 19 */ 3257 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3258 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3259 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ 3260 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ 3261 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3262 3263 /* Bit 18 : Set as input pin 18 */ 3264 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3265 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3266 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ 3267 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ 3268 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3269 3270 /* Bit 17 : Set as input pin 17 */ 3271 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3272 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3273 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ 3274 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ 3275 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3276 3277 /* Bit 16 : Set as input pin 16 */ 3278 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3279 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3280 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ 3281 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ 3282 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3283 3284 /* Bit 15 : Set as input pin 15 */ 3285 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3286 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3287 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ 3288 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ 3289 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3290 3291 /* Bit 14 : Set as input pin 14 */ 3292 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3293 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3294 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ 3295 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ 3296 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3297 3298 /* Bit 13 : Set as input pin 13 */ 3299 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3300 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3301 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ 3302 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ 3303 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3304 3305 /* Bit 12 : Set as input pin 12 */ 3306 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3307 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3308 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ 3309 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ 3310 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3311 3312 /* Bit 11 : Set as input pin 11 */ 3313 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3314 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3315 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ 3316 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ 3317 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3318 3319 /* Bit 10 : Set as input pin 10 */ 3320 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3321 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3322 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ 3323 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ 3324 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3325 3326 /* Bit 9 : Set as input pin 9 */ 3327 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3328 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3329 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ 3330 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ 3331 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3332 3333 /* Bit 8 : Set as input pin 8 */ 3334 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3335 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3336 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ 3337 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ 3338 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3339 3340 /* Bit 7 : Set as input pin 7 */ 3341 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3342 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3343 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ 3344 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ 3345 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3346 3347 /* Bit 6 : Set as input pin 6 */ 3348 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3349 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3350 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ 3351 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ 3352 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3353 3354 /* Bit 5 : Set as input pin 5 */ 3355 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3356 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3357 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ 3358 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ 3359 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3360 3361 /* Bit 4 : Set as input pin 4 */ 3362 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3363 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3364 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ 3365 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ 3366 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3367 3368 /* Bit 3 : Set as input pin 3 */ 3369 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3370 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3371 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ 3372 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ 3373 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3374 3375 /* Bit 2 : Set as input pin 2 */ 3376 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3377 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3378 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ 3379 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ 3380 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3381 3382 /* Bit 1 : Set as input pin 1 */ 3383 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3384 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3385 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ 3386 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ 3387 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3388 3389 /* Bit 0 : Set as input pin 0 */ 3390 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3391 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3392 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ 3393 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ 3394 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ 3395 3396 /* Register: GPIO_LATCH */ 3397 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ 3398 3399 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ 3400 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3401 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3402 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ 3403 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ 3404 3405 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ 3406 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3407 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3408 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ 3409 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ 3410 3411 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ 3412 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3413 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3414 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ 3415 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ 3416 3417 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ 3418 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3419 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3420 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ 3421 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ 3422 3423 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ 3424 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3425 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3426 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ 3427 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ 3428 3429 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ 3430 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3431 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3432 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ 3433 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ 3434 3435 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ 3436 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3437 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3438 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ 3439 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ 3440 3441 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ 3442 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3443 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3444 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ 3445 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ 3446 3447 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ 3448 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3449 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3450 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ 3451 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ 3452 3453 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ 3454 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3455 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3456 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ 3457 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ 3458 3459 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ 3460 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3461 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3462 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ 3463 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ 3464 3465 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ 3466 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3467 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3468 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ 3469 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ 3470 3471 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ 3472 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3473 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3474 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ 3475 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ 3476 3477 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ 3478 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3479 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3480 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ 3481 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ 3482 3483 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ 3484 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3485 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3486 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ 3487 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ 3488 3489 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ 3490 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3491 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3492 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ 3493 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ 3494 3495 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ 3496 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3497 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3498 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ 3499 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ 3500 3501 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ 3502 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3503 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3504 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ 3505 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ 3506 3507 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ 3508 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3509 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3510 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ 3511 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ 3512 3513 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ 3514 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3515 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3516 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ 3517 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ 3518 3519 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ 3520 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3521 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3522 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ 3523 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ 3524 3525 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ 3526 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3527 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3528 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ 3529 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ 3530 3531 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ 3532 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3533 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3534 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ 3535 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ 3536 3537 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ 3538 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3539 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3540 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ 3541 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ 3542 3543 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ 3544 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3545 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3546 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ 3547 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ 3548 3549 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ 3550 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3551 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3552 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ 3553 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ 3554 3555 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ 3556 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3557 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3558 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ 3559 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ 3560 3561 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ 3562 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3563 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3564 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ 3565 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ 3566 3567 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ 3568 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3569 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3570 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ 3571 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ 3572 3573 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ 3574 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3575 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3576 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ 3577 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ 3578 3579 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ 3580 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3581 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3582 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ 3583 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ 3584 3585 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ 3586 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3587 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3588 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ 3589 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ 3590 3591 /* Register: GPIO_DETECTMODE */ 3592 /* Description: Select between default DETECT signal behavior and LDETECT mode */ 3593 3594 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ 3595 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 3596 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 3597 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ 3598 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ 3599 3600 /* Register: GPIO_PIN_CNF */ 3601 /* Description: Description collection: Configuration of GPIO pins */ 3602 3603 /* Bits 17..16 : Pin sensing mechanism */ 3604 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 3605 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 3606 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ 3607 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ 3608 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ 3609 3610 /* Bits 10..8 : Drive configuration */ 3611 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 3612 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 3613 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ 3614 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ 3615 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ 3616 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ 3617 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ 3618 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 3619 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ 3620 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ 3621 3622 /* Bits 3..2 : Pull configuration */ 3623 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 3624 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 3625 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ 3626 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ 3627 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ 3628 3629 /* Bit 1 : Connect or disconnect input buffer */ 3630 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 3631 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 3632 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ 3633 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ 3634 3635 /* Bit 0 : Pin direction. Same physical register as DIR register */ 3636 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 3637 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 3638 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ 3639 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ 3640 3641 3642 /* Peripheral: POWER */ 3643 /* Description: Power control */ 3644 3645 /* Register: POWER_TASKS_CONSTLAT */ 3646 /* Description: Enable Constant Latency mode */ 3647 3648 /* Bit 0 : Enable Constant Latency mode */ 3649 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ 3650 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ 3651 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ 3652 3653 /* Register: POWER_TASKS_LOWPWR */ 3654 /* Description: Enable Low-power mode (variable latency) */ 3655 3656 /* Bit 0 : Enable Low-power mode (variable latency) */ 3657 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ 3658 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ 3659 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ 3660 3661 /* Register: POWER_EVENTS_POFWARN */ 3662 /* Description: Power failure warning */ 3663 3664 /* Bit 0 : Power failure warning */ 3665 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ 3666 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ 3667 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ 3668 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ 3669 3670 /* Register: POWER_EVENTS_SLEEPENTER */ 3671 /* Description: CPU entered WFI/WFE sleep */ 3672 3673 /* Bit 0 : CPU entered WFI/WFE sleep */ 3674 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ 3675 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ 3676 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ 3677 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ 3678 3679 /* Register: POWER_EVENTS_SLEEPEXIT */ 3680 /* Description: CPU exited WFI/WFE sleep */ 3681 3682 /* Bit 0 : CPU exited WFI/WFE sleep */ 3683 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ 3684 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ 3685 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ 3686 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ 3687 3688 /* Register: POWER_INTENSET */ 3689 /* Description: Enable interrupt */ 3690 3691 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ 3692 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 3693 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 3694 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 3695 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 3696 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ 3697 3698 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ 3699 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 3700 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 3701 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 3702 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 3703 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ 3704 3705 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */ 3706 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3707 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3708 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 3709 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 3710 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ 3711 3712 /* Register: POWER_INTENCLR */ 3713 /* Description: Disable interrupt */ 3714 3715 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ 3716 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 3717 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 3718 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 3719 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 3720 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ 3721 3722 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ 3723 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 3724 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 3725 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 3726 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 3727 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ 3728 3729 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */ 3730 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3731 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3732 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 3733 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 3734 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ 3735 3736 /* Register: POWER_RESETREAS */ 3737 /* Description: Reset reason */ 3738 3739 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ 3740 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 3741 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 3742 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ 3743 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ 3744 3745 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ 3746 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 3747 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 3748 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ 3749 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ 3750 3751 /* Bit 3 : Reset from CPU lock-up detected */ 3752 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 3753 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 3754 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ 3755 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ 3756 3757 /* Bit 2 : Reset from soft reset detected */ 3758 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 3759 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 3760 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ 3761 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ 3762 3763 /* Bit 1 : Reset from watchdog detected */ 3764 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 3765 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 3766 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ 3767 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ 3768 3769 /* Bit 0 : Reset from pin-reset detected */ 3770 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 3771 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 3772 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ 3773 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ 3774 3775 /* Register: POWER_SYSTEMOFF */ 3776 /* Description: System OFF register */ 3777 3778 /* Bit 0 : Enable System OFF mode */ 3779 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 3780 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 3781 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ 3782 3783 /* Register: POWER_POFCON */ 3784 /* Description: Power failure comparator configuration */ 3785 3786 /* Bits 4..1 : Power failure comparator threshold setting */ 3787 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 3788 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 3789 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ 3790 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ 3791 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ 3792 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ 3793 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ 3794 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ 3795 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ 3796 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ 3797 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ 3798 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ 3799 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ 3800 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ 3801 3802 /* Bit 0 : Enable or disable power failure comparator */ 3803 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 3804 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 3805 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ 3806 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ 3807 3808 /* Register: POWER_GPREGRET */ 3809 /* Description: General purpose retention register */ 3810 3811 /* Bits 7..0 : General purpose retention register */ 3812 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 3813 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 3814 3815 /* Register: POWER_GPREGRET2 */ 3816 /* Description: General purpose retention register */ 3817 3818 /* Bits 7..0 : General purpose retention register */ 3819 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 3820 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 3821 3822 /* Register: POWER_DCDCEN */ 3823 /* Description: DC/DC enable register */ 3824 3825 /* Bit 0 : Enable or disable DC/DC converter */ 3826 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 3827 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 3828 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ 3829 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ 3830 3831 /* Register: POWER_RAM_POWER */ 3832 /* Description: Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ 3833 3834 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ 3835 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 3836 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 3837 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ 3838 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ 3839 3840 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ 3841 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 3842 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 3843 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ 3844 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ 3845 3846 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ 3847 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 3848 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 3849 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ 3850 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ 3851 3852 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ 3853 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 3854 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 3855 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ 3856 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ 3857 3858 /* Register: POWER_RAM_POWERSET */ 3859 /* Description: Description cluster: RAMn power control set register */ 3860 3861 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 3862 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 3863 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 3864 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ 3865 3866 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 3867 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 3868 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 3869 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ 3870 3871 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ 3872 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 3873 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 3874 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ 3875 3876 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ 3877 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 3878 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 3879 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ 3880 3881 /* Register: POWER_RAM_POWERCLR */ 3882 /* Description: Description cluster: RAMn power control clear register */ 3883 3884 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 3885 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 3886 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 3887 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ 3888 3889 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 3890 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 3891 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 3892 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ 3893 3894 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ 3895 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 3896 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 3897 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ 3898 3899 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ 3900 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 3901 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 3902 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ 3903 3904 3905 /* Peripheral: PPI */ 3906 /* Description: Programmable Peripheral Interconnect */ 3907 3908 /* Register: PPI_TASKS_CHG_EN */ 3909 /* Description: Description cluster: Enable channel group n */ 3910 3911 /* Bit 0 : Enable channel group n */ 3912 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 3913 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 3914 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ 3915 3916 /* Register: PPI_TASKS_CHG_DIS */ 3917 /* Description: Description cluster: Disable channel group n */ 3918 3919 /* Bit 0 : Disable channel group n */ 3920 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 3921 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 3922 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ 3923 3924 /* Register: PPI_CHEN */ 3925 /* Description: Channel enable register */ 3926 3927 /* Bit 31 : Enable or disable channel 31 */ 3928 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3929 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 3930 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ 3931 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ 3932 3933 /* Bit 30 : Enable or disable channel 30 */ 3934 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3935 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 3936 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ 3937 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ 3938 3939 /* Bit 29 : Enable or disable channel 29 */ 3940 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3941 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 3942 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ 3943 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ 3944 3945 /* Bit 28 : Enable or disable channel 28 */ 3946 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3947 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 3948 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ 3949 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ 3950 3951 /* Bit 27 : Enable or disable channel 27 */ 3952 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3953 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 3954 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ 3955 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ 3956 3957 /* Bit 26 : Enable or disable channel 26 */ 3958 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3959 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 3960 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ 3961 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ 3962 3963 /* Bit 25 : Enable or disable channel 25 */ 3964 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3965 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 3966 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ 3967 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ 3968 3969 /* Bit 24 : Enable or disable channel 24 */ 3970 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3971 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 3972 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ 3973 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ 3974 3975 /* Bit 23 : Enable or disable channel 23 */ 3976 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3977 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 3978 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ 3979 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ 3980 3981 /* Bit 22 : Enable or disable channel 22 */ 3982 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3983 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 3984 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ 3985 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ 3986 3987 /* Bit 21 : Enable or disable channel 21 */ 3988 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3989 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 3990 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ 3991 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ 3992 3993 /* Bit 20 : Enable or disable channel 20 */ 3994 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3995 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 3996 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ 3997 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ 3998 3999 /* Bit 9 : Enable or disable channel 9 */ 4000 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4001 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 4002 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ 4003 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ 4004 4005 /* Bit 8 : Enable or disable channel 8 */ 4006 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4007 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 4008 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ 4009 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ 4010 4011 /* Bit 7 : Enable or disable channel 7 */ 4012 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4013 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 4014 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ 4015 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ 4016 4017 /* Bit 6 : Enable or disable channel 6 */ 4018 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4019 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 4020 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ 4021 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ 4022 4023 /* Bit 5 : Enable or disable channel 5 */ 4024 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4025 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 4026 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ 4027 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ 4028 4029 /* Bit 4 : Enable or disable channel 4 */ 4030 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4031 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 4032 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ 4033 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ 4034 4035 /* Bit 3 : Enable or disable channel 3 */ 4036 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4037 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 4038 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ 4039 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ 4040 4041 /* Bit 2 : Enable or disable channel 2 */ 4042 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4043 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 4044 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ 4045 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ 4046 4047 /* Bit 1 : Enable or disable channel 1 */ 4048 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4049 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 4050 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ 4051 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ 4052 4053 /* Bit 0 : Enable or disable channel 0 */ 4054 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4055 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 4056 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 4057 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 4058 4059 /* Register: PPI_CHENSET */ 4060 /* Description: Channel enable set register */ 4061 4062 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ 4063 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4064 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 4065 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ 4066 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ 4067 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ 4068 4069 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ 4070 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4071 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 4072 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ 4073 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ 4074 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ 4075 4076 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ 4077 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4078 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 4079 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ 4080 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ 4081 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ 4082 4083 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ 4084 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4085 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 4086 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ 4087 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ 4088 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ 4089 4090 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ 4091 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4092 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 4093 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ 4094 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ 4095 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ 4096 4097 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ 4098 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4099 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 4100 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ 4101 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ 4102 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ 4103 4104 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ 4105 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4106 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 4107 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ 4108 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ 4109 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ 4110 4111 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ 4112 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4113 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 4114 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ 4115 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ 4116 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ 4117 4118 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ 4119 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4120 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 4121 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ 4122 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ 4123 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ 4124 4125 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ 4126 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4127 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 4128 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ 4129 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ 4130 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ 4131 4132 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ 4133 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4134 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 4135 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ 4136 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ 4137 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ 4138 4139 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ 4140 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4141 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 4142 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ 4143 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ 4144 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ 4145 4146 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ 4147 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4148 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 4149 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ 4150 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ 4151 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ 4152 4153 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ 4154 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4155 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 4156 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ 4157 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ 4158 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ 4159 4160 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ 4161 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4162 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 4163 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ 4164 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ 4165 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ 4166 4167 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ 4168 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4169 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 4170 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ 4171 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ 4172 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ 4173 4174 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ 4175 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4176 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 4177 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ 4178 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ 4179 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ 4180 4181 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ 4182 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4183 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 4184 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ 4185 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ 4186 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ 4187 4188 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ 4189 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4190 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 4191 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ 4192 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ 4193 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ 4194 4195 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ 4196 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4197 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 4198 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ 4199 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ 4200 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ 4201 4202 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ 4203 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4204 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 4205 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ 4206 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ 4207 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ 4208 4209 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ 4210 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4211 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 4212 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ 4213 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ 4214 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 4215 4216 /* Register: PPI_CHENCLR */ 4217 /* Description: Channel enable clear register */ 4218 4219 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ 4220 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4221 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 4222 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ 4223 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ 4224 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ 4225 4226 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ 4227 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4228 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 4229 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ 4230 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ 4231 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ 4232 4233 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ 4234 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4235 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 4236 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ 4237 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ 4238 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ 4239 4240 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ 4241 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4242 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 4243 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ 4244 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ 4245 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ 4246 4247 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ 4248 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4249 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 4250 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ 4251 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ 4252 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ 4253 4254 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ 4255 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4256 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 4257 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ 4258 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ 4259 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ 4260 4261 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ 4262 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4263 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 4264 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ 4265 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ 4266 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ 4267 4268 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ 4269 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4270 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 4271 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ 4272 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ 4273 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ 4274 4275 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ 4276 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4277 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 4278 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ 4279 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ 4280 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ 4281 4282 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ 4283 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4284 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 4285 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ 4286 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ 4287 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ 4288 4289 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ 4290 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4291 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 4292 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ 4293 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ 4294 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ 4295 4296 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ 4297 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4298 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 4299 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ 4300 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ 4301 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ 4302 4303 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ 4304 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4305 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 4306 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ 4307 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ 4308 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ 4309 4310 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ 4311 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4312 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 4313 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ 4314 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ 4315 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ 4316 4317 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ 4318 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4319 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 4320 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ 4321 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ 4322 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ 4323 4324 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ 4325 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4326 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 4327 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ 4328 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ 4329 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ 4330 4331 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ 4332 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4333 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 4334 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ 4335 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ 4336 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ 4337 4338 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ 4339 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4340 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 4341 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ 4342 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ 4343 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ 4344 4345 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ 4346 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4347 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 4348 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ 4349 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ 4350 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ 4351 4352 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ 4353 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4354 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 4355 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ 4356 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ 4357 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ 4358 4359 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ 4360 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4361 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 4362 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ 4363 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ 4364 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ 4365 4366 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ 4367 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4368 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 4369 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ 4370 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ 4371 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ 4372 4373 /* Register: PPI_CH_EEP */ 4374 /* Description: Description cluster: Channel n event endpoint */ 4375 4376 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ 4377 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ 4378 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ 4379 4380 /* Register: PPI_CH_TEP */ 4381 /* Description: Description cluster: Channel n task endpoint */ 4382 4383 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ 4384 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 4385 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 4386 4387 /* Register: PPI_CHG */ 4388 /* Description: Description collection: Channel group n */ 4389 4390 /* Bit 31 : Include or exclude channel 31 */ 4391 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4392 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 4393 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ 4394 #define PPI_CHG_CH31_Included (1UL) /*!< Include */ 4395 4396 /* Bit 30 : Include or exclude channel 30 */ 4397 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4398 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 4399 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ 4400 #define PPI_CHG_CH30_Included (1UL) /*!< Include */ 4401 4402 /* Bit 29 : Include or exclude channel 29 */ 4403 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4404 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 4405 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ 4406 #define PPI_CHG_CH29_Included (1UL) /*!< Include */ 4407 4408 /* Bit 28 : Include or exclude channel 28 */ 4409 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4410 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 4411 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ 4412 #define PPI_CHG_CH28_Included (1UL) /*!< Include */ 4413 4414 /* Bit 27 : Include or exclude channel 27 */ 4415 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4416 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 4417 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ 4418 #define PPI_CHG_CH27_Included (1UL) /*!< Include */ 4419 4420 /* Bit 26 : Include or exclude channel 26 */ 4421 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4422 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 4423 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ 4424 #define PPI_CHG_CH26_Included (1UL) /*!< Include */ 4425 4426 /* Bit 25 : Include or exclude channel 25 */ 4427 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4428 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 4429 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ 4430 #define PPI_CHG_CH25_Included (1UL) /*!< Include */ 4431 4432 /* Bit 24 : Include or exclude channel 24 */ 4433 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4434 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 4435 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ 4436 #define PPI_CHG_CH24_Included (1UL) /*!< Include */ 4437 4438 /* Bit 23 : Include or exclude channel 23 */ 4439 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4440 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 4441 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ 4442 #define PPI_CHG_CH23_Included (1UL) /*!< Include */ 4443 4444 /* Bit 22 : Include or exclude channel 22 */ 4445 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4446 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 4447 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ 4448 #define PPI_CHG_CH22_Included (1UL) /*!< Include */ 4449 4450 /* Bit 21 : Include or exclude channel 21 */ 4451 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4452 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 4453 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ 4454 #define PPI_CHG_CH21_Included (1UL) /*!< Include */ 4455 4456 /* Bit 20 : Include or exclude channel 20 */ 4457 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4458 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 4459 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ 4460 #define PPI_CHG_CH20_Included (1UL) /*!< Include */ 4461 4462 /* Bit 9 : Include or exclude channel 9 */ 4463 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4464 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 4465 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ 4466 #define PPI_CHG_CH9_Included (1UL) /*!< Include */ 4467 4468 /* Bit 8 : Include or exclude channel 8 */ 4469 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4470 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 4471 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ 4472 #define PPI_CHG_CH8_Included (1UL) /*!< Include */ 4473 4474 /* Bit 7 : Include or exclude channel 7 */ 4475 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4476 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 4477 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ 4478 #define PPI_CHG_CH7_Included (1UL) /*!< Include */ 4479 4480 /* Bit 6 : Include or exclude channel 6 */ 4481 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4482 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 4483 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ 4484 #define PPI_CHG_CH6_Included (1UL) /*!< Include */ 4485 4486 /* Bit 5 : Include or exclude channel 5 */ 4487 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4488 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 4489 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ 4490 #define PPI_CHG_CH5_Included (1UL) /*!< Include */ 4491 4492 /* Bit 4 : Include or exclude channel 4 */ 4493 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4494 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 4495 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ 4496 #define PPI_CHG_CH4_Included (1UL) /*!< Include */ 4497 4498 /* Bit 3 : Include or exclude channel 3 */ 4499 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4500 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 4501 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ 4502 #define PPI_CHG_CH3_Included (1UL) /*!< Include */ 4503 4504 /* Bit 2 : Include or exclude channel 2 */ 4505 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4506 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 4507 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ 4508 #define PPI_CHG_CH2_Included (1UL) /*!< Include */ 4509 4510 /* Bit 1 : Include or exclude channel 1 */ 4511 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4512 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 4513 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ 4514 #define PPI_CHG_CH1_Included (1UL) /*!< Include */ 4515 4516 /* Bit 0 : Include or exclude channel 0 */ 4517 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4518 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 4519 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ 4520 #define PPI_CHG_CH0_Included (1UL) /*!< Include */ 4521 4522 /* Register: PPI_FORK_TEP */ 4523 /* Description: Description cluster: Channel n task endpoint */ 4524 4525 /* Bits 31..0 : Pointer to task register */ 4526 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 4527 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 4528 4529 4530 /* Peripheral: QDEC */ 4531 /* Description: Quadrature Decoder */ 4532 4533 /* Register: QDEC_TASKS_START */ 4534 /* Description: Task starting the quadrature decoder */ 4535 4536 /* Bit 0 : Task starting the quadrature decoder */ 4537 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4538 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4539 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4540 4541 /* Register: QDEC_TASKS_STOP */ 4542 /* Description: Task stopping the quadrature decoder */ 4543 4544 /* Bit 0 : Task stopping the quadrature decoder */ 4545 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4546 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4547 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4548 4549 /* Register: QDEC_TASKS_READCLRACC */ 4550 /* Description: Read and clear ACC and ACCDBL */ 4551 4552 /* Bit 0 : Read and clear ACC and ACCDBL */ 4553 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ 4554 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ 4555 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ 4556 4557 /* Register: QDEC_TASKS_RDCLRACC */ 4558 /* Description: Read and clear ACC */ 4559 4560 /* Bit 0 : Read and clear ACC */ 4561 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ 4562 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ 4563 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ 4564 4565 /* Register: QDEC_TASKS_RDCLRDBL */ 4566 /* Description: Read and clear ACCDBL */ 4567 4568 /* Bit 0 : Read and clear ACCDBL */ 4569 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ 4570 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ 4571 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ 4572 4573 /* Register: QDEC_EVENTS_SAMPLERDY */ 4574 /* Description: Event being generated for every new sample value written to the SAMPLE register */ 4575 4576 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ 4577 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ 4578 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ 4579 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ 4580 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ 4581 4582 /* Register: QDEC_EVENTS_REPORTRDY */ 4583 /* Description: Non-null report ready */ 4584 4585 /* Bit 0 : Non-null report ready */ 4586 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ 4587 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ 4588 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ 4589 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ 4590 4591 /* Register: QDEC_EVENTS_ACCOF */ 4592 /* Description: ACC or ACCDBL register overflow */ 4593 4594 /* Bit 0 : ACC or ACCDBL register overflow */ 4595 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ 4596 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ 4597 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ 4598 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ 4599 4600 /* Register: QDEC_EVENTS_DBLRDY */ 4601 /* Description: Double displacement(s) detected */ 4602 4603 /* Bit 0 : Double displacement(s) detected */ 4604 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ 4605 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ 4606 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ 4607 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ 4608 4609 /* Register: QDEC_EVENTS_STOPPED */ 4610 /* Description: QDEC has been stopped */ 4611 4612 /* Bit 0 : QDEC has been stopped */ 4613 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 4614 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 4615 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 4616 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 4617 4618 /* Register: QDEC_SHORTS */ 4619 /* Description: Shortcuts between local events and tasks */ 4620 4621 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ 4622 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ 4623 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ 4624 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 4625 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 4626 4627 /* Bit 5 : Shortcut between event DBLRDY and task STOP */ 4628 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ 4629 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ 4630 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 4631 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 4632 4633 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ 4634 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ 4635 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ 4636 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ 4637 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ 4638 4639 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */ 4640 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ 4641 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ 4642 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 4643 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 4644 4645 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ 4646 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ 4647 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ 4648 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ 4649 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ 4650 4651 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ 4652 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 4653 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 4654 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 4655 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 4656 4657 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ 4658 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 4659 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 4660 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 4661 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 4662 4663 /* Register: QDEC_INTENSET */ 4664 /* Description: Enable interrupt */ 4665 4666 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */ 4667 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 4668 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 4669 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 4670 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 4671 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 4672 4673 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ 4674 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 4675 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 4676 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 4677 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 4678 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ 4679 4680 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */ 4681 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4682 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4683 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 4684 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 4685 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ 4686 4687 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ 4688 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4689 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4690 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 4691 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 4692 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ 4693 4694 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ 4695 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4696 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4697 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 4698 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 4699 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ 4700 4701 /* Register: QDEC_INTENCLR */ 4702 /* Description: Disable interrupt */ 4703 4704 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */ 4705 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 4706 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 4707 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 4708 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 4709 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 4710 4711 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ 4712 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 4713 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 4714 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 4715 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 4716 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ 4717 4718 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */ 4719 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4720 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4721 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 4722 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 4723 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ 4724 4725 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ 4726 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4727 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4728 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 4729 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 4730 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ 4731 4732 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ 4733 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4734 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4735 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 4736 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 4737 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ 4738 4739 /* Register: QDEC_ENABLE */ 4740 /* Description: Enable the quadrature decoder */ 4741 4742 /* Bit 0 : Enable or disable the quadrature decoder */ 4743 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 4744 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 4745 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 4746 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 4747 4748 /* Register: QDEC_LEDPOL */ 4749 /* Description: LED output pin polarity */ 4750 4751 /* Bit 0 : LED output pin polarity */ 4752 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 4753 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 4754 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ 4755 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ 4756 4757 /* Register: QDEC_SAMPLEPER */ 4758 /* Description: Sample period */ 4759 4760 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ 4761 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 4762 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 4763 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ 4764 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ 4765 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ 4766 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ 4767 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ 4768 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ 4769 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ 4770 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ 4771 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ 4772 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ 4773 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ 4774 4775 /* Register: QDEC_SAMPLE */ 4776 /* Description: Motion sample value */ 4777 4778 /* Bits 31..0 : Last motion sample */ 4779 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 4780 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 4781 4782 /* Register: QDEC_REPORTPER */ 4783 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ 4784 4785 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ 4786 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 4787 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 4788 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ 4789 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ 4790 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ 4791 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ 4792 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ 4793 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ 4794 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ 4795 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ 4796 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ 4797 4798 /* Register: QDEC_ACC */ 4799 /* Description: Register accumulating the valid transitions */ 4800 4801 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ 4802 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ 4803 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ 4804 4805 /* Register: QDEC_ACCREAD */ 4806 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ 4807 4808 /* Bits 31..0 : Snapshot of the ACC register. */ 4809 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ 4810 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ 4811 4812 /* Register: QDEC_PSEL_LED */ 4813 /* Description: Pin select for LED signal */ 4814 4815 /* Bit 31 : Connection */ 4816 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4817 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4818 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ 4819 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4820 4821 /* Bits 4..0 : Pin number */ 4822 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ 4823 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ 4824 4825 /* Register: QDEC_PSEL_A */ 4826 /* Description: Pin select for A signal */ 4827 4828 /* Bit 31 : Connection */ 4829 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4830 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4831 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ 4832 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4833 4834 /* Bits 4..0 : Pin number */ 4835 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ 4836 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ 4837 4838 /* Register: QDEC_PSEL_B */ 4839 /* Description: Pin select for B signal */ 4840 4841 /* Bit 31 : Connection */ 4842 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4843 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4844 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ 4845 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4846 4847 /* Bits 4..0 : Pin number */ 4848 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ 4849 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ 4850 4851 /* Register: QDEC_DBFEN */ 4852 /* Description: Enable input debounce filters */ 4853 4854 /* Bit 0 : Enable input debounce filters */ 4855 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 4856 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 4857 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ 4858 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ 4859 4860 /* Register: QDEC_LEDPRE */ 4861 /* Description: Time period the LED is switched ON prior to sampling */ 4862 4863 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */ 4864 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 4865 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 4866 4867 /* Register: QDEC_ACCDBL */ 4868 /* Description: Register accumulating the number of detected double transitions */ 4869 4870 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ 4871 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 4872 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 4873 4874 /* Register: QDEC_ACCDBLREAD */ 4875 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ 4876 4877 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ 4878 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 4879 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 4880 4881 4882 /* Peripheral: RADIO */ 4883 /* Description: 2.4 GHz radio */ 4884 4885 /* Register: RADIO_TASKS_TXEN */ 4886 /* Description: Enable RADIO in TX mode */ 4887 4888 /* Bit 0 : Enable RADIO in TX mode */ 4889 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ 4890 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ 4891 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ 4892 4893 /* Register: RADIO_TASKS_RXEN */ 4894 /* Description: Enable RADIO in RX mode */ 4895 4896 /* Bit 0 : Enable RADIO in RX mode */ 4897 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ 4898 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ 4899 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ 4900 4901 /* Register: RADIO_TASKS_START */ 4902 /* Description: Start RADIO */ 4903 4904 /* Bit 0 : Start RADIO */ 4905 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4906 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4907 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4908 4909 /* Register: RADIO_TASKS_STOP */ 4910 /* Description: Stop RADIO */ 4911 4912 /* Bit 0 : Stop RADIO */ 4913 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4914 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4915 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4916 4917 /* Register: RADIO_TASKS_DISABLE */ 4918 /* Description: Disable RADIO */ 4919 4920 /* Bit 0 : Disable RADIO */ 4921 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ 4922 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ 4923 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ 4924 4925 /* Register: RADIO_TASKS_RSSISTART */ 4926 /* Description: Start the RSSI and take one single sample of the receive signal strength */ 4927 4928 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ 4929 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ 4930 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ 4931 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ 4932 4933 /* Register: RADIO_TASKS_RSSISTOP */ 4934 /* Description: Stop the RSSI measurement */ 4935 4936 /* Bit 0 : Stop the RSSI measurement */ 4937 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ 4938 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ 4939 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ 4940 4941 /* Register: RADIO_TASKS_BCSTART */ 4942 /* Description: Start the bit counter */ 4943 4944 /* Bit 0 : Start the bit counter */ 4945 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ 4946 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ 4947 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ 4948 4949 /* Register: RADIO_TASKS_BCSTOP */ 4950 /* Description: Stop the bit counter */ 4951 4952 /* Bit 0 : Stop the bit counter */ 4953 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ 4954 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ 4955 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ 4956 4957 /* Register: RADIO_EVENTS_READY */ 4958 /* Description: RADIO has ramped up and is ready to be started */ 4959 4960 /* Bit 0 : RADIO has ramped up and is ready to be started */ 4961 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 4962 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 4963 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ 4964 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ 4965 4966 /* Register: RADIO_EVENTS_ADDRESS */ 4967 /* Description: Address sent or received */ 4968 4969 /* Bit 0 : Address sent or received */ 4970 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ 4971 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ 4972 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ 4973 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ 4974 4975 /* Register: RADIO_EVENTS_PAYLOAD */ 4976 /* Description: Packet payload sent or received */ 4977 4978 /* Bit 0 : Packet payload sent or received */ 4979 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ 4980 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ 4981 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ 4982 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ 4983 4984 /* Register: RADIO_EVENTS_END */ 4985 /* Description: Packet sent or received */ 4986 4987 /* Bit 0 : Packet sent or received */ 4988 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 4989 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 4990 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 4991 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 4992 4993 /* Register: RADIO_EVENTS_DISABLED */ 4994 /* Description: RADIO has been disabled */ 4995 4996 /* Bit 0 : RADIO has been disabled */ 4997 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ 4998 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ 4999 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ 5000 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ 5001 5002 /* Register: RADIO_EVENTS_DEVMATCH */ 5003 /* Description: A device address match occurred on the last received packet */ 5004 5005 /* Bit 0 : A device address match occurred on the last received packet */ 5006 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ 5007 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ 5008 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ 5009 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ 5010 5011 /* Register: RADIO_EVENTS_DEVMISS */ 5012 /* Description: No device address match occurred on the last received packet */ 5013 5014 /* Bit 0 : No device address match occurred on the last received packet */ 5015 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ 5016 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ 5017 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ 5018 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ 5019 5020 /* Register: RADIO_EVENTS_RSSIEND */ 5021 /* Description: Sampling of receive signal strength complete */ 5022 5023 /* Bit 0 : Sampling of receive signal strength complete */ 5024 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ 5025 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ 5026 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ 5027 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ 5028 5029 /* Register: RADIO_EVENTS_BCMATCH */ 5030 /* Description: Bit counter reached bit count value */ 5031 5032 /* Bit 0 : Bit counter reached bit count value */ 5033 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ 5034 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ 5035 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ 5036 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ 5037 5038 /* Register: RADIO_EVENTS_CRCOK */ 5039 /* Description: Packet received with CRC ok */ 5040 5041 /* Bit 0 : Packet received with CRC ok */ 5042 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ 5043 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ 5044 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ 5045 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ 5046 5047 /* Register: RADIO_EVENTS_CRCERROR */ 5048 /* Description: Packet received with CRC error */ 5049 5050 /* Bit 0 : Packet received with CRC error */ 5051 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ 5052 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ 5053 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ 5054 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ 5055 5056 /* Register: RADIO_EVENTS_TXREADY */ 5057 /* Description: RADIO has ramped up and is ready to be started TX path */ 5058 5059 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */ 5060 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ 5061 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ 5062 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ 5063 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ 5064 5065 /* Register: RADIO_EVENTS_RXREADY */ 5066 /* Description: RADIO has ramped up and is ready to be started RX path */ 5067 5068 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */ 5069 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ 5070 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ 5071 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ 5072 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ 5073 5074 /* Register: RADIO_EVENTS_PHYEND */ 5075 /* Description: Generated when last bit is sent on air, or received from air */ 5076 5077 /* Bit 0 : Generated when last bit is sent on air, or received from air */ 5078 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ 5079 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ 5080 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ 5081 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ 5082 5083 /* Register: RADIO_SHORTS */ 5084 /* Description: Shortcuts between local events and tasks */ 5085 5086 /* Bit 21 : Shortcut between event PHYEND and task START */ 5087 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ 5088 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ 5089 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ 5090 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ 5091 5092 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */ 5093 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ 5094 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ 5095 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 5096 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 5097 5098 /* Bit 19 : Shortcut between event RXREADY and task START */ 5099 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ 5100 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ 5101 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 5102 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 5103 5104 /* Bit 18 : Shortcut between event TXREADY and task START */ 5105 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ 5106 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ 5107 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 5108 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 5109 5110 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ 5111 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 5112 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 5113 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ 5114 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ 5115 5116 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ 5117 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 5118 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 5119 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 5120 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 5121 5122 /* Bit 5 : Shortcut between event END and task START */ 5123 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 5124 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 5125 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 5126 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 5127 5128 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ 5129 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 5130 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 5131 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ 5132 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ 5133 5134 /* Bit 3 : Shortcut between event DISABLED and task RXEN */ 5135 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 5136 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 5137 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ 5138 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ 5139 5140 /* Bit 2 : Shortcut between event DISABLED and task TXEN */ 5141 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 5142 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 5143 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ 5144 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ 5145 5146 /* Bit 1 : Shortcut between event END and task DISABLE */ 5147 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 5148 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 5149 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 5150 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 5151 5152 /* Bit 0 : Shortcut between event READY and task START */ 5153 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 5154 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 5155 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ 5156 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ 5157 5158 /* Register: RADIO_INTENSET */ 5159 /* Description: Enable interrupt */ 5160 5161 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */ 5162 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 5163 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 5164 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 5165 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 5166 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ 5167 5168 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */ 5169 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 5170 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 5171 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 5172 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 5173 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ 5174 5175 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */ 5176 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 5177 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 5178 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 5179 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 5180 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ 5181 5182 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ 5183 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 5184 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 5185 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 5186 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 5187 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ 5188 5189 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */ 5190 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 5191 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 5192 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 5193 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 5194 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ 5195 5196 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ 5197 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 5198 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 5199 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 5200 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 5201 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ 5202 5203 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ 5204 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 5205 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 5206 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 5207 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 5208 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ 5209 5210 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ 5211 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 5212 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 5213 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 5214 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 5215 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ 5216 5217 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ 5218 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 5219 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 5220 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 5221 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 5222 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ 5223 5224 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */ 5225 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 5226 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 5227 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 5228 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 5229 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ 5230 5231 /* Bit 3 : Write '1' to enable interrupt for event END */ 5232 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 5233 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 5234 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 5235 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 5236 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ 5237 5238 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ 5239 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 5240 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 5241 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 5242 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 5243 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ 5244 5245 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ 5246 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 5247 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 5248 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 5249 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 5250 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ 5251 5252 /* Bit 0 : Write '1' to enable interrupt for event READY */ 5253 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 5254 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 5255 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 5256 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 5257 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ 5258 5259 /* Register: RADIO_INTENCLR */ 5260 /* Description: Disable interrupt */ 5261 5262 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */ 5263 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 5264 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 5265 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 5266 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 5267 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ 5268 5269 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */ 5270 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 5271 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 5272 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 5273 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 5274 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ 5275 5276 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */ 5277 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 5278 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 5279 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 5280 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 5281 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ 5282 5283 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ 5284 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 5285 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 5286 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 5287 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 5288 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ 5289 5290 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */ 5291 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 5292 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 5293 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 5294 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 5295 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ 5296 5297 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ 5298 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 5299 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 5300 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 5301 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 5302 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ 5303 5304 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ 5305 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 5306 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 5307 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 5308 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 5309 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ 5310 5311 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ 5312 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 5313 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 5314 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 5315 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 5316 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ 5317 5318 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ 5319 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 5320 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 5321 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 5322 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 5323 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ 5324 5325 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */ 5326 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 5327 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 5328 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 5329 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 5330 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ 5331 5332 /* Bit 3 : Write '1' to disable interrupt for event END */ 5333 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 5334 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 5335 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 5336 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 5337 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ 5338 5339 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ 5340 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 5341 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 5342 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 5343 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 5344 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ 5345 5346 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ 5347 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 5348 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 5349 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 5350 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 5351 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ 5352 5353 /* Bit 0 : Write '1' to disable interrupt for event READY */ 5354 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 5355 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 5356 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 5357 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 5358 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ 5359 5360 /* Register: RADIO_CRCSTATUS */ 5361 /* Description: CRC status */ 5362 5363 /* Bit 0 : CRC status of packet received */ 5364 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 5365 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 5366 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ 5367 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ 5368 5369 /* Register: RADIO_RXMATCH */ 5370 /* Description: Received address */ 5371 5372 /* Bits 2..0 : Received address */ 5373 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 5374 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 5375 5376 /* Register: RADIO_RXCRC */ 5377 /* Description: CRC field of previously received packet */ 5378 5379 /* Bits 23..0 : CRC field of previously received packet */ 5380 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 5381 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 5382 5383 /* Register: RADIO_DAI */ 5384 /* Description: Device address match index */ 5385 5386 /* Bits 2..0 : Device address match index */ 5387 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 5388 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 5389 5390 /* Register: RADIO_PDUSTAT */ 5391 /* Description: Payload status */ 5392 5393 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ 5394 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ 5395 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ 5396 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ 5397 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ 5398 5399 /* Register: RADIO_PACKETPTR */ 5400 /* Description: Packet pointer */ 5401 5402 /* Bits 31..0 : Packet pointer */ 5403 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ 5404 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ 5405 5406 /* Register: RADIO_FREQUENCY */ 5407 /* Description: Frequency */ 5408 5409 /* Bit 8 : Channel map selection */ 5410 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ 5411 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ 5412 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ 5413 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ 5414 5415 /* Bits 6..0 : Radio channel frequency */ 5416 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 5417 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 5418 5419 /* Register: RADIO_TXPOWER */ 5420 /* Description: Output power */ 5421 5422 /* Bits 7..0 : RADIO output power */ 5423 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 5424 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 5425 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ 5426 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ 5427 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ 5428 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ 5429 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ 5430 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ 5431 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ 5432 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ 5433 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ 5434 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ 5435 5436 /* Register: RADIO_MODE */ 5437 /* Description: Data rate and modulation */ 5438 5439 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ 5440 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 5441 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 5442 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */ 5443 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ 5444 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ 5445 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ 5446 5447 /* Register: RADIO_PCNF0 */ 5448 /* Description: Packet configuration register 0 */ 5449 5450 /* Bit 26 : Indicates if LENGTH field contains CRC or not */ 5451 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ 5452 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ 5453 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ 5454 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ 5455 5456 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ 5457 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ 5458 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ 5459 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ 5460 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ 5461 5462 /* Bit 20 : Include or exclude S1 field in RAM */ 5463 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ 5464 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ 5465 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ 5466 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ 5467 5468 /* Bits 19..16 : Length on air of S1 field in number of bits */ 5469 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 5470 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 5471 5472 /* Bit 8 : Length on air of S0 field in number of bytes */ 5473 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 5474 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 5475 5476 /* Bits 3..0 : Length on air of LENGTH field in number of bits */ 5477 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 5478 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 5479 5480 /* Register: RADIO_PCNF1 */ 5481 /* Description: Packet configuration register 1 */ 5482 5483 /* Bit 25 : Enable or disable packet whitening */ 5484 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 5485 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 5486 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ 5487 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ 5488 5489 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ 5490 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 5491 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 5492 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 5493 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 5494 5495 /* Bits 18..16 : Base address length in number of bytes */ 5496 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 5497 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 5498 5499 /* Bits 15..8 : Static length in number of bytes */ 5500 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 5501 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 5502 5503 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ 5504 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 5505 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 5506 5507 /* Register: RADIO_BASE0 */ 5508 /* Description: Base address 0 */ 5509 5510 /* Bits 31..0 : Base address 0 */ 5511 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ 5512 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ 5513 5514 /* Register: RADIO_BASE1 */ 5515 /* Description: Base address 1 */ 5516 5517 /* Bits 31..0 : Base address 1 */ 5518 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ 5519 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ 5520 5521 /* Register: RADIO_PREFIX0 */ 5522 /* Description: Prefixes bytes for logical addresses 0-3 */ 5523 5524 /* Bits 31..24 : Address prefix 3. */ 5525 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 5526 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 5527 5528 /* Bits 23..16 : Address prefix 2. */ 5529 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 5530 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 5531 5532 /* Bits 15..8 : Address prefix 1. */ 5533 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 5534 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 5535 5536 /* Bits 7..0 : Address prefix 0. */ 5537 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 5538 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 5539 5540 /* Register: RADIO_PREFIX1 */ 5541 /* Description: Prefixes bytes for logical addresses 4-7 */ 5542 5543 /* Bits 31..24 : Address prefix 7. */ 5544 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 5545 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 5546 5547 /* Bits 23..16 : Address prefix 6. */ 5548 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 5549 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 5550 5551 /* Bits 15..8 : Address prefix 5. */ 5552 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 5553 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 5554 5555 /* Bits 7..0 : Address prefix 4. */ 5556 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 5557 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 5558 5559 /* Register: RADIO_TXADDRESS */ 5560 /* Description: Transmit address select */ 5561 5562 /* Bits 2..0 : Transmit address select */ 5563 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 5564 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 5565 5566 /* Register: RADIO_RXADDRESSES */ 5567 /* Description: Receive address select */ 5568 5569 /* Bit 7 : Enable or disable reception on logical address 7. */ 5570 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 5571 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 5572 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ 5573 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ 5574 5575 /* Bit 6 : Enable or disable reception on logical address 6. */ 5576 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 5577 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 5578 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ 5579 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ 5580 5581 /* Bit 5 : Enable or disable reception on logical address 5. */ 5582 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 5583 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 5584 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ 5585 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ 5586 5587 /* Bit 4 : Enable or disable reception on logical address 4. */ 5588 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 5589 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 5590 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ 5591 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ 5592 5593 /* Bit 3 : Enable or disable reception on logical address 3. */ 5594 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 5595 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 5596 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ 5597 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ 5598 5599 /* Bit 2 : Enable or disable reception on logical address 2. */ 5600 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 5601 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 5602 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ 5603 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ 5604 5605 /* Bit 1 : Enable or disable reception on logical address 1. */ 5606 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 5607 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 5608 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ 5609 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ 5610 5611 /* Bit 0 : Enable or disable reception on logical address 0. */ 5612 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 5613 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 5614 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ 5615 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ 5616 5617 /* Register: RADIO_CRCCNF */ 5618 /* Description: CRC configuration */ 5619 5620 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ 5621 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 5622 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 5623 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ 5624 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ 5625 5626 /* Bits 1..0 : CRC length in number of bytes */ 5627 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 5628 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 5629 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ 5630 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ 5631 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ 5632 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ 5633 5634 /* Register: RADIO_CRCPOLY */ 5635 /* Description: CRC polynomial */ 5636 5637 /* Bits 23..0 : CRC polynomial */ 5638 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 5639 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 5640 5641 /* Register: RADIO_CRCINIT */ 5642 /* Description: CRC initial value */ 5643 5644 /* Bits 23..0 : CRC initial value */ 5645 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 5646 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 5647 5648 /* Register: RADIO_TIFS */ 5649 /* Description: Interframe spacing in us */ 5650 5651 /* Bits 9..0 : Interframe spacing in us. */ 5652 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 5653 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 5654 5655 /* Register: RADIO_RSSISAMPLE */ 5656 /* Description: RSSI sample */ 5657 5658 /* Bits 6..0 : RSSI sample. */ 5659 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 5660 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 5661 5662 /* Register: RADIO_STATE */ 5663 /* Description: Current radio state */ 5664 5665 /* Bits 3..0 : Current radio state */ 5666 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 5667 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 5668 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ 5669 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ 5670 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ 5671 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ 5672 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ 5673 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ 5674 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ 5675 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ 5676 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ 5677 5678 /* Register: RADIO_DATAWHITEIV */ 5679 /* Description: Data whitening initial value */ 5680 5681 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ 5682 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 5683 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 5684 5685 /* Register: RADIO_BCC */ 5686 /* Description: Bit counter compare */ 5687 5688 /* Bits 31..0 : Bit counter compare */ 5689 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ 5690 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ 5691 5692 /* Register: RADIO_DAB */ 5693 /* Description: Description collection: Device address base segment n */ 5694 5695 /* Bits 31..0 : Device address base segment n */ 5696 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ 5697 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ 5698 5699 /* Register: RADIO_DAP */ 5700 /* Description: Description collection: Device address prefix n */ 5701 5702 /* Bits 15..0 : Device address prefix n */ 5703 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 5704 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 5705 5706 /* Register: RADIO_DACNF */ 5707 /* Description: Device address match configuration */ 5708 5709 /* Bit 15 : TxAdd for device address 7 */ 5710 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 5711 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 5712 5713 /* Bit 14 : TxAdd for device address 6 */ 5714 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 5715 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 5716 5717 /* Bit 13 : TxAdd for device address 5 */ 5718 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 5719 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 5720 5721 /* Bit 12 : TxAdd for device address 4 */ 5722 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 5723 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 5724 5725 /* Bit 11 : TxAdd for device address 3 */ 5726 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 5727 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 5728 5729 /* Bit 10 : TxAdd for device address 2 */ 5730 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 5731 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 5732 5733 /* Bit 9 : TxAdd for device address 1 */ 5734 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 5735 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 5736 5737 /* Bit 8 : TxAdd for device address 0 */ 5738 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 5739 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 5740 5741 /* Bit 7 : Enable or disable device address matching using device address 7 */ 5742 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 5743 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 5744 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ 5745 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ 5746 5747 /* Bit 6 : Enable or disable device address matching using device address 6 */ 5748 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 5749 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 5750 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ 5751 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ 5752 5753 /* Bit 5 : Enable or disable device address matching using device address 5 */ 5754 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 5755 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 5756 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ 5757 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ 5758 5759 /* Bit 4 : Enable or disable device address matching using device address 4 */ 5760 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 5761 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 5762 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ 5763 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ 5764 5765 /* Bit 3 : Enable or disable device address matching using device address 3 */ 5766 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 5767 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 5768 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ 5769 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ 5770 5771 /* Bit 2 : Enable or disable device address matching using device address 2 */ 5772 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 5773 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 5774 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ 5775 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ 5776 5777 /* Bit 1 : Enable or disable device address matching using device address 1 */ 5778 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 5779 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 5780 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ 5781 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ 5782 5783 /* Bit 0 : Enable or disable device address matching using device address 0 */ 5784 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 5785 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 5786 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ 5787 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ 5788 5789 /* Register: RADIO_MODECNF0 */ 5790 /* Description: Radio mode configuration register 0 */ 5791 5792 /* Bits 9..8 : Default TX value */ 5793 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ 5794 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ 5795 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ 5796 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ 5797 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ 5798 5799 /* Bit 0 : Radio ramp-up time */ 5800 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ 5801 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ 5802 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ 5803 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ 5804 5805 /* Register: RADIO_POWER */ 5806 /* Description: Peripheral power control */ 5807 5808 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ 5809 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5810 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5811 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ 5812 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ 5813 5814 5815 /* Peripheral: RNG */ 5816 /* Description: Random Number Generator */ 5817 5818 /* Register: RNG_TASKS_START */ 5819 /* Description: Task starting the random number generator */ 5820 5821 /* Bit 0 : Task starting the random number generator */ 5822 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5823 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5824 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5825 5826 /* Register: RNG_TASKS_STOP */ 5827 /* Description: Task stopping the random number generator */ 5828 5829 /* Bit 0 : Task stopping the random number generator */ 5830 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5831 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5832 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5833 5834 /* Register: RNG_EVENTS_VALRDY */ 5835 /* Description: Event being generated for every new random number written to the VALUE register */ 5836 5837 /* Bit 0 : Event being generated for every new random number written to the VALUE register */ 5838 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ 5839 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ 5840 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ 5841 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ 5842 5843 /* Register: RNG_SHORTS */ 5844 /* Description: Shortcuts between local events and tasks */ 5845 5846 /* Bit 0 : Shortcut between event VALRDY and task STOP */ 5847 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 5848 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 5849 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 5850 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 5851 5852 /* Register: RNG_INTENSET */ 5853 /* Description: Enable interrupt */ 5854 5855 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */ 5856 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 5857 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 5858 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 5859 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 5860 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ 5861 5862 /* Register: RNG_INTENCLR */ 5863 /* Description: Disable interrupt */ 5864 5865 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */ 5866 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 5867 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 5868 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 5869 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 5870 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ 5871 5872 /* Register: RNG_CONFIG */ 5873 /* Description: Configuration register */ 5874 5875 /* Bit 0 : Bias correction */ 5876 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 5877 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 5878 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ 5879 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ 5880 5881 /* Register: RNG_VALUE */ 5882 /* Description: Output random number */ 5883 5884 /* Bits 7..0 : Generated random number */ 5885 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 5886 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 5887 5888 5889 /* Peripheral: RTC */ 5890 /* Description: Real time counter 0 */ 5891 5892 /* Register: RTC_TASKS_START */ 5893 /* Description: Start RTC COUNTER */ 5894 5895 /* Bit 0 : Start RTC COUNTER */ 5896 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5897 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5898 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5899 5900 /* Register: RTC_TASKS_STOP */ 5901 /* Description: Stop RTC COUNTER */ 5902 5903 /* Bit 0 : Stop RTC COUNTER */ 5904 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5905 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5906 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5907 5908 /* Register: RTC_TASKS_CLEAR */ 5909 /* Description: Clear RTC COUNTER */ 5910 5911 /* Bit 0 : Clear RTC COUNTER */ 5912 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 5913 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 5914 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 5915 5916 /* Register: RTC_TASKS_TRIGOVRFLW */ 5917 /* Description: Set COUNTER to 0xFFFFF0 */ 5918 5919 /* Bit 0 : Set COUNTER to 0xFFFFF0 */ 5920 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 5921 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 5922 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ 5923 5924 /* Register: RTC_EVENTS_TICK */ 5925 /* Description: Event on COUNTER increment */ 5926 5927 /* Bit 0 : Event on COUNTER increment */ 5928 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 5929 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 5930 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ 5931 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ 5932 5933 /* Register: RTC_EVENTS_OVRFLW */ 5934 /* Description: Event on COUNTER overflow */ 5935 5936 /* Bit 0 : Event on COUNTER overflow */ 5937 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 5938 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 5939 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ 5940 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ 5941 5942 /* Register: RTC_EVENTS_COMPARE */ 5943 /* Description: Description collection: Compare event on CC[n] match */ 5944 5945 /* Bit 0 : Compare event on CC[n] match */ 5946 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 5947 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 5948 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 5949 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 5950 5951 /* Register: RTC_INTENSET */ 5952 /* Description: Enable interrupt */ 5953 5954 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 5955 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5956 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5957 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 5958 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 5959 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 5960 5961 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 5962 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5963 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5964 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 5965 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 5966 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 5967 5968 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 5969 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5970 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5971 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 5972 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 5973 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 5974 5975 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 5976 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5977 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5978 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5979 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5980 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 5981 5982 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ 5983 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5984 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5985 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 5986 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 5987 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 5988 5989 /* Bit 0 : Write '1' to enable interrupt for event TICK */ 5990 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5991 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5992 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 5993 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 5994 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 5995 5996 /* Register: RTC_INTENCLR */ 5997 /* Description: Disable interrupt */ 5998 5999 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 6000 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6001 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6002 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6003 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6004 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 6005 6006 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 6007 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6008 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6009 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6010 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6011 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 6012 6013 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 6014 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6015 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6016 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6017 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6018 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 6019 6020 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 6021 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6022 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6023 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6024 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6025 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 6026 6027 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ 6028 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6029 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6030 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6031 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6032 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 6033 6034 /* Bit 0 : Write '1' to disable interrupt for event TICK */ 6035 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 6036 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 6037 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 6038 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 6039 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 6040 6041 /* Register: RTC_EVTEN */ 6042 /* Description: Enable or disable event routing */ 6043 6044 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ 6045 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6046 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6047 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 6048 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ 6049 6050 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */ 6051 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6052 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6053 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ 6054 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ 6055 6056 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */ 6057 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6058 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6059 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ 6060 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ 6061 6062 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ 6063 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6064 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6065 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 6066 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ 6067 6068 /* Bit 1 : Enable or disable event routing for event OVRFLW */ 6069 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6070 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6071 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 6072 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ 6073 6074 /* Bit 0 : Enable or disable event routing for event TICK */ 6075 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 6076 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 6077 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 6078 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ 6079 6080 /* Register: RTC_EVTENSET */ 6081 /* Description: Enable event routing */ 6082 6083 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ 6084 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6085 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6086 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6087 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6088 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 6089 6090 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ 6091 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6092 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6093 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6094 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6095 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ 6096 6097 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ 6098 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6099 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6100 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6101 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6102 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ 6103 6104 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ 6105 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6106 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6107 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6108 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6109 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 6110 6111 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ 6112 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6113 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6114 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6115 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6116 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 6117 6118 /* Bit 0 : Write '1' to enable event routing for event TICK */ 6119 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 6120 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 6121 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 6122 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 6123 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 6124 6125 /* Register: RTC_EVTENCLR */ 6126 /* Description: Disable event routing */ 6127 6128 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ 6129 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6130 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6131 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6132 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6133 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 6134 6135 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ 6136 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6137 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6138 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6139 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6140 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 6141 6142 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ 6143 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6144 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6145 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6146 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6147 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 6148 6149 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ 6150 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6151 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6152 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6153 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6154 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 6155 6156 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ 6157 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6158 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6159 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6160 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6161 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 6162 6163 /* Bit 0 : Write '1' to disable event routing for event TICK */ 6164 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 6165 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 6166 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 6167 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 6168 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 6169 6170 /* Register: RTC_COUNTER */ 6171 /* Description: Current COUNTER value */ 6172 6173 /* Bits 23..0 : Counter value */ 6174 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 6175 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 6176 6177 /* Register: RTC_PRESCALER */ 6178 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ 6179 6180 /* Bits 11..0 : Prescaler value */ 6181 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 6182 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 6183 6184 /* Register: RTC_CC */ 6185 /* Description: Description collection: Compare register n */ 6186 6187 /* Bits 23..0 : Compare value */ 6188 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 6189 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 6190 6191 6192 /* Peripheral: SAADC */ 6193 /* Description: Analog to Digital Converter */ 6194 6195 /* Register: SAADC_TASKS_START */ 6196 /* Description: Start the ADC and prepare the result buffer in RAM */ 6197 6198 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */ 6199 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6200 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6201 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 6202 6203 /* Register: SAADC_TASKS_SAMPLE */ 6204 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ 6205 6206 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ 6207 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ 6208 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ 6209 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ 6210 6211 /* Register: SAADC_TASKS_STOP */ 6212 /* Description: Stop the ADC and terminate any on-going conversion */ 6213 6214 /* Bit 0 : Stop the ADC and terminate any on-going conversion */ 6215 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6216 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6217 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 6218 6219 /* Register: SAADC_TASKS_CALIBRATEOFFSET */ 6220 /* Description: Starts offset auto-calibration */ 6221 6222 /* Bit 0 : Starts offset auto-calibration */ 6223 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ 6224 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ 6225 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ 6226 6227 /* Register: SAADC_EVENTS_STARTED */ 6228 /* Description: The ADC has started */ 6229 6230 /* Bit 0 : The ADC has started */ 6231 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 6232 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 6233 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ 6234 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ 6235 6236 /* Register: SAADC_EVENTS_END */ 6237 /* Description: The ADC has filled up the Result buffer */ 6238 6239 /* Bit 0 : The ADC has filled up the Result buffer */ 6240 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 6241 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 6242 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 6243 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 6244 6245 /* Register: SAADC_EVENTS_DONE */ 6246 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 6247 6248 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 6249 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 6250 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 6251 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ 6252 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ 6253 6254 /* Register: SAADC_EVENTS_RESULTDONE */ 6255 /* Description: A result is ready to get transferred to RAM. */ 6256 6257 /* Bit 0 : A result is ready to get transferred to RAM. */ 6258 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ 6259 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ 6260 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ 6261 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ 6262 6263 /* Register: SAADC_EVENTS_CALIBRATEDONE */ 6264 /* Description: Calibration is complete */ 6265 6266 /* Bit 0 : Calibration is complete */ 6267 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ 6268 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ 6269 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ 6270 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ 6271 6272 /* Register: SAADC_EVENTS_STOPPED */ 6273 /* Description: The ADC has stopped */ 6274 6275 /* Bit 0 : The ADC has stopped */ 6276 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 6277 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 6278 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 6279 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 6280 6281 /* Register: SAADC_EVENTS_CH_LIMITH */ 6282 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ 6283 6284 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ 6285 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ 6286 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ 6287 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ 6288 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ 6289 6290 /* Register: SAADC_EVENTS_CH_LIMITL */ 6291 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ 6292 6293 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ 6294 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ 6295 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ 6296 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ 6297 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ 6298 6299 /* Register: SAADC_INTEN */ 6300 /* Description: Enable or disable interrupt */ 6301 6302 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ 6303 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6304 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6305 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ 6306 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ 6307 6308 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ 6309 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6310 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6311 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ 6312 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ 6313 6314 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ 6315 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6316 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6317 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ 6318 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ 6319 6320 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ 6321 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6322 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6323 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ 6324 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ 6325 6326 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ 6327 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6328 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6329 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ 6330 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ 6331 6332 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ 6333 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6334 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6335 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ 6336 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ 6337 6338 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ 6339 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6340 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6341 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ 6342 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ 6343 6344 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ 6345 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6346 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6347 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ 6348 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ 6349 6350 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ 6351 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6352 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6353 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ 6354 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ 6355 6356 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ 6357 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6358 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6359 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ 6360 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ 6361 6362 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ 6363 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6364 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6365 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ 6366 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ 6367 6368 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ 6369 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6370 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6371 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ 6372 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ 6373 6374 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ 6375 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6376 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6377 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ 6378 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ 6379 6380 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ 6381 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6382 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6383 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ 6384 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ 6385 6386 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ 6387 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6388 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6389 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ 6390 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ 6391 6392 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ 6393 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6394 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6395 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ 6396 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ 6397 6398 /* Bit 5 : Enable or disable interrupt for event STOPPED */ 6399 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6400 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6401 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 6402 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 6403 6404 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ 6405 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6406 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6407 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ 6408 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ 6409 6410 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */ 6411 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6412 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6413 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ 6414 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ 6415 6416 /* Bit 2 : Enable or disable interrupt for event DONE */ 6417 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ 6418 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 6419 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ 6420 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ 6421 6422 /* Bit 1 : Enable or disable interrupt for event END */ 6423 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ 6424 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ 6425 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ 6426 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ 6427 6428 /* Bit 0 : Enable or disable interrupt for event STARTED */ 6429 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6430 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6431 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 6432 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 6433 6434 /* Register: SAADC_INTENSET */ 6435 /* Description: Enable interrupt */ 6436 6437 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ 6438 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6439 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6440 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6441 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6442 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ 6443 6444 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ 6445 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6446 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6447 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6448 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6449 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ 6450 6451 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ 6452 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6453 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6454 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6455 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6456 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ 6457 6458 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ 6459 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6460 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6461 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6462 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6463 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ 6464 6465 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ 6466 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6467 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6468 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6469 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6470 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ 6471 6472 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ 6473 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6474 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6475 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6476 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6477 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ 6478 6479 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ 6480 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6481 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6482 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6483 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6484 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ 6485 6486 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ 6487 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6488 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6489 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6490 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6491 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ 6492 6493 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ 6494 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6495 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6496 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6497 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6498 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ 6499 6500 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ 6501 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6502 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6503 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6504 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6505 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ 6506 6507 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ 6508 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6509 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6510 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6511 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6512 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ 6513 6514 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ 6515 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6516 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6517 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6518 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6519 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ 6520 6521 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ 6522 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6523 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6524 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6525 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6526 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ 6527 6528 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ 6529 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6530 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6531 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6532 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6533 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ 6534 6535 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ 6536 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6537 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6538 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6539 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6540 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ 6541 6542 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ 6543 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6544 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6545 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6546 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6547 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ 6548 6549 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */ 6550 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6551 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6552 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 6553 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 6554 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 6555 6556 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ 6557 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6558 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6559 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 6560 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 6561 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ 6562 6563 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ 6564 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6565 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6566 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 6567 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 6568 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ 6569 6570 /* Bit 2 : Write '1' to enable interrupt for event DONE */ 6571 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ 6572 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 6573 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 6574 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 6575 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ 6576 6577 /* Bit 1 : Write '1' to enable interrupt for event END */ 6578 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 6579 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 6580 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 6581 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 6582 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ 6583 6584 /* Bit 0 : Write '1' to enable interrupt for event STARTED */ 6585 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6586 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6587 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 6588 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 6589 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ 6590 6591 /* Register: SAADC_INTENCLR */ 6592 /* Description: Disable interrupt */ 6593 6594 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ 6595 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 6596 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 6597 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6598 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6599 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ 6600 6601 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ 6602 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 6603 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 6604 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6605 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6606 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ 6607 6608 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ 6609 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 6610 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 6611 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6612 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6613 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ 6614 6615 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ 6616 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 6617 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 6618 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6619 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6620 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ 6621 6622 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ 6623 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 6624 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 6625 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6626 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6627 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ 6628 6629 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ 6630 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 6631 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 6632 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6633 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6634 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ 6635 6636 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ 6637 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 6638 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 6639 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6640 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6641 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ 6642 6643 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ 6644 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 6645 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 6646 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6647 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6648 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ 6649 6650 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ 6651 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 6652 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 6653 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6654 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6655 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ 6656 6657 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ 6658 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 6659 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 6660 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6661 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6662 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ 6663 6664 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ 6665 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 6666 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 6667 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6668 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6669 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ 6670 6671 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ 6672 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 6673 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 6674 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6675 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6676 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ 6677 6678 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ 6679 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 6680 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 6681 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6682 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6683 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ 6684 6685 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ 6686 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 6687 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 6688 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6689 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6690 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ 6691 6692 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ 6693 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 6694 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 6695 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 6696 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 6697 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ 6698 6699 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ 6700 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 6701 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 6702 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 6703 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 6704 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ 6705 6706 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */ 6707 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 6708 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6709 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 6710 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 6711 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 6712 6713 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ 6714 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 6715 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 6716 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 6717 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 6718 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ 6719 6720 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ 6721 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 6722 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 6723 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 6724 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 6725 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ 6726 6727 /* Bit 2 : Write '1' to disable interrupt for event DONE */ 6728 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ 6729 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 6730 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 6731 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 6732 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 6733 6734 /* Bit 1 : Write '1' to disable interrupt for event END */ 6735 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 6736 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 6737 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 6738 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 6739 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ 6740 6741 /* Bit 0 : Write '1' to disable interrupt for event STARTED */ 6742 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 6743 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6744 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 6745 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 6746 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 6747 6748 /* Register: SAADC_STATUS */ 6749 /* Description: Status */ 6750 6751 /* Bit 0 : Status */ 6752 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 6753 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 6754 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ 6755 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ 6756 6757 /* Register: SAADC_ENABLE */ 6758 /* Description: Enable or disable ADC */ 6759 6760 /* Bit 0 : Enable or disable ADC */ 6761 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6762 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6763 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ 6764 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ 6765 6766 /* Register: SAADC_CH_PSELP */ 6767 /* Description: Description cluster: Input positive pin selection for CH[n] */ 6768 6769 /* Bits 4..0 : Analog positive input channel */ 6770 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ 6771 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ 6772 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ 6773 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ 6774 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ 6775 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ 6776 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ 6777 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ 6778 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ 6779 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ 6780 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ 6781 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ 6782 6783 /* Register: SAADC_CH_PSELN */ 6784 /* Description: Description cluster: Input negative pin selection for CH[n] */ 6785 6786 /* Bits 4..0 : Analog negative input, enables differential channel */ 6787 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ 6788 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ 6789 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ 6790 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ 6791 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ 6792 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ 6793 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ 6794 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ 6795 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ 6796 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ 6797 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ 6798 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ 6799 6800 /* Register: SAADC_CH_CONFIG */ 6801 /* Description: Description cluster: Input configuration for CH[n] */ 6802 6803 /* Bit 24 : Enable burst mode */ 6804 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ 6805 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ 6806 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ 6807 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ 6808 6809 /* Bit 20 : Enable differential mode */ 6810 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ 6811 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 6812 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ 6813 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ 6814 6815 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ 6816 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ 6817 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ 6818 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ 6819 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ 6820 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ 6821 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ 6822 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ 6823 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ 6824 6825 /* Bit 12 : Reference control */ 6826 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ 6827 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 6828 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ 6829 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ 6830 6831 /* Bits 10..8 : Gain control */ 6832 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ 6833 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ 6834 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ 6835 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ 6836 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ 6837 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ 6838 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ 6839 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ 6840 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ 6841 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ 6842 6843 /* Bits 5..4 : Negative channel resistor control */ 6844 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ 6845 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ 6846 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ 6847 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ 6848 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ 6849 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 6850 6851 /* Bits 1..0 : Positive channel resistor control */ 6852 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ 6853 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ 6854 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ 6855 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ 6856 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ 6857 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 6858 6859 /* Register: SAADC_CH_LIMIT */ 6860 /* Description: Description cluster: High/low limits for event monitoring a channel */ 6861 6862 /* Bits 31..16 : High level limit */ 6863 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ 6864 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ 6865 6866 /* Bits 15..0 : Low level limit */ 6867 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ 6868 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ 6869 6870 /* Register: SAADC_RESOLUTION */ 6871 /* Description: Resolution configuration */ 6872 6873 /* Bits 2..0 : Set the resolution */ 6874 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ 6875 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ 6876 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ 6877 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ 6878 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ 6879 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ 6880 6881 /* Register: SAADC_OVERSAMPLE */ 6882 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ 6883 6884 /* Bits 3..0 : Oversample control */ 6885 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ 6886 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ 6887 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ 6888 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ 6889 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ 6890 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ 6891 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ 6892 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ 6893 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ 6894 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ 6895 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ 6896 6897 /* Register: SAADC_SAMPLERATE */ 6898 /* Description: Controls normal or continuous sample rate */ 6899 6900 /* Bit 12 : Select mode for sample rate control */ 6901 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ 6902 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ 6903 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ 6904 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ 6905 6906 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ 6907 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ 6908 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ 6909 6910 /* Register: SAADC_RESULT_PTR */ 6911 /* Description: Data pointer */ 6912 6913 /* Bits 31..0 : Data pointer */ 6914 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6915 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6916 6917 /* Register: SAADC_RESULT_MAXCNT */ 6918 /* Description: Maximum number of buffer words to transfer */ 6919 6920 /* Bits 14..0 : Maximum number of buffer words to transfer */ 6921 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6922 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6923 6924 /* Register: SAADC_RESULT_AMOUNT */ 6925 /* Description: Number of buffer words transferred since last START */ 6926 6927 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ 6928 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6929 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6930 6931 6932 /* Peripheral: SPI */ 6933 /* Description: Serial Peripheral Interface */ 6934 6935 /* Register: SPI_EVENTS_READY */ 6936 /* Description: TXD byte sent and RXD byte received */ 6937 6938 /* Bit 0 : TXD byte sent and RXD byte received */ 6939 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 6940 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 6941 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ 6942 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ 6943 6944 /* Register: SPI_INTENSET */ 6945 /* Description: Enable interrupt */ 6946 6947 /* Bit 2 : Write '1' to enable interrupt for event READY */ 6948 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ 6949 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 6950 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 6951 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 6952 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ 6953 6954 /* Register: SPI_INTENCLR */ 6955 /* Description: Disable interrupt */ 6956 6957 /* Bit 2 : Write '1' to disable interrupt for event READY */ 6958 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ 6959 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 6960 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 6961 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 6962 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ 6963 6964 /* Register: SPI_ENABLE */ 6965 /* Description: Enable SPI */ 6966 6967 /* Bits 3..0 : Enable or disable SPI */ 6968 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6969 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6970 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ 6971 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ 6972 6973 /* Register: SPI_PSEL_SCK */ 6974 /* Description: Pin select for SCK */ 6975 6976 /* Bit 31 : Connection */ 6977 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6978 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6979 #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 6980 #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6981 6982 /* Bits 4..0 : Pin number */ 6983 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 6984 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 6985 6986 /* Register: SPI_PSEL_MOSI */ 6987 /* Description: Pin select for MOSI signal */ 6988 6989 /* Bit 31 : Connection */ 6990 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6991 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6992 #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 6993 #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6994 6995 /* Bits 4..0 : Pin number */ 6996 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 6997 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 6998 6999 /* Register: SPI_PSEL_MISO */ 7000 /* Description: Pin select for MISO signal */ 7001 7002 /* Bit 31 : Connection */ 7003 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7004 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7005 #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7006 #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7007 7008 /* Bits 4..0 : Pin number */ 7009 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7010 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7011 7012 /* Register: SPI_RXD */ 7013 /* Description: RXD register */ 7014 7015 /* Bits 7..0 : RX data received. Double buffered */ 7016 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 7017 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 7018 7019 /* Register: SPI_TXD */ 7020 /* Description: TXD register */ 7021 7022 /* Bits 7..0 : TX data to send. Double buffered. */ 7023 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 7024 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 7025 7026 /* Register: SPI_FREQUENCY */ 7027 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ 7028 7029 /* Bits 31..0 : SPI master data rate */ 7030 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 7031 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 7032 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 7033 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 7034 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 7035 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 7036 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 7037 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 7038 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 7039 7040 /* Register: SPI_CONFIG */ 7041 /* Description: Configuration register */ 7042 7043 /* Bit 2 : Serial clock (SCK) polarity */ 7044 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 7045 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 7046 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 7047 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 7048 7049 /* Bit 1 : Serial clock (SCK) phase */ 7050 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 7051 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 7052 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 7053 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 7054 7055 /* Bit 0 : Bit order */ 7056 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 7057 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 7058 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 7059 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 7060 7061 7062 /* Peripheral: SPIM */ 7063 /* Description: Serial Peripheral Interface Master with EasyDMA */ 7064 7065 /* Register: SPIM_TASKS_START */ 7066 /* Description: Start SPI transaction */ 7067 7068 /* Bit 0 : Start SPI transaction */ 7069 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 7070 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 7071 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 7072 7073 /* Register: SPIM_TASKS_STOP */ 7074 /* Description: Stop SPI transaction */ 7075 7076 /* Bit 0 : Stop SPI transaction */ 7077 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 7078 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 7079 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 7080 7081 /* Register: SPIM_TASKS_SUSPEND */ 7082 /* Description: Suspend SPI transaction */ 7083 7084 /* Bit 0 : Suspend SPI transaction */ 7085 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 7086 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 7087 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 7088 7089 /* Register: SPIM_TASKS_RESUME */ 7090 /* Description: Resume SPI transaction */ 7091 7092 /* Bit 0 : Resume SPI transaction */ 7093 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 7094 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 7095 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 7096 7097 /* Register: SPIM_EVENTS_STOPPED */ 7098 /* Description: SPI transaction has stopped */ 7099 7100 /* Bit 0 : SPI transaction has stopped */ 7101 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 7102 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 7103 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 7104 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 7105 7106 /* Register: SPIM_EVENTS_ENDRX */ 7107 /* Description: End of RXD buffer reached */ 7108 7109 /* Bit 0 : End of RXD buffer reached */ 7110 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 7111 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 7112 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 7113 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 7114 7115 /* Register: SPIM_EVENTS_END */ 7116 /* Description: End of RXD buffer and TXD buffer reached */ 7117 7118 /* Bit 0 : End of RXD buffer and TXD buffer reached */ 7119 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7120 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7121 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 7122 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 7123 7124 /* Register: SPIM_EVENTS_ENDTX */ 7125 /* Description: End of TXD buffer reached */ 7126 7127 /* Bit 0 : End of TXD buffer reached */ 7128 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 7129 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 7130 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ 7131 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ 7132 7133 /* Register: SPIM_EVENTS_STARTED */ 7134 /* Description: Transaction started */ 7135 7136 /* Bit 0 : Transaction started */ 7137 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 7138 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 7139 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ 7140 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ 7141 7142 /* Register: SPIM_SHORTS */ 7143 /* Description: Shortcuts between local events and tasks */ 7144 7145 /* Bit 17 : Shortcut between event END and task START */ 7146 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 7147 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 7148 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 7149 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 7150 7151 /* Register: SPIM_INTENSET */ 7152 /* Description: Enable interrupt */ 7153 7154 /* Bit 19 : Write '1' to enable interrupt for event STARTED */ 7155 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7156 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7157 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7158 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7159 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 7160 7161 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 7162 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7163 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7164 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7165 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7166 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 7167 7168 /* Bit 6 : Write '1' to enable interrupt for event END */ 7169 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 7170 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7171 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7172 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7173 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ 7174 7175 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 7176 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7177 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7178 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7179 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7180 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 7181 7182 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 7183 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7184 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7185 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7186 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7187 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 7188 7189 /* Register: SPIM_INTENCLR */ 7190 /* Description: Disable interrupt */ 7191 7192 /* Bit 19 : Write '1' to disable interrupt for event STARTED */ 7193 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7194 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7195 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7196 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7197 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 7198 7199 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 7200 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7201 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7202 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7203 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7204 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 7205 7206 /* Bit 6 : Write '1' to disable interrupt for event END */ 7207 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 7208 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7209 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7210 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7211 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ 7212 7213 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 7214 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7215 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7216 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7217 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7218 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 7219 7220 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 7221 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7222 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7223 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7224 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7225 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 7226 7227 /* Register: SPIM_ENABLE */ 7228 /* Description: Enable SPIM */ 7229 7230 /* Bits 3..0 : Enable or disable SPIM */ 7231 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7232 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7233 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ 7234 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ 7235 7236 /* Register: SPIM_PSEL_SCK */ 7237 /* Description: Pin select for SCK */ 7238 7239 /* Bit 31 : Connection */ 7240 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7241 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7242 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 7243 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7244 7245 /* Bits 4..0 : Pin number */ 7246 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 7247 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 7248 7249 /* Register: SPIM_PSEL_MOSI */ 7250 /* Description: Pin select for MOSI signal */ 7251 7252 /* Bit 31 : Connection */ 7253 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7254 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7255 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 7256 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7257 7258 /* Bits 4..0 : Pin number */ 7259 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 7260 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 7261 7262 /* Register: SPIM_PSEL_MISO */ 7263 /* Description: Pin select for MISO signal */ 7264 7265 /* Bit 31 : Connection */ 7266 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7267 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7268 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7269 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7270 7271 /* Bits 4..0 : Pin number */ 7272 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7273 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7274 7275 /* Register: SPIM_FREQUENCY */ 7276 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ 7277 7278 /* Bits 31..0 : SPI master data rate */ 7279 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 7280 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 7281 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 7282 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 7283 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 7284 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 7285 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 7286 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 7287 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 7288 7289 /* Register: SPIM_RXD_PTR */ 7290 /* Description: Data pointer */ 7291 7292 /* Bits 31..0 : Data pointer */ 7293 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7294 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7295 7296 /* Register: SPIM_RXD_MAXCNT */ 7297 /* Description: Maximum number of bytes in receive buffer */ 7298 7299 /* Bits 13..0 : Maximum number of bytes in receive buffer */ 7300 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7301 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7302 7303 /* Register: SPIM_RXD_AMOUNT */ 7304 /* Description: Number of bytes transferred in the last transaction */ 7305 7306 /* Bits 13..0 : Number of bytes transferred in the last transaction */ 7307 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7308 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7309 7310 /* Register: SPIM_RXD_LIST */ 7311 /* Description: EasyDMA list type */ 7312 7313 /* Bits 1..0 : List type */ 7314 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7315 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7316 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7317 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7318 7319 /* Register: SPIM_TXD_PTR */ 7320 /* Description: Data pointer */ 7321 7322 /* Bits 31..0 : Data pointer */ 7323 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7324 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7325 7326 /* Register: SPIM_TXD_MAXCNT */ 7327 /* Description: Maximum number of bytes in transmit buffer */ 7328 7329 /* Bits 13..0 : Maximum number of bytes in transmit buffer */ 7330 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7331 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7332 7333 /* Register: SPIM_TXD_AMOUNT */ 7334 /* Description: Number of bytes transferred in the last transaction */ 7335 7336 /* Bits 13..0 : Number of bytes transferred in the last transaction */ 7337 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7338 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7339 7340 /* Register: SPIM_TXD_LIST */ 7341 /* Description: EasyDMA list type */ 7342 7343 /* Bits 1..0 : List type */ 7344 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7345 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7346 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7347 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7348 7349 /* Register: SPIM_CONFIG */ 7350 /* Description: Configuration register */ 7351 7352 /* Bit 2 : Serial clock (SCK) polarity */ 7353 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 7354 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 7355 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 7356 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 7357 7358 /* Bit 1 : Serial clock (SCK) phase */ 7359 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 7360 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 7361 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 7362 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 7363 7364 /* Bit 0 : Bit order */ 7365 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 7366 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 7367 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 7368 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 7369 7370 /* Register: SPIM_ORC */ 7371 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 7372 7373 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 7374 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 7375 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 7376 7377 7378 /* Peripheral: SPIS */ 7379 /* Description: SPI Slave */ 7380 7381 /* Register: SPIS_TASKS_ACQUIRE */ 7382 /* Description: Acquire SPI semaphore */ 7383 7384 /* Bit 0 : Acquire SPI semaphore */ 7385 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ 7386 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ 7387 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ 7388 7389 /* Register: SPIS_TASKS_RELEASE */ 7390 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ 7391 7392 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ 7393 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ 7394 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ 7395 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ 7396 7397 /* Register: SPIS_EVENTS_END */ 7398 /* Description: Granted transaction completed */ 7399 7400 /* Bit 0 : Granted transaction completed */ 7401 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7402 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7403 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 7404 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 7405 7406 /* Register: SPIS_EVENTS_ENDRX */ 7407 /* Description: End of RXD buffer reached */ 7408 7409 /* Bit 0 : End of RXD buffer reached */ 7410 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 7411 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 7412 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 7413 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 7414 7415 /* Register: SPIS_EVENTS_ACQUIRED */ 7416 /* Description: Semaphore acquired */ 7417 7418 /* Bit 0 : Semaphore acquired */ 7419 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ 7420 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ 7421 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ 7422 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ 7423 7424 /* Register: SPIS_SHORTS */ 7425 /* Description: Shortcuts between local events and tasks */ 7426 7427 /* Bit 2 : Shortcut between event END and task ACQUIRE */ 7428 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 7429 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 7430 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ 7431 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ 7432 7433 /* Register: SPIS_INTENSET */ 7434 /* Description: Enable interrupt */ 7435 7436 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ 7437 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 7438 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 7439 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 7440 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 7441 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ 7442 7443 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 7444 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7445 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7446 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7447 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7448 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 7449 7450 /* Bit 1 : Write '1' to enable interrupt for event END */ 7451 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 7452 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7453 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7454 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7455 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ 7456 7457 /* Register: SPIS_INTENCLR */ 7458 /* Description: Disable interrupt */ 7459 7460 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ 7461 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 7462 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 7463 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 7464 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 7465 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ 7466 7467 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 7468 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7469 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7470 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7471 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7472 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 7473 7474 /* Bit 1 : Write '1' to disable interrupt for event END */ 7475 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 7476 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7477 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7478 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7479 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ 7480 7481 /* Register: SPIS_SEMSTAT */ 7482 /* Description: Semaphore status register */ 7483 7484 /* Bits 1..0 : Semaphore status */ 7485 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 7486 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 7487 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ 7488 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ 7489 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ 7490 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ 7491 7492 /* Register: SPIS_STATUS */ 7493 /* Description: Status from last transaction */ 7494 7495 /* Bit 1 : RX buffer overflow detected, and prevented */ 7496 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 7497 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 7498 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ 7499 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ 7500 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ 7501 7502 /* Bit 0 : TX buffer over-read detected, and prevented */ 7503 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 7504 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 7505 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ 7506 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ 7507 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ 7508 7509 /* Register: SPIS_ENABLE */ 7510 /* Description: Enable SPI slave */ 7511 7512 /* Bits 3..0 : Enable or disable SPI slave */ 7513 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7514 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7515 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ 7516 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ 7517 7518 /* Register: SPIS_PSEL_SCK */ 7519 /* Description: Pin select for SCK */ 7520 7521 /* Bit 31 : Connection */ 7522 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7523 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7524 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 7525 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7526 7527 /* Bits 4..0 : Pin number */ 7528 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 7529 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 7530 7531 /* Register: SPIS_PSEL_MISO */ 7532 /* Description: Pin select for MISO signal */ 7533 7534 /* Bit 31 : Connection */ 7535 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7536 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7537 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7538 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7539 7540 /* Bits 4..0 : Pin number */ 7541 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7542 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7543 7544 /* Register: SPIS_PSEL_MOSI */ 7545 /* Description: Pin select for MOSI signal */ 7546 7547 /* Bit 31 : Connection */ 7548 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7549 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7550 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 7551 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7552 7553 /* Bits 4..0 : Pin number */ 7554 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 7555 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 7556 7557 /* Register: SPIS_PSEL_CSN */ 7558 /* Description: Pin select for CSN signal */ 7559 7560 /* Bit 31 : Connection */ 7561 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7562 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7563 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ 7564 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7565 7566 /* Bits 4..0 : Pin number */ 7567 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ 7568 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ 7569 7570 /* Register: SPIS_RXD_PTR */ 7571 /* Description: RXD data pointer */ 7572 7573 /* Bits 31..0 : RXD data pointer */ 7574 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7575 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7576 7577 /* Register: SPIS_RXD_MAXCNT */ 7578 /* Description: Maximum number of bytes in receive buffer */ 7579 7580 /* Bits 13..0 : Maximum number of bytes in receive buffer */ 7581 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7582 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7583 7584 /* Register: SPIS_RXD_AMOUNT */ 7585 /* Description: Number of bytes received in last granted transaction */ 7586 7587 /* Bits 13..0 : Number of bytes received in the last granted transaction */ 7588 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7589 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7590 7591 /* Register: SPIS_RXD_LIST */ 7592 /* Description: EasyDMA list type */ 7593 7594 /* Bits 1..0 : List type */ 7595 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7596 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7597 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7598 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7599 7600 /* Register: SPIS_TXD_PTR */ 7601 /* Description: TXD data pointer */ 7602 7603 /* Bits 31..0 : TXD data pointer */ 7604 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7605 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7606 7607 /* Register: SPIS_TXD_MAXCNT */ 7608 /* Description: Maximum number of bytes in transmit buffer */ 7609 7610 /* Bits 13..0 : Maximum number of bytes in transmit buffer */ 7611 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7612 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7613 7614 /* Register: SPIS_TXD_AMOUNT */ 7615 /* Description: Number of bytes transmitted in last granted transaction */ 7616 7617 /* Bits 13..0 : Number of bytes transmitted in last granted transaction */ 7618 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7619 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7620 7621 /* Register: SPIS_TXD_LIST */ 7622 /* Description: EasyDMA list type */ 7623 7624 /* Bits 1..0 : List type */ 7625 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7626 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7627 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7628 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7629 7630 /* Register: SPIS_CONFIG */ 7631 /* Description: Configuration register */ 7632 7633 /* Bit 2 : Serial clock (SCK) polarity */ 7634 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 7635 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 7636 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 7637 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 7638 7639 /* Bit 1 : Serial clock (SCK) phase */ 7640 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 7641 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 7642 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 7643 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 7644 7645 /* Bit 0 : Bit order */ 7646 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 7647 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 7648 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 7649 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 7650 7651 /* Register: SPIS_DEF */ 7652 /* Description: Default character. Character clocked out in case of an ignored transaction. */ 7653 7654 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ 7655 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 7656 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 7657 7658 /* Register: SPIS_ORC */ 7659 /* Description: Over-read character */ 7660 7661 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ 7662 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 7663 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 7664 7665 7666 /* Peripheral: TEMP */ 7667 /* Description: Temperature Sensor */ 7668 7669 /* Register: TEMP_TASKS_START */ 7670 /* Description: Start temperature measurement */ 7671 7672 /* Bit 0 : Start temperature measurement */ 7673 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 7674 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 7675 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 7676 7677 /* Register: TEMP_TASKS_STOP */ 7678 /* Description: Stop temperature measurement */ 7679 7680 /* Bit 0 : Stop temperature measurement */ 7681 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 7682 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 7683 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 7684 7685 /* Register: TEMP_EVENTS_DATARDY */ 7686 /* Description: Temperature measurement complete, data ready */ 7687 7688 /* Bit 0 : Temperature measurement complete, data ready */ 7689 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ 7690 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ 7691 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ 7692 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ 7693 7694 /* Register: TEMP_INTENSET */ 7695 /* Description: Enable interrupt */ 7696 7697 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */ 7698 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 7699 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 7700 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 7701 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 7702 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ 7703 7704 /* Register: TEMP_INTENCLR */ 7705 /* Description: Disable interrupt */ 7706 7707 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */ 7708 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 7709 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 7710 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 7711 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 7712 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ 7713 7714 /* Register: TEMP_TEMP */ 7715 /* Description: Temperature in degC (0.25deg steps) */ 7716 7717 /* Bits 31..0 : Temperature in degC (0.25deg steps) */ 7718 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ 7719 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ 7720 7721 /* Register: TEMP_A0 */ 7722 /* Description: Slope of first piecewise linear function */ 7723 7724 /* Bits 11..0 : Slope of first piecewise linear function */ 7725 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ 7726 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ 7727 7728 /* Register: TEMP_A1 */ 7729 /* Description: Slope of second piecewise linear function */ 7730 7731 /* Bits 11..0 : Slope of second piecewise linear function */ 7732 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ 7733 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ 7734 7735 /* Register: TEMP_A2 */ 7736 /* Description: Slope of third piecewise linear function */ 7737 7738 /* Bits 11..0 : Slope of third piecewise linear function */ 7739 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ 7740 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ 7741 7742 /* Register: TEMP_A3 */ 7743 /* Description: Slope of fourth piecewise linear function */ 7744 7745 /* Bits 11..0 : Slope of fourth piecewise linear function */ 7746 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ 7747 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ 7748 7749 /* Register: TEMP_A4 */ 7750 /* Description: Slope of fifth piecewise linear function */ 7751 7752 /* Bits 11..0 : Slope of fifth piecewise linear function */ 7753 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ 7754 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ 7755 7756 /* Register: TEMP_A5 */ 7757 /* Description: Slope of sixth piecewise linear function */ 7758 7759 /* Bits 11..0 : Slope of sixth piecewise linear function */ 7760 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ 7761 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ 7762 7763 /* Register: TEMP_B0 */ 7764 /* Description: y-intercept of first piecewise linear function */ 7765 7766 /* Bits 13..0 : y-intercept of first piecewise linear function */ 7767 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ 7768 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ 7769 7770 /* Register: TEMP_B1 */ 7771 /* Description: y-intercept of second piecewise linear function */ 7772 7773 /* Bits 13..0 : y-intercept of second piecewise linear function */ 7774 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ 7775 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ 7776 7777 /* Register: TEMP_B2 */ 7778 /* Description: y-intercept of third piecewise linear function */ 7779 7780 /* Bits 13..0 : y-intercept of third piecewise linear function */ 7781 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ 7782 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ 7783 7784 /* Register: TEMP_B3 */ 7785 /* Description: y-intercept of fourth piecewise linear function */ 7786 7787 /* Bits 13..0 : y-intercept of fourth piecewise linear function */ 7788 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ 7789 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ 7790 7791 /* Register: TEMP_B4 */ 7792 /* Description: y-intercept of fifth piecewise linear function */ 7793 7794 /* Bits 13..0 : y-intercept of fifth piecewise linear function */ 7795 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ 7796 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ 7797 7798 /* Register: TEMP_B5 */ 7799 /* Description: y-intercept of sixth piecewise linear function */ 7800 7801 /* Bits 13..0 : y-intercept of sixth piecewise linear function */ 7802 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ 7803 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ 7804 7805 /* Register: TEMP_T0 */ 7806 /* Description: End point of first piecewise linear function */ 7807 7808 /* Bits 7..0 : End point of first piecewise linear function */ 7809 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ 7810 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ 7811 7812 /* Register: TEMP_T1 */ 7813 /* Description: End point of second piecewise linear function */ 7814 7815 /* Bits 7..0 : End point of second piecewise linear function */ 7816 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ 7817 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ 7818 7819 /* Register: TEMP_T2 */ 7820 /* Description: End point of third piecewise linear function */ 7821 7822 /* Bits 7..0 : End point of third piecewise linear function */ 7823 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ 7824 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ 7825 7826 /* Register: TEMP_T3 */ 7827 /* Description: End point of fourth piecewise linear function */ 7828 7829 /* Bits 7..0 : End point of fourth piecewise linear function */ 7830 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ 7831 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ 7832 7833 /* Register: TEMP_T4 */ 7834 /* Description: End point of fifth piecewise linear function */ 7835 7836 /* Bits 7..0 : End point of fifth piecewise linear function */ 7837 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ 7838 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ 7839 7840 7841 /* Peripheral: TIMER */ 7842 /* Description: Timer/Counter 0 */ 7843 7844 /* Register: TIMER_TASKS_START */ 7845 /* Description: Start Timer */ 7846 7847 /* Bit 0 : Start Timer */ 7848 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 7849 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 7850 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 7851 7852 /* Register: TIMER_TASKS_STOP */ 7853 /* Description: Stop Timer */ 7854 7855 /* Bit 0 : Stop Timer */ 7856 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 7857 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 7858 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 7859 7860 /* Register: TIMER_TASKS_COUNT */ 7861 /* Description: Increment Timer (Counter mode only) */ 7862 7863 /* Bit 0 : Increment Timer (Counter mode only) */ 7864 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 7865 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 7866 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ 7867 7868 /* Register: TIMER_TASKS_CLEAR */ 7869 /* Description: Clear time */ 7870 7871 /* Bit 0 : Clear time */ 7872 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 7873 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 7874 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 7875 7876 /* Register: TIMER_TASKS_SHUTDOWN */ 7877 /* Description: Deprecated register - Shut down timer */ 7878 7879 /* Bit 0 : Deprecated field - Shut down timer */ 7880 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 7881 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 7882 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ 7883 7884 /* Register: TIMER_TASKS_CAPTURE */ 7885 /* Description: Description collection: Capture Timer value to CC[n] register */ 7886 7887 /* Bit 0 : Capture Timer value to CC[n] register */ 7888 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 7889 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 7890 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 7891 7892 /* Register: TIMER_EVENTS_COMPARE */ 7893 /* Description: Description collection: Compare event on CC[n] match */ 7894 7895 /* Bit 0 : Compare event on CC[n] match */ 7896 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 7897 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 7898 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 7899 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 7900 7901 /* Register: TIMER_SHORTS */ 7902 /* Description: Shortcuts between local events and tasks */ 7903 7904 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ 7905 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ 7906 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ 7907 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ 7908 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ 7909 7910 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ 7911 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ 7912 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ 7913 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ 7914 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ 7915 7916 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ 7917 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 7918 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 7919 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ 7920 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ 7921 7922 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ 7923 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 7924 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 7925 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ 7926 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ 7927 7928 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ 7929 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 7930 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 7931 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ 7932 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ 7933 7934 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ 7935 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 7936 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 7937 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 7938 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 7939 7940 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ 7941 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ 7942 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ 7943 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7944 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7945 7946 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ 7947 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ 7948 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ 7949 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7950 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7951 7952 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ 7953 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 7954 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 7955 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7956 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7957 7958 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ 7959 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 7960 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 7961 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7962 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7963 7964 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ 7965 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 7966 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 7967 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7968 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7969 7970 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 7971 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 7972 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 7973 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 7974 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 7975 7976 /* Register: TIMER_INTENSET */ 7977 /* Description: Enable interrupt */ 7978 7979 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ 7980 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 7981 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 7982 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 7983 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 7984 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ 7985 7986 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ 7987 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 7988 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 7989 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 7990 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 7991 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ 7992 7993 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 7994 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 7995 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 7996 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 7997 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 7998 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 7999 8000 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 8001 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8002 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8003 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8004 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8005 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 8006 8007 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 8008 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8009 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8010 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8011 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8012 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 8013 8014 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 8015 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8016 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8017 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8018 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8019 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 8020 8021 /* Register: TIMER_INTENCLR */ 8022 /* Description: Disable interrupt */ 8023 8024 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ 8025 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 8026 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 8027 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 8028 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 8029 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ 8030 8031 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ 8032 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 8033 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 8034 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 8035 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 8036 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ 8037 8038 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 8039 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 8040 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 8041 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 8042 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 8043 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 8044 8045 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 8046 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8047 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8048 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8049 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8050 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 8051 8052 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 8053 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8054 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8055 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8056 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8057 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 8058 8059 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 8060 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8061 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8062 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8063 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8064 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 8065 8066 /* Register: TIMER_MODE */ 8067 /* Description: Timer mode selection */ 8068 8069 /* Bits 1..0 : Timer mode */ 8070 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 8071 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 8072 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 8073 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 8074 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 8075 8076 /* Register: TIMER_BITMODE */ 8077 /* Description: Configure the number of bits used by the TIMER */ 8078 8079 /* Bits 1..0 : Timer bit width */ 8080 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 8081 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 8082 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 8083 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 8084 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 8085 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 8086 8087 /* Register: TIMER_PRESCALER */ 8088 /* Description: Timer prescaler register */ 8089 8090 /* Bits 3..0 : Prescaler value */ 8091 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 8092 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 8093 8094 /* Register: TIMER_CC */ 8095 /* Description: Description collection: Capture/Compare register n */ 8096 8097 /* Bits 31..0 : Capture/Compare value */ 8098 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 8099 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 8100 8101 8102 /* Peripheral: TWI */ 8103 /* Description: I2C compatible Two-Wire Interface */ 8104 8105 /* Register: TWI_TASKS_STARTRX */ 8106 /* Description: Start TWI receive sequence */ 8107 8108 /* Bit 0 : Start TWI receive sequence */ 8109 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 8110 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 8111 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 8112 8113 /* Register: TWI_TASKS_STARTTX */ 8114 /* Description: Start TWI transmit sequence */ 8115 8116 /* Bit 0 : Start TWI transmit sequence */ 8117 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 8118 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 8119 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 8120 8121 /* Register: TWI_TASKS_STOP */ 8122 /* Description: Stop TWI transaction */ 8123 8124 /* Bit 0 : Stop TWI transaction */ 8125 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8126 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8127 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 8128 8129 /* Register: TWI_TASKS_SUSPEND */ 8130 /* Description: Suspend TWI transaction */ 8131 8132 /* Bit 0 : Suspend TWI transaction */ 8133 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 8134 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 8135 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 8136 8137 /* Register: TWI_TASKS_RESUME */ 8138 /* Description: Resume TWI transaction */ 8139 8140 /* Bit 0 : Resume TWI transaction */ 8141 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 8142 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 8143 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 8144 8145 /* Register: TWI_EVENTS_STOPPED */ 8146 /* Description: TWI stopped */ 8147 8148 /* Bit 0 : TWI stopped */ 8149 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8150 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8151 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 8152 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 8153 8154 /* Register: TWI_EVENTS_RXDREADY */ 8155 /* Description: TWI RXD byte received */ 8156 8157 /* Bit 0 : TWI RXD byte received */ 8158 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ 8159 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ 8160 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ 8161 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ 8162 8163 /* Register: TWI_EVENTS_TXDSENT */ 8164 /* Description: TWI TXD byte sent */ 8165 8166 /* Bit 0 : TWI TXD byte sent */ 8167 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ 8168 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ 8169 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ 8170 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ 8171 8172 /* Register: TWI_EVENTS_ERROR */ 8173 /* Description: TWI error */ 8174 8175 /* Bit 0 : TWI error */ 8176 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 8177 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 8178 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 8179 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 8180 8181 /* Register: TWI_EVENTS_BB */ 8182 /* Description: TWI byte boundary, generated before each byte that is sent or received */ 8183 8184 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ 8185 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ 8186 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ 8187 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ 8188 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ 8189 8190 /* Register: TWI_EVENTS_SUSPENDED */ 8191 /* Description: TWI entered the suspended state */ 8192 8193 /* Bit 0 : TWI entered the suspended state */ 8194 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ 8195 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ 8196 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ 8197 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ 8198 8199 /* Register: TWI_SHORTS */ 8200 /* Description: Shortcuts between local events and tasks */ 8201 8202 /* Bit 1 : Shortcut between event BB and task STOP */ 8203 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ 8204 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ 8205 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ 8206 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ 8207 8208 /* Bit 0 : Shortcut between event BB and task SUSPEND */ 8209 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ 8210 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ 8211 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8212 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8213 8214 /* Register: TWI_INTENSET */ 8215 /* Description: Enable interrupt */ 8216 8217 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ 8218 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8219 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8220 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8221 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8222 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 8223 8224 /* Bit 14 : Write '1' to enable interrupt for event BB */ 8225 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ 8226 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ 8227 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ 8228 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ 8229 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ 8230 8231 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 8232 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8233 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8234 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8235 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8236 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ 8237 8238 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ 8239 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 8240 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 8241 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ 8242 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ 8243 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ 8244 8245 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ 8246 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 8247 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 8248 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ 8249 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ 8250 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ 8251 8252 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 8253 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8254 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8255 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 8256 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 8257 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 8258 8259 /* Register: TWI_INTENCLR */ 8260 /* Description: Disable interrupt */ 8261 8262 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ 8263 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8264 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8265 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8266 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8267 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 8268 8269 /* Bit 14 : Write '1' to disable interrupt for event BB */ 8270 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ 8271 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ 8272 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ 8273 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ 8274 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ 8275 8276 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 8277 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8278 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8279 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8280 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8281 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 8282 8283 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ 8284 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 8285 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 8286 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ 8287 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ 8288 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ 8289 8290 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ 8291 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 8292 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 8293 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ 8294 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ 8295 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ 8296 8297 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 8298 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8299 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8300 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 8301 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 8302 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 8303 8304 /* Register: TWI_ERRORSRC */ 8305 /* Description: Error source */ 8306 8307 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 8308 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 8309 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 8310 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ 8311 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ 8312 8313 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 8314 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 8315 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 8316 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ 8317 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ 8318 8319 /* Bit 0 : Overrun error */ 8320 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 8321 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 8322 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ 8323 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ 8324 8325 /* Register: TWI_ENABLE */ 8326 /* Description: Enable TWI */ 8327 8328 /* Bits 3..0 : Enable or disable TWI */ 8329 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 8330 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 8331 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ 8332 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ 8333 8334 /* Register: TWI_PSEL_SCL */ 8335 /* Description: Pin select for SCL */ 8336 8337 /* Bit 31 : Connection */ 8338 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8339 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8340 #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 8341 #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8342 8343 /* Bits 4..0 : Pin number */ 8344 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 8345 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 8346 8347 /* Register: TWI_PSEL_SDA */ 8348 /* Description: Pin select for SDA */ 8349 8350 /* Bit 31 : Connection */ 8351 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8352 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8353 #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 8354 #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8355 8356 /* Bits 4..0 : Pin number */ 8357 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 8358 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 8359 8360 /* Register: TWI_RXD */ 8361 /* Description: RXD register */ 8362 8363 /* Bits 7..0 : RXD register */ 8364 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 8365 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 8366 8367 /* Register: TWI_TXD */ 8368 /* Description: TXD register */ 8369 8370 /* Bits 7..0 : TXD register */ 8371 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 8372 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 8373 8374 /* Register: TWI_FREQUENCY */ 8375 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ 8376 8377 /* Bits 31..0 : TWI master clock frequency */ 8378 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 8379 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 8380 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 8381 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 8382 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ 8383 8384 /* Register: TWI_ADDRESS */ 8385 /* Description: Address used in the TWI transfer */ 8386 8387 /* Bits 6..0 : Address used in the TWI transfer */ 8388 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 8389 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 8390 8391 8392 /* Peripheral: TWIM */ 8393 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */ 8394 8395 /* Register: TWIM_TASKS_STARTRX */ 8396 /* Description: Start TWI receive sequence */ 8397 8398 /* Bit 0 : Start TWI receive sequence */ 8399 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 8400 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 8401 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 8402 8403 /* Register: TWIM_TASKS_STARTTX */ 8404 /* Description: Start TWI transmit sequence */ 8405 8406 /* Bit 0 : Start TWI transmit sequence */ 8407 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 8408 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 8409 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 8410 8411 /* Register: TWIM_TASKS_STOP */ 8412 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 8413 8414 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 8415 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8416 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8417 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 8418 8419 /* Register: TWIM_TASKS_SUSPEND */ 8420 /* Description: Suspend TWI transaction */ 8421 8422 /* Bit 0 : Suspend TWI transaction */ 8423 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 8424 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 8425 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 8426 8427 /* Register: TWIM_TASKS_RESUME */ 8428 /* Description: Resume TWI transaction */ 8429 8430 /* Bit 0 : Resume TWI transaction */ 8431 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 8432 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 8433 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 8434 8435 /* Register: TWIM_EVENTS_STOPPED */ 8436 /* Description: TWI stopped */ 8437 8438 /* Bit 0 : TWI stopped */ 8439 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8440 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8441 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 8442 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 8443 8444 /* Register: TWIM_EVENTS_ERROR */ 8445 /* Description: TWI error */ 8446 8447 /* Bit 0 : TWI error */ 8448 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 8449 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 8450 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 8451 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 8452 8453 /* Register: TWIM_EVENTS_SUSPENDED */ 8454 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ 8455 8456 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ 8457 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ 8458 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ 8459 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ 8460 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ 8461 8462 /* Register: TWIM_EVENTS_RXSTARTED */ 8463 /* Description: Receive sequence started */ 8464 8465 /* Bit 0 : Receive sequence started */ 8466 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 8467 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 8468 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8469 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 8470 8471 /* Register: TWIM_EVENTS_TXSTARTED */ 8472 /* Description: Transmit sequence started */ 8473 8474 /* Bit 0 : Transmit sequence started */ 8475 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 8476 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 8477 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8478 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 8479 8480 /* Register: TWIM_EVENTS_LASTRX */ 8481 /* Description: Byte boundary, starting to receive the last byte */ 8482 8483 /* Bit 0 : Byte boundary, starting to receive the last byte */ 8484 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ 8485 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ 8486 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ 8487 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ 8488 8489 /* Register: TWIM_EVENTS_LASTTX */ 8490 /* Description: Byte boundary, starting to transmit the last byte */ 8491 8492 /* Bit 0 : Byte boundary, starting to transmit the last byte */ 8493 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ 8494 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ 8495 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ 8496 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ 8497 8498 /* Register: TWIM_SHORTS */ 8499 /* Description: Shortcuts between local events and tasks */ 8500 8501 /* Bit 12 : Shortcut between event LASTRX and task STOP */ 8502 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ 8503 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ 8504 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ 8505 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ 8506 8507 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ 8508 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ 8509 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ 8510 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8511 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8512 8513 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ 8514 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ 8515 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ 8516 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ 8517 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ 8518 8519 /* Bit 9 : Shortcut between event LASTTX and task STOP */ 8520 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ 8521 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ 8522 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ 8523 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ 8524 8525 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ 8526 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ 8527 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ 8528 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8529 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8530 8531 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */ 8532 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ 8533 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ 8534 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 8535 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 8536 8537 /* Register: TWIM_INTEN */ 8538 /* Description: Enable or disable interrupt */ 8539 8540 /* Bit 24 : Enable or disable interrupt for event LASTTX */ 8541 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8542 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8543 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ 8544 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ 8545 8546 /* Bit 23 : Enable or disable interrupt for event LASTRX */ 8547 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8548 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8549 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ 8550 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ 8551 8552 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 8553 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8554 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8555 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 8556 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 8557 8558 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 8559 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8560 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8561 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 8562 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 8563 8564 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */ 8565 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8566 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8567 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ 8568 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ 8569 8570 /* Bit 9 : Enable or disable interrupt for event ERROR */ 8571 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8572 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8573 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 8574 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 8575 8576 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 8577 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8578 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8579 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 8580 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 8581 8582 /* Register: TWIM_INTENSET */ 8583 /* Description: Enable interrupt */ 8584 8585 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */ 8586 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8587 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8588 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 8589 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 8590 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ 8591 8592 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */ 8593 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8594 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8595 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 8596 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 8597 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ 8598 8599 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 8600 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8601 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8602 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8603 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8604 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 8605 8606 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 8607 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8608 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8609 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8610 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8611 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 8612 8613 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ 8614 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8615 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8616 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8617 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8618 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 8619 8620 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 8621 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8622 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8623 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8624 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8625 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 8626 8627 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 8628 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8629 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8630 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 8631 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 8632 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 8633 8634 /* Register: TWIM_INTENCLR */ 8635 /* Description: Disable interrupt */ 8636 8637 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */ 8638 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8639 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8640 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 8641 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 8642 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ 8643 8644 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */ 8645 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8646 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8647 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 8648 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 8649 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ 8650 8651 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 8652 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8653 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8654 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8655 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8656 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 8657 8658 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 8659 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8660 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8661 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8662 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8663 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 8664 8665 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ 8666 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8667 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8668 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8669 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8670 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 8671 8672 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 8673 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8674 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8675 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8676 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8677 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 8678 8679 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 8680 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8681 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8682 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 8683 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 8684 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 8685 8686 /* Register: TWIM_ERRORSRC */ 8687 /* Description: Error source */ 8688 8689 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 8690 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 8691 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 8692 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 8693 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 8694 8695 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 8696 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 8697 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 8698 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ 8699 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ 8700 8701 /* Bit 0 : Overrun error */ 8702 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 8703 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 8704 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ 8705 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ 8706 8707 /* Register: TWIM_ENABLE */ 8708 /* Description: Enable TWIM */ 8709 8710 /* Bits 3..0 : Enable or disable TWIM */ 8711 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 8712 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 8713 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ 8714 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ 8715 8716 /* Register: TWIM_PSEL_SCL */ 8717 /* Description: Pin select for SCL signal */ 8718 8719 /* Bit 31 : Connection */ 8720 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8721 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8722 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 8723 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8724 8725 /* Bits 4..0 : Pin number */ 8726 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 8727 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 8728 8729 /* Register: TWIM_PSEL_SDA */ 8730 /* Description: Pin select for SDA signal */ 8731 8732 /* Bit 31 : Connection */ 8733 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8734 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8735 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 8736 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8737 8738 /* Bits 4..0 : Pin number */ 8739 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 8740 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 8741 8742 /* Register: TWIM_FREQUENCY */ 8743 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ 8744 8745 /* Bits 31..0 : TWI master clock frequency */ 8746 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 8747 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 8748 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 8749 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 8750 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ 8751 8752 /* Register: TWIM_RXD_PTR */ 8753 /* Description: Data pointer */ 8754 8755 /* Bits 31..0 : Data pointer */ 8756 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 8757 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 8758 8759 /* Register: TWIM_RXD_MAXCNT */ 8760 /* Description: Maximum number of bytes in receive buffer */ 8761 8762 /* Bits 13..0 : Maximum number of bytes in receive buffer */ 8763 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 8764 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 8765 8766 /* Register: TWIM_RXD_AMOUNT */ 8767 /* Description: Number of bytes transferred in the last transaction */ 8768 8769 /* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 8770 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 8771 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 8772 8773 /* Register: TWIM_RXD_LIST */ 8774 /* Description: EasyDMA list type */ 8775 8776 /* Bits 2..0 : List type */ 8777 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 8778 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 8779 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 8780 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 8781 8782 /* Register: TWIM_TXD_PTR */ 8783 /* Description: Data pointer */ 8784 8785 /* Bits 31..0 : Data pointer */ 8786 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 8787 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 8788 8789 /* Register: TWIM_TXD_MAXCNT */ 8790 /* Description: Maximum number of bytes in transmit buffer */ 8791 8792 /* Bits 13..0 : Maximum number of bytes in transmit buffer */ 8793 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 8794 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 8795 8796 /* Register: TWIM_TXD_AMOUNT */ 8797 /* Description: Number of bytes transferred in the last transaction */ 8798 8799 /* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 8800 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 8801 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 8802 8803 /* Register: TWIM_TXD_LIST */ 8804 /* Description: EasyDMA list type */ 8805 8806 /* Bits 2..0 : List type */ 8807 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 8808 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 8809 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 8810 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 8811 8812 /* Register: TWIM_ADDRESS */ 8813 /* Description: Address used in the TWI transfer */ 8814 8815 /* Bits 6..0 : Address used in the TWI transfer */ 8816 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 8817 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 8818 8819 8820 /* Peripheral: TWIS */ 8821 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */ 8822 8823 /* Register: TWIS_TASKS_STOP */ 8824 /* Description: Stop TWI transaction */ 8825 8826 /* Bit 0 : Stop TWI transaction */ 8827 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8828 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8829 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 8830 8831 /* Register: TWIS_TASKS_SUSPEND */ 8832 /* Description: Suspend TWI transaction */ 8833 8834 /* Bit 0 : Suspend TWI transaction */ 8835 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 8836 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 8837 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 8838 8839 /* Register: TWIS_TASKS_RESUME */ 8840 /* Description: Resume TWI transaction */ 8841 8842 /* Bit 0 : Resume TWI transaction */ 8843 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 8844 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 8845 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ 8846 8847 /* Register: TWIS_TASKS_PREPARERX */ 8848 /* Description: Prepare the TWI slave to respond to a write command */ 8849 8850 /* Bit 0 : Prepare the TWI slave to respond to a write command */ 8851 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ 8852 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ 8853 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ 8854 8855 /* Register: TWIS_TASKS_PREPARETX */ 8856 /* Description: Prepare the TWI slave to respond to a read command */ 8857 8858 /* Bit 0 : Prepare the TWI slave to respond to a read command */ 8859 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ 8860 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ 8861 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ 8862 8863 /* Register: TWIS_EVENTS_STOPPED */ 8864 /* Description: TWI stopped */ 8865 8866 /* Bit 0 : TWI stopped */ 8867 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8868 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8869 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ 8870 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ 8871 8872 /* Register: TWIS_EVENTS_ERROR */ 8873 /* Description: TWI error */ 8874 8875 /* Bit 0 : TWI error */ 8876 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 8877 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 8878 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 8879 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 8880 8881 /* Register: TWIS_EVENTS_RXSTARTED */ 8882 /* Description: Receive sequence started */ 8883 8884 /* Bit 0 : Receive sequence started */ 8885 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 8886 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 8887 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8888 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 8889 8890 /* Register: TWIS_EVENTS_TXSTARTED */ 8891 /* Description: Transmit sequence started */ 8892 8893 /* Bit 0 : Transmit sequence started */ 8894 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 8895 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 8896 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 8897 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 8898 8899 /* Register: TWIS_EVENTS_WRITE */ 8900 /* Description: Write command received */ 8901 8902 /* Bit 0 : Write command received */ 8903 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ 8904 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ 8905 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ 8906 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ 8907 8908 /* Register: TWIS_EVENTS_READ */ 8909 /* Description: Read command received */ 8910 8911 /* Bit 0 : Read command received */ 8912 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ 8913 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ 8914 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ 8915 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ 8916 8917 /* Register: TWIS_SHORTS */ 8918 /* Description: Shortcuts between local events and tasks */ 8919 8920 /* Bit 14 : Shortcut between event READ and task SUSPEND */ 8921 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ 8922 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ 8923 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8924 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8925 8926 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */ 8927 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ 8928 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ 8929 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8930 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8931 8932 /* Register: TWIS_INTEN */ 8933 /* Description: Enable or disable interrupt */ 8934 8935 /* Bit 26 : Enable or disable interrupt for event READ */ 8936 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ 8937 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ 8938 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ 8939 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ 8940 8941 /* Bit 25 : Enable or disable interrupt for event WRITE */ 8942 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 8943 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ 8944 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ 8945 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ 8946 8947 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 8948 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8949 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8950 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 8951 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 8952 8953 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 8954 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8955 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8956 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 8957 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 8958 8959 /* Bit 9 : Enable or disable interrupt for event ERROR */ 8960 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8961 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8962 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 8963 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 8964 8965 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 8966 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8967 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8968 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 8969 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 8970 8971 /* Register: TWIS_INTENSET */ 8972 /* Description: Enable interrupt */ 8973 8974 /* Bit 26 : Write '1' to enable interrupt for event READ */ 8975 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ 8976 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ 8977 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ 8978 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ 8979 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ 8980 8981 /* Bit 25 : Write '1' to enable interrupt for event WRITE */ 8982 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 8983 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ 8984 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ 8985 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ 8986 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ 8987 8988 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 8989 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8990 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8991 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8992 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8993 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 8994 8995 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 8996 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8997 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8998 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8999 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9000 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9001 9002 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 9003 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9004 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9005 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9006 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9007 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9008 9009 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 9010 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9011 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9012 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9013 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9014 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 9015 9016 /* Register: TWIS_INTENCLR */ 9017 /* Description: Disable interrupt */ 9018 9019 /* Bit 26 : Write '1' to disable interrupt for event READ */ 9020 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ 9021 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ 9022 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ 9023 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ 9024 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ 9025 9026 /* Bit 25 : Write '1' to disable interrupt for event WRITE */ 9027 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9028 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9029 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ 9030 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ 9031 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ 9032 9033 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 9034 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9035 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9036 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9037 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9038 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9039 9040 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 9041 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9042 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9043 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9044 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9045 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9046 9047 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 9048 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9049 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9050 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9051 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9052 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9053 9054 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 9055 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9056 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9057 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9058 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9059 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 9060 9061 /* Register: TWIS_ERRORSRC */ 9062 /* Description: Error source */ 9063 9064 /* Bit 3 : TX buffer over-read detected, and prevented */ 9065 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ 9066 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 9067 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ 9068 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ 9069 9070 /* Bit 2 : NACK sent after receiving a data byte */ 9071 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 9072 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 9073 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 9074 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 9075 9076 /* Bit 0 : RX buffer overflow detected, and prevented */ 9077 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ 9078 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 9079 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ 9080 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ 9081 9082 /* Register: TWIS_MATCH */ 9083 /* Description: Status register indicating which address had a match */ 9084 9085 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ 9086 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ 9087 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ 9088 9089 /* Register: TWIS_ENABLE */ 9090 /* Description: Enable TWIS */ 9091 9092 /* Bits 3..0 : Enable or disable TWIS */ 9093 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9094 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9095 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ 9096 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ 9097 9098 /* Register: TWIS_PSEL_SCL */ 9099 /* Description: Pin select for SCL signal */ 9100 9101 /* Bit 31 : Connection */ 9102 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9103 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9104 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 9105 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9106 9107 /* Bits 4..0 : Pin number */ 9108 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 9109 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 9110 9111 /* Register: TWIS_PSEL_SDA */ 9112 /* Description: Pin select for SDA signal */ 9113 9114 /* Bit 31 : Connection */ 9115 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9116 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9117 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 9118 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9119 9120 /* Bits 4..0 : Pin number */ 9121 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 9122 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 9123 9124 /* Register: TWIS_RXD_PTR */ 9125 /* Description: RXD Data pointer */ 9126 9127 /* Bits 31..0 : RXD Data pointer */ 9128 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9129 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9130 9131 /* Register: TWIS_RXD_MAXCNT */ 9132 /* Description: Maximum number of bytes in RXD buffer */ 9133 9134 /* Bits 13..0 : Maximum number of bytes in RXD buffer */ 9135 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9136 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9137 9138 /* Register: TWIS_RXD_AMOUNT */ 9139 /* Description: Number of bytes transferred in the last RXD transaction */ 9140 9141 /* Bits 13..0 : Number of bytes transferred in the last RXD transaction */ 9142 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9143 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9144 9145 /* Register: TWIS_RXD_LIST */ 9146 /* Description: EasyDMA list type */ 9147 9148 /* Bits 1..0 : List type */ 9149 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9150 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9151 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9152 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9153 9154 /* Register: TWIS_TXD_PTR */ 9155 /* Description: TXD Data pointer */ 9156 9157 /* Bits 31..0 : TXD Data pointer */ 9158 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9159 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9160 9161 /* Register: TWIS_TXD_MAXCNT */ 9162 /* Description: Maximum number of bytes in TXD buffer */ 9163 9164 /* Bits 13..0 : Maximum number of bytes in TXD buffer */ 9165 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9166 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9167 9168 /* Register: TWIS_TXD_AMOUNT */ 9169 /* Description: Number of bytes transferred in the last TXD transaction */ 9170 9171 /* Bits 13..0 : Number of bytes transferred in the last TXD transaction */ 9172 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9173 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9174 9175 /* Register: TWIS_TXD_LIST */ 9176 /* Description: EasyDMA list type */ 9177 9178 /* Bits 1..0 : List type */ 9179 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9180 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9181 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9182 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9183 9184 /* Register: TWIS_ADDRESS */ 9185 /* Description: Description collection: TWI slave address n */ 9186 9187 /* Bits 6..0 : TWI slave address */ 9188 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 9189 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 9190 9191 /* Register: TWIS_CONFIG */ 9192 /* Description: Configuration register for the address match mechanism */ 9193 9194 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ 9195 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ 9196 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ 9197 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ 9198 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ 9199 9200 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ 9201 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ 9202 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ 9203 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ 9204 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ 9205 9206 /* Register: TWIS_ORC */ 9207 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9208 9209 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9210 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 9211 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 9212 9213 9214 /* Peripheral: UART */ 9215 /* Description: Universal Asynchronous Receiver/Transmitter */ 9216 9217 /* Register: UART_TASKS_STARTRX */ 9218 /* Description: Start UART receiver */ 9219 9220 /* Bit 0 : Start UART receiver */ 9221 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 9222 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 9223 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 9224 9225 /* Register: UART_TASKS_STOPRX */ 9226 /* Description: Stop UART receiver */ 9227 9228 /* Bit 0 : Stop UART receiver */ 9229 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ 9230 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ 9231 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ 9232 9233 /* Register: UART_TASKS_STARTTX */ 9234 /* Description: Start UART transmitter */ 9235 9236 /* Bit 0 : Start UART transmitter */ 9237 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 9238 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 9239 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 9240 9241 /* Register: UART_TASKS_STOPTX */ 9242 /* Description: Stop UART transmitter */ 9243 9244 /* Bit 0 : Stop UART transmitter */ 9245 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ 9246 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ 9247 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ 9248 9249 /* Register: UART_TASKS_SUSPEND */ 9250 /* Description: Suspend UART */ 9251 9252 /* Bit 0 : Suspend UART */ 9253 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 9254 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 9255 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ 9256 9257 /* Register: UART_EVENTS_CTS */ 9258 /* Description: CTS is activated (set low). Clear To Send. */ 9259 9260 /* Bit 0 : CTS is activated (set low). Clear To Send. */ 9261 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ 9262 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ 9263 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ 9264 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ 9265 9266 /* Register: UART_EVENTS_NCTS */ 9267 /* Description: CTS is deactivated (set high). Not Clear To Send. */ 9268 9269 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ 9270 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ 9271 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ 9272 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ 9273 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ 9274 9275 /* Register: UART_EVENTS_RXDRDY */ 9276 /* Description: Data received in RXD */ 9277 9278 /* Bit 0 : Data received in RXD */ 9279 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ 9280 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ 9281 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ 9282 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ 9283 9284 /* Register: UART_EVENTS_TXDRDY */ 9285 /* Description: Data sent from TXD */ 9286 9287 /* Bit 0 : Data sent from TXD */ 9288 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ 9289 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ 9290 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ 9291 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ 9292 9293 /* Register: UART_EVENTS_ERROR */ 9294 /* Description: Error detected */ 9295 9296 /* Bit 0 : Error detected */ 9297 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 9298 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 9299 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 9300 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 9301 9302 /* Register: UART_EVENTS_RXTO */ 9303 /* Description: Receiver timeout */ 9304 9305 /* Bit 0 : Receiver timeout */ 9306 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ 9307 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ 9308 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ 9309 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ 9310 9311 /* Register: UART_SHORTS */ 9312 /* Description: Shortcuts between local events and tasks */ 9313 9314 /* Bit 4 : Shortcut between event NCTS and task STOPRX */ 9315 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 9316 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 9317 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 9318 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 9319 9320 /* Bit 3 : Shortcut between event CTS and task STARTRX */ 9321 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 9322 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 9323 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 9324 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 9325 9326 /* Register: UART_INTENSET */ 9327 /* Description: Enable interrupt */ 9328 9329 /* Bit 17 : Write '1' to enable interrupt for event RXTO */ 9330 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9331 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9332 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9333 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9334 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ 9335 9336 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 9337 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9338 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9339 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9340 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9341 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9342 9343 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ 9344 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9345 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9346 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9347 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9348 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 9349 9350 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ 9351 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9352 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9353 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9354 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9355 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 9356 9357 /* Bit 1 : Write '1' to enable interrupt for event NCTS */ 9358 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9359 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9360 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9361 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9362 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ 9363 9364 /* Bit 0 : Write '1' to enable interrupt for event CTS */ 9365 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 9366 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 9367 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 9368 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 9369 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ 9370 9371 /* Register: UART_INTENCLR */ 9372 /* Description: Disable interrupt */ 9373 9374 /* Bit 17 : Write '1' to disable interrupt for event RXTO */ 9375 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9376 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9377 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9378 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9379 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 9380 9381 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 9382 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9383 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9384 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9385 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9386 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9387 9388 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ 9389 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9390 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9391 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9392 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9393 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ 9394 9395 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ 9396 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9397 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9398 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9399 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9400 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ 9401 9402 /* Bit 1 : Write '1' to disable interrupt for event NCTS */ 9403 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9404 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9405 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9406 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9407 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 9408 9409 /* Bit 0 : Write '1' to disable interrupt for event CTS */ 9410 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 9411 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 9412 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 9413 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 9414 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 9415 9416 /* Register: UART_ERRORSRC */ 9417 /* Description: Error source */ 9418 9419 /* Bit 3 : Break condition */ 9420 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 9421 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 9422 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 9423 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 9424 9425 /* Bit 2 : Framing error occurred */ 9426 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 9427 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 9428 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 9429 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 9430 9431 /* Bit 1 : Parity error */ 9432 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 9433 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 9434 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 9435 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 9436 9437 /* Bit 0 : Overrun error */ 9438 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 9439 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 9440 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 9441 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 9442 9443 /* Register: UART_ENABLE */ 9444 /* Description: Enable UART */ 9445 9446 /* Bits 3..0 : Enable or disable UART */ 9447 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9448 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9449 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ 9450 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ 9451 9452 /* Register: UART_PSEL_RTS */ 9453 /* Description: Pin select for RTS */ 9454 9455 /* Bit 31 : Connection */ 9456 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9457 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9458 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 9459 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9460 9461 /* Bits 4..0 : Pin number */ 9462 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 9463 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 9464 9465 /* Register: UART_PSEL_TXD */ 9466 /* Description: Pin select for TXD */ 9467 9468 /* Bit 31 : Connection */ 9469 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9470 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9471 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 9472 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9473 9474 /* Bits 4..0 : Pin number */ 9475 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 9476 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 9477 9478 /* Register: UART_PSEL_CTS */ 9479 /* Description: Pin select for CTS */ 9480 9481 /* Bit 31 : Connection */ 9482 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9483 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9484 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 9485 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9486 9487 /* Bits 4..0 : Pin number */ 9488 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 9489 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 9490 9491 /* Register: UART_PSEL_RXD */ 9492 /* Description: Pin select for RXD */ 9493 9494 /* Bit 31 : Connection */ 9495 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9496 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9497 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 9498 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9499 9500 /* Bits 4..0 : Pin number */ 9501 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 9502 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 9503 9504 /* Register: UART_RXD */ 9505 /* Description: RXD register */ 9506 9507 /* Bits 7..0 : RX data received in previous transfers, double buffered */ 9508 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 9509 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 9510 9511 /* Register: UART_TXD */ 9512 /* Description: TXD register */ 9513 9514 /* Bits 7..0 : TX data to be transferred */ 9515 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 9516 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 9517 9518 /* Register: UART_BAUDRATE */ 9519 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 9520 9521 /* Bits 31..0 : Baud rate */ 9522 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 9523 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 9524 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 9525 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 9526 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 9527 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 9528 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ 9529 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 9530 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ 9531 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 9532 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ 9533 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 9534 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ 9535 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 9536 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ 9537 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ 9538 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 9539 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ 9540 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ 9541 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ 9542 9543 /* Register: UART_CONFIG */ 9544 /* Description: Configuration of parity and hardware flow control */ 9545 9546 /* Bit 4 : Stop bits */ 9547 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 9548 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 9549 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ 9550 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 9551 9552 /* Bits 3..1 : Parity */ 9553 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 9554 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 9555 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 9556 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ 9557 9558 /* Bit 0 : Hardware flow control */ 9559 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 9560 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 9561 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 9562 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 9563 9564 9565 /* Peripheral: UARTE */ 9566 /* Description: UART with EasyDMA */ 9567 9568 /* Register: UARTE_TASKS_STARTRX */ 9569 /* Description: Start UART receiver */ 9570 9571 /* Bit 0 : Start UART receiver */ 9572 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 9573 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 9574 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ 9575 9576 /* Register: UARTE_TASKS_STOPRX */ 9577 /* Description: Stop UART receiver */ 9578 9579 /* Bit 0 : Stop UART receiver */ 9580 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ 9581 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ 9582 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ 9583 9584 /* Register: UARTE_TASKS_STARTTX */ 9585 /* Description: Start UART transmitter */ 9586 9587 /* Bit 0 : Start UART transmitter */ 9588 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 9589 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 9590 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ 9591 9592 /* Register: UARTE_TASKS_STOPTX */ 9593 /* Description: Stop UART transmitter */ 9594 9595 /* Bit 0 : Stop UART transmitter */ 9596 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ 9597 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ 9598 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ 9599 9600 /* Register: UARTE_TASKS_FLUSHRX */ 9601 /* Description: Flush RX FIFO into RX buffer */ 9602 9603 /* Bit 0 : Flush RX FIFO into RX buffer */ 9604 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ 9605 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ 9606 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ 9607 9608 /* Register: UARTE_EVENTS_CTS */ 9609 /* Description: CTS is activated (set low). Clear To Send. */ 9610 9611 /* Bit 0 : CTS is activated (set low). Clear To Send. */ 9612 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ 9613 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ 9614 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ 9615 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ 9616 9617 /* Register: UARTE_EVENTS_NCTS */ 9618 /* Description: CTS is deactivated (set high). Not Clear To Send. */ 9619 9620 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ 9621 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ 9622 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ 9623 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ 9624 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ 9625 9626 /* Register: UARTE_EVENTS_RXDRDY */ 9627 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ 9628 9629 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ 9630 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ 9631 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ 9632 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ 9633 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ 9634 9635 /* Register: UARTE_EVENTS_ENDRX */ 9636 /* Description: Receive buffer is filled up */ 9637 9638 /* Bit 0 : Receive buffer is filled up */ 9639 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 9640 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 9641 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ 9642 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ 9643 9644 /* Register: UARTE_EVENTS_TXDRDY */ 9645 /* Description: Data sent from TXD */ 9646 9647 /* Bit 0 : Data sent from TXD */ 9648 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ 9649 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ 9650 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ 9651 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ 9652 9653 /* Register: UARTE_EVENTS_ENDTX */ 9654 /* Description: Last TX byte transmitted */ 9655 9656 /* Bit 0 : Last TX byte transmitted */ 9657 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 9658 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 9659 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ 9660 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ 9661 9662 /* Register: UARTE_EVENTS_ERROR */ 9663 /* Description: Error detected */ 9664 9665 /* Bit 0 : Error detected */ 9666 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 9667 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 9668 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 9669 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 9670 9671 /* Register: UARTE_EVENTS_RXTO */ 9672 /* Description: Receiver timeout */ 9673 9674 /* Bit 0 : Receiver timeout */ 9675 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ 9676 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ 9677 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ 9678 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ 9679 9680 /* Register: UARTE_EVENTS_RXSTARTED */ 9681 /* Description: UART receiver has started */ 9682 9683 /* Bit 0 : UART receiver has started */ 9684 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 9685 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 9686 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 9687 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ 9688 9689 /* Register: UARTE_EVENTS_TXSTARTED */ 9690 /* Description: UART transmitter has started */ 9691 9692 /* Bit 0 : UART transmitter has started */ 9693 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 9694 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 9695 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ 9696 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ 9697 9698 /* Register: UARTE_EVENTS_TXSTOPPED */ 9699 /* Description: Transmitter stopped */ 9700 9701 /* Bit 0 : Transmitter stopped */ 9702 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ 9703 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ 9704 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ 9705 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ 9706 9707 /* Register: UARTE_SHORTS */ 9708 /* Description: Shortcuts between local events and tasks */ 9709 9710 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */ 9711 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 9712 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 9713 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 9714 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 9715 9716 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */ 9717 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 9718 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 9719 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 9720 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 9721 9722 /* Register: UARTE_INTEN */ 9723 /* Description: Enable or disable interrupt */ 9724 9725 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ 9726 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9727 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9728 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ 9729 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ 9730 9731 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 9732 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9733 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9734 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 9735 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 9736 9737 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 9738 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9739 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9740 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 9741 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 9742 9743 /* Bit 17 : Enable or disable interrupt for event RXTO */ 9744 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9745 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9746 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ 9747 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ 9748 9749 /* Bit 9 : Enable or disable interrupt for event ERROR */ 9750 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9751 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9752 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 9753 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 9754 9755 /* Bit 8 : Enable or disable interrupt for event ENDTX */ 9756 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9757 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9758 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ 9759 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ 9760 9761 /* Bit 7 : Enable or disable interrupt for event TXDRDY */ 9762 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9763 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9764 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ 9765 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ 9766 9767 /* Bit 4 : Enable or disable interrupt for event ENDRX */ 9768 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9769 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9770 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ 9771 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ 9772 9773 /* Bit 2 : Enable or disable interrupt for event RXDRDY */ 9774 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9775 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9776 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ 9777 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ 9778 9779 /* Bit 1 : Enable or disable interrupt for event NCTS */ 9780 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9781 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9782 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ 9783 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ 9784 9785 /* Bit 0 : Enable or disable interrupt for event CTS */ 9786 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ 9787 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ 9788 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ 9789 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ 9790 9791 /* Register: UARTE_INTENSET */ 9792 /* Description: Enable interrupt */ 9793 9794 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ 9795 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9796 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9797 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 9798 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 9799 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ 9800 9801 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 9802 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9803 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9804 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9805 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9806 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 9807 9808 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 9809 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9810 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9811 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9812 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9813 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9814 9815 /* Bit 17 : Write '1' to enable interrupt for event RXTO */ 9816 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9817 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9818 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9819 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9820 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ 9821 9822 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 9823 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9824 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9825 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9826 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9827 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9828 9829 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 9830 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9831 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9832 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 9833 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 9834 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 9835 9836 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ 9837 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9838 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9839 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9840 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9841 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 9842 9843 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 9844 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9845 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9846 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 9847 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 9848 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 9849 9850 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ 9851 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9852 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9853 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9854 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9855 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 9856 9857 /* Bit 1 : Write '1' to enable interrupt for event NCTS */ 9858 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9859 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9860 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9861 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9862 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ 9863 9864 /* Bit 0 : Write '1' to enable interrupt for event CTS */ 9865 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 9866 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 9867 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 9868 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 9869 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ 9870 9871 /* Register: UARTE_INTENCLR */ 9872 /* Description: Disable interrupt */ 9873 9874 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ 9875 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9876 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9877 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 9878 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 9879 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ 9880 9881 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 9882 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9883 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9884 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9885 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9886 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9887 9888 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 9889 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9890 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9891 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9892 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9893 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9894 9895 /* Bit 17 : Write '1' to disable interrupt for event RXTO */ 9896 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9897 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9898 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9899 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9900 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 9901 9902 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 9903 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9904 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9905 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9906 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9907 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9908 9909 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 9910 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9911 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9912 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 9913 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 9914 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 9915 9916 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ 9917 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9918 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9919 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9920 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9921 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ 9922 9923 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 9924 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9925 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9926 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 9927 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 9928 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 9929 9930 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ 9931 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9932 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9933 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9934 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9935 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ 9936 9937 /* Bit 1 : Write '1' to disable interrupt for event NCTS */ 9938 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9939 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9940 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9941 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9942 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 9943 9944 /* Bit 0 : Write '1' to disable interrupt for event CTS */ 9945 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 9946 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 9947 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 9948 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 9949 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 9950 9951 /* Register: UARTE_ERRORSRC */ 9952 /* Description: Error source This register is read/write one to clear. */ 9953 9954 /* Bit 3 : Break condition */ 9955 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 9956 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 9957 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 9958 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 9959 9960 /* Bit 2 : Framing error occurred */ 9961 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 9962 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 9963 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 9964 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 9965 9966 /* Bit 1 : Parity error */ 9967 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 9968 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 9969 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 9970 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 9971 9972 /* Bit 0 : Overrun error */ 9973 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 9974 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 9975 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 9976 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 9977 9978 /* Register: UARTE_ENABLE */ 9979 /* Description: Enable UART */ 9980 9981 /* Bits 3..0 : Enable or disable UARTE */ 9982 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9983 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9984 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ 9985 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ 9986 9987 /* Register: UARTE_PSEL_RTS */ 9988 /* Description: Pin select for RTS signal */ 9989 9990 /* Bit 31 : Connection */ 9991 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9992 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9993 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 9994 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9995 9996 /* Bits 4..0 : Pin number */ 9997 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 9998 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 9999 10000 /* Register: UARTE_PSEL_TXD */ 10001 /* Description: Pin select for TXD signal */ 10002 10003 /* Bit 31 : Connection */ 10004 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10005 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10006 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 10007 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10008 10009 /* Bits 4..0 : Pin number */ 10010 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 10011 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 10012 10013 /* Register: UARTE_PSEL_CTS */ 10014 /* Description: Pin select for CTS signal */ 10015 10016 /* Bit 31 : Connection */ 10017 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10018 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10019 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 10020 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10021 10022 /* Bits 4..0 : Pin number */ 10023 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 10024 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 10025 10026 /* Register: UARTE_PSEL_RXD */ 10027 /* Description: Pin select for RXD signal */ 10028 10029 /* Bit 31 : Connection */ 10030 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10031 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10032 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 10033 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10034 10035 /* Bits 4..0 : Pin number */ 10036 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 10037 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 10038 10039 /* Register: UARTE_BAUDRATE */ 10040 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 10041 10042 /* Bits 31..0 : Baud rate */ 10043 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 10044 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 10045 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 10046 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 10047 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 10048 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 10049 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 10050 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 10051 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 10052 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 10053 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 10054 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 10055 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 10056 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 10057 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 10058 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 10059 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 10060 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 10061 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 10062 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ 10063 10064 /* Register: UARTE_RXD_PTR */ 10065 /* Description: Data pointer */ 10066 10067 /* Bits 31..0 : Data pointer */ 10068 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 10069 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 10070 10071 /* Register: UARTE_RXD_MAXCNT */ 10072 /* Description: Maximum number of bytes in receive buffer */ 10073 10074 /* Bits 9..0 : Maximum number of bytes in receive buffer */ 10075 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 10076 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 10077 10078 /* Register: UARTE_RXD_AMOUNT */ 10079 /* Description: Number of bytes transferred in the last transaction */ 10080 10081 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 10082 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 10083 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 10084 10085 /* Register: UARTE_TXD_PTR */ 10086 /* Description: Data pointer */ 10087 10088 /* Bits 31..0 : Data pointer */ 10089 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 10090 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 10091 10092 /* Register: UARTE_TXD_MAXCNT */ 10093 /* Description: Maximum number of bytes in transmit buffer */ 10094 10095 /* Bits 9..0 : Maximum number of bytes in transmit buffer */ 10096 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 10097 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 10098 10099 /* Register: UARTE_TXD_AMOUNT */ 10100 /* Description: Number of bytes transferred in the last transaction */ 10101 10102 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 10103 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 10104 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 10105 10106 /* Register: UARTE_CONFIG */ 10107 /* Description: Configuration of parity and hardware flow control */ 10108 10109 /* Bit 4 : Stop bits */ 10110 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 10111 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 10112 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ 10113 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 10114 10115 /* Bits 3..1 : Parity */ 10116 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 10117 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 10118 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 10119 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ 10120 10121 /* Bit 0 : Hardware flow control */ 10122 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 10123 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 10124 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 10125 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 10126 10127 10128 /* Peripheral: UICR */ 10129 /* Description: User information configuration registers */ 10130 10131 /* Register: UICR_NRFFW */ 10132 /* Description: Description collection: Reserved for Nordic firmware design */ 10133 10134 /* Bits 31..0 : Reserved for Nordic firmware design */ 10135 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ 10136 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ 10137 10138 /* Register: UICR_NRFHW */ 10139 /* Description: Description collection: Reserved for Nordic hardware design */ 10140 10141 /* Bits 31..0 : Reserved for Nordic hardware design */ 10142 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ 10143 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ 10144 10145 /* Register: UICR_CUSTOMER */ 10146 /* Description: Description collection: Reserved for customer */ 10147 10148 /* Bits 31..0 : Reserved for customer */ 10149 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ 10150 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ 10151 10152 /* Register: UICR_NRFMDK */ 10153 /* Description: Description collection: Reserved for Nordic MDK */ 10154 10155 /* Bits 31..0 : Reserved for Nordic MDK */ 10156 #define UICR_NRFMDK_NRFMDK_Pos (0UL) /*!< Position of NRFMDK field. */ 10157 #define UICR_NRFMDK_NRFMDK_Msk (0xFFFFFFFFUL << UICR_NRFMDK_NRFMDK_Pos) /*!< Bit mask of NRFMDK field. */ 10158 10159 /* Register: UICR_PSELRESET */ 10160 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ 10161 10162 /* Bit 31 : Connection */ 10163 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10164 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10165 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ 10166 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10167 10168 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ 10169 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ 10170 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ 10171 10172 /* Register: UICR_APPROTECT */ 10173 /* Description: Access port protection */ 10174 10175 /* Bits 7..0 : Enable or disable access port protection. */ 10176 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 10177 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 10178 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ 10179 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ 10180 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ 10181 10182 10183 /* Peripheral: WDT */ 10184 /* Description: Watchdog Timer */ 10185 10186 /* Register: WDT_TASKS_START */ 10187 /* Description: Start the watchdog */ 10188 10189 /* Bit 0 : Start the watchdog */ 10190 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 10191 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 10192 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 10193 10194 /* Register: WDT_EVENTS_TIMEOUT */ 10195 /* Description: Watchdog timeout */ 10196 10197 /* Bit 0 : Watchdog timeout */ 10198 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ 10199 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ 10200 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ 10201 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ 10202 10203 /* Register: WDT_INTENSET */ 10204 /* Description: Enable interrupt */ 10205 10206 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ 10207 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 10208 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 10209 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 10210 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 10211 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ 10212 10213 /* Register: WDT_INTENCLR */ 10214 /* Description: Disable interrupt */ 10215 10216 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ 10217 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 10218 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 10219 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 10220 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 10221 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ 10222 10223 /* Register: WDT_RUNSTATUS */ 10224 /* Description: Run status */ 10225 10226 /* Bit 0 : Indicates whether or not the watchdog is running */ 10227 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 10228 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 10229 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ 10230 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ 10231 10232 /* Register: WDT_REQSTATUS */ 10233 /* Description: Request status */ 10234 10235 /* Bit 7 : Request status for RR[7] register */ 10236 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 10237 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 10238 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ 10239 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ 10240 10241 /* Bit 6 : Request status for RR[6] register */ 10242 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 10243 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 10244 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ 10245 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ 10246 10247 /* Bit 5 : Request status for RR[5] register */ 10248 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 10249 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 10250 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ 10251 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ 10252 10253 /* Bit 4 : Request status for RR[4] register */ 10254 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 10255 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 10256 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ 10257 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ 10258 10259 /* Bit 3 : Request status for RR[3] register */ 10260 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 10261 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 10262 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ 10263 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ 10264 10265 /* Bit 2 : Request status for RR[2] register */ 10266 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 10267 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 10268 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ 10269 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ 10270 10271 /* Bit 1 : Request status for RR[1] register */ 10272 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 10273 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 10274 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ 10275 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ 10276 10277 /* Bit 0 : Request status for RR[0] register */ 10278 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 10279 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 10280 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ 10281 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ 10282 10283 /* Register: WDT_CRV */ 10284 /* Description: Counter reload value */ 10285 10286 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ 10287 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ 10288 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ 10289 10290 /* Register: WDT_RREN */ 10291 /* Description: Enable register for reload request registers */ 10292 10293 /* Bit 7 : Enable or disable RR[7] register */ 10294 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 10295 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 10296 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ 10297 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ 10298 10299 /* Bit 6 : Enable or disable RR[6] register */ 10300 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 10301 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 10302 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ 10303 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ 10304 10305 /* Bit 5 : Enable or disable RR[5] register */ 10306 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 10307 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 10308 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ 10309 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ 10310 10311 /* Bit 4 : Enable or disable RR[4] register */ 10312 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 10313 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 10314 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ 10315 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ 10316 10317 /* Bit 3 : Enable or disable RR[3] register */ 10318 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 10319 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 10320 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ 10321 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ 10322 10323 /* Bit 2 : Enable or disable RR[2] register */ 10324 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 10325 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 10326 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ 10327 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ 10328 10329 /* Bit 1 : Enable or disable RR[1] register */ 10330 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 10331 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 10332 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ 10333 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ 10334 10335 /* Bit 0 : Enable or disable RR[0] register */ 10336 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 10337 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 10338 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ 10339 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ 10340 10341 /* Register: WDT_CONFIG */ 10342 /* Description: Configuration register */ 10343 10344 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ 10345 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 10346 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 10347 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ 10348 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ 10349 10350 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ 10351 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 10352 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 10353 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ 10354 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ 10355 10356 /* Register: WDT_RR */ 10357 /* Description: Description collection: Reload request n */ 10358 10359 /* Bits 31..0 : Reload request register */ 10360 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 10361 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 10362 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ 10363 10364 10365 /*lint --flb "Leave library region" */ 10366 #endif 10367
