1 /* 2 Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52805.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. April 2024 36 * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:01 37 * from File 'nrf52805.svd', 38 * last modified on Monday, 22.04.2024 13:20:06 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52805 49 * @{ 50 */ 51 52 53 #ifndef NRF52805_H 54 #define NRF52805_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52805 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 TWIM0_TWIS0_TWI0_IRQn = 3, /*!< 3 TWIM0_TWIS0_TWI0 */ 90 SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ 91 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 92 SAADC_IRQn = 7, /*!< 7 SAADC */ 93 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 94 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 95 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 96 RTC0_IRQn = 11, /*!< 11 RTC0 */ 97 TEMP_IRQn = 12, /*!< 12 TEMP */ 98 RNG_IRQn = 13, /*!< 13 RNG */ 99 ECB_IRQn = 14, /*!< 14 ECB */ 100 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 101 WDT_IRQn = 16, /*!< 16 WDT */ 102 RTC1_IRQn = 17, /*!< 17 RTC1 */ 103 QDEC_IRQn = 18, /*!< 18 QDEC */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_IRQn = 22, /*!< 22 SWI2 */ 107 SWI3_IRQn = 23, /*!< 23 SWI3 */ 108 SWI4_IRQn = 24, /*!< 24 SWI4 */ 109 SWI5_IRQn = 25 /*!< 25 SWI5 */ 110 } IRQn_Type; 111 112 113 114 /* =========================================================================================================================== */ 115 /* ================ Processor and Core Peripheral Section ================ */ 116 /* =========================================================================================================================== */ 117 118 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 119 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 120 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 121 #define __DSP_PRESENT 1 /*!< DSP present or not */ 122 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 123 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 124 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 125 #define __MPU_PRESENT 1 /*!< MPU present */ 126 #define __FPU_PRESENT 0 /*!< FPU present */ 127 128 129 /** @} */ /* End of group Configuration_of_CMSIS */ 130 131 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 132 #include "system_nrf52805.h" /*!< nrf52805 System */ 133 134 #ifndef __IM /*!< Fallback for older CMSIS versions */ 135 #define __IM __I 136 #endif 137 #ifndef __OM /*!< Fallback for older CMSIS versions */ 138 #define __OM __O 139 #endif 140 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 141 #define __IOM __IO 142 #endif 143 144 145 /* ======================================== Start of section using anonymous unions ======================================== */ 146 #if defined (__CC_ARM) 147 #pragma push 148 #pragma anon_unions 149 #elif defined (__ICCARM__) 150 #pragma language=extended 151 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 152 #pragma clang diagnostic push 153 #pragma clang diagnostic ignored "-Wc11-extensions" 154 #pragma clang diagnostic ignored "-Wreserved-id-macro" 155 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 156 #pragma clang diagnostic ignored "-Wnested-anon-types" 157 #elif defined (__GNUC__) 158 /* anonymous unions are enabled by default */ 159 #elif defined (__TMS470__) 160 /* anonymous unions are enabled by default */ 161 #elif defined (__TASKING__) 162 #pragma warning 586 163 #elif defined (__CSMC__) 164 /* anonymous unions are enabled by default */ 165 #else 166 #warning Not supported compiler type 167 #endif 168 169 170 /* =========================================================================================================================== */ 171 /* ================ Device Specific Cluster Section ================ */ 172 /* =========================================================================================================================== */ 173 174 175 /** @addtogroup Device_Peripheral_clusters 176 * @{ 177 */ 178 179 180 /** 181 * @brief FICR_INFO [INFO] (Device info) 182 */ 183 typedef struct { 184 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 185 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 186 configuration */ 187 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 188 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 189 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 190 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 191 192 193 /** 194 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 195 */ 196 typedef struct { 197 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 198 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 199 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 200 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 201 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 202 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 203 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 204 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 205 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 206 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 207 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 208 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 209 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 210 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 211 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 212 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 213 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 214 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 215 216 217 /** 218 * @brief POWER_RAM [RAM] (Unspecified) 219 */ 220 typedef struct { 221 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. 222 The RAM size will vary depending on product 223 variant, and the RAMn register will only 224 be present if the corresponding RAM AHB 225 slave is present on the device. */ 226 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 227 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 228 register */ 229 __IM uint32_t RESERVED; 230 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 231 232 233 /** 234 * @brief UART_PSEL [PSEL] (Unspecified) 235 */ 236 typedef struct { 237 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 238 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 239 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 240 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 241 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 242 243 244 /** 245 * @brief UARTE_PSEL [PSEL] (Unspecified) 246 */ 247 typedef struct { 248 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 249 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 250 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 251 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 252 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 253 254 255 /** 256 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 257 */ 258 typedef struct { 259 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 260 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 261 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 262 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 263 264 265 /** 266 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 267 */ 268 typedef struct { 269 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 270 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 271 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 272 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 273 274 275 /** 276 * @brief TWI_PSEL [PSEL] (Unspecified) 277 */ 278 typedef struct { 279 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 280 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 281 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 282 283 284 /** 285 * @brief TWIM_PSEL [PSEL] (Unspecified) 286 */ 287 typedef struct { 288 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 289 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 290 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 291 292 293 /** 294 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 295 */ 296 typedef struct { 297 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 298 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 299 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 300 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 301 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 302 303 304 /** 305 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 306 */ 307 typedef struct { 308 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 309 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 310 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 311 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 312 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 313 314 315 /** 316 * @brief TWIS_PSEL [PSEL] (Unspecified) 317 */ 318 typedef struct { 319 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 320 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 321 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 322 323 324 /** 325 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 326 */ 327 typedef struct { 328 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 329 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 330 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 331 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 332 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 333 334 335 /** 336 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 337 */ 338 typedef struct { 339 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 340 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 341 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 342 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 343 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 344 345 346 /** 347 * @brief SPI_PSEL [PSEL] (Unspecified) 348 */ 349 typedef struct { 350 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 351 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 352 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 353 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 354 355 356 /** 357 * @brief SPIM_PSEL [PSEL] (Unspecified) 358 */ 359 typedef struct { 360 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 361 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 362 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 363 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 364 365 366 /** 367 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 368 */ 369 typedef struct { 370 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 371 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 372 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 373 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 374 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 375 376 377 /** 378 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 379 */ 380 typedef struct { 381 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 382 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 383 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 384 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 385 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 386 387 388 /** 389 * @brief SPIS_PSEL [PSEL] (Unspecified) 390 */ 391 typedef struct { 392 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 393 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 394 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 395 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 396 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 397 398 399 /** 400 * @brief SPIS_RXD [RXD] (Unspecified) 401 */ 402 typedef struct { 403 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 404 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 405 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 406 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 407 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 408 409 410 /** 411 * @brief SPIS_TXD [TXD] (Unspecified) 412 */ 413 typedef struct { 414 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 415 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 416 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 417 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 418 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 419 420 421 /** 422 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 423 */ 424 typedef struct { 425 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 426 above CH[n].LIMIT.HIGH */ 427 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 428 below CH[n].LIMIT.LOW */ 429 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 430 431 432 /** 433 * @brief SAADC_CH [CH] (Unspecified) 434 */ 435 typedef struct { 436 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 437 for CH[n] */ 438 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 439 for CH[n] */ 440 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 441 CH[n] */ 442 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 443 monitoring a channel */ 444 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 445 446 447 /** 448 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 449 */ 450 typedef struct { 451 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 452 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 453 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 454 START */ 455 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 456 457 458 /** 459 * @brief QDEC_PSEL [PSEL] (Unspecified) 460 */ 461 typedef struct { 462 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 463 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 464 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 465 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 466 467 468 /** 469 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 470 */ 471 typedef struct { 472 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 473 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 474 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 475 476 477 /** 478 * @brief PPI_CH [CH] (PPI Channel) 479 */ 480 typedef struct { 481 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 482 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 483 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 484 485 486 /** 487 * @brief PPI_FORK [FORK] (Fork) 488 */ 489 typedef struct { 490 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 491 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 492 493 494 /** @} */ /* End of group Device_Peripheral_clusters */ 495 496 497 /* =========================================================================================================================== */ 498 /* ================ Device Specific Peripheral Section ================ */ 499 /* =========================================================================================================================== */ 500 501 502 /** @addtogroup Device_Peripheral_peripherals 503 * @{ 504 */ 505 506 507 508 /* =========================================================================================================================== */ 509 /* ================ FICR ================ */ 510 /* =========================================================================================================================== */ 511 512 513 /** 514 * @brief Factory information configuration registers (FICR) 515 */ 516 517 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 518 __IM uint32_t RESERVED[4]; 519 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 520 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 521 __IM uint32_t RESERVED1[18]; 522 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 523 __IM uint32_t RESERVED2[6]; 524 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 525 n */ 526 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ 527 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 528 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 529 __IM uint32_t RESERVED3[21]; 530 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 531 __IM uint32_t RESERVED4[188]; 532 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 533 coefficients */ 534 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 535 536 537 538 /* =========================================================================================================================== */ 539 /* ================ UICR ================ */ 540 /* =========================================================================================================================== */ 541 542 543 /** 544 * @brief User information configuration registers (UICR) 545 */ 546 547 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 548 __IM uint32_t RESERVED[5]; 549 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 550 design */ 551 __IM uint32_t RESERVED1[2]; 552 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 553 design */ 554 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 555 __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ 556 __IM uint32_t RESERVED2[56]; 557 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 558 function (see POWER chapter for details) */ 559 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 560 } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 561 562 563 564 /* =========================================================================================================================== */ 565 /* ================ BPROT ================ */ 566 /* =========================================================================================================================== */ 567 568 569 /** 570 * @brief Block Protect (BPROT) 571 */ 572 573 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 574 __IM uint32_t RESERVED[384]; 575 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 576 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 577 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 578 } NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ 579 580 581 582 /* =========================================================================================================================== */ 583 /* ================ APPROTECT ================ */ 584 /* =========================================================================================================================== */ 585 586 587 /** 588 * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) 589 */ 590 591 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 592 __IM uint32_t RESERVED[340]; 593 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 594 next reset. */ 595 __IM uint32_t RESERVED1; 596 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 597 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 598 599 600 601 /* =========================================================================================================================== */ 602 /* ================ CLOCK ================ */ 603 /* =========================================================================================================================== */ 604 605 606 /** 607 * @brief Clock control (CLOCK) 608 */ 609 610 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 611 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 612 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 613 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 614 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 615 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 616 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 617 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 618 __IM uint32_t RESERVED[57]; 619 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 620 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 621 __IM uint32_t RESERVED1; 622 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 623 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 624 __IM uint32_t RESERVED2[124]; 625 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 626 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 627 __IM uint32_t RESERVED3[63]; 628 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 629 triggered */ 630 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 631 __IM uint32_t RESERVED4; 632 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 633 triggered */ 634 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 635 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 636 task was triggered */ 637 __IM uint32_t RESERVED5[62]; 638 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 639 __IM uint32_t RESERVED6[7]; 640 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 641 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 642 643 644 645 /* =========================================================================================================================== */ 646 /* ================ POWER ================ */ 647 /* =========================================================================================================================== */ 648 649 650 /** 651 * @brief Power control (POWER) 652 */ 653 654 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 655 __IM uint32_t RESERVED[30]; 656 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 657 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 658 __IM uint32_t RESERVED1[34]; 659 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 660 __IM uint32_t RESERVED2[2]; 661 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 662 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 663 __IM uint32_t RESERVED3[122]; 664 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 665 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 666 __IM uint32_t RESERVED4[61]; 667 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 668 __IM uint32_t RESERVED5[63]; 669 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 670 __IM uint32_t RESERVED6[3]; 671 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 672 __IM uint32_t RESERVED7[2]; 673 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 674 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 675 __IM uint32_t RESERVED8[21]; 676 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 677 __IM uint32_t RESERVED9[225]; 678 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 679 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 680 681 682 683 /* =========================================================================================================================== */ 684 /* ================ P0 ================ */ 685 /* =========================================================================================================================== */ 686 687 688 /** 689 * @brief GPIO Port (P0) 690 */ 691 692 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 693 __IM uint32_t RESERVED[321]; 694 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 695 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 696 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 697 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 698 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 699 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 700 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 701 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 702 have met the criteria set in the PIN_CNF[n].SENSE 703 registers */ 704 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 705 and LDETECT mode */ 706 __IM uint32_t RESERVED1[118]; 707 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 708 pins */ 709 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 710 711 712 713 /* =========================================================================================================================== */ 714 /* ================ RADIO ================ */ 715 /* =========================================================================================================================== */ 716 717 718 /** 719 * @brief 2.4 GHz radio (RADIO) 720 */ 721 722 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 723 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 724 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 725 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 726 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 727 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 728 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 729 the receive signal strength */ 730 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 731 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 732 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 733 __IM uint32_t RESERVED[55]; 734 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 735 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 736 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 737 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 738 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 739 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 740 packet */ 741 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 742 received packet */ 743 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 744 __IM uint32_t RESERVED1[2]; 745 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 746 __IM uint32_t RESERVED2; 747 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 748 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 749 __IM uint32_t RESERVED3[7]; 750 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 751 TX path */ 752 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 753 RX path */ 754 __IM uint32_t RESERVED4[4]; 755 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 756 from air */ 757 __IM uint32_t RESERVED5[36]; 758 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 759 __IM uint32_t RESERVED6[64]; 760 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 761 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 762 __IM uint32_t RESERVED7[61]; 763 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 764 __IM uint32_t RESERVED8; 765 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 766 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 767 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 768 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 769 __IM uint32_t RESERVED9[59]; 770 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 771 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 772 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 773 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 774 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 775 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 776 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 777 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 778 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 779 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 780 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 781 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 782 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 783 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 784 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 785 __IM uint32_t RESERVED10; 786 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 787 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 788 __IM uint32_t RESERVED11; 789 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 790 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 791 __IM uint32_t RESERVED12[2]; 792 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 793 __IM uint32_t RESERVED13[39]; 794 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 795 n */ 796 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 797 n */ 798 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 799 __IM uint32_t RESERVED14[3]; 800 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 801 __IM uint32_t RESERVED15[618]; 802 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 803 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 804 805 806 807 /* =========================================================================================================================== */ 808 /* ================ UART0 ================ */ 809 /* =========================================================================================================================== */ 810 811 812 /** 813 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 814 */ 815 816 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 817 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 818 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 819 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 820 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 821 __IM uint32_t RESERVED[3]; 822 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 823 __IM uint32_t RESERVED1[56]; 824 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 825 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 826 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 827 __IM uint32_t RESERVED2[4]; 828 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 829 __IM uint32_t RESERVED3; 830 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 831 __IM uint32_t RESERVED4[7]; 832 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 833 __IM uint32_t RESERVED5[46]; 834 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 835 __IM uint32_t RESERVED6[64]; 836 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 837 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 838 __IM uint32_t RESERVED7[93]; 839 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 840 __IM uint32_t RESERVED8[31]; 841 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 842 __IM uint32_t RESERVED9; 843 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 844 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 845 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 846 __IM uint32_t RESERVED10; 847 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 848 selected. */ 849 __IM uint32_t RESERVED11[17]; 850 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 851 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 852 853 854 855 /* =========================================================================================================================== */ 856 /* ================ UARTE0 ================ */ 857 /* =========================================================================================================================== */ 858 859 860 /** 861 * @brief UART with EasyDMA (UARTE0) 862 */ 863 864 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 865 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 866 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 867 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 868 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 869 __IM uint32_t RESERVED[7]; 870 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 871 __IM uint32_t RESERVED1[52]; 872 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 873 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 874 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 875 transferred to Data RAM) */ 876 __IM uint32_t RESERVED2; 877 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 878 __IM uint32_t RESERVED3[2]; 879 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 880 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 881 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 882 __IM uint32_t RESERVED4[7]; 883 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 884 __IM uint32_t RESERVED5; 885 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 886 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 887 __IM uint32_t RESERVED6; 888 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 889 __IM uint32_t RESERVED7[41]; 890 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 891 __IM uint32_t RESERVED8[63]; 892 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 893 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 894 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 895 __IM uint32_t RESERVED9[93]; 896 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 897 to clear. */ 898 __IM uint32_t RESERVED10[31]; 899 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 900 __IM uint32_t RESERVED11; 901 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 902 __IM uint32_t RESERVED12[3]; 903 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 904 selected. */ 905 __IM uint32_t RESERVED13[3]; 906 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 907 __IM uint32_t RESERVED14; 908 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 909 __IM uint32_t RESERVED15[7]; 910 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 911 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 912 913 914 915 /* =========================================================================================================================== */ 916 /* ================ TWI0 ================ */ 917 /* =========================================================================================================================== */ 918 919 920 /** 921 * @brief I2C compatible Two-Wire Interface (TWI0) 922 */ 923 924 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 925 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 926 __IM uint32_t RESERVED; 927 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 928 __IM uint32_t RESERVED1[2]; 929 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 930 __IM uint32_t RESERVED2; 931 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 932 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 933 __IM uint32_t RESERVED3[56]; 934 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 935 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 936 __IM uint32_t RESERVED4[4]; 937 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 938 __IM uint32_t RESERVED5; 939 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 940 __IM uint32_t RESERVED6[4]; 941 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 942 that is sent or received */ 943 __IM uint32_t RESERVED7[3]; 944 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 945 __IM uint32_t RESERVED8[45]; 946 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 947 __IM uint32_t RESERVED9[64]; 948 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 949 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 950 __IM uint32_t RESERVED10[110]; 951 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 952 __IM uint32_t RESERVED11[14]; 953 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 954 __IM uint32_t RESERVED12; 955 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 956 __IM uint32_t RESERVED13[2]; 957 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 958 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 959 __IM uint32_t RESERVED14; 960 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 961 source selected. */ 962 __IM uint32_t RESERVED15[24]; 963 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 964 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 965 966 967 968 /* =========================================================================================================================== */ 969 /* ================ TWIM0 ================ */ 970 /* =========================================================================================================================== */ 971 972 973 /** 974 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 975 */ 976 977 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 978 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 979 __IM uint32_t RESERVED; 980 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 981 __IM uint32_t RESERVED1[2]; 982 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 983 TWI master is not suspended. */ 984 __IM uint32_t RESERVED2; 985 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 986 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 987 __IM uint32_t RESERVED3[56]; 988 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 989 __IM uint32_t RESERVED4[7]; 990 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 991 __IM uint32_t RESERVED5[8]; 992 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 993 now suspended. */ 994 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 995 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 996 __IM uint32_t RESERVED6[2]; 997 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 998 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 999 byte */ 1000 __IM uint32_t RESERVED7[39]; 1001 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1002 __IM uint32_t RESERVED8[63]; 1003 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1004 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1005 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1006 __IM uint32_t RESERVED9[110]; 1007 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1008 __IM uint32_t RESERVED10[14]; 1009 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1010 __IM uint32_t RESERVED11; 1011 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1012 __IM uint32_t RESERVED12[5]; 1013 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1014 source selected. */ 1015 __IM uint32_t RESERVED13[3]; 1016 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1017 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1018 __IM uint32_t RESERVED14[13]; 1019 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1020 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1021 1022 1023 1024 /* =========================================================================================================================== */ 1025 /* ================ TWIS0 ================ */ 1026 /* =========================================================================================================================== */ 1027 1028 1029 /** 1030 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 1031 */ 1032 1033 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1034 __IM uint32_t RESERVED[5]; 1035 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1036 __IM uint32_t RESERVED1; 1037 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1038 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1039 __IM uint32_t RESERVED2[3]; 1040 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1041 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1042 __IM uint32_t RESERVED3[51]; 1043 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1044 __IM uint32_t RESERVED4[7]; 1045 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1046 __IM uint32_t RESERVED5[9]; 1047 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1048 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1049 __IM uint32_t RESERVED6[4]; 1050 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1051 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1052 __IM uint32_t RESERVED7[37]; 1053 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1054 __IM uint32_t RESERVED8[63]; 1055 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1056 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1057 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1058 __IM uint32_t RESERVED9[113]; 1059 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1060 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1061 a match */ 1062 __IM uint32_t RESERVED10[10]; 1063 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1064 __IM uint32_t RESERVED11; 1065 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1066 __IM uint32_t RESERVED12[9]; 1067 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1068 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1069 __IM uint32_t RESERVED13[13]; 1070 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1071 __IM uint32_t RESERVED14; 1072 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1073 mechanism */ 1074 __IM uint32_t RESERVED15[10]; 1075 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1076 of an over-read of the transmit buffer. */ 1077 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1078 1079 1080 1081 /* =========================================================================================================================== */ 1082 /* ================ SPI0 ================ */ 1083 /* =========================================================================================================================== */ 1084 1085 1086 /** 1087 * @brief Serial Peripheral Interface (SPI0) 1088 */ 1089 1090 typedef struct { /*!< (@ 0x40004000) SPI0 Structure */ 1091 __IM uint32_t RESERVED[66]; 1092 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1093 __IM uint32_t RESERVED1[126]; 1094 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1095 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1096 __IM uint32_t RESERVED2[125]; 1097 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1098 __IM uint32_t RESERVED3; 1099 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1100 __IM uint32_t RESERVED4; 1101 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1102 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1103 __IM uint32_t RESERVED5; 1104 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1105 source selected. */ 1106 __IM uint32_t RESERVED6[11]; 1107 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1108 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1109 1110 1111 1112 /* =========================================================================================================================== */ 1113 /* ================ SPIM0 ================ */ 1114 /* =========================================================================================================================== */ 1115 1116 1117 /** 1118 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) 1119 */ 1120 1121 typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ 1122 __IM uint32_t RESERVED[4]; 1123 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1124 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1125 __IM uint32_t RESERVED1; 1126 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1127 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1128 __IM uint32_t RESERVED2[56]; 1129 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1130 __IM uint32_t RESERVED3[2]; 1131 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1132 __IM uint32_t RESERVED4; 1133 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1134 __IM uint32_t RESERVED5; 1135 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1136 __IM uint32_t RESERVED6[10]; 1137 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1138 __IM uint32_t RESERVED7[44]; 1139 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1140 __IM uint32_t RESERVED8[64]; 1141 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1142 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1143 __IM uint32_t RESERVED9[125]; 1144 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1145 __IM uint32_t RESERVED10; 1146 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1147 __IM uint32_t RESERVED11[4]; 1148 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1149 source selected. */ 1150 __IM uint32_t RESERVED12[3]; 1151 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1152 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1153 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1154 __IM uint32_t RESERVED13[26]; 1155 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1156 case and over-read of the TXD buffer. */ 1157 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1158 1159 1160 1161 /* =========================================================================================================================== */ 1162 /* ================ SPIS0 ================ */ 1163 /* =========================================================================================================================== */ 1164 1165 1166 /** 1167 * @brief SPI Slave (SPIS0) 1168 */ 1169 1170 typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ 1171 __IM uint32_t RESERVED[9]; 1172 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1173 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1174 to acquire it */ 1175 __IM uint32_t RESERVED1[54]; 1176 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1177 __IM uint32_t RESERVED2[2]; 1178 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1179 __IM uint32_t RESERVED3[5]; 1180 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1181 __IM uint32_t RESERVED4[53]; 1182 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1183 __IM uint32_t RESERVED5[64]; 1184 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1185 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1186 __IM uint32_t RESERVED6[61]; 1187 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1188 __IM uint32_t RESERVED7[15]; 1189 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1190 __IM uint32_t RESERVED8[47]; 1191 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1192 __IM uint32_t RESERVED9; 1193 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1194 __IM uint32_t RESERVED10[7]; 1195 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1196 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1197 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1198 __IM uint32_t RESERVED11; 1199 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1200 of an ignored transaction. */ 1201 __IM uint32_t RESERVED12[24]; 1202 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1203 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1204 1205 1206 1207 /* =========================================================================================================================== */ 1208 /* ================ GPIOTE ================ */ 1209 /* =========================================================================================================================== */ 1210 1211 1212 /** 1213 * @brief GPIO Tasks and Events (GPIOTE) 1214 */ 1215 1216 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1217 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1218 specified in CONFIG[n].PSEL. Action on pin 1219 is configured in CONFIG[n].POLARITY. */ 1220 __IM uint32_t RESERVED[4]; 1221 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1222 specified in CONFIG[n].PSEL. Action on pin 1223 is to set it high. */ 1224 __IM uint32_t RESERVED1[4]; 1225 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1226 specified in CONFIG[n].PSEL. Action on pin 1227 is to set it low. */ 1228 __IM uint32_t RESERVED2[32]; 1229 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1230 pin specified in CONFIG[n].PSEL */ 1231 __IM uint32_t RESERVED3[23]; 1232 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1233 with SENSE mechanism enabled */ 1234 __IM uint32_t RESERVED4[97]; 1235 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1236 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1237 __IM uint32_t RESERVED5[129]; 1238 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1239 SET[n], and CLR[n] tasks and IN[n] event */ 1240 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1241 1242 1243 1244 /* =========================================================================================================================== */ 1245 /* ================ SAADC ================ */ 1246 /* =========================================================================================================================== */ 1247 1248 1249 /** 1250 * @brief Analog to Digital Converter (SAADC) 1251 */ 1252 1253 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1254 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1255 RAM */ 1256 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1257 are sampled */ 1258 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1259 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1260 __IM uint32_t RESERVED[60]; 1261 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1262 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1263 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1264 on the mode, multiple conversions might 1265 be needed for a result to be transferred 1266 to RAM. */ 1267 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1268 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1269 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1270 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1271 __IM uint32_t RESERVED1[106]; 1272 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1273 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1274 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1275 __IM uint32_t RESERVED2[61]; 1276 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1277 __IM uint32_t RESERVED3[63]; 1278 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1279 __IM uint32_t RESERVED4[3]; 1280 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1281 __IM uint32_t RESERVED5[24]; 1282 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1283 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1284 not be combined with SCAN. The RESOLUTION 1285 is applied before averaging, thus for high 1286 OVERSAMPLE a higher RESOLUTION should be 1287 used. */ 1288 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1289 __IM uint32_t RESERVED6[12]; 1290 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1291 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1292 1293 1294 1295 /* =========================================================================================================================== */ 1296 /* ================ TIMER0 ================ */ 1297 /* =========================================================================================================================== */ 1298 1299 1300 /** 1301 * @brief Timer/Counter 0 (TIMER0) 1302 */ 1303 1304 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1305 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1306 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1307 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1308 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1309 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1310 __IM uint32_t RESERVED[11]; 1311 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1312 CC[n] register */ 1313 __IM uint32_t RESERVED1[58]; 1314 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1315 match */ 1316 __IM uint32_t RESERVED2[42]; 1317 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1318 __IM uint32_t RESERVED3[64]; 1319 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1320 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1321 __IM uint32_t RESERVED4[126]; 1322 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1323 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1324 __IM uint32_t RESERVED5; 1325 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1326 __IM uint32_t RESERVED6[11]; 1327 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1328 n */ 1329 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1330 1331 1332 1333 /* =========================================================================================================================== */ 1334 /* ================ RTC0 ================ */ 1335 /* =========================================================================================================================== */ 1336 1337 1338 /** 1339 * @brief Real time counter 0 (RTC0) 1340 */ 1341 1342 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1343 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1344 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1345 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1346 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1347 __IM uint32_t RESERVED[60]; 1348 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1349 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1350 __IM uint32_t RESERVED1[14]; 1351 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1352 match */ 1353 __IM uint32_t RESERVED2[109]; 1354 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1355 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1356 __IM uint32_t RESERVED3[13]; 1357 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1358 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1359 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1360 __IM uint32_t RESERVED4[110]; 1361 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1362 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1363 t be written when RTC is stopped */ 1364 __IM uint32_t RESERVED5[13]; 1365 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1366 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1367 1368 1369 1370 /* =========================================================================================================================== */ 1371 /* ================ TEMP ================ */ 1372 /* =========================================================================================================================== */ 1373 1374 1375 /** 1376 * @brief Temperature Sensor (TEMP) 1377 */ 1378 1379 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1380 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1381 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1382 __IM uint32_t RESERVED[62]; 1383 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1384 __IM uint32_t RESERVED1[128]; 1385 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1386 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1387 __IM uint32_t RESERVED2[127]; 1388 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1389 __IM uint32_t RESERVED3[5]; 1390 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1391 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1392 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1393 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1394 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1395 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1396 __IM uint32_t RESERVED4[2]; 1397 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1398 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1399 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1400 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1401 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1402 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1403 __IM uint32_t RESERVED5[2]; 1404 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1405 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1406 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1407 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1408 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1409 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1410 1411 1412 1413 /* =========================================================================================================================== */ 1414 /* ================ RNG ================ */ 1415 /* =========================================================================================================================== */ 1416 1417 1418 /** 1419 * @brief Random Number Generator (RNG) 1420 */ 1421 1422 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1423 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1424 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1425 __IM uint32_t RESERVED[62]; 1426 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1427 written to the VALUE register */ 1428 __IM uint32_t RESERVED1[63]; 1429 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1430 __IM uint32_t RESERVED2[64]; 1431 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1432 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1433 __IM uint32_t RESERVED3[126]; 1434 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1435 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1436 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1437 1438 1439 1440 /* =========================================================================================================================== */ 1441 /* ================ ECB ================ */ 1442 /* =========================================================================================================================== */ 1443 1444 1445 /** 1446 * @brief AES ECB Mode Encryption (ECB) 1447 */ 1448 1449 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1450 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1451 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1452 __IM uint32_t RESERVED[62]; 1453 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1454 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1455 task or due to an error */ 1456 __IM uint32_t RESERVED1[127]; 1457 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1458 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1459 __IM uint32_t RESERVED2[126]; 1460 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1461 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1462 1463 1464 1465 /* =========================================================================================================================== */ 1466 /* ================ AAR ================ */ 1467 /* =========================================================================================================================== */ 1468 1469 1470 /** 1471 * @brief Accelerated Address Resolver (AAR) 1472 */ 1473 1474 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1475 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1476 in the IRK data structure */ 1477 __IM uint32_t RESERVED; 1478 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1479 __IM uint32_t RESERVED1[61]; 1480 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1481 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1482 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1483 __IM uint32_t RESERVED2[126]; 1484 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1485 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1486 __IM uint32_t RESERVED3[61]; 1487 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1488 __IM uint32_t RESERVED4[63]; 1489 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1490 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1491 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1492 __IM uint32_t RESERVED5; 1493 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1494 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1495 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1496 1497 1498 1499 /* =========================================================================================================================== */ 1500 /* ================ CCM ================ */ 1501 /* =========================================================================================================================== */ 1502 1503 1504 /** 1505 * @brief AES CCM Mode Encryption (CCM) 1506 */ 1507 1508 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1509 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1510 will stop by itself when completed. */ 1511 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1512 stop by itself when completed. */ 1513 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1514 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1515 the contents of the RATEOVERRIDE register 1516 for any ongoing encryption/decryption */ 1517 __IM uint32_t RESERVED[60]; 1518 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1519 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1520 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1521 __IM uint32_t RESERVED1[61]; 1522 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1523 __IM uint32_t RESERVED2[64]; 1524 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1525 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1526 __IM uint32_t RESERVED3[61]; 1527 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1528 __IM uint32_t RESERVED4[63]; 1529 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1530 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1531 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1532 NONCE vector */ 1533 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1534 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1535 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1536 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1537 = Extended. */ 1538 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1539 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1540 1541 1542 1543 /* =========================================================================================================================== */ 1544 /* ================ WDT ================ */ 1545 /* =========================================================================================================================== */ 1546 1547 1548 /** 1549 * @brief Watchdog Timer (WDT) 1550 */ 1551 1552 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1553 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1554 __IM uint32_t RESERVED[63]; 1555 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1556 __IM uint32_t RESERVED1[128]; 1557 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1558 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1559 __IM uint32_t RESERVED2[61]; 1560 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1561 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1562 __IM uint32_t RESERVED3[63]; 1563 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1564 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1565 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1566 __IM uint32_t RESERVED4[60]; 1567 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1568 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1569 1570 1571 1572 /* =========================================================================================================================== */ 1573 /* ================ QDEC ================ */ 1574 /* =========================================================================================================================== */ 1575 1576 1577 /** 1578 * @brief Quadrature Decoder (QDEC) 1579 */ 1580 1581 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1582 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1583 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1584 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1585 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1586 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1587 __IM uint32_t RESERVED[59]; 1588 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1589 written to the SAMPLE register */ 1590 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1591 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1592 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1593 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1594 __IM uint32_t RESERVED1[59]; 1595 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1596 __IM uint32_t RESERVED2[64]; 1597 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1598 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1599 __IM uint32_t RESERVED3[125]; 1600 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1601 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1602 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1603 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1604 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1605 and DBLRDY events can be generated */ 1606 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1607 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1608 READCLRACC or RDCLRACC task */ 1609 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1610 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1611 __IM uint32_t RESERVED4[5]; 1612 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1613 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1614 double transitions */ 1615 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1616 or RDCLRDBL task */ 1617 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1618 1619 1620 1621 /* =========================================================================================================================== */ 1622 /* ================ EGU0 ================ */ 1623 /* =========================================================================================================================== */ 1624 1625 1626 /** 1627 * @brief Event generator unit 0 (EGU0) 1628 */ 1629 1630 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1631 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1632 the corresponding TRIGGERED[n] event */ 1633 __IM uint32_t RESERVED[48]; 1634 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1635 by triggering the corresponding TRIGGER[n] 1636 task */ 1637 __IM uint32_t RESERVED1[112]; 1638 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1639 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1640 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1641 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1642 1643 1644 1645 /* =========================================================================================================================== */ 1646 /* ================ SWI0 ================ */ 1647 /* =========================================================================================================================== */ 1648 1649 1650 /** 1651 * @brief Software interrupt 0 (SWI0) 1652 */ 1653 1654 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1655 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1656 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1657 1658 1659 1660 /* =========================================================================================================================== */ 1661 /* ================ NVMC ================ */ 1662 /* =========================================================================================================================== */ 1663 1664 1665 /** 1666 * @brief Non Volatile Memory Controller (NVMC) 1667 */ 1668 1669 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1670 __IM uint32_t RESERVED[256]; 1671 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1672 __IM uint32_t RESERVED1[64]; 1673 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1674 1675 union { 1676 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1677 __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1678 page in code area, equivalent to ERASEPAGE */ 1679 }; 1680 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1681 __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1682 page in code area, equivalent to ERASEPAGE */ 1683 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1684 registers */ 1685 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1686 area */ 1687 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1688 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1689 1690 1691 1692 /* =========================================================================================================================== */ 1693 /* ================ PPI ================ */ 1694 /* =========================================================================================================================== */ 1695 1696 1697 /** 1698 * @brief Programmable Peripheral Interconnect (PPI) 1699 */ 1700 1701 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1702 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1703 __IM uint32_t RESERVED[308]; 1704 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1705 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1706 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1707 __IM uint32_t RESERVED1; 1708 __IOM PPI_CH_Type CH[10]; /*!< (@ 0x00000510) PPI Channel */ 1709 __IM uint32_t RESERVED2[168]; 1710 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 1711 __IM uint32_t RESERVED3[62]; 1712 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1713 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1714 1715 1716 /** @} */ /* End of group Device_Peripheral_peripherals */ 1717 1718 1719 /* =========================================================================================================================== */ 1720 /* ================ Device Specific Peripheral Address Map ================ */ 1721 /* =========================================================================================================================== */ 1722 1723 1724 /** @addtogroup Device_Peripheral_peripheralAddr 1725 * @{ 1726 */ 1727 1728 #define NRF_FICR_BASE 0x10000000UL 1729 #define NRF_UICR_BASE 0x10001000UL 1730 #define NRF_BPROT_BASE 0x40000000UL 1731 #define NRF_APPROTECT_BASE 0x40000000UL 1732 #define NRF_CLOCK_BASE 0x40000000UL 1733 #define NRF_POWER_BASE 0x40000000UL 1734 #define NRF_P0_BASE 0x50000000UL 1735 #define NRF_RADIO_BASE 0x40001000UL 1736 #define NRF_UART0_BASE 0x40002000UL 1737 #define NRF_UARTE0_BASE 0x40002000UL 1738 #define NRF_TWI0_BASE 0x40003000UL 1739 #define NRF_TWIM0_BASE 0x40003000UL 1740 #define NRF_TWIS0_BASE 0x40003000UL 1741 #define NRF_SPI0_BASE 0x40004000UL 1742 #define NRF_SPIM0_BASE 0x40004000UL 1743 #define NRF_SPIS0_BASE 0x40004000UL 1744 #define NRF_GPIOTE_BASE 0x40006000UL 1745 #define NRF_SAADC_BASE 0x40007000UL 1746 #define NRF_TIMER0_BASE 0x40008000UL 1747 #define NRF_TIMER1_BASE 0x40009000UL 1748 #define NRF_TIMER2_BASE 0x4000A000UL 1749 #define NRF_RTC0_BASE 0x4000B000UL 1750 #define NRF_TEMP_BASE 0x4000C000UL 1751 #define NRF_RNG_BASE 0x4000D000UL 1752 #define NRF_ECB_BASE 0x4000E000UL 1753 #define NRF_AAR_BASE 0x4000F000UL 1754 #define NRF_CCM_BASE 0x4000F000UL 1755 #define NRF_WDT_BASE 0x40010000UL 1756 #define NRF_RTC1_BASE 0x40011000UL 1757 #define NRF_QDEC_BASE 0x40012000UL 1758 #define NRF_EGU0_BASE 0x40014000UL 1759 #define NRF_SWI0_BASE 0x40014000UL 1760 #define NRF_EGU1_BASE 0x40015000UL 1761 #define NRF_SWI1_BASE 0x40015000UL 1762 #define NRF_SWI2_BASE 0x40016000UL 1763 #define NRF_SWI3_BASE 0x40017000UL 1764 #define NRF_SWI4_BASE 0x40018000UL 1765 #define NRF_SWI5_BASE 0x40019000UL 1766 #define NRF_NVMC_BASE 0x4001E000UL 1767 #define NRF_PPI_BASE 0x4001F000UL 1768 1769 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1770 1771 1772 /* =========================================================================================================================== */ 1773 /* ================ Peripheral declaration ================ */ 1774 /* =========================================================================================================================== */ 1775 1776 1777 /** @addtogroup Device_Peripheral_declaration 1778 * @{ 1779 */ 1780 1781 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1782 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1783 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 1784 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 1785 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1786 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1787 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 1788 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1789 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1790 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 1791 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1792 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 1793 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 1794 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1795 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 1796 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 1797 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1798 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 1799 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1800 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1801 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1802 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1803 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1804 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1805 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1806 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1807 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1808 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1809 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1810 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1811 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 1812 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 1813 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 1814 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 1815 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 1816 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 1817 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 1818 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 1819 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1820 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1821 1822 /** @} */ /* End of group Device_Peripheral_declaration */ 1823 1824 1825 /* ========================================= End of section using anonymous unions ========================================= */ 1826 #if defined (__CC_ARM) 1827 #pragma pop 1828 #elif defined (__ICCARM__) 1829 /* leave anonymous unions enabled */ 1830 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 1831 #pragma clang diagnostic pop 1832 #elif defined (__GNUC__) 1833 /* anonymous unions are enabled by default */ 1834 #elif defined (__TMS470__) 1835 /* anonymous unions are enabled by default */ 1836 #elif defined (__TASKING__) 1837 #pragma warning restore 1838 #elif defined (__CSMC__) 1839 /* anonymous unions are enabled by default */ 1840 #endif 1841 1842 1843 #ifdef __cplusplus 1844 } 1845 #endif 1846 1847 #endif /* NRF52805_H */ 1848 1849 1850 /** @} */ /* End of group nrf52805 */ 1851 1852 /** @} */ /* End of group Nordic Semiconductor */ 1853
