1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_WDT_H__
35 #define NRF_WDT_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if !defined(NRF_WDT0) && defined(NRF_WDT)
44 #define NRF_WDT0 NRF_WDT
45 #endif
46
47 /**
48 * @defgroup nrf_wdt_hal WDT HAL
49 * @{
50 * @ingroup nrf_wdt
51 * @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral.
52 */
53
54 /**
55 * @brief Macro getting pointer to the structure of registers of the WDT peripheral.
56 *
57 * @param[in] idx WDT instance index.
58 *
59 * @return Pointer to the structure of registers of the WDT peripheral.
60 */
61 #define NRF_WDT_INST_GET(idx) NRFX_CONCAT(NRF_, WDT, idx)
62
63 #if defined(WDT_TASKS_STOP_TASKS_STOP_Msk) || defined (__NRFX_DOXYGEN__)
64 /** @brief Presence of Task STOP functionality. */
65 #define NRF_WDT_HAS_STOP 1
66 #else
67 #define NRF_WDT_HAS_STOP 0
68 #endif
69
70 #if defined(WDT_NMIENSET_TIMEOUT_Msk) || defined (__NRFX_DOXYGEN__)
71 /** @brief Presence of non-maskable interrupt configuration. */
72 #define NRF_WDT_HAS_NMI 1
73 #else
74 #define NRF_WDT_HAS_NMI 0
75 #endif
76
77 /** @brief Number of WDT channels. */
78 #define NRF_WDT_CHANNEL_NUMBER 0x8UL
79
80 /** @brief WDT register reload value. */
81 #define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value; should not be modified. */
82
83 /** @brief WDT tasks. */
84 typedef enum
85 {
86 NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
87 #if NRF_WDT_HAS_STOP
88 NRF_WDT_TASK_STOP = offsetof(NRF_WDT_Type, TASKS_STOP), /**< Task for stopping WDT. */
89 #endif
90 } nrf_wdt_task_t;
91
92 /** @brief WDT events. */
93 typedef enum
94 {
95 NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
96 #if NRF_WDT_HAS_STOP
97 NRF_WDT_EVENT_STOPPED = offsetof(NRF_WDT_Type, EVENTS_STOPPED), /**< Event from WDT stop. */
98 #endif
99 } nrf_wdt_event_t;
100
101 /** @brief WDT behavior in the SLEEP or HALT CPU modes. */
102 typedef enum
103 {
104 NRF_WDT_BEHAVIOUR_RUN_SLEEP_MASK = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */
105 NRF_WDT_BEHAVIOUR_RUN_HALT_MASK = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */
106 #if NRF_WDT_HAS_STOP
107 NRF_WDT_BEHAVIOUR_STOP_ENABLE_MASK = WDT_CONFIG_STOPEN_Msk, /**< WDT allows stopping. */
108 #endif
109 } nrf_wdt_behaviour_mask_t;
110
111 /** @brief WDT reload request registers. */
112 typedef enum
113 {
114 NRF_WDT_RR0 = 0, /**< Reload request register 0. */
115 NRF_WDT_RR1, /**< Reload request register 1. */
116 NRF_WDT_RR2, /**< Reload request register 2. */
117 NRF_WDT_RR3, /**< Reload request register 3. */
118 NRF_WDT_RR4, /**< Reload request register 4. */
119 NRF_WDT_RR5, /**< Reload request register 5. */
120 NRF_WDT_RR6, /**< Reload request register 6. */
121 NRF_WDT_RR7 /**< Reload request register 7. */
122 } nrf_wdt_rr_register_t;
123
124 /** @brief WDT reload request registers mask. */
125 typedef enum
126 {
127 NRF_WDT_RR0_MASK = (1UL << NRF_WDT_RR0), /**< Mask for reload request register 0. */
128 NRF_WDT_RR1_MASK = (1UL << NRF_WDT_RR1), /**< Mask for reload request register 1. */
129 NRF_WDT_RR2_MASK = (1UL << NRF_WDT_RR2), /**< Mask for reload request register 2. */
130 NRF_WDT_RR3_MASK = (1UL << NRF_WDT_RR3), /**< Mask for reload request register 3. */
131 NRF_WDT_RR4_MASK = (1UL << NRF_WDT_RR4), /**< Mask for reload request register 4. */
132 NRF_WDT_RR5_MASK = (1UL << NRF_WDT_RR5), /**< Mask for reload request register 5. */
133 NRF_WDT_RR6_MASK = (1UL << NRF_WDT_RR6), /**< Mask for reload request register 6. */
134 NRF_WDT_RR7_MASK = (1UL << NRF_WDT_RR7), /**< Mask for reload request register 7. */
135 } nrf_wdt_rr_register_mask_t;
136
137 /** @brief WDT interrupts. */
138 typedef enum
139 {
140 NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
141 #if NRF_WDT_HAS_STOP
142 NRF_WDT_INT_STOPPED_MASK = WDT_INTENSET_STOPPED_Msk, /**< WDT interrupt from stop event. */
143 #endif
144 } nrf_wdt_int_mask_t;
145
146 /**
147 * @brief Function for configuring the watchdog behaviour when the CPU is sleeping or halted.
148 *
149 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
150 * @param[in] mask Watchdog behaviour mask, created using @ref nrf_wdt_behaviour_mask_t.
151 */
152 NRF_STATIC_INLINE void nrf_wdt_behaviour_set(NRF_WDT_Type * p_reg, uint32_t mask);
153
154 /**
155 * @brief Function for starting the WDT task.
156 *
157 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
158 * @param[in] task Task.
159 */
160 NRF_STATIC_INLINE void nrf_wdt_task_trigger(NRF_WDT_Type * p_reg, nrf_wdt_task_t task);
161
162 /**
163 * @brief Function for clearing the WDT event register.
164 *
165 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
166 * @param[in] event Event.
167 */
168 NRF_STATIC_INLINE void nrf_wdt_event_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event);
169
170 /**
171 * @brief Function for retrieving the state of the WDT event.
172 *
173 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
174 * @param[in] event Event to be checked.
175 *
176 * @retval true The event has been generated.
177 * @retval false The event has not been generated.
178 */
179 NRF_STATIC_INLINE bool nrf_wdt_event_check(NRF_WDT_Type const * p_reg, nrf_wdt_event_t event);
180
181 /**
182 * @brief Function for enabling the specified interrupts.
183 *
184 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
185 * @param[in] mask Mask of interrupts to be enabled.
186 * Use @ref nrf_wdt_int_mask_t values for bit masking.
187 */
188 NRF_STATIC_INLINE void nrf_wdt_int_enable(NRF_WDT_Type * p_reg, uint32_t mask);
189
190 /**
191 * @brief Function for checking if the specified interrupts are enabled.
192 *
193 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
194 * @param[in] mask Mask of interrupts to be checked.
195 * Use @ref nrf_wdt_int_mask_t values for bit masking.
196 *
197 * @return Mask of enabled interrupts.
198 */
199 NRF_STATIC_INLINE uint32_t nrf_wdt_int_enable_check(NRF_WDT_Type const * p_reg, uint32_t mask);
200
201 /**
202 * @brief Function for disabling the specified interrupts.
203 *
204 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
205 * @param[in] mask Mask of interrupts to be disabled.
206 * Use @ref nrf_wdt_int_mask_t values for bit masking.
207 */
208 NRF_STATIC_INLINE void nrf_wdt_int_disable(NRF_WDT_Type * p_reg, uint32_t mask);
209
210 #if NRF_WDT_HAS_NMI
211 /**
212 * @brief Function for enabling the specified non-maskable interrupts.
213 *
214 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
215 * @param[in] mask Mask of interrupts to be enabled.
216 * Use @ref nrf_wdt_int_mask_t values for bit masking.
217 */
218 NRF_STATIC_INLINE void nrf_wdt_nmi_int_enable(NRF_WDT_Type * p_reg, uint32_t mask);
219
220 /**
221 * @brief Function for checking if the specified non-maskable interrupts are enabled.
222 *
223 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
224 * @param[in] mask Mask of interrupts to be checked.
225 * Use @ref nrf_wdt_int_mask_t values for bit masking.
226 *
227 * @return Mask of enabled interrupts.
228 */
229 NRF_STATIC_INLINE uint32_t nrf_wdt_nmi_int_enable_check(NRF_WDT_Type const * p_reg, uint32_t mask);
230
231 /**
232 * @brief Function for disabling a specified non-maskable interrupts.
233 *
234 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
235 * @param[in] mask Mask of interrupts to be disabled.
236 * Use @ref nrf_wdt_int_mask_t values for bit masking.
237 */
238 NRF_STATIC_INLINE void nrf_wdt_nmi_int_disable(NRF_WDT_Type * p_reg, uint32_t mask);
239 #endif
240
241 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
242 /**
243 * @brief Function for setting the subscribe configuration for a given
244 * WDT task.
245 *
246 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
247 * @param[in] task Task for which to set the configuration.
248 * @param[in] channel Channel through which to subscribe events.
249 */
250 NRF_STATIC_INLINE void nrf_wdt_subscribe_set(NRF_WDT_Type * p_reg,
251 nrf_wdt_task_t task,
252 uint8_t channel);
253
254 /**
255 * @brief Function for clearing the subscribe configuration for a given
256 * WDT task.
257 *
258 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
259 * @param[in] task Task for which to clear the configuration.
260 */
261 NRF_STATIC_INLINE void nrf_wdt_subscribe_clear(NRF_WDT_Type * p_reg, nrf_wdt_task_t task);
262
263 /**
264 * @brief Function for setting the publish configuration for a given
265 * WDT event.
266 *
267 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
268 * @param[in] event Event for which to set the configuration.
269 * @param[in] channel Channel through which to publish the event.
270 */
271 NRF_STATIC_INLINE void nrf_wdt_publish_set(NRF_WDT_Type * p_reg,
272 nrf_wdt_event_t event,
273 uint8_t channel);
274
275 /**
276 * @brief Function for clearing the publish configuration for a given
277 * WDT event.
278 *
279 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
280 * @param[in] event Event for which to clear the configuration.
281 */
282 NRF_STATIC_INLINE void nrf_wdt_publish_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event);
283 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
284
285 /**
286 * @brief Function for returning the address of a specific WDT task register.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] task Task.
290 *
291 * @return Address of requested task register.
292 */
293 NRF_STATIC_INLINE uint32_t nrf_wdt_task_address_get(NRF_WDT_Type const * p_reg,
294 nrf_wdt_task_t task);
295
296 /**
297 * @brief Function for returning the address of a specific WDT event register.
298 *
299 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
300 * @param[in] event Event.
301 *
302 * @return Address of requested event register.
303 */
304 NRF_STATIC_INLINE uint32_t nrf_wdt_event_address_get(NRF_WDT_Type const * p_reg,
305 nrf_wdt_event_t event);
306
307 /**
308 * @brief Function for retrieving the watchdog status.
309 *
310 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
311 *
312 * @retval true The watchdog is started.
313 * @retval false The watchdog is not started.
314 */
315 NRF_STATIC_INLINE bool nrf_wdt_started_check(NRF_WDT_Type const * p_reg);
316
317 /**
318 * @brief Function for retrieving the watchdog reload request status for specified register.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] rr_register Reload request register to be checked.
322 *
323 * @retval true Reload request is running.
324 * @retval false No reload requests are running.
325 */
326 NRF_STATIC_INLINE bool nrf_wdt_request_status_check(NRF_WDT_Type const * p_reg,
327 nrf_wdt_rr_register_t rr_register);
328
329 /**
330 * @brief Function for retrieving the watchdog reload requests status mask.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 *
334 * @return Running reload requests mask, constructed with @ref nrf_wdt_rr_register_mask_t.
335 */
336 NRF_STATIC_INLINE uint32_t nrf_wdt_request_status_get(NRF_WDT_Type const * p_reg);
337
338 /**
339 * @brief Function for setting the watchdog reload value.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] reload_value Watchdog counter initial value.
343 */
344 NRF_STATIC_INLINE void nrf_wdt_reload_value_set(NRF_WDT_Type * p_reg, uint32_t reload_value);
345
346 /**
347 * @brief Function for retrieving the watchdog reload value.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 *
351 * @return Reload value.
352 */
353 NRF_STATIC_INLINE uint32_t nrf_wdt_reload_value_get(NRF_WDT_Type const * p_reg);
354
355 /**
356 * @brief Function for enabling a specific reload request register.
357 *
358 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
359 * @param[in] rr_register Reload request register to be enabled.
360 */
361 NRF_STATIC_INLINE void nrf_wdt_reload_request_enable(NRF_WDT_Type * p_reg,
362 nrf_wdt_rr_register_t rr_register);
363
364 /**
365 * @brief Function for disabling a specific reload request register.
366 *
367 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
368 * @param[in] rr_register Reload request register to be disabled.
369 */
370 NRF_STATIC_INLINE void nrf_wdt_reload_request_disable(NRF_WDT_Type * p_reg,
371 nrf_wdt_rr_register_t rr_register);
372
373 /**
374 * @brief Function for retrieving the status of a specific reload request register.
375 *
376 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
377 * @param[in] rr_register Reload request register to be checked.
378 *
379 * @retval true The reload request register is enabled.
380 * @retval false The reload request register is not enabled.
381 */
382 NRF_STATIC_INLINE bool nrf_wdt_reload_request_enable_check(NRF_WDT_Type const * p_reg,
383 nrf_wdt_rr_register_t rr_register);
384
385 /**
386 * @brief Function for setting a specific reload request register.
387 *
388 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
389 * @param[in] rr_register Reload request register to set.
390 */
391 NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type * p_reg,
392 nrf_wdt_rr_register_t rr_register);
393
394 #if NRF_WDT_HAS_STOP
395 /**
396 * @brief Function for enabling or disabling stopping the watchdog.
397 *
398 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
399 * @param[in] enable True if stopping is to be enabled, false otherwise.
400 */
401 NRF_STATIC_INLINE void nrf_wdt_task_stop_enable_set(NRF_WDT_Type * p_reg, bool enable);
402 #endif
403
404 #ifndef NRF_DECLARE_ONLY
405
nrf_wdt_behaviour_set(NRF_WDT_Type * p_reg,uint32_t mask)406 NRF_STATIC_INLINE void nrf_wdt_behaviour_set(NRF_WDT_Type * p_reg, uint32_t mask)
407 {
408 p_reg->CONFIG = mask;
409 }
410
nrf_wdt_task_trigger(NRF_WDT_Type * p_reg,nrf_wdt_task_t task)411 NRF_STATIC_INLINE void nrf_wdt_task_trigger(NRF_WDT_Type * p_reg, nrf_wdt_task_t task)
412 {
413 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x01UL;
414 }
415
nrf_wdt_event_clear(NRF_WDT_Type * p_reg,nrf_wdt_event_t event)416 NRF_STATIC_INLINE void nrf_wdt_event_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event)
417 {
418 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
419 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
420 }
421
nrf_wdt_event_check(NRF_WDT_Type const * p_reg,nrf_wdt_event_t event)422 NRF_STATIC_INLINE bool nrf_wdt_event_check(NRF_WDT_Type const * p_reg, nrf_wdt_event_t event)
423 {
424 return nrf_event_check(p_reg, event);
425 }
426
nrf_wdt_int_enable(NRF_WDT_Type * p_reg,uint32_t mask)427 NRF_STATIC_INLINE void nrf_wdt_int_enable(NRF_WDT_Type * p_reg, uint32_t mask)
428 {
429 p_reg->INTENSET = mask;
430 }
431
nrf_wdt_int_enable_check(NRF_WDT_Type const * p_reg,uint32_t mask)432 NRF_STATIC_INLINE uint32_t nrf_wdt_int_enable_check(NRF_WDT_Type const * p_reg, uint32_t mask)
433 {
434 return p_reg->INTENSET & mask;
435 }
436
nrf_wdt_int_disable(NRF_WDT_Type * p_reg,uint32_t mask)437 NRF_STATIC_INLINE void nrf_wdt_int_disable(NRF_WDT_Type * p_reg, uint32_t mask)
438 {
439 p_reg->INTENCLR = mask;
440 }
441
442 #if NRF_WDT_HAS_NMI
nrf_wdt_nmi_int_enable(NRF_WDT_Type * p_reg,uint32_t mask)443 NRF_STATIC_INLINE void nrf_wdt_nmi_int_enable(NRF_WDT_Type * p_reg, uint32_t mask)
444 {
445 p_reg->NMIENSET = mask;
446 }
447
nrf_wdt_nmi_int_enable_check(NRF_WDT_Type const * p_reg,uint32_t mask)448 NRF_STATIC_INLINE uint32_t nrf_wdt_nmi_int_enable_check(NRF_WDT_Type const * p_reg, uint32_t mask)
449 {
450 return p_reg->NMIENSET & mask;
451 }
452
nrf_wdt_nmi_int_disable(NRF_WDT_Type * p_reg,uint32_t mask)453 NRF_STATIC_INLINE void nrf_wdt_nmi_int_disable(NRF_WDT_Type * p_reg, uint32_t mask)
454 {
455 p_reg->NMIENCLR = mask;
456 }
457 #endif
458
459 #if defined(DPPI_PRESENT)
nrf_wdt_subscribe_set(NRF_WDT_Type * p_reg,nrf_wdt_task_t task,uint8_t channel)460 NRF_STATIC_INLINE void nrf_wdt_subscribe_set(NRF_WDT_Type * p_reg,
461 nrf_wdt_task_t task,
462 uint8_t channel)
463 {
464 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
465 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
466 }
467
nrf_wdt_subscribe_clear(NRF_WDT_Type * p_reg,nrf_wdt_task_t task)468 NRF_STATIC_INLINE void nrf_wdt_subscribe_clear(NRF_WDT_Type * p_reg, nrf_wdt_task_t task)
469 {
470 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
471 }
472
nrf_wdt_publish_set(NRF_WDT_Type * p_reg,nrf_wdt_event_t event,uint8_t channel)473 NRF_STATIC_INLINE void nrf_wdt_publish_set(NRF_WDT_Type * p_reg,
474 nrf_wdt_event_t event,
475 uint8_t channel)
476 {
477 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
478 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
479 }
480
nrf_wdt_publish_clear(NRF_WDT_Type * p_reg,nrf_wdt_event_t event)481 NRF_STATIC_INLINE void nrf_wdt_publish_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event)
482 {
483 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
484 }
485 #endif // defined(DPPI_PRESENT)
486
nrf_wdt_task_address_get(NRF_WDT_Type const * p_reg,nrf_wdt_task_t task)487 NRF_STATIC_INLINE uint32_t nrf_wdt_task_address_get(NRF_WDT_Type const * p_reg,
488 nrf_wdt_task_t task)
489 {
490 return ((uint32_t)p_reg + (uint32_t)task);
491 }
492
nrf_wdt_event_address_get(NRF_WDT_Type const * p_reg,nrf_wdt_event_t event)493 NRF_STATIC_INLINE uint32_t nrf_wdt_event_address_get(NRF_WDT_Type const * p_reg,
494 nrf_wdt_event_t event)
495 {
496 return ((uint32_t)p_reg + (uint32_t)event);
497 }
498
nrf_wdt_started_check(NRF_WDT_Type const * p_reg)499 NRF_STATIC_INLINE bool nrf_wdt_started_check(NRF_WDT_Type const * p_reg)
500 {
501 #if defined(WDT_RUNSTATUS_RUNSTATUS_Msk)
502 return (bool)(p_reg->RUNSTATUS & WDT_RUNSTATUS_RUNSTATUS_Msk);
503 #else
504 return (bool)(p_reg->RUNSTATUS & WDT_RUNSTATUS_RUNSTATUSWDT_Msk);
505 #endif
506 }
507
nrf_wdt_request_status_check(NRF_WDT_Type const * p_reg,nrf_wdt_rr_register_t rr_register)508 NRF_STATIC_INLINE bool nrf_wdt_request_status_check(NRF_WDT_Type const * p_reg,
509 nrf_wdt_rr_register_t rr_register)
510 {
511 return (bool)(((p_reg->REQSTATUS) >> rr_register) & 0x1UL);
512 }
513
nrf_wdt_request_status_get(NRF_WDT_Type const * p_reg)514 NRF_STATIC_INLINE uint32_t nrf_wdt_request_status_get(NRF_WDT_Type const * p_reg)
515 {
516 return p_reg->REQSTATUS;
517 }
518
nrf_wdt_reload_value_set(NRF_WDT_Type * p_reg,uint32_t reload_value)519 NRF_STATIC_INLINE void nrf_wdt_reload_value_set(NRF_WDT_Type * p_reg, uint32_t reload_value)
520 {
521 p_reg->CRV = reload_value;
522 }
523
nrf_wdt_reload_value_get(NRF_WDT_Type const * p_reg)524 NRF_STATIC_INLINE uint32_t nrf_wdt_reload_value_get(NRF_WDT_Type const * p_reg)
525 {
526 return (uint32_t)p_reg->CRV;
527 }
528
nrf_wdt_reload_request_enable(NRF_WDT_Type * p_reg,nrf_wdt_rr_register_t rr_register)529 NRF_STATIC_INLINE void nrf_wdt_reload_request_enable(NRF_WDT_Type * p_reg,
530 nrf_wdt_rr_register_t rr_register)
531 {
532 p_reg->RREN |= 0x1UL << rr_register;
533 }
534
nrf_wdt_reload_request_disable(NRF_WDT_Type * p_reg,nrf_wdt_rr_register_t rr_register)535 NRF_STATIC_INLINE void nrf_wdt_reload_request_disable(NRF_WDT_Type * p_reg,
536 nrf_wdt_rr_register_t rr_register)
537 {
538 p_reg->RREN &= ~(0x1UL << rr_register);
539 }
540
nrf_wdt_reload_request_enable_check(NRF_WDT_Type const * p_reg,nrf_wdt_rr_register_t rr_register)541 NRF_STATIC_INLINE bool nrf_wdt_reload_request_enable_check(NRF_WDT_Type const * p_reg,
542 nrf_wdt_rr_register_t rr_register)
543 {
544 return (bool)(p_reg->RREN & (0x1UL << rr_register));
545 }
546
nrf_wdt_reload_request_set(NRF_WDT_Type * p_reg,nrf_wdt_rr_register_t rr_register)547 NRF_STATIC_INLINE void nrf_wdt_reload_request_set(NRF_WDT_Type * p_reg,
548 nrf_wdt_rr_register_t rr_register)
549 {
550 p_reg->RR[rr_register] = NRF_WDT_RR_VALUE;
551 }
552
553 #if NRF_WDT_HAS_STOP
nrf_wdt_task_stop_enable_set(NRF_WDT_Type * p_reg,bool enable)554 NRF_STATIC_INLINE void nrf_wdt_task_stop_enable_set(NRF_WDT_Type * p_reg, bool enable)
555 {
556 p_reg->TSEN = enable ? NRF_WDT_RR_VALUE : 0;
557 }
558 #endif
559
560 #endif // NRF_DECLARE_ONLY
561
562 /** @} */
563
564 #ifdef __cplusplus
565 }
566 #endif
567
568 #endif // NRF_WDT_H__
569
