1 /*
2  * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice, this
11  *    list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  *    contributors may be used to endorse or promote products derived from this
19  *    software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef NRF_VPR_CSR_VTIM_H__
35 #define NRF_VPR_CSR_VTIM_H__
36 
37 #include <nrfx.h>
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 /**
44  * @defgroup nrf_vpr_csr_vtim_hal VPR CSR VTIM HAL
45  * @{
46  * @ingroup nrf_vpr
47  * @brief   Hardware access layer for managing the VPR RISC-V CPU Control
48  *          and Status Registers for VPR Timer (VPR CSR VTIM).
49  */
50 
51 /** @brief Counter modes. */
52 typedef enum
53 {
54     NRF_VPR_CSR_VTIM_COUNT_STOP             = VPRCSR_NORDIC_CNTMODE0_CNTMODE0_STOP,     ///< Counter stops at 0.
55     NRF_VPR_CSR_VTIM_COUNT_WRAP             = VPRCSR_NORDIC_CNTMODE0_CNTMODE0_WRAP,     ///< Counter will continue counting from 0xFFF.
56     NRF_VPR_CSR_VTIM_COUNT_RELOAD           = VPRCSR_NORDIC_CNTMODE0_CNTMODE0_RELOAD,   ///< Counter will continue counting from the value in counter top.
57     NRF_VPR_CSR_VTIM_COUNT_TRIGGER_COMBINED = VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGCOMB, ///< Trigger (counter 0) or combined (counter 1) mode.
58                                                                                         /**< Trigger (applies to counter 0): Counter stops at 0.
59                                                                                          *   Counting will restart when a VIO event happens.
60                                                                                          *   Combined (applies to counter 1): Counter 1 acts as an extension of counter 0.
61                                                                                          *   (16 most significant bits of a 32-bit counter.) */
62 } nrf_vpr_csr_vtim_count_t;
63 
64 /**
65  * @brief Function for getting the counter mode.
66  *
67  * @param[in] counter Index of the counter.
68  *
69  * @return Counter mode.
70  */
71 NRF_STATIC_INLINE nrf_vpr_csr_vtim_count_t nrf_vpr_cst_vtim_count_mode_get(uint8_t counter);
72 
73 /**
74  * @brief Function for setting the counter mode.
75  *
76  * @param[in] counter Index of the counter.
77  * @param[in] mode    Counter mode to be set.
78  */
79 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_count_mode_set(uint8_t                  counter,
80                                                        nrf_vpr_csr_vtim_count_t mode);
81 
82 /**
83  * @brief Function for getting the counter value.
84  *
85  * @param[in] counter Index of the counter.
86  *
87  * @return Counter value.
88  */
89 NRF_STATIC_INLINE uint16_t nrf_vpr_csr_vtim_simple_counter_get(uint8_t counter);
90 
91 /**
92  * @brief Function for setting the counter value.
93  *
94  * @param[in] counter Index of the counter.
95  * @param[in] value   Value to be set.
96  */
97 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_set(uint8_t counter, uint16_t value);
98 
99 /**
100  * @brief Function for getting the counter top.
101  *
102  * @param[in] counter Index of the counter.
103  *
104  * @return Counter top.
105  */
106 NRF_STATIC_INLINE uint16_t nrf_vpr_csr_vtim_simple_counter_top_get(uint8_t counter);
107 
108 /**
109  * @brief Function for setting the counter top.
110  *
111  * @param[in] counter Index of the counter.
112  * @param[in] value   Top value to be set.
113  */
114 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_top_set(uint8_t counter, uint16_t value);
115 
116 /**
117  * @brief Function for setting the counter add.
118  *
119  * @param[in] counter Index of the counter.
120  * @param[in] value   Add value to be set.
121  */
122 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_add_set(uint8_t counter, uint16_t value);
123 
124 /**
125  * @brief Function for setting the wait register.
126  *
127  * Writing to this register will stall the CPU until counter reaches 0.
128  *
129  * @param[in] counter Index of the counter.
130  * @param[in] write   True if @p value is to be writtten to the counter value before starting the wait.
131  *                    False otherwise.
132  * @param[in] value   Value to be written to the counter if @p write is true.
133  */
134 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_wait_set(uint8_t  counter,
135                                                         bool     write,
136                                                         uint16_t value);
137 
138 /**
139  * @brief Function for getting the combined counter value.
140  *
141  * @note Lower 16 bits represent counter 0, while higher 16 bits represent counter 1.
142  *
143  * @return Counter value.
144  */
145 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_vtim_combined_counter_get(void);
146 
147 /**
148  * @brief Function for setting the combined counter value.
149  *
150  * @note Lower 16 bits represent counter 0, while higher 16 bits represent counter 1.
151  *
152  * @param[in] value Value to be set.
153  */
154 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_set(uint32_t value);
155 
156 /**
157  * @brief Function for getting the combined counter top.
158  *
159  * @note Lower 16 bits represent counter 0, while higher 16 bits represent counter 1.
160  *
161  * @return Counter top.
162  */
163 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_vtim_combined_counter_top_get(void);
164 
165 /**
166  * @brief Function for setting the combined counter top.
167  *
168  * @note Lower 16 bits represent counter 0, while higher 16 bits represent counter 1.
169  *
170  * @param[in] value Top value to be set.
171  */
172 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_top_set(uint32_t value);
173 
174 /**
175  * @brief Function for setting the combined counter add.
176  *
177  * @note This function should be used in 32-bit counter mode.
178  *
179  * @param[in] value Add value to be set.
180  */
181 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_add_set(uint32_t value);
182 
183 /**
184  * @brief Function for triggering the wait.
185  *
186  * Writing to this register will stall the CPU until 32-bit counter reaches 0.
187  *
188  * @note This function should be used in 32-bit counter mode.
189  */
190 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_wait_trigger(void);
191 
192 #ifndef NRF_DECLARE_ONLY
193 
nrf_vpr_cst_vtim_count_mode_get(uint8_t counter)194 NRF_STATIC_INLINE nrf_vpr_csr_vtim_count_t nrf_vpr_cst_vtim_count_mode_get(uint8_t counter)
195 {
196     switch (counter)
197     {
198         case 0:
199             return nrf_csr_read(VPRCSR_NORDIC_CNTMODE0);
200         case 1:
201             return nrf_csr_read(VPRCSR_NORDIC_CNTMODE1);
202         default:
203             NRFX_ASSERT(false);
204             return 0;
205     }
206 }
207 
nrf_vpr_csr_vtim_count_mode_set(uint8_t counter,nrf_vpr_csr_vtim_count_t mode)208 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_count_mode_set(uint8_t                  counter,
209                                                        nrf_vpr_csr_vtim_count_t mode)
210 {
211     switch (counter)
212     {
213         case 0:
214             nrf_csr_write(VPRCSR_NORDIC_CNTMODE0, mode);
215             break;
216         case 1:
217             nrf_csr_write(VPRCSR_NORDIC_CNTMODE1, mode);
218             break;
219         default:
220             NRFX_ASSERT(false);
221             break;
222     }
223 }
224 
nrf_vpr_csr_vtim_simple_counter_get(uint8_t counter)225 NRF_STATIC_INLINE uint16_t nrf_vpr_csr_vtim_simple_counter_get(uint8_t counter)
226 {
227     switch (counter)
228     {
229         case 0:
230             return (uint16_t)nrf_csr_read(VPRCSR_NORDIC_CNT0);
231         case 1:
232             return (uint16_t)nrf_csr_read(VPRCSR_NORDIC_CNT1);
233         default:
234             NRFX_ASSERT(false);
235             return 0;
236     }
237 }
238 
nrf_vpr_csr_vtim_simple_counter_set(uint8_t counter,uint16_t value)239 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_set(uint8_t counter, uint16_t value)
240 {
241     switch (counter)
242     {
243         case 0:
244             nrf_csr_write(VPRCSR_NORDIC_CNT0, (uint32_t)value);
245             break;
246         case 1:
247             nrf_csr_write(VPRCSR_NORDIC_CNT1, (uint32_t)value);
248             break;
249         default:
250             NRFX_ASSERT(false);
251             break;
252     }
253 }
254 
nrf_vpr_csr_vtim_simple_counter_top_get(uint8_t counter)255 NRF_STATIC_INLINE uint16_t nrf_vpr_csr_vtim_simple_counter_top_get(uint8_t counter)
256 {
257     switch (counter)
258     {
259         case 0:
260             return (nrf_csr_read(VPRCSR_NORDIC_CNTTOP) & VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk)
261                    >> VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos;
262         case 1:
263             return (nrf_csr_read(VPRCSR_NORDIC_CNTTOP) & VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk)
264                    >> VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos;
265         default:
266             return 0;
267     }
268 }
269 
nrf_vpr_csr_vtim_simple_counter_top_set(uint8_t counter,uint16_t value)270 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_top_set(uint8_t counter, uint16_t value)
271 {
272     uint32_t reg;
273 
274     switch (counter)
275     {
276         case 0:
277             reg = nrf_csr_read(VPRCSR_NORDIC_CNTTOP);
278             reg &= ~VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk;
279             reg |= value << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos;
280             nrf_csr_write(VPRCSR_NORDIC_CNTTOP, reg);
281             break;
282         case 1:
283             reg = nrf_csr_read(VPRCSR_NORDIC_CNTTOP);
284             reg &= ~VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk;
285             reg |= value << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos;
286             nrf_csr_write(VPRCSR_NORDIC_CNTTOP, reg);
287             break;
288         default:
289             NRFX_ASSERT(false);
290             break;
291     }
292 }
293 
nrf_vpr_csr_vtim_simple_counter_add_set(uint8_t counter,uint16_t value)294 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_counter_add_set(uint8_t counter, uint16_t value)
295 {
296     switch (counter)
297     {
298         case 0:
299             nrf_csr_write(VPRCSR_NORDIC_CNTADD0, value);
300             break;
301         case 1:
302             nrf_csr_write(VPRCSR_NORDIC_CNTADD1, value);
303             break;
304         default:
305             NRFX_ASSERT(false);
306             break;
307     }
308 }
309 
nrf_vpr_csr_vtim_simple_wait_set(uint8_t counter,bool write,uint16_t value)310 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_simple_wait_set(uint8_t counter, bool write, uint16_t value)
311 {
312     switch (counter)
313     {
314         case 0:
315             nrf_csr_write(VPRCSR_NORDIC_WAIT0,
316                       ((write ? VPRCSR_NORDIC_WAIT0_WRITEDATA_WRITE :
317                                 VPRCSR_NORDIC_WAIT0_WRITEDATA_WAIT)
318                        << VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos) |
319                       (value << VPRCSR_NORDIC_WAIT0_DATA_Pos));
320             break;
321         case 1:
322             nrf_csr_write(VPRCSR_NORDIC_WAIT1,
323                       ((write ? VPRCSR_NORDIC_WAIT1_WRITEDATA_WRITE :
324                                 VPRCSR_NORDIC_WAIT1_WRITEDATA_WAIT)
325                        << VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos) |
326                       (value << VPRCSR_NORDIC_WAIT1_DATA_Pos));
327             break;
328         default:
329             NRFX_ASSERT(false);
330             break;
331     }
332 }
333 
nrf_vpr_csr_vtim_combined_counter_get(void)334 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_vtim_combined_counter_get(void)
335 {
336     return nrf_csr_read(VPRCSR_NORDIC_CNT);
337 }
338 
nrf_vpr_csr_vtim_combined_counter_set(uint32_t value)339 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_set(uint32_t value)
340 {
341     nrf_csr_write(VPRCSR_NORDIC_CNT, value);
342 }
343 
nrf_vpr_csr_vtim_combined_counter_top_get(void)344 NRF_STATIC_INLINE uint32_t nrf_vpr_csr_vtim_combined_counter_top_get(void)
345 {
346     return nrf_csr_read(VPRCSR_NORDIC_CNTTOP);
347 }
348 
nrf_vpr_csr_vtim_combined_counter_top_set(uint32_t value)349 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_top_set(uint32_t value)
350 {
351     nrf_csr_write(VPRCSR_NORDIC_CNTTOP, value);
352 }
353 
nrf_vpr_csr_vtim_combined_counter_add_set(uint32_t value)354 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_counter_add_set(uint32_t value)
355 {
356     nrf_csr_write(VPRCSR_NORDIC_CNTADD, value);
357 }
358 
nrf_vpr_csr_vtim_combined_wait_trigger(void)359 NRF_STATIC_INLINE void nrf_vpr_csr_vtim_combined_wait_trigger(void)
360 {
361     /* Writing any value will trigger wait. */
362     nrf_csr_write(VPRCSR_NORDIC_WAIT, VPRCSR_NORDIC_WAIT_VAL_Msk);
363 }
364 
365 #endif // NRF_DECLARE_ONLY
366 
367 /** @} */
368 
369 #ifdef __cplusplus
370 }
371 #endif
372 
373 #endif // NRF_VPR_CSR_VTIM_H__
374