1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_VPR_H__
35 #define NRF_VPR_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_vpr_hal VPR HAL
45 * @{
46 * @ingroup nrf_vpr
47 * @brief Hardware access layer for managing the VPR RISC-V CPU unit (VPR).
48 */
49
50 /** @brief Symbol specifying maximum number of available events triggered. */
51 #define NRF_VPR_EVENTS_TRIGGERED_COUNT VPR_EVENTS_TRIGGERED_MaxCount
52
53 /** @brief Macro for creating the interrupt bitmask for all event channels */
54 #define NRF_VPR_ALL_CHANNELS_INT_MASK \
55 ((uint32_t) (((1ULL << NRF_VPR_EVENTS_TRIGGERED_COUNT) - 1) \
56 << VPR_EVENTS_TRIGGERED_MinIndex))
57
58 /** @brief Macro used as an mask to clear all triggered interrupts within CSR */
59 #define NRF_VPR_TASK_TRIGGER_ALL_MASK UINT32_MAX
60
61 /** @brief Symbol specifying minimal index of TRIGGERED events array that is implemented. */
62 #define NRF_VPR_EVENTS_TRIGGERED_MIN VPR_EVENTS_TRIGGERED_MinIndex
63
64 /** @brief Symbol specifying maximal index of TRIGGERED events array that is implemented. */
65 #define NRF_VPR_EVENTS_TRIGGERED_MAX VPR_EVENTS_TRIGGERED_MaxIndex
66
67 /** @brief Symbol specifying minimal index of TRIGGER tasks array that is implemented. */
68 #define NRF_VPR_TASKS_TRIGGER_MIN VPR_TASKS_TRIGGER_MinIndex
69
70 /** @brief Symbol specifying maximal index of TRIGGER tasks array that is implemented. */
71 #define NRF_VPR_TASKS_TRIGGER_MAX VPR_TASKS_TRIGGER_MaxIndex
72
73 /** @brief VPR events. */
74 typedef enum
75 {
76 #if NRF_VPR_EVENTS_TRIGGERED_MIN < 16
77 NRF_VPR_EVENT_TRIGGERED_0 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[0]), /**< Triggered 0 event.*/
78 NRF_VPR_EVENT_TRIGGERED_1 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[1]), /**< Triggered 1 event.*/
79 NRF_VPR_EVENT_TRIGGERED_2 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[2]), /**< Triggered 2 event.*/
80 NRF_VPR_EVENT_TRIGGERED_3 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[3]), /**< Triggered 3 event.*/
81 NRF_VPR_EVENT_TRIGGERED_4 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[4]), /**< Triggered 4 event.*/
82 NRF_VPR_EVENT_TRIGGERED_5 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[5]), /**< Triggered 5 event.*/
83 NRF_VPR_EVENT_TRIGGERED_6 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[6]), /**< Triggered 6 event.*/
84 NRF_VPR_EVENT_TRIGGERED_7 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[7]), /**< Triggered 7 event.*/
85 NRF_VPR_EVENT_TRIGGERED_8 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[8]), /**< Triggered 8 event.*/
86 NRF_VPR_EVENT_TRIGGERED_9 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[9]), /**< Triggered 9 event.*/
87 NRF_VPR_EVENT_TRIGGERED_10 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[10]), /**< Triggered 10 event.*/
88 NRF_VPR_EVENT_TRIGGERED_11 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[11]), /**< Triggered 11 event.*/
89 NRF_VPR_EVENT_TRIGGERED_12 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[12]), /**< Triggered 12 event.*/
90 NRF_VPR_EVENT_TRIGGERED_13 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[13]), /**< Triggered 13 event.*/
91 NRF_VPR_EVENT_TRIGGERED_14 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[14]), /**< Triggered 14 event.*/
92 NRF_VPR_EVENT_TRIGGERED_15 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[15]), /**< Triggered 15 event.*/
93 #endif
94 NRF_VPR_EVENT_TRIGGERED_16 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[16]), /**< Triggered 16 event.*/
95 NRF_VPR_EVENT_TRIGGERED_17 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[17]), /**< Triggered 17 event.*/
96 NRF_VPR_EVENT_TRIGGERED_18 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[18]), /**< Triggered 18 event.*/
97 NRF_VPR_EVENT_TRIGGERED_19 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[19]), /**< Triggered 19 event.*/
98 NRF_VPR_EVENT_TRIGGERED_20 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[20]), /**< Triggered 20 event.*/
99 NRF_VPR_EVENT_TRIGGERED_21 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[21]), /**< Triggered 21 event.*/
100 NRF_VPR_EVENT_TRIGGERED_22 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[22]), /**< Triggered 22 event.*/
101 #if NRF_VPR_EVENTS_TRIGGERED_MAX > 22
102 NRF_VPR_EVENT_TRIGGERED_23 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[23]), /**< Triggered 23 event.*/
103 NRF_VPR_EVENT_TRIGGERED_24 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[24]), /**< Triggered 24 event.*/
104 NRF_VPR_EVENT_TRIGGERED_25 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[25]), /**< Triggered 25 event.*/
105 NRF_VPR_EVENT_TRIGGERED_26 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[26]), /**< Triggered 26 event.*/
106 NRF_VPR_EVENT_TRIGGERED_27 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[27]), /**< Triggered 27 event.*/
107 NRF_VPR_EVENT_TRIGGERED_28 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[28]), /**< Triggered 28 event.*/
108 NRF_VPR_EVENT_TRIGGERED_29 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[29]), /**< Triggered 29 event.*/
109 NRF_VPR_EVENT_TRIGGERED_30 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[30]), /**< Triggered 30 event.*/
110 NRF_VPR_EVENT_TRIGGERED_31 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[31]), /**< Triggered 31 event.*/
111 #endif
112 } nrf_vpr_event_t;
113
114 /** @brief VPR interrupts. */
115 typedef enum
116 {
117 #if NRF_VPR_EVENTS_TRIGGERED_MIN < 16
118 NRF_VPR_INT_TRIGGERED_0_MASK = VPR_INTENSET_TRIGGERED0_Msk, /**< Triggered 0 interrupt mask. */
119 NRF_VPR_INT_TRIGGERED_1_MASK = VPR_INTENSET_TRIGGERED1_Msk, /**< Triggered 1 interrupt mask. */
120 NRF_VPR_INT_TRIGGERED_2_MASK = VPR_INTENSET_TRIGGERED2_Msk, /**< Triggered 2 interrupt mask. */
121 NRF_VPR_INT_TRIGGERED_3_MASK = VPR_INTENSET_TRIGGERED3_Msk, /**< Triggered 3 interrupt mask. */
122 NRF_VPR_INT_TRIGGERED_4_MASK = VPR_INTENSET_TRIGGERED4_Msk, /**< Triggered 4 interrupt mask. */
123 NRF_VPR_INT_TRIGGERED_5_MASK = VPR_INTENSET_TRIGGERED5_Msk, /**< Triggered 5 interrupt mask. */
124 NRF_VPR_INT_TRIGGERED_6_MASK = VPR_INTENSET_TRIGGERED6_Msk, /**< Triggered 6 interrupt mask. */
125 NRF_VPR_INT_TRIGGERED_7_MASK = VPR_INTENSET_TRIGGERED7_Msk, /**< Triggered 7 interrupt mask. */
126 NRF_VPR_INT_TRIGGERED_8_MASK = VPR_INTENSET_TRIGGERED8_Msk, /**< Triggered 8 interrupt mask. */
127 NRF_VPR_INT_TRIGGERED_9_MASK = VPR_INTENSET_TRIGGERED9_Msk, /**< Triggered 9 interrupt mask. */
128 NRF_VPR_INT_TRIGGERED_10_MASK = VPR_INTENSET_TRIGGERED10_Msk, /**< Triggered 10 interrupt mask. */
129 NRF_VPR_INT_TRIGGERED_11_MASK = VPR_INTENSET_TRIGGERED11_Msk, /**< Triggered 11 interrupt mask. */
130 NRF_VPR_INT_TRIGGERED_12_MASK = VPR_INTENSET_TRIGGERED12_Msk, /**< Triggered 12 interrupt mask. */
131 NRF_VPR_INT_TRIGGERED_13_MASK = VPR_INTENSET_TRIGGERED13_Msk, /**< Triggered 13 interrupt mask. */
132 NRF_VPR_INT_TRIGGERED_14_MASK = VPR_INTENSET_TRIGGERED14_Msk, /**< Triggered 14 interrupt mask. */
133 NRF_VPR_INT_TRIGGERED_15_MASK = VPR_INTENSET_TRIGGERED15_Msk, /**< Triggered 15 interrupt mask. */
134 #endif
135 NRF_VPR_INT_TRIGGERED_16_MASK = VPR_INTENSET_TRIGGERED16_Msk, /**< Triggered 16 interrupt mask. */
136 NRF_VPR_INT_TRIGGERED_17_MASK = VPR_INTENSET_TRIGGERED17_Msk, /**< Triggered 17 interrupt mask. */
137 NRF_VPR_INT_TRIGGERED_18_MASK = VPR_INTENSET_TRIGGERED18_Msk, /**< Triggered 18 interrupt mask. */
138 NRF_VPR_INT_TRIGGERED_19_MASK = VPR_INTENSET_TRIGGERED19_Msk, /**< Triggered 19 interrupt mask. */
139 NRF_VPR_INT_TRIGGERED_20_MASK = VPR_INTENSET_TRIGGERED20_Msk, /**< Triggered 20 interrupt mask. */
140 NRF_VPR_INT_TRIGGERED_21_MASK = VPR_INTENSET_TRIGGERED21_Msk, /**< Triggered 21 interrupt mask. */
141 NRF_VPR_INT_TRIGGERED_22_MASK = VPR_INTENSET_TRIGGERED22_Msk, /**< Triggered 22 interrupt mask. */
142 #if NRF_VPR_EVENTS_TRIGGERED_MAX > 22
143 NRF_VPR_INT_TRIGGERED_23_MASK = VPR_INTENSET_TRIGGERED23_Msk, /**< Triggered 23 interrupt mask. */
144 NRF_VPR_INT_TRIGGERED_24_MASK = VPR_INTENSET_TRIGGERED24_Msk, /**< Triggered 24 interrupt mask. */
145 NRF_VPR_INT_TRIGGERED_25_MASK = VPR_INTENSET_TRIGGERED25_Msk, /**< Triggered 25 interrupt mask. */
146 NRF_VPR_INT_TRIGGERED_26_MASK = VPR_INTENSET_TRIGGERED26_Msk, /**< Triggered 26 interrupt mask. */
147 NRF_VPR_INT_TRIGGERED_27_MASK = VPR_INTENSET_TRIGGERED27_Msk, /**< Triggered 27 interrupt mask. */
148 NRF_VPR_INT_TRIGGERED_28_MASK = VPR_INTENSET_TRIGGERED28_Msk, /**< Triggered 28 interrupt mask. */
149 NRF_VPR_INT_TRIGGERED_29_MASK = VPR_INTENSET_TRIGGERED29_Msk, /**< Triggered 29 interrupt mask. */
150 NRF_VPR_INT_TRIGGERED_30_MASK = VPR_INTENSET_TRIGGERED30_Msk, /**< Triggered 30 interrupt mask. */
151 NRF_VPR_INT_TRIGGERED_31_MASK = VPR_INTENSET_TRIGGERED31_Msk, /**< Triggered 31 interrupt mask. */
152 #endif
153 } nrf_vpr_int_mask_t;
154
155 /** @brief VPR tasks. */
156 typedef enum
157 {
158 #if NRF_VPR_TASKS_TRIGGER_MIN < 16
159 NRF_VPR_TASK_TRIGGER_0 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[0]), /**< Trigger 0 task. */
160 NRF_VPR_TASK_TRIGGER_1 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[1]), /**< Trigger 1 task. */
161 NRF_VPR_TASK_TRIGGER_2 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[2]), /**< Trigger 2 task. */
162 NRF_VPR_TASK_TRIGGER_3 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[3]), /**< Trigger 3 task. */
163 NRF_VPR_TASK_TRIGGER_4 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[4]), /**< Trigger 4 task. */
164 NRF_VPR_TASK_TRIGGER_5 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[5]), /**< Trigger 5 task. */
165 NRF_VPR_TASK_TRIGGER_6 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[6]), /**< Trigger 6 task. */
166 NRF_VPR_TASK_TRIGGER_7 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[7]), /**< Trigger 7 task. */
167 NRF_VPR_TASK_TRIGGER_8 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[8]), /**< Trigger 8 task. */
168 NRF_VPR_TASK_TRIGGER_9 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[9]), /**< Trigger 9 task. */
169 NRF_VPR_TASK_TRIGGER_10 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[10]), /**< Trigger 10 task. */
170 NRF_VPR_TASK_TRIGGER_11 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[11]), /**< Trigger 11 task. */
171 NRF_VPR_TASK_TRIGGER_12 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[12]), /**< Trigger 12 task. */
172 NRF_VPR_TASK_TRIGGER_13 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[13]), /**< Trigger 13 task. */
173 NRF_VPR_TASK_TRIGGER_14 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[14]), /**< Trigger 14 task. */
174 NRF_VPR_TASK_TRIGGER_15 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[15]), /**< Trigger 15 task. */
175 #endif
176 NRF_VPR_TASK_TRIGGER_16 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[16]), /**< Trigger 16 task. */
177 NRF_VPR_TASK_TRIGGER_17 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[17]), /**< Trigger 17 task. */
178 NRF_VPR_TASK_TRIGGER_18 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[18]), /**< Trigger 18 task. */
179 NRF_VPR_TASK_TRIGGER_19 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[19]), /**< Trigger 19 task. */
180 NRF_VPR_TASK_TRIGGER_20 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[20]), /**< Trigger 20 task. */
181 NRF_VPR_TASK_TRIGGER_21 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[21]), /**< Trigger 21 task. */
182 NRF_VPR_TASK_TRIGGER_22 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[22]), /**< Trigger 22 task. */
183 #if NRF_VPR_TASKS_TRIGGER_MAX > 22
184 NRF_VPR_TASK_TRIGGER_23 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[23]), /**< Trigger 23 task. */
185 NRF_VPR_TASK_TRIGGER_24 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[24]), /**< Trigger 24 task. */
186 NRF_VPR_TASK_TRIGGER_25 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[25]), /**< Trigger 25 task. */
187 NRF_VPR_TASK_TRIGGER_26 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[26]), /**< Trigger 26 task. */
188 NRF_VPR_TASK_TRIGGER_27 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[27]), /**< Trigger 27 task. */
189 NRF_VPR_TASK_TRIGGER_28 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[28]), /**< Trigger 28 task. */
190 NRF_VPR_TASK_TRIGGER_29 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[29]), /**< Trigger 29 task. */
191 NRF_VPR_TASK_TRIGGER_30 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[30]), /**< Trigger 30 task. */
192 NRF_VPR_TASK_TRIGGER_31 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[31]), /**< Trigger 31 task. */
193 #endif
194 } nrf_vpr_task_t;
195
196 /** @brief Debug Mode Control signals. */
197 typedef enum
198 {
199 NRF_VPR_DMCONTROL_DMACTIVE, /** Debug module active. */
200 NRF_VPR_DMCONTROL_NDMRESET, /** Negative system reset signal. */
201 } nrf_vpr_dmcontrol_t;
202
203 /** @brief Debug Mode Control signal masks. */
204 typedef enum
205 {
206 NRF_VPR_DMCONTROL_DMACTIVE_MASK = VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk, /** Debug module active mask. */
207 NRF_VPR_DMCONTROL_NDMRESET_MASK = VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk, /** Negative system reset signal mask. */
208 } nrf_vpr_dmcontrol_mask_t;
209
210 /**
211 * @brief Function for triggering the specified VPR task.
212 *
213 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
214 * @param[in] task Task to be triggered.
215 */
216 NRF_STATIC_INLINE void nrf_vpr_task_trigger(NRF_VPR_Type * p_reg, nrf_vpr_task_t task);
217
218 /**
219 * @brief Function for getting the address of the specified VPR task register.
220 *
221 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
222 * @param[in] task Specified task.
223 *
224 * @return Address of the specified task register.
225 */
226 NRF_STATIC_INLINE uint32_t nrf_vpr_task_address_get(NRF_VPR_Type const * p_reg,
227 nrf_vpr_task_t task);
228
229 /**
230 * @brief Function for getting the specified VPR TRIGGER task.
231 *
232 * @param[in] index Task index.
233 *
234 * @return The specified VPR TRIGGER task.
235 */
236 NRF_STATIC_INLINE nrf_vpr_task_t nrf_vpr_trigger_task_get(uint8_t index);
237
238 /**
239 * @brief Function for clearing the specified VPR event.
240 *
241 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242 * @param[in] event Event to clear.
243 */
244 NRF_STATIC_INLINE void nrf_vpr_event_clear(NRF_VPR_Type * p_reg, nrf_vpr_event_t event);
245
246 /**
247 * @brief Function for retrieving the state of the VPR event.
248 *
249 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
250 * @param[in] event Event to be checked.
251 *
252 * @retval true The event has been generated.
253 * @retval false The event has not been generated.
254 */
255 NRF_STATIC_INLINE bool nrf_vpr_event_check(NRF_VPR_Type const * p_reg, nrf_vpr_event_t event);
256
257 /**
258 * @brief Function for getting the address of the specified VPR event register.
259 *
260 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
261 * @param[in] event Specified event.
262 *
263 * @return Address of the specified event register.
264 */
265 NRF_STATIC_INLINE uint32_t nrf_vpr_event_address_get(NRF_VPR_Type const * p_reg,
266 nrf_vpr_event_t event);
267
268 /**
269 * @brief Function for getting the specified VPR TRIGGERED event.
270 *
271 * @param[in] index Event index.
272 *
273 * @return The specified VPR TRIGGERED event.
274 */
275 NRF_STATIC_INLINE nrf_vpr_event_t nrf_vpr_triggered_event_get(uint8_t index);
276
277 /**
278 * @brief Function for enabling specified interrupts.
279 *
280 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
281 * @param[in] mask Mask of interrupts to be enabled.
282 * Use @ref nrf_vpr_int_mask_t values for bit masking.
283 */
284 NRF_STATIC_INLINE void nrf_vpr_int_enable(NRF_VPR_Type * p_reg, uint32_t mask);
285
286 /**
287 * @brief Function for disabling specified interrupts.
288 *
289 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
290 * @param[in] mask Mask of interrupts to be disabled.
291 * Use @ref nrf_vpr_int_mask_t values for bit masking.
292 */
293 NRF_STATIC_INLINE void nrf_vpr_int_disable(NRF_VPR_Type * p_reg, uint32_t mask);
294
295 /**
296 * @brief Function for checking if the specified interrupts are enabled.
297 *
298 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
299 * @param[in] mask Mask of interrupts to be checked.
300 * Use @ref nrf_vpr_int_mask_t values for bit masking.
301 *
302 * @return Mask of enabled interrupts.
303 */
304 NRF_STATIC_INLINE uint32_t nrf_vpr_int_enable_check(NRF_VPR_Type const * p_reg,
305 uint32_t mask);
306
307 /**
308 * @brief Function for setting the state of the CPU after core reset.
309 *
310 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
311 * @param[in] enable True if CPU is to be running, false if stopped.
312 */
313 NRF_STATIC_INLINE void nrf_vpr_cpurun_set(NRF_VPR_Type * p_reg,
314 bool enable);
315
316 /**
317 * @brief Function for getting the state of the CPU after core reset.
318 *
319 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
320 *
321 * @retval true CPU is to be running after core reset.
322 * @retval false CPU is to be stopped after core reset.
323 */
324 NRF_STATIC_INLINE bool nrf_vpr_cpurun_get(NRF_VPR_Type const * p_reg);
325
326 /**
327 * @brief Function for setting the initial value of the program counter after CPU reset.
328 *
329 * @note This address value must be 64-bit aligned.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] pc Initial value of the program counter to be set.
333 */
334 NRF_STATIC_INLINE void nrf_vpr_initpc_set(NRF_VPR_Type * p_reg,
335 uint32_t pc);
336
337 /**
338 * @brief Function for getting the initial value of the program counter after CPU reset.
339 *
340 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
341 *
342 * @return Initial value of the program counter.
343 */
344 NRF_STATIC_INLINE uint32_t nrf_vpr_initpc_get(NRF_VPR_Type const * p_reg);
345
346 /**
347 * @brief Function for setting the specified debug mode control signal.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] signal Signal to be set.
351 * @param[in] enable True if signal is to be 1, false if 0.
352 */
353 NRF_STATIC_INLINE void nrf_vpr_debugif_dmcontrol_set(NRF_VPR_Type * p_reg,
354 nrf_vpr_dmcontrol_t signal,
355 bool enable);
356
357 /**
358 * @brief Function for setting the mask of debug mode control signals.
359 *
360 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
361 * @param[in] mask Mask of signals to be set.
362 * Use @ref nrf_vpr_dmcontrol_mask_t values for bit masking.
363 */
364 NRF_STATIC_INLINE void nrf_vpr_debugif_dmcontrol_mask_set(NRF_VPR_Type * p_reg,
365 uint32_t mask);
366
367 /**
368 * @brief Function for getting the debug mode control signals.
369 *
370 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
371 * @param[in] signal Signal to be retrieved.
372 *
373 * @retval true Signal is logical 1.
374 * @retval false Signal is logical 0.
375 */
376 NRF_STATIC_INLINE bool nrf_vpr_debugif_dmcontrol_get(NRF_VPR_Type const * p_reg,
377 nrf_vpr_dmcontrol_t signal);
378
379 #ifndef NRF_DECLARE_ONLY
nrf_vpr_task_trigger(NRF_VPR_Type * p_reg,nrf_vpr_task_t task)380 NRF_STATIC_INLINE void nrf_vpr_task_trigger(NRF_VPR_Type * p_reg, nrf_vpr_task_t task)
381 {
382 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
383 }
384
nrf_vpr_task_address_get(NRF_VPR_Type const * p_reg,nrf_vpr_task_t task)385 NRF_STATIC_INLINE uint32_t nrf_vpr_task_address_get(NRF_VPR_Type const * p_reg,
386 nrf_vpr_task_t task)
387 {
388 return nrf_task_event_address_get(p_reg, task);
389 }
390
nrf_vpr_trigger_task_get(uint8_t index)391 NRF_STATIC_INLINE nrf_vpr_task_t nrf_vpr_trigger_task_get(uint8_t index)
392 {
393 return (nrf_vpr_task_t)NRFX_OFFSETOF(NRF_VPR_Type, TASKS_TRIGGER[index]);
394 }
395
nrf_vpr_event_clear(NRF_VPR_Type * p_reg,nrf_vpr_event_t event)396 NRF_STATIC_INLINE void nrf_vpr_event_clear(NRF_VPR_Type * p_reg, nrf_vpr_event_t event)
397 {
398 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
399 }
400
nrf_vpr_event_check(NRF_VPR_Type const * p_reg,nrf_vpr_event_t event)401 NRF_STATIC_INLINE bool nrf_vpr_event_check(NRF_VPR_Type const * p_reg, nrf_vpr_event_t event)
402 {
403 return nrf_event_check(p_reg, event);
404 }
405
nrf_vpr_event_address_get(NRF_VPR_Type const * p_reg,nrf_vpr_event_t event)406 NRF_STATIC_INLINE uint32_t nrf_vpr_event_address_get(NRF_VPR_Type const * p_reg,
407 nrf_vpr_event_t event)
408 {
409 return nrf_task_event_address_get(p_reg, event);
410 }
411
nrf_vpr_triggered_event_get(uint8_t index)412 NRF_STATIC_INLINE nrf_vpr_event_t nrf_vpr_triggered_event_get(uint8_t index)
413 {
414 return (nrf_vpr_event_t)NRFX_OFFSETOF(NRF_VPR_Type, EVENTS_TRIGGERED[index]);
415 }
416
nrf_vpr_int_enable(NRF_VPR_Type * p_reg,uint32_t mask)417 NRF_STATIC_INLINE void nrf_vpr_int_enable(NRF_VPR_Type * p_reg, uint32_t mask)
418 {
419 p_reg->INTENSET = mask;
420 }
421
nrf_vpr_int_disable(NRF_VPR_Type * p_reg,uint32_t mask)422 NRF_STATIC_INLINE void nrf_vpr_int_disable(NRF_VPR_Type * p_reg, uint32_t mask)
423 {
424 p_reg->INTENCLR = mask;
425 }
426
nrf_vpr_int_enable_check(NRF_VPR_Type const * p_reg,uint32_t mask)427 NRF_STATIC_INLINE uint32_t nrf_vpr_int_enable_check(NRF_VPR_Type const * p_reg,
428 uint32_t mask)
429 {
430 return p_reg->INTENSET & mask;
431 }
432
nrf_vpr_cpurun_set(NRF_VPR_Type * p_reg,bool enable)433 NRF_STATIC_INLINE void nrf_vpr_cpurun_set(NRF_VPR_Type * p_reg,
434 bool enable)
435 {
436 p_reg->CPURUN = (enable ? VPR_CPURUN_EN_Running : VPR_CPURUN_EN_Stopped) << VPR_CPURUN_EN_Pos;
437 }
438
nrf_vpr_cpurun_get(NRF_VPR_Type const * p_reg)439 NRF_STATIC_INLINE bool nrf_vpr_cpurun_get(NRF_VPR_Type const * p_reg)
440 {
441 return (p_reg->CPURUN & VPR_CPURUN_EN_Msk) >> VPR_CPURUN_EN_Pos;
442 }
443
nrf_vpr_initpc_set(NRF_VPR_Type * p_reg,uint32_t pc)444 NRF_STATIC_INLINE void nrf_vpr_initpc_set(NRF_VPR_Type * p_reg,
445 uint32_t pc)
446 {
447 NRFX_ASSERT((pc & 0x7FUL) == 0);
448 p_reg->INITPC = pc;
449 }
450
nrf_vpr_initpc_get(NRF_VPR_Type const * p_reg)451 NRF_STATIC_INLINE uint32_t nrf_vpr_initpc_get(NRF_VPR_Type const * p_reg)
452 {
453 return p_reg->INITPC;
454 }
455
nrf_vpr_debugif_dmcontrol_set(NRF_VPR_Type * p_reg,nrf_vpr_dmcontrol_t signal,bool enable)456 NRF_STATIC_INLINE void nrf_vpr_debugif_dmcontrol_set(NRF_VPR_Type * p_reg,
457 nrf_vpr_dmcontrol_t signal,
458 bool enable)
459 {
460 switch (signal)
461 {
462 case NRF_VPR_DMCONTROL_DMACTIVE:
463 p_reg->DEBUGIF.DMCONTROL = ((p_reg->DEBUGIF.DMCONTROL &
464 ~VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk) |
465 ((enable ? VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled :
466 VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled)
467 << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos));
468 break;
469 case NRF_VPR_DMCONTROL_NDMRESET:
470 p_reg->DEBUGIF.DMCONTROL = ((p_reg->DEBUGIF.DMCONTROL &
471 ~VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk) |
472 ((enable ? VPR_DEBUGIF_DMCONTROL_NDMRESET_Active :
473 VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive)
474 << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos));
475 break;
476 default:
477 NRFX_ASSERT(0);
478 }
479 }
480
nrf_vpr_debugif_dmcontrol_mask_set(NRF_VPR_Type * p_reg,uint32_t mask)481 NRF_STATIC_INLINE void nrf_vpr_debugif_dmcontrol_mask_set(NRF_VPR_Type * p_reg,
482 uint32_t mask)
483 {
484 p_reg->DEBUGIF.DMCONTROL = mask;
485 }
486
nrf_vpr_debugif_dmcontrol_get(NRF_VPR_Type const * p_reg,nrf_vpr_dmcontrol_t signal)487 NRF_STATIC_INLINE bool nrf_vpr_debugif_dmcontrol_get(NRF_VPR_Type const * p_reg,
488 nrf_vpr_dmcontrol_t signal)
489 {
490 switch (signal)
491 {
492 case NRF_VPR_DMCONTROL_DMACTIVE:
493 return ((p_reg->DEBUGIF.DMCONTROL & VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk)
494 >> VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos);
495 case NRF_VPR_DMCONTROL_NDMRESET:
496 return ((p_reg->DEBUGIF.DMCONTROL & VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk)
497 >> VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos);
498 default:
499 NRFX_ASSERT(0);
500 return false;
501 }
502 }
503
504 #endif // NRF_DECLARE_ONLY
505
506 /** @} */
507
508 #ifdef __cplusplus
509 }
510 #endif
511
512 #endif // NRF_VPR_H__
513
