1 /*
2 * Copyright (c) 2023 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_UICR_H_
35 #define NRF_UICR_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_uicr_hal UICR HAL
45 * @{
46 * @ingroup nrf_icr
47 * @brief Hardware access layer for managing the User Information Configuration Registers (UICR) peripheral.
48 */
49
50 #if defined(UICR_MEM_CONFIG_READ_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether memory configuration through UICR is present. */
52 #define NRF_UICR_HAS_MEM_CONFIG 1
53 #else
54 #define NRF_UICR_HAS_MEM_CONFIG 0
55 #endif
56
57 #if defined(UICR_PERIPH_CONFIG_PROCESSOR_Msk) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether peripheral configuration through UICR is present. */
59 #define NRF_UICR_HAS_PERIPH_CONFIG 1
60 #else
61 #define NRF_UICR_HAS_PERIPH_CONFIG 0
62 #endif
63
64 #if defined(UICR_GRTC_CC_OWN_CC0_Msk) || defined(__NRFX_DOXYGEN__)
65 /** @brief Symbol indicating whether feature configuration through UICR is present. */
66 #define NRF_UICR_HAS_FEATURE_CONFIG 1
67 #else
68 #define NRF_UICR_HAS_FEATURE_CONFIG 0
69 #endif
70
71 #if defined(UICR_MAILBOX_CONFIG_SIZE_Msk) || defined(__NRFX_DOXYGEN__)
72 /** @brief Symbol indicating whether mailbox configuration through UICR is present. */
73 #define NRF_UICR_HAS_MAILBOX 1
74 #else
75 #define NRF_UICR_HAS_MAILBOX 0
76 #endif
77
78 #if defined(UICR_INITSVTOR_INITSVTOR_Msk) || defined(__NRFX_DOXYGEN__)
79 /** @brief Symbol indicating whether VTOR configuration through UICR is present. */
80 #define NRF_UICR_HAS_VTOR 1
81 #else
82 #define NRF_UICR_HAS_VTOR 0
83 #endif
84
85 #if defined(UICR_PTREXTUICR_PTREXTUICR_Msk) || defined(__NRFX_DOXYGEN__)
86 /** @brief Symbol indicating whether extended UICR is present. */
87 #define NRF_UICR_HAS_PTREXT 1
88 #else
89 #define NRF_UICR_HAS_PTREXT 0
90 #endif
91
92 #if defined(UICREXTENDED_GPIO_OWN_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
93 /** @brief Symbol indicating whether GPIO feature is present. */
94 #define NRF_UICR_HAS_FEATURE_GPIO 1
95 #else
96 #define NRF_UICR_HAS_FEATURE_GPIO 0
97 #endif
98
99 #if defined(UICR_BOOTCONF_READ_Msk) || defined(__NRFX_DOXYGEN__)
100 /** @brief Symbol indicating whether immutable boot region configuration is present. */
101 #define NRF_UICR_HAS_BOOTCONF 1
102 #else
103 #define NRF_UICR_HAS_BOOTCONF 0
104 #endif
105
106 #if (defined(UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Msk) & \
107 defined(UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Msk)) || defined(__NRFX_DOXYGEN__)
108 /**
109 * @brief Symbol indicating whether linking channels of DPPI as either source or sink is configured
110 * using the LINK.DIR and LINK.EN registers.
111 */
112 #define NRF_UICR_HAS_CH_LINK_DIR_EN 1
113 #else
114 #define NRF_UICR_HAS_CH_LINK_DIR_EN 0
115 #endif
116
117 /** @brief Number of memory blocks. */
118 #define NRF_UICR_MEM_COUNT UICR_MEM_MaxCount
119
120 /** @brief Number of peripherals. */
121 #define NRF_UICR_PERIPH_COUNT UICR_PERIPH_MaxCount
122
123 #if NRF_UICR_HAS_FEATURE_GPIO
124 /** @brief Number of GPIOs. */
125 #define NRF_UICR_GPIO_COUNT UICREXTENDED_GPIO_MaxCount
126 #endif
127
128 /** @brief Number of GPIOTE channels. */
129 #define NRF_UICR_GPIOTE_CH_COUNT UICR_GPIOTE_MaxCount
130
131 /** @brief Number of global IPCTs. */
132 #define NRF_UICR_IPCT_GLOBAL_COUNT UICR_IPCT_GLOBAL_MaxCount
133
134 /** @brief Number of local IPCTs. */
135 #define NRF_UICR_DPPI_LOCAL_COUNT UICR_DPPI_LOCAL_MaxCount
136
137 /** @brief Number of global DPPIs. */
138 #define NRF_UICR_DPPI_GLOBAL_COUNT UICR_DPPI_GLOBAL_MaxCount
139
140 /** @brief Number of IPCMAPs. */
141 #define NRF_UICR_IPCMAP_COUNT UICR_IPCMAP_MaxCount
142
143 /** @brief Number of MAILBOXes. */
144 #define NRF_UICR_MAILBOX_COUNT UICR_MAILBOX_MaxCount
145
146 /** @brief Immutable boot region permissions bitmask. */
147 #define NRF_UICR_BOOTCONF_PERM_MASK (UICR_BOOTCONF_READ_Msk | UICR_BOOTCONF_WRITE_Msk | \
148 UICR_BOOTCONF_EXECUTE_Msk | UICR_BOOTCONF_SECURE_Msk)
149
150 #if NRF_UICR_HAS_MEM_CONFIG
151 /**
152 * @brief Memory permissions mask.
153 *
154 * @note When bit is set, the selected action is not allowed.
155 */
156 typedef enum
157 {
158 NRF_UICR_MEM_CONFIG_PERM_READ_MASK = UICR_MEM_CONFIG_READ_Msk, /**< Read access. */
159 NRF_UICR_MEM_CONFIG_PERM_WRITE_MASK = UICR_MEM_CONFIG_WRITE_Msk, /**< Write access. */
160 NRF_UICR_MEM_CONFIG_PERM_EXECUTE_MASK = UICR_MEM_CONFIG_EXECUTE_Msk, /**< Software execute. */
161 NRF_UICR_MEM_CONFIG_PERM_NONSECURE_MASK = UICR_MEM_CONFIG_SECURE_Msk, /**< Non-secure access. */
162 } nrf_uicr_mem_config_perm_mask_t;
163
164 /** @brief Memory configuration. */
165 typedef struct
166 {
167 uint32_t permissions; /**< Permissions. */
168 nrf_owner_t owner; /**< Owner identifier. */
169 uint32_t address; /**< Block start address. */
170 } nrf_uicr_mem_config_t;
171 #endif
172
173 #if NRF_UICR_HAS_FEATURE_CONFIG
174 /**
175 * @brief Feature index mask.
176 *
177 * @note Ownership of the pin is indicated by bit not set.
178 */
179 typedef enum
180 {
181 NRF_UICR_FEATURE_INDEX_0_MASK = UICR_GPIOTE_CH_OWN_CH0_Msk, /**< Feature index 0. */
182 NRF_UICR_FEATURE_INDEX_1_MASK = UICR_GPIOTE_CH_OWN_CH1_Msk, /**< Feature index 1. */
183 NRF_UICR_FEATURE_INDEX_2_MASK = UICR_GPIOTE_CH_OWN_CH2_Msk, /**< Feature index 2. */
184 NRF_UICR_FEATURE_INDEX_3_MASK = UICR_GPIOTE_CH_OWN_CH3_Msk, /**< Feature index 3. */
185 NRF_UICR_FEATURE_INDEX_4_MASK = UICR_GPIOTE_CH_OWN_CH4_Msk, /**< Feature index 4. */
186 NRF_UICR_FEATURE_INDEX_5_MASK = UICR_GPIOTE_CH_OWN_CH5_Msk, /**< Feature index 5. */
187 NRF_UICR_FEATURE_INDEX_6_MASK = UICR_GPIOTE_CH_OWN_CH6_Msk, /**< Feature index 6. */
188 NRF_UICR_FEATURE_INDEX_7_MASK = UICR_GPIOTE_CH_OWN_CH7_Msk, /**< Feature index 7. */
189 NRF_UICR_FEATURE_INDEX_8_MASK = UICR_GPIOTE_CH_OWN_CH8_Msk, /**< Feature index 8. */
190 NRF_UICR_FEATURE_INDEX_9_MASK = UICR_GPIOTE_CH_OWN_CH9_Msk, /**< Feature index 9. */
191 NRF_UICR_FEATURE_INDEX_10_MASK = UICR_GPIOTE_CH_OWN_CH10_Msk, /**< Feature index 10. */
192 NRF_UICR_FEATURE_INDEX_11_MASK = UICR_GPIOTE_CH_OWN_CH11_Msk, /**< Feature index 11. */
193 NRF_UICR_FEATURE_INDEX_12_MASK = UICR_GPIOTE_CH_OWN_CH12_Msk, /**< Feature index 12. */
194 NRF_UICR_FEATURE_INDEX_13_MASK = UICR_GPIOTE_CH_OWN_CH13_Msk, /**< Feature index 13. */
195 NRF_UICR_FEATURE_INDEX_14_MASK = UICR_GPIOTE_CH_OWN_CH14_Msk, /**< Feature index 14. */
196 NRF_UICR_FEATURE_INDEX_15_MASK = UICR_GPIOTE_CH_OWN_CH15_Msk, /**< Feature index 15. */
197 NRF_UICR_FEATURE_INDEX_16_MASK = UICR_GPIOTE_CH_OWN_CH16_Msk, /**< Feature index 16. */
198 NRF_UICR_FEATURE_INDEX_17_MASK = UICR_GPIOTE_CH_OWN_CH17_Msk, /**< Feature index 17. */
199 NRF_UICR_FEATURE_INDEX_18_MASK = UICR_GPIOTE_CH_OWN_CH18_Msk, /**< Feature index 18. */
200 NRF_UICR_FEATURE_INDEX_19_MASK = UICR_GPIOTE_CH_OWN_CH19_Msk, /**< Feature index 19. */
201 NRF_UICR_FEATURE_INDEX_20_MASK = UICR_GPIOTE_CH_OWN_CH20_Msk, /**< Feature index 20. */
202 NRF_UICR_FEATURE_INDEX_21_MASK = UICR_GPIOTE_CH_OWN_CH21_Msk, /**< Feature index 21. */
203 NRF_UICR_FEATURE_INDEX_22_MASK = UICR_GPIOTE_CH_OWN_CH22_Msk, /**< Feature index 22. */
204 NRF_UICR_FEATURE_INDEX_23_MASK = UICR_GPIOTE_CH_OWN_CH23_Msk, /**< Feature index 23. */
205 NRF_UICR_FEATURE_INDEX_24_MASK = UICR_GPIOTE_CH_OWN_CH24_Msk, /**< Feature index 24. */
206 NRF_UICR_FEATURE_INDEX_25_MASK = UICR_GPIOTE_CH_OWN_CH25_Msk, /**< Feature index 25. */
207 NRF_UICR_FEATURE_INDEX_26_MASK = UICR_GPIOTE_CH_OWN_CH26_Msk, /**< Feature index 26. */
208 NRF_UICR_FEATURE_INDEX_27_MASK = UICR_GPIOTE_CH_OWN_CH27_Msk, /**< Feature index 27. */
209 NRF_UICR_FEATURE_INDEX_28_MASK = UICR_GPIOTE_CH_OWN_CH28_Msk, /**< Feature index 28. */
210 NRF_UICR_FEATURE_INDEX_29_MASK = UICR_GPIOTE_CH_OWN_CH29_Msk, /**< Feature index 29. */
211 NRF_UICR_FEATURE_INDEX_30_MASK = UICR_GPIOTE_CH_OWN_CH30_Msk, /**< Feature index 30. */
212 NRF_UICR_FEATURE_INDEX_31_MASK = UICR_GPIOTE_CH_OWN_CH31_Msk, /**< Feature index 31. */
213 } nrf_uicr_feature_index_mask_t;
214
215 /** @brief UICR features. */
216 typedef enum
217 {
218 NRF_UICR_FEATURE_GPIO, /**< GPIO port. */
219 NRF_UICR_FEATURE_GPIOTE_CH, /**< GPIOTE channel. */
220 NRF_UICR_FEATURE_IPCT_LOCAL_CH, /**< Local IPCT channel. */
221 NRF_UICR_FEATURE_IPCT_LOCAL_INTERRUPT, /**< Local IPCT interrupt. */
222 NRF_UICR_FEATURE_IPCT_GLOBAL_CH, /**< Global IPCT channel. */
223 NRF_UICR_FEATURE_IPCT_GLOBAL_INTERRUPT, /**< Global IPCT interrupt. */
224 NRF_UICR_FEATURE_DPPI_LOCAL_CH, /**< Local DPPI channel. */
225 NRF_UICR_FEATURE_DPPI_LOCAL_CHG, /**< Local DPPI channel group. */
226 NRF_UICR_FEATURE_DPPI_GLOBAL_CH, /**< Global DPPI channel. */
227 NRF_UICR_FEATURE_DPPI_GLOBAL_CHG, /**< Global DPPI channel group. */
228 NRF_UICR_FEATURE_GRTC_CC, /**< GRTC compare channel. */
229 } nrf_uicr_feature_t;
230
231 /** @brief IPCMAP pair. */
232 typedef struct
233 {
234 uint8_t ipct_channel; /**< IPCT channel number. */
235 nrf_domain_t domain; /**< Domain ID. */
236 } nrf_uicr_ipcmap_pair_t;
237
238 /** @brief IPCMAP configuration. */
239 typedef struct
240 {
241 nrf_uicr_ipcmap_pair_t source; /**< Source side. */
242 nrf_uicr_ipcmap_pair_t sink; /**< Sink side. */
243 } nrf_uicr_ipcmap_config_t;
244
245 /** @brief DPPI link. */
246 typedef struct
247 {
248 uint32_t source; /**< Source side. */
249 uint32_t sink; /**< Sink side. */
250 } nrf_uicr_dppi_link_t;
251 #endif // NRF_UICR_HAS_FEATURE_CONFIG
252
253 #if NRF_UICR_HAS_PERIPH_CONFIG
254 /** @brief Peripheral configuration. */
255 typedef struct
256 {
257 bool secattr; /**< Security mapping. */
258 bool dmasec; /**< Security attribution for the DMA transfer. */
259 nrf_processor_t processor; /**< Processor ID. */
260 uint32_t address; /**< Peripheral address. */
261 } nrf_uicr_periph_config_t;
262 #endif
263
264 #if NRF_UICR_HAS_MAILBOX
265 /** @brief MAILBOX configuration. */
266 typedef struct
267 {
268 uint16_t size; /**< Memory size. */
269 nrf_owner_t owner; /**< Remote owner identification. */
270 bool secure; /**< Secure permission. */
271 } nrf_uicr_mailbox_config_t;
272 #endif
273
274 #if NRF_UICR_HAS_BOOTCONF
275 /**
276 * @brief Immutable boot region permissions mask.
277 *
278 * @note When bit is set, the selected action is allowed.
279 */
280 typedef enum
281 {
282 NRF_UICR_BOOT_REGION_PERM_READ_MASK = UICR_BOOTCONF_READ_Msk, ///< Read access.
283 NRF_UICR_BOOT_REGION_PERM_WRITE_MASK = UICR_BOOTCONF_WRITE_Msk, ///< Write access.
284 NRF_UICR_BOOT_REGION_PERM_EXECUTE_MASK = UICR_BOOTCONF_EXECUTE_Msk, ///< Software execute.
285 NRF_UICR_BOOT_REGION_PERM_SECURE_MASK = UICR_BOOTCONF_SECURE_Msk, ///< Secure-only access.
286 } nrf_uicr_boot_region_perm_mask_t;
287
288 /** @brief Immutable boot region configuration. */
289 typedef struct
290 {
291 uint32_t permissions; ///< Permissions created using @ref nrf_uicr_boot_region_perm_mask_t.
292 bool writeonce; ///< True if writes to the boot region are to be applied only when the current data is 0xFFFFFFFF.
293 bool lock; ///< True if RRAMC configuration registers for the boot region are to be read-only.
294 uint16_t size_kb; ///< Region size in kBs. */
295 } nrf_uicr_boot_region_config_t;
296 #endif
297
298 #if NRF_UICR_HAS_MEM_CONFIG
299 /**
300 * @brief Function for getting the configuration of the memory block.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] index Index of the memory block.
304 *
305 * @return Configuration of the specified memory block.
306 */
307 NRF_STATIC_INLINE nrf_uicr_mem_config_t nrf_uicr_mem_config_get(NRF_UICR_Type const * p_reg,
308 uint8_t index);
309
310 /**
311 * @brief Function for getting the size of the memory block.
312 *
313 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
314 * @param[in] index Index of the memory block.
315 *
316 * @return Size of the specified memory block in bytes.
317 */
318 NRF_STATIC_INLINE uint32_t nrf_uicr_mem_size_get(NRF_UICR_Type const * p_reg, uint8_t index);
319 #endif
320
321 #if NRF_UICR_HAS_PERIPH_CONFIG
322 /**
323 * @brief Function for getting the configuration of the peripheral.
324 *
325 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
326 * @param[in] index Index of the peripheral.
327 *
328 * @return Configuration of the specified peripheral.
329 */
330 NRF_STATIC_INLINE nrf_uicr_periph_config_t nrf_uicr_periph_config_get(NRF_UICR_Type const * p_reg,
331 uint8_t index);
332 #endif
333
334 #if NRF_UICR_HAS_FEATURE_CONFIG
335 /**
336 * @brief Function for getting the ownership requests of the feature.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] feature Feature to be accessed.
340 * @param[in] index Index of the feature. Only used for applicable features, otherwise skipped.
341 *
342 * @return Ownership requests mask of the specified feature.
343 */
344 NRF_STATIC_INLINE uint32_t nrf_uicr_feature_own_get(NRF_UICR_Type const * p_reg,
345 nrf_uicr_feature_t feature,
346 uint8_t index);
347
348 /**
349 * @brief Function for getting the permission requests of the feature.
350 *
351 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
352 * @param[in] feature Feature to be accessed.
353 * @param[in] index Index of the feature. Only used for applicable features, otherwise skipped.
354 *
355 * @return Permission requests mask of the specified feature.
356 */
357 NRF_STATIC_INLINE uint32_t nrf_uicr_feature_secure_get(NRF_UICR_Type const * p_reg,
358 nrf_uicr_feature_t feature,
359 uint8_t index);
360
361 /**
362 * @brief Function for getting the linking requests of the feature.
363 *
364 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
365 * @param[in] feature Feature to be accessed.
366 * @param[in] index Index of the feature. Only used for applicable features, otherwise skipped.
367 *
368 * @return Linking requests masks for source and sink of the specified feature.
369 */
370 NRF_STATIC_INLINE nrf_uicr_dppi_link_t nrf_uicr_feature_link_get(NRF_UICR_Type const * p_reg,
371 nrf_uicr_feature_t feature,
372 uint8_t index);
373
374 /**
375 * @brief Function for getting the configuration of the IPCMAP channel.
376 *
377 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
378 * @param[in] index Index of the IPCMAP channel.
379 *
380 * @return Configuration of the specified IPCMAP channel.
381 */
382 NRF_STATIC_INLINE nrf_uicr_ipcmap_config_t nrf_uicr_ipcmap_config_get(NRF_UICR_Type const * p_reg,
383 uint8_t index);
384 #endif
385
386 #if NRF_UICR_HAS_MAILBOX
387 /**
388 * @brief Function for getting the address of the MAILBOX.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] index Index of the memory block.
392 *
393 * @return Start address of the specified MAILBOX.
394 */
395 NRF_STATIC_INLINE uint32_t nrf_uicr_mailbox_address_get(NRF_UICR_Type const * p_reg, uint8_t index);
396
397 /**
398 * @brief Function for getting the configuration of the MAILBOX.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] index Index of the MAILBOX.
402 *
403 * @return Configuration of the specified MAILBOX.
404 */
405 NRF_STATIC_INLINE
406 nrf_uicr_mailbox_config_t nrf_uicr_mailbox_config_get(NRF_UICR_Type const * p_reg,
407 uint8_t index);
408 #endif
409
410 #if NRF_UICR_HAS_VTOR
411 /**
412 * @brief Function for getting the initial value of the secure VTOR (Vector Table Offset Register).
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 *
416 * @return Initial value of the secure VTOR.
417 */
418 NRF_STATIC_INLINE uint32_t nrf_uicr_initsvtor_get(NRF_UICR_Type const * p_reg);
419
420 /**
421 * @brief Function for getting the initial value of the non-secure VTOR.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 *
425 * @return Initial value of the non-secure VTOR.
426 */
427 NRF_STATIC_INLINE uint32_t nrf_uicr_initnsvtor_get(NRF_UICR_Type const * p_reg);
428 #endif
429
430 #if NRF_UICR_HAS_PTREXT
431 /**
432 * @brief Function for getting the pointer to the extended UICR.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 *
436 * @return Pointer to the extended UICR.
437 */
438 NRF_STATIC_INLINE uint32_t * nrf_uicr_ptrextuicr_get(NRF_UICR_Type const * p_reg);
439 #endif
440
441 #if NRF_UICR_HAS_BOOTCONF
442 /**
443 * @brief Function for setting the configuration of the immutable boot region.
444 *
445 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
446 * @param[in] p_config Pointer to the configuration structure.
447 */
448 NRF_STATIC_INLINE
449 void nrf_uicr_boot_region_config_set(NRF_UICR_Type * p_reg,
450 nrf_uicr_boot_region_config_t const * p_config);
451
452 /**
453 * @brief Function for getting the configuration of the immutable boot region.
454 *
455 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
456 * @param[in] p_config Pointer to the structure to be filled with immutable boot region settings.
457 *
458 * @retval true Configuration is applied.
459 * @retval false Register is equal to 0xFFFFFFFF, meaning that configuration is not applied.
460 */
461 NRF_STATIC_INLINE bool nrf_uicr_boot_region_config_get(NRF_UICR_Type const * p_reg,
462 nrf_uicr_boot_region_config_t * p_config);
463 #endif
464
465 #if NRF_UICR_HAS_FEATURE_GPIO
466 /**
467 * @brief Function for getting the GPIO instance address associated with the specified GPIO entry.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] index Index of GPIO entry.
471 *
472 * @return GPIO instance address.
473 */
474 NRF_STATIC_INLINE uint32_t nrf_uicr_gpio_instance_get(NRF_UICREXTENDED_Type const * p_reg,
475 uint8_t index);
476
477 /**
478 * @brief Function for getting the CTRLSEL configuration associated with the specified GPIO pin.
479 *
480 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
481 * @param[in] pin_number Absolute pin number.
482 *
483 * @return CTRLSEL configuration.
484 */
485 NRF_STATIC_INLINE uint32_t nrf_uicr_gpio_ctrlsel_get(NRF_UICREXTENDED_Type const * p_reg,
486 uint32_t pin_number);
487 #endif
488
489 #ifndef NRF_DECLARE_ONLY
490
491 #if NRF_UICR_HAS_MEM_CONFIG
nrf_uicr_mem_config_get(NRF_UICR_Type const * p_reg,uint8_t index)492 NRF_STATIC_INLINE nrf_uicr_mem_config_t nrf_uicr_mem_config_get(NRF_UICR_Type const * p_reg,
493 uint8_t index)
494 {
495 NRFX_ASSERT(index < NRF_UICR_MEM_COUNT);
496 nrf_uicr_mem_config_t config;
497
498 config.permissions = (p_reg->MEM[index].CONFIG &
499 (UICR_MEM_CONFIG_READ_Msk | UICR_MEM_CONFIG_WRITE_Msk |
500 UICR_MEM_CONFIG_EXECUTE_Msk | UICR_MEM_CONFIG_SECURE_Msk)
501 >> UICR_MEM_CONFIG_READ_Pos);
502
503 config.owner = (nrf_owner_t)((p_reg->MEM[index].CONFIG & UICR_MEM_CONFIG_OWNERID_Msk) >>
504 UICR_MEM_CONFIG_OWNERID_Pos);
505
506 /* Address should not be bit-shifted, as it contains bits [31:12]. The rest should be all zeroes. */
507 config.address = (p_reg->MEM[index].CONFIG & UICR_MEM_CONFIG_ADDRESS_Msk);
508
509 return config;
510 }
511
nrf_uicr_mem_size_get(NRF_UICR_Type const * p_reg,uint8_t index)512 NRF_STATIC_INLINE uint32_t nrf_uicr_mem_size_get(NRF_UICR_Type const * p_reg, uint8_t index)
513 {
514 NRFX_ASSERT(index < NRF_UICR_MEM_COUNT);
515 return p_reg->MEM[index].SIZE;
516 }
517 #endif
518
519 #if NRF_UICR_HAS_PERIPH_CONFIG
nrf_uicr_periph_config_get(NRF_UICR_Type const * p_reg,uint8_t index)520 NRF_STATIC_INLINE nrf_uicr_periph_config_t nrf_uicr_periph_config_get(NRF_UICR_Type const * p_reg,
521 uint8_t index)
522 {
523 NRFX_ASSERT(index < NRF_UICR_PERIPH_COUNT);
524 nrf_uicr_periph_config_t config;
525
526 config.secattr = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_SECURE_Msk) >>
527 UICR_PERIPH_CONFIG_SECURE_Pos;
528
529 config.dmasec = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_DMASEC_Msk) >>
530 UICR_PERIPH_CONFIG_DMASEC_Pos;
531
532 config.processor = (nrf_processor_t)((p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_PROCESSOR_Msk)
533 >> UICR_PERIPH_CONFIG_PROCESSOR_Pos);
534
535 /* Address should not be bit-shifted, as it contains bits [31:12]. The rest should be all zeroes. */
536 config.address = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_ADDRESS_Msk);
537
538 return config;
539 }
540 #endif
541
542 #if NRF_UICR_HAS_FEATURE_CONFIG
nrf_uicr_feature_own_get(NRF_UICR_Type const * p_reg,nrf_uicr_feature_t feature,uint8_t index)543 NRF_STATIC_INLINE uint32_t nrf_uicr_feature_own_get(NRF_UICR_Type const * p_reg,
544 nrf_uicr_feature_t feature,
545 uint8_t index)
546 {
547 switch (feature)
548 {
549 #if NRF_UICR_HAS_FEATURE_GPIO
550 case NRF_UICR_FEATURE_GPIO:
551 NRFX_ASSERT(index < NRF_UICR_GPIO_COUNT);
552 return ((NRF_UICREXTENDED_Type *)nrf_uicr_ptrextuicr_get(p_reg))->GPIO[index].OWN;
553 #endif
554
555 case NRF_UICR_FEATURE_GPIOTE_CH:
556 NRFX_ASSERT(index < NRF_UICR_GPIOTE_CH_COUNT);
557 return p_reg->GPIOTE[index].CH.OWN;
558
559 case NRF_UICR_FEATURE_IPCT_GLOBAL_CH:
560 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT);
561 return p_reg->IPCT.GLOBAL[index].CH.OWN;
562
563 case NRF_UICR_FEATURE_IPCT_GLOBAL_INTERRUPT:
564 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT);
565 return p_reg->IPCT.GLOBAL[index].INTERRUPT.OWN;
566
567 case NRF_UICR_FEATURE_DPPI_GLOBAL_CH:
568 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT);
569 return p_reg->DPPI.GLOBAL[index].CH.OWN;
570
571 case NRF_UICR_FEATURE_DPPI_GLOBAL_CHG:
572 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT);
573 return p_reg->DPPI.GLOBAL[index].CHG.OWN;
574
575 case NRF_UICR_FEATURE_GRTC_CC:
576 return p_reg->GRTC.CC.OWN;
577
578 default:
579 NRFX_ASSERT(false);
580 return 0;
581 }
582 }
583
nrf_uicr_feature_secure_get(NRF_UICR_Type const * p_reg,nrf_uicr_feature_t feature,uint8_t index)584 NRF_STATIC_INLINE uint32_t nrf_uicr_feature_secure_get(NRF_UICR_Type const * p_reg,
585 nrf_uicr_feature_t feature,
586 uint8_t index)
587 {
588 switch (feature)
589 {
590 #if NRF_UICR_HAS_FEATURE_GPIO
591 case NRF_UICR_FEATURE_GPIO:
592 NRFX_ASSERT(index < NRF_UICR_GPIO_COUNT);
593 return ((NRF_UICREXTENDED_Type *)nrf_uicr_ptrextuicr_get(p_reg))->GPIO[index].SECURE;
594 #endif
595
596 case NRF_UICR_FEATURE_GPIOTE_CH:
597 NRFX_ASSERT(index < NRF_UICR_GPIOTE_CH_COUNT);
598 return p_reg->GPIOTE[index].CH.SECURE;
599
600 case NRF_UICR_FEATURE_IPCT_LOCAL_CH:
601 return p_reg->IPCT.LOCAL.CH.SECURE;
602
603 case NRF_UICR_FEATURE_IPCT_LOCAL_INTERRUPT:
604 return p_reg->IPCT.LOCAL.INTERRUPT.SECURE;
605
606 case NRF_UICR_FEATURE_IPCT_GLOBAL_CH:
607 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT);
608 return p_reg->IPCT.GLOBAL[index].CH.SECURE;
609
610 case NRF_UICR_FEATURE_IPCT_GLOBAL_INTERRUPT:
611 NRFX_ASSERT(index < NRF_UICR_IPCT_GLOBAL_COUNT);
612 return p_reg->IPCT.GLOBAL[index].INTERRUPT.SECURE;
613
614 case NRF_UICR_FEATURE_DPPI_LOCAL_CH:
615 NRFX_ASSERT(index < NRF_UICR_DPPI_LOCAL_COUNT);
616 return p_reg->DPPI.LOCAL[index].CH.SECURE;
617
618 case NRF_UICR_FEATURE_DPPI_LOCAL_CHG:
619 NRFX_ASSERT(index < NRF_UICR_DPPI_LOCAL_COUNT);
620 return p_reg->DPPI.LOCAL[index].CHG.SECURE;
621
622 case NRF_UICR_FEATURE_DPPI_GLOBAL_CH:
623 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT);
624 return p_reg->DPPI.GLOBAL[index].CH.SECURE;
625
626 case NRF_UICR_FEATURE_DPPI_GLOBAL_CHG:
627 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT);
628 return p_reg->DPPI.GLOBAL[index].CHG.SECURE;
629
630 case NRF_UICR_FEATURE_GRTC_CC:
631 return p_reg->GRTC.CC.SECURE;
632
633 default:
634 NRFX_ASSERT(false);
635 return 0;
636 }
637 }
638
nrf_uicr_feature_link_get(NRF_UICR_Type const * p_reg,nrf_uicr_feature_t feature,uint8_t index)639 NRF_STATIC_INLINE nrf_uicr_dppi_link_t nrf_uicr_feature_link_get(NRF_UICR_Type const * p_reg,
640 nrf_uicr_feature_t feature,
641 uint8_t index)
642 {
643 nrf_uicr_dppi_link_t link;
644
645 switch (feature)
646 {
647 case NRF_UICR_FEATURE_DPPI_LOCAL_CH:
648 NRFX_ASSERT(index < NRF_UICR_DPPI_LOCAL_COUNT);
649 #if NRF_UICR_HAS_CH_LINK_DIR_EN
650 link.source = p_reg->DPPI.LOCAL[index].CH.LINK.EN | ~p_reg->DPPI.LOCAL[index].CH.LINK.DIR;
651 link.sink = p_reg->DPPI.LOCAL[index].CH.LINK.EN | p_reg->DPPI.LOCAL[index].CH.LINK.DIR;
652 #else
653 link.source = p_reg->DPPI.LOCAL[index].CH.LINK.SOURCE;
654 link.sink = p_reg->DPPI.LOCAL[index].CH.LINK.SINK;
655 #endif
656 break;
657
658 case NRF_UICR_FEATURE_DPPI_GLOBAL_CH:
659 NRFX_ASSERT(index < NRF_UICR_DPPI_GLOBAL_COUNT);
660 #if NRF_UICR_HAS_CH_LINK_DIR_EN
661 link.source = p_reg->DPPI.GLOBAL[index].CH.LINK.EN | ~p_reg->DPPI.GLOBAL[index].CH.LINK.DIR;
662 link.sink = p_reg->DPPI.GLOBAL[index].CH.LINK.EN | p_reg->DPPI.GLOBAL[index].CH.LINK.DIR;
663 #else
664 link.source = p_reg->DPPI.GLOBAL[index].CH.LINK.SOURCE;
665 link.sink = p_reg->DPPI.GLOBAL[index].CH.LINK.SINK;
666 #endif
667 break;
668
669 default:
670 NRFX_ASSERT(false);
671 break;
672 }
673
674 return link;
675 }
676
nrf_uicr_ipcmap_config_get(NRF_UICR_Type const * p_reg,uint8_t index)677 NRF_STATIC_INLINE nrf_uicr_ipcmap_config_t nrf_uicr_ipcmap_config_get(NRF_UICR_Type const * p_reg,
678 uint8_t index)
679 {
680 NRFX_ASSERT(index < NRF_UICR_IPCMAP_COUNT);
681 nrf_uicr_ipcmap_config_t map;
682
683 map.source.ipct_channel = (p_reg->IPCMAP[index] & UICR_IPCMAP_IPCTCHSOURCE_Msk)
684 >> UICR_IPCMAP_IPCTCHSOURCE_Pos;
685
686 map.source.domain = (nrf_domain_t)((p_reg->IPCMAP[index] & UICR_IPCMAP_DOMAINIDSOURCE_Msk)
687 >> UICR_IPCMAP_DOMAINIDSOURCE_Pos);
688
689 map.sink.ipct_channel = (p_reg->IPCMAP[index] & UICR_IPCMAP_IPCTCHSINK_Msk)
690 >> UICR_IPCMAP_IPCTCHSINK_Pos;
691
692 map.sink.domain = (nrf_domain_t)((p_reg->IPCMAP[index] & UICR_IPCMAP_DOMAINIDSINK_Msk)
693 >> UICR_IPCMAP_DOMAINIDSINK_Pos);
694
695 return map;
696 }
697 #endif
698
699 #if NRF_UICR_HAS_MAILBOX
nrf_uicr_mailbox_address_get(NRF_UICR_Type const * p_reg,uint8_t index)700 NRF_STATIC_INLINE uint32_t nrf_uicr_mailbox_address_get(NRF_UICR_Type const * p_reg, uint8_t index)
701 {
702 NRFX_ASSERT(index < NRF_UICR_MAILBOX_COUNT);
703
704 return p_reg->MAILBOX[index].ADDRESS;
705 }
706
707 NRF_STATIC_INLINE
nrf_uicr_mailbox_config_get(NRF_UICR_Type const * p_reg,uint8_t index)708 nrf_uicr_mailbox_config_t nrf_uicr_mailbox_config_get(NRF_UICR_Type const * p_reg,
709 uint8_t index)
710 {
711 NRFX_ASSERT(index < NRF_UICR_MAILBOX_COUNT);
712 nrf_uicr_mailbox_config_t config;
713
714 config.size = (p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_SIZE_Msk)
715 >> UICR_MAILBOX_CONFIG_SIZE_Pos;
716
717 config.owner = (nrf_owner_t)((p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_OWNERID_Msk)
718 >> UICR_MAILBOX_CONFIG_OWNERID_Pos);
719
720 config.secure = (p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_SECURE_Msk)
721 >> UICR_MAILBOX_CONFIG_SECURE_Pos;
722
723 return config;
724 }
725 #endif
726
727 #if NRF_UICR_HAS_VTOR
nrf_uicr_initsvtor_get(NRF_UICR_Type const * p_reg)728 NRF_STATIC_INLINE uint32_t nrf_uicr_initsvtor_get(NRF_UICR_Type const * p_reg)
729 {
730 return p_reg->INITSVTOR;
731 }
732
nrf_uicr_initnsvtor_get(NRF_UICR_Type const * p_reg)733 NRF_STATIC_INLINE uint32_t nrf_uicr_initnsvtor_get(NRF_UICR_Type const * p_reg)
734 {
735 return p_reg->INITNSVTOR;
736 }
737 #endif
738
739 #if NRF_UICR_HAS_PTREXT
nrf_uicr_ptrextuicr_get(NRF_UICR_Type const * p_reg)740 NRF_STATIC_INLINE uint32_t * nrf_uicr_ptrextuicr_get(NRF_UICR_Type const * p_reg)
741 {
742 return (uint32_t *)p_reg->PTREXTUICR;
743 }
744 #endif
745
746 #if NRF_UICR_HAS_BOOTCONF
747
748 NRF_STATIC_INLINE
nrf_uicr_boot_region_config_set(NRF_UICR_Type * p_reg,nrf_uicr_boot_region_config_t const * p_config)749 void nrf_uicr_boot_region_config_set(NRF_UICR_Type * p_reg,
750 nrf_uicr_boot_region_config_t const * p_config)
751 {
752 p_reg->BOOTCONF = (((p_config->permissions & NRF_UICR_BOOTCONF_PERM_MASK)) |
753 ((p_config->writeonce ? UICR_BOOTCONF_WRITEONCE_Enabled :
754 UICR_BOOTCONF_WRITEONCE_Disabled)
755 << UICR_BOOTCONF_WRITE_Pos) |
756 ((p_config->lock ? UICR_BOOTCONF_LOCK_Enabled:
757 UICR_BOOTCONF_LOCK_Disabled) << UICR_BOOTCONF_LOCK_Pos) |
758 ((p_config->size_kb << UICR_BOOTCONF_SIZE_Pos) & UICR_BOOTCONF_SIZE_Msk));
759 }
760
nrf_uicr_boot_region_config_get(NRF_UICR_Type const * p_reg,nrf_uicr_boot_region_config_t * p_config)761 NRF_STATIC_INLINE bool nrf_uicr_boot_region_config_get(NRF_UICR_Type const * p_reg,
762 nrf_uicr_boot_region_config_t * p_config)
763 {
764 uint32_t reg = p_reg->BOOTCONF;
765 p_config->permissions = reg & NRF_UICR_BOOTCONF_PERM_MASK;
766 p_config->writeonce = ((reg & UICR_BOOTCONF_WRITEONCE_Msk) >> UICR_BOOTCONF_WRITEONCE_Pos) ==
767 UICR_BOOTCONF_WRITEONCE_Enabled;
768 p_config->lock = ((reg & UICR_BOOTCONF_LOCK_Msk) >> UICR_BOOTCONF_LOCK_Pos) ==
769 UICR_BOOTCONF_LOCK_Enabled;
770 p_config->size_kb = (reg & UICR_BOOTCONF_SIZE_Msk) >> UICR_BOOTCONF_SIZE_Pos;
771 return (reg != UICR_BOOTCONF_ResetValue);
772 }
773 #endif
774
775 #if NRF_UICR_HAS_FEATURE_GPIO
nrf_uicr_gpio_instance_get(NRF_UICREXTENDED_Type const * p_reg,uint8_t index)776 NRF_STATIC_INLINE uint32_t nrf_uicr_gpio_instance_get(NRF_UICREXTENDED_Type const * p_reg,
777 uint8_t index)
778 {
779 NRFX_ASSERT(index < NRF_UICR_GPIO_COUNT);
780 return p_reg->GPIO[index].INSTANCE;
781 }
782
nrf_uicr_gpio_ctrlsel_get(NRF_UICREXTENDED_Type const * p_reg,uint32_t pin_number)783 NRF_STATIC_INLINE uint32_t nrf_uicr_gpio_ctrlsel_get(NRF_UICREXTENDED_Type const * p_reg,
784 uint32_t pin_number)
785 {
786 uint32_t port = NRF_PIN_NUMBER_TO_PORT(pin_number);
787 uint32_t pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
788 NRFX_ASSERT(port < NRF_UICR_GPIO_COUNT);
789 return p_reg->GPIO[port].PIN[pin].CTRLSEL;
790 }
791 #endif
792
793 #endif // NRF_DECLARE_ONLY
794
795 /** @} */
796
797 #ifdef __cplusplus
798 }
799 #endif
800
801 #endif /* NRF_UICR_H_ */
802
