1 /*
2 * Copyright (c) 2015 - 2024, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_UARTE_H__
35 #define NRF_UARTE_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA)
44 #define NRF_UARTE_CLOCKPIN_TXD_NEEDED 1
45 #endif
46
47 #if defined(NRF54H20_ENGA_XXAA)
48 #define NRF_UARTE_CLOCKPIN_RTS_NEEDED 1
49 #endif
50
51 #define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
52
53 /**
54 * @defgroup nrf_uarte_hal UARTE HAL
55 * @{
56 * @ingroup nrf_uarte
57 * @brief Hardware access layer for managing the UARTE peripheral.
58 */
59
60 /**
61 * @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
62 *
63 * @param[in] idx UARTE instance index.
64 *
65 * @return Pointer to the structure of registers of the UARTE peripheral.
66 */
67 #define NRF_UARTE_INST_GET(idx) NRFX_CONCAT(NRF_, UARTE, idx)
68
69 #if defined(UARTE_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
70 /** @brief Symbol indicating whether dedicated DMA register is present. */
71 #define NRF_UARTE_HAS_DMA_REG 1
72 #else
73 #define NRF_UARTE_HAS_DMA_REG 0
74 #endif
75
76 #if (defined(UARTE_TASKS_DMA_RX_START_START_Msk) && defined(UARTE_EVENTS_DMA_RX_END_END_Msk)) || \
77 defined(__NRFX_DOXYGEN__)
78 /** @brief Symbol indicating whether UARTE DMA tasks and events are present. */
79 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 1
80 #else
81 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 0
82 #endif
83
84 #if defined(UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk) || defined(__NRFX_DOXYGEN__)
85 /** @brief Symbol indicating whether UARTE DMA shortcuts are present. */
86 #define NRF_UARTE_HAS_DMA_SHORTS 1
87 #else
88 #define NRF_UARTE_HAS_DMA_SHORTS 0
89 #endif
90
91 #if defined(UARTE_SHORTS_ENDTX_STOPTX_Msk) || defined(UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk) || \
92 defined(__NRFX_DOXYGEN__)
93 /** @brief Symbol indicating whether UARTE ENDTX_STOPTX shortcut is present. */
94 #define NRF_UARTE_HAS_ENDTX_STOPTX_SHORT 1
95 #else
96 #define NRF_UARTE_HAS_ENDTX_STOPTX_SHORT 0
97 #endif
98
99 /** @brief Base frequency value 128 MHz for UARTE. */
100 #define NRF_UARTE_BASE_FREQUENCY_128MHZ (NRFX_MHZ_TO_HZ(128UL))
101 /** @brief Base frequency value 64 MHz for UARTE. */
102 #define NRF_UARTE_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
103 /** @brief Base frequency value 16 MHz for UARTE. */
104 #define NRF_UARTE_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
105
106 #if !defined(NRF_UARTE_IS_128MHZ_UARTE)
107 /** @brief Macro for checking whether the base frequency for the specified UARTE is 128 MHz. */
108 #define NRF_UARTE_IS_128MHZ_UARTE(p_reg) \
109 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_128MHZ), \
110 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(UARTE00), (p_reg == NRF_UARTE00), (false))), \
111 (false)))
112 #endif
113
114 #if !defined(NRF_UARTE_IS_64MHZ_UARTE)
115 /** @brief Macro for checking whether the base frequency for the specified UARTE is 64 MHz. */
116 #define NRF_UARTE_IS_64MHZ_UARTE(p_reg) \
117 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_64MHZ), \
118 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(UARTE00), (p_reg == NRF_UARTE00), (false))), \
119 (false)))
120 #endif
121
122 /**
123 * @brief Macro for getting base frequency value in Hz for the specified UARTE.
124 *
125 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
126 */
127 #define NRF_UARTE_BASE_FREQUENCY_GET(p_reg) \
128 ((NRF_UARTE_IS_128MHZ_UARTE(p_reg)) ? (NRF_UARTE_BASE_FREQUENCY_128MHZ): \
129 ((NRF_UARTE_IS_64MHZ_UARTE(p_reg)) ? (NRF_UARTE_BASE_FREQUENCY_64MHZ) : \
130 (NRF_UARTE_BASE_FREQUENCY_16MHZ)))
131
132 /** @brief UARTE tasks. */
133 typedef enum
134 {
135 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
136 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.START), ///< Start UART receiver.
137 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.STOP), ///< Stop UART receiver.
138 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.START), ///< Start UART transmitter.
139 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.STOP), ///< Stop UART transmitter.
140 #else
141 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
142 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
143 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
144 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
145 #endif
146 NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
147 } nrf_uarte_task_t;
148
149 /** @brief UARTE events. */
150 typedef enum
151 {
152 NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
153 NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
154 NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
155 NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
156 NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
157 NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
158 NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED), ///< Transmitted stopped.
159 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
160 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.END), ///< Receive buffer is filled up.
161 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.END), ///< Last TX byte transmitted.
162 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.READY), ///< Receiver has started.
163 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.READY), ///< Transmitter has started.
164 #else
165 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
166 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
167 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
168 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
169 #endif
170 } nrf_uarte_event_t;
171
172 /** @brief Types of UARTE shortcuts. */
173 typedef enum
174 {
175 #if NRF_UARTE_HAS_DMA_SHORTS
176 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk, ///< Shortcut between ENDRX event and STARTRX task.
177 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Msk, ///< Shortcut between ENDRX event and STOPRX task.
178 NRF_UARTE_SHORT_ENDTX_STOPTX = UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk ///< Shortcut between ENDTX event and STOPTX task.
179 #else
180 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
181 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task.
182 #if NRF_UARTE_HAS_ENDTX_STOPTX_SHORT
183 NRF_UARTE_SHORT_ENDTX_STOPTX = UARTE_SHORTS_ENDTX_STOPTX_Msk ///< Shortcut between ENDTX event and STOPTX task.
184 #endif
185 #endif
186 } nrf_uarte_short_t;
187
188
189 /** @brief UARTE interrupts. */
190 typedef enum
191 {
192 NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
193 NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
194 NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
195 NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
196 NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
197 NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
198 NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk, ///< Interrupt on TXSTOPPED event.
199 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
200 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
201 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
202 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
203 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
204 #else
205 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
206 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
207 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
208 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
209 #endif
210 } nrf_uarte_int_mask_t;
211
212 /** @brief Baudrates supported by UARTE. */
213 typedef enum
214 {
215 NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
216 NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
217 NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
218 NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
219 NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
220 NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
221 NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
222 NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
223 NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
224 NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
225 NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
226 NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
227 NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
228 NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
229 NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
230 NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
231 NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
232 NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
233 } nrf_uarte_baudrate_t;
234
235 /** @brief Types of UARTE error masks. */
236 typedef enum
237 {
238 NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
239 NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
240 NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
241 NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
242 } nrf_uarte_error_mask_t;
243
244 /** @brief Types of UARTE parity modes. */
245 typedef enum
246 {
247 NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
248 NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
249 } nrf_uarte_parity_t;
250
251 /** @brief Types of UARTE flow control modes. */
252 typedef enum
253 {
254 NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
255 NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
256 } nrf_uarte_hwfc_t;
257
258 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
259 /** @brief Types of UARTE stop bit modes. */
260 typedef enum
261 {
262 NRF_UARTE_STOP_ONE = UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos, ///< One stop bit.
263 NRF_UARTE_STOP_TWO = UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos ///< Two stop bits.
264 } nrf_uarte_stop_t;
265 #endif
266
267 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
268 /** @brief Types of UARTE parity types. */
269 typedef enum
270 {
271 NRF_UARTE_PARITYTYPE_EVEN = UARTE_CONFIG_PARITYTYPE_Even << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity even.
272 NRF_UARTE_PARITYTYPE_ODD = UARTE_CONFIG_PARITYTYPE_Odd << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity odd.
273 } nrf_uarte_paritytype_t;
274 #endif
275
276 /** @brief Structure for UARTE transmission configuration. */
277 typedef struct
278 {
279 nrf_uarte_hwfc_t hwfc; ///< Flow control configuration.
280 nrf_uarte_parity_t parity; ///< Parity configuration.
281 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
282 nrf_uarte_stop_t stop; ///< Stop bits.
283 #endif
284 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
285 nrf_uarte_paritytype_t paritytype; ///< Parity type.
286 #endif
287 } nrf_uarte_config_t;
288
289 /**
290 * @brief Function for clearing a specific UARTE event.
291 *
292 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
293 * @param[in] event Event to clear.
294 */
295 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
296
297 /**
298 * @brief Function for retrieving the state of the UARTE event.
299 *
300 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
301 * @param[in] event Event to be checked.
302 *
303 * @retval true The event has been generated.
304 * @retval false The event has not been generated.
305 */
306 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
307 nrf_uarte_event_t event);
308
309 /**
310 * @brief Function for returning the address of the specified UARTE event register.
311 *
312 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
313 * @param[in] event The specified event.
314 *
315 * @return Address of specified event register.
316 */
317 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
318 nrf_uarte_event_t event);
319
320 /**
321 * @brief Function for configuring UARTE shortcuts.
322 *
323 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
324 * @param[in] mask Shortcuts to be set.
325 */
326 NRF_STATIC_INLINE void nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg, uint32_t mask);
327
328 /**
329 * @brief Function for getting UARTE shortcuts.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] mask Shortcuts to be checked.
333 *
334 * @return Mask of requested shortcuts which were enabled.
335 */
336 NRF_STATIC_INLINE uint32_t nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg, uint32_t mask);
337
338 /**
339 * @brief Function for enabling UARTE shortcuts.
340 *
341 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
342 * @param[in] mask Shortcuts to be enabled.
343 */
344 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
345
346 /**
347 * @brief Function for disabling UARTE shortcuts.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] mask Shortcuts to be disabled.
351 */
352 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
353
354 /**
355 * @brief Function for enabling UARTE interrupts.
356 *
357 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
358 * @param[in] mask Mask of interrupts to be enabled.
359 * Use @ref nrf_uarte_int_mask_t values for bit masking.
360 */
361 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
362
363 /**
364 * @brief Function for checking if the specified interrupts are enabled.
365 *
366 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
367 * @param[in] mask Mask of interrupts to be checked.
368 * Use @ref nrf_uarte_int_mask_t values for bit masking.
369 *
370 * @return Mask of enabled interrupts.
371 */
372 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask);
373
374 /**
375 * @brief Function for disabling the specified interrupts.
376 *
377 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
378 * @param[in] mask Mask of interrupts to be disabled.
379 * Use @ref nrf_uarte_int_mask_t values for bit masking.
380 */
381 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
382
383 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
384 /**
385 * @brief Function for setting the subscribe configuration for a given
386 * UARTE task.
387 *
388 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
389 * @param[in] task Task for which to set the configuration.
390 * @param[in] channel Channel through which to subscribe events.
391 */
392 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
393 nrf_uarte_task_t task,
394 uint8_t channel);
395
396 /**
397 * @brief Function for clearing the subscribe configuration for a given
398 * UARTE task.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] task Task for which to clear the configuration.
402 */
403 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
404 nrf_uarte_task_t task);
405
406 /**
407 * @brief Function for setting the publish configuration for a given
408 * UARTE event.
409 *
410 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
411 * @param[in] event Event for which to set the configuration.
412 * @param[in] channel Channel through which to publish the event.
413 */
414 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
415 nrf_uarte_event_t event,
416 uint8_t channel);
417
418 /**
419 * @brief Function for clearing the publish configuration for a given
420 * UARTE event.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] event Event for which to clear the configuration.
424 */
425 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
426 nrf_uarte_event_t event);
427 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
428
429 /**
430 * @brief Function for getting error source mask. Function is clearing error source flags after reading.
431 *
432 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
433 *
434 * @return Mask with error source flags.
435 */
436 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
437
438 /**
439 * @brief Function for enabling UARTE.
440 *
441 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
442 */
443 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
444
445 /**
446 * @brief Function for disabling UARTE.
447 *
448 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
449 */
450 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
451
452 /**
453 * @brief Function for checking if the UARTE is enabled.
454 *
455 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
456 *
457 * @retval true The UARTE is enabled.
458 * @retval false The UARTE is not enabled.
459 */
460 NRF_STATIC_INLINE bool nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg);
461
462 /**
463 * @brief Function for configuring TX/RX pins.
464 *
465 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
466 * @param[in] pseltxd TXD pin number.
467 * @param[in] pselrxd RXD pin number.
468 */
469 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
470 uint32_t pseltxd,
471 uint32_t pselrxd);
472
473 /**
474 * @brief Function for disconnecting TX/RX pins.
475 *
476 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
477 */
478 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
479
480 /**
481 * @brief Function for getting TX pin selection.
482 *
483 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
484 *
485 * @return TX pin selection.
486 */
487 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg);
488
489 /**
490 * @brief Function for getting RX pin selection.
491 *
492 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
493 *
494 * @return RX pin selection.
495 */
496 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg);
497
498 /**
499 * @brief Function for getting RTS pin selection.
500 *
501 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
502 *
503 * @return RTS pin selection.
504 */
505 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg);
506
507 /**
508 * @brief Function for getting CTS pin selection.
509 *
510 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
511 *
512 * @return CTS pin selection.
513 */
514 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg);
515
516 /**
517 * @brief Function for configuring flow control pins.
518 *
519 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
520 * @param[in] pselrts RTS pin number.
521 * @param[in] pselcts CTS pin number.
522 */
523 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
524 uint32_t pselrts,
525 uint32_t pselcts);
526
527 /**
528 * @brief Function for disconnecting flow control pins.
529 *
530 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
531 */
532 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
533
534 /**
535 * @brief Function for starting an UARTE task.
536 *
537 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
538 * @param[in] task Task.
539 */
540 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
541
542 /**
543 * @brief Function for returning the address of the specified task register.
544 *
545 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
546 * @param[in] task Task.
547 *
548 * @return Task address.
549 */
550 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
551 nrf_uarte_task_t task);
552
553 /**
554 * @brief Function for configuring UARTE.
555 *
556 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
557 * @param[in] p_cfg Pointer to UARTE settings structure.
558 */
559 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
560 nrf_uarte_config_t const * p_cfg);
561
562 /**
563 * @brief Function for setting UARTE baud rate.
564 *
565 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
566 * @param[in] baudrate Baud rate.
567 */
568 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
569 nrf_uarte_baudrate_t baudrate);
570
571 /**
572 * @brief Function for setting the transmit buffer.
573 *
574 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
575 * @param[in] p_buffer Pointer to the buffer with data to send.
576 * @param[in] length Maximum number of data bytes to transmit.
577 */
578 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
579 uint8_t const * p_buffer,
580 size_t length);
581
582 /**
583 * @brief Function for getting the transmit buffer address.
584 *
585 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
586 *
587 * @return Pointer to the transmit buffer.
588 */
589 NRF_STATIC_INLINE uint8_t const * nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg);
590
591 /**
592 * @brief Function for getting number of bytes transmitted in the last transaction.
593 *
594 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
595 *
596 * @retval Amount of bytes transmitted.
597 */
598 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg);
599
600 /**
601 * @brief Function for setting the receive buffer.
602 *
603 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
604 * @param[in] p_buffer Pointer to the buffer for received data.
605 * @param[in] length Maximum number of data bytes to receive.
606 */
607 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
608 uint8_t * p_buffer,
609 size_t length);
610
611 /**
612 * @brief Function for getting the reception buffer address.
613 *
614 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
615 *
616 * @return Pointer to the reception buffer.
617 */
618 NRF_STATIC_INLINE uint8_t * nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg);
619
620 /**
621 * @brief Function for getting number of bytes received in the last transaction.
622 *
623 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
624 *
625 * @retval Amount of bytes received.
626 */
627 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg);
628
629 #ifndef NRF_DECLARE_ONLY
nrf_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)630 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
631 {
632 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
633 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
634 }
635
nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)636 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
637 nrf_uarte_event_t event)
638 {
639 return nrf_event_check(p_reg, event);
640 }
641
nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)642 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
643 nrf_uarte_event_t event)
644 {
645 return nrf_task_event_address_get(p_reg, event);
646 }
647
nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg,uint32_t mask)648 NRF_STATIC_INLINE void nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg, uint32_t mask)
649 {
650 p_reg->SHORTS = mask;
651 }
652
nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg,uint32_t mask)653 NRF_STATIC_INLINE uint32_t nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg, uint32_t mask)
654 {
655 return p_reg->SHORTS & mask;
656 }
657
nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)658 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
659 {
660 p_reg->SHORTS |= mask;
661 }
662
nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)663 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
664 {
665 p_reg->SHORTS &= ~(mask);
666 }
667
nrf_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)668 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
669 {
670 p_reg->INTENSET = mask;
671 }
672
nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)673 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask)
674 {
675 return p_reg->INTENSET & mask;
676 }
677
nrf_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)678 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
679 {
680 p_reg->INTENCLR = mask;
681 }
682
683 #if defined(DPPI_PRESENT)
nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)684 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
685 nrf_uarte_task_t task,
686 uint8_t channel)
687 {
688 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
689 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
690 }
691
nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)692 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
693 nrf_uarte_task_t task)
694 {
695 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
696 }
697
nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)698 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
699 nrf_uarte_event_t event,
700 uint8_t channel)
701 {
702 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
703 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
704 }
705
nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)706 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
707 nrf_uarte_event_t event)
708 {
709 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
710 }
711 #endif // defined(DPPI_PRESENT)
712
nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)713 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
714 {
715 uint32_t errsrc_mask = p_reg->ERRORSRC;
716 p_reg->ERRORSRC = errsrc_mask;
717 return errsrc_mask;
718 }
719
nrf_uarte_enable(NRF_UARTE_Type * p_reg)720 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
721 {
722 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
723 }
724
nrf_uarte_disable(NRF_UARTE_Type * p_reg)725 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
726 {
727 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
728 }
729
nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg)730 NRF_STATIC_INLINE bool nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg)
731 {
732 return p_reg->ENABLE == UARTE_ENABLE_ENABLE_Enabled;
733 }
734
nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)735 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
736 uint32_t pseltxd,
737 uint32_t pselrxd)
738 {
739 p_reg->PSEL.TXD = pseltxd;
740 p_reg->PSEL.RXD = pselrxd;
741 }
742
nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)743 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
744 {
745 nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
746 }
747
nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)748 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
749 {
750 return p_reg->PSEL.TXD;
751 }
752
nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)753 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
754 {
755 return p_reg->PSEL.RXD;
756 }
757
nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)758 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
759 {
760 return p_reg->PSEL.RTS;
761 }
762
nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)763 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
764 {
765 return p_reg->PSEL.CTS;
766 }
767
nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)768 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
769 uint32_t pselrts,
770 uint32_t pselcts)
771 {
772 p_reg->PSEL.RTS = pselrts;
773 p_reg->PSEL.CTS = pselcts;
774 }
775
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)776 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
777 {
778 nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
779 }
780
nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)781 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
782 {
783 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
784 }
785
nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)786 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
787 nrf_uarte_task_t task)
788 {
789 return (uint32_t)p_reg + (uint32_t)task;
790 }
791
nrf_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)792 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
793 nrf_uarte_config_t const * p_cfg)
794 {
795 p_reg->CONFIG = (uint32_t)p_cfg->parity
796 #if defined(UARTE_CONFIG_STOP_Msk)
797 | (uint32_t)p_cfg->stop
798 #endif
799 #if defined(UARTE_CONFIG_PARITYTYPE_Msk)
800 | (uint32_t)p_cfg->paritytype
801 #endif
802 | (uint32_t)p_cfg->hwfc;
803 }
804
nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)805 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
806 {
807 p_reg->BAUDRATE = baudrate;
808 }
809
nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)810 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
811 uint8_t const * p_buffer,
812 size_t length)
813 {
814 #if NRF_UARTE_HAS_DMA_REG
815 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
816 p_reg->DMA.TX.MAXCNT = length;
817 #else
818 p_reg->TXD.PTR = (uint32_t)p_buffer;
819 p_reg->TXD.MAXCNT = length;
820 #endif
821 }
822
nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)823 NRF_STATIC_INLINE uint8_t const * nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)
824 {
825 #if NRF_UARTE_HAS_DMA_REG
826 return (uint8_t const *)p_reg->DMA.TX.PTR;
827 #else
828 return (uint8_t const *)p_reg->TXD.PTR;
829 #endif
830 }
831
nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)832 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
833 {
834 #if NRF_UARTE_HAS_DMA_REG
835 return p_reg->DMA.TX.AMOUNT;
836 #else
837 return p_reg->TXD.AMOUNT;
838 #endif
839 }
840
nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)841 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
842 uint8_t * p_buffer,
843 size_t length)
844 {
845 #if NRF_UARTE_HAS_DMA_REG
846 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
847 p_reg->DMA.RX.MAXCNT = length;
848 #else
849 p_reg->RXD.PTR = (uint32_t)p_buffer;
850 p_reg->RXD.MAXCNT = length;
851 #endif
852 }
853
nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg)854 NRF_STATIC_INLINE uint8_t * nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg)
855 {
856 #if NRF_UARTE_HAS_DMA_REG
857 return (uint8_t *)p_reg->DMA.RX.PTR;
858 #else
859 return (uint8_t *)p_reg->RXD.PTR;
860 #endif
861 }
862
nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)863 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
864 {
865 #if NRF_UARTE_HAS_DMA_REG
866 return p_reg->DMA.RX.AMOUNT;
867 #else
868 return p_reg->RXD.AMOUNT;
869 #endif
870 }
871 #endif // NRF_DECLARE_ONLY
872
873 /** @} */
874
875 #ifdef __cplusplus
876 }
877 #endif
878
879 #endif // NRF_UARTE_H__
880
